Video ICs System control servo BU38603 / BU38703 / BU38803 The BU38603, BU38703 and BU38803 are servo controller ICs for VCRs. They contain a high-speed, 8-bit CPU and perform the processing required for the drum, capstan, FV and PV completely in software, allowing a large reduction in the number of external components required. They also contain high-performance linear amplifiers, eliminating the need for interface ICs. Specialized hardware is included for items that require high-speed processing, to allow efficient utilization of the CPU. Applications •VHS VCRs and camcorders •1)Features CPU 499 commands (69 types) Memory-mapped I / O Minimum command execution time: 250ns (8MHz) 2)ROM capacity BU38603: 16384 × 8 bit BU38703: 24576 × 8 bit BU38803: 32768 × 8 bit 3) RAM capacity: 512 × 8bit 4) Interrupt Pattern generator: 1 Watch-dog timer: 1 External interrupts: 1 FG interrupts: 5 Internal interrupts: 7 Two timers, serial transmission, interrupt, VHSW, CTL interval timer (fixed) / VISS ∗ Multi-layer interrupts possible. 5) Free-running counter: 19 bit 6) PWM output: 12 bit × 2 7) Pattern generator 17 bits from FRC MSB used. Output Internal: 3 bit External (PO): 5 bit External (PIO): 6 bit 8) Programmable pre-scaler CFG: 7 bit CTL: 6 bit 9) Head amplifier / chroma rotary Generated from pattern generator output. 10) Built-in AGC. Five-bits used to switch the gain control registers for the CTL amplifier. 11) CTL counter: 1 / 30 or 1 / 25 12) Data shift PLL calculation: 24 bit 13) Timer: 8 bit × 2 14) Synchronous serial input/output: 8 bit × 1 15) VH PULSE V separeted from composite synchronous snal. Pseudo V generated from pattern generator output. Superimposed pseudo H synchronized with the composite synchronous signal. 16) VISS / VASS VASS 0 / 1 discrimination VISS discrimination threshold: 3 Aspect discrimination. D / A CTL switching. 17) Standard I / O Parallel I / O (PIO): 32 bit Parallel output (PO): 6 bit 18) A / D converter: 8 bits × 8 channels Can be masked-programmed to be parallel inputs. 19) Watch-dog timer Setting period: 4 20) Linear circuits DFG: amplifier / comparator CFG: amplifier / comparator CTL: differential amplifier / comparator DPG: comparator 1 Video ICs BU38603 / BU38703 / BU38803 •Absolute maximum ratings (Ta = 25°C) Limits Symbol Parameter VDD, VDDA, VDAD Applied voltage Unit 0.3 ~ 7.0∗2 VSS – 0.3 ~ VDD + 0.3 V Pin applied voltage VIN Power dissipation Pd 500∗1 mW Tstg – 55 ~ + 125 °C Storage temperature range V ∗1 Reduced by 5mW for each increase in Ta of 1°C over 25°C. ∗2 Use with VSS = VSSA = VSAD, and VDD = VDDA = VDAD. •Recommended operating conditions Parameter Power supply voltage Symbol Limits Unit VDD, VDDA, VDDB 4.5 ~ 5.5 V Clock frequency FCK 8 MHz Operating temperature Topr – 25 ~ + 75 °C •Block diagram CPU ROM / RAM PO0-PO5 P1-P31 P0 Data bus PWM PWM0 PWM1 PTG VHSW AHSW PI / O Timer SI SO SCK SI / O Head amp, chroma HAMPSW CHROT ENVIN (P0) Interrupts VH PULSE FV CSYNC Watchdog ADC0-ADC7 FRC A / D converter Servo mode register Data shift COUNTP PBCTL CFG, CTL division Linear time counter VISSVASS Gain control Vref Linear CTL + CTL – CTLAMPOUT CTLAMP – DFGIN DFGOUT DPGIN CFGIN CFGOUT 2 RESETB Video ICs BU38603 / BU38703 / BU38803 •Pin descriptions Pin No. Pin name 1 VSAD 2 Function Pin No. Pin name 41 CHROT ADC0 42 FV Pseudo Vsync output 3 ADC1 43 VDD Logic circuit power supply 4 ADC2 Can be optionally mask – programmed 44 PWM0 5 ADC3 to be either A / D or parallel inputs. 45 PWM1 6 ADC4 46 P21 7 ADC5 47 P20 8 ADC6 48 P19 9 ADC7 49 P18 10 VDAD A / D convertor circuit power supply. 50 P17 11 DFGOUT Drum FG amplifier output 51 P16 12 DFGIN Drum FG amplifier input 52 P15 13 DPGIN Drum PG comparator input 53 P14 14 CFGIN Capstan FG amplifier input 54 P13 15 CFGOUT Capstan FG amplifier output 55 P12 16 VSSA Linear circuit GND 56 P11 17 Vref Internal BIAS and power-on reset pin 57 P10 18 CTLAMP – CTL amplifier – input 58 P9 19 CTLAMPOUT CTL amplifier output 59 PO2 20 CTL – CTL coil – connection 60 PO1 21 CTL + CTL coil + connection 61 PO0 22 VDDA Linear circuit power supply 62 CLOCKO 23 RESETB Power supply reset 63 CLOCKI 24 TEST Test mode input (normally GND) 64 VSS 25 PO5 65 P8 26 PO4 66 P7 27 P31 67 P6 28 P30 68 P5 29 P29 69 P4 30 P28 70 P3 31 P27 71 P2 32 P26 72 P1 33 P25 73 P0 Parallel I / O and external interrupt 34 P24 74 SI Serial I / O data input 35 P23 75 SO Serial I / O data I / O 36 P22 76 SCK Serial I / O clock I / O 37 PO3 Parallel output and pattern generator output 77 ENVIN Envelope detector logic input 38 VHSW Pattern generator VHSW output 78 CSYNC Composite signal logic input 39 AHSW Pattern generator AHSW output 79 COUNTP 40 HAMPSW Head amplifier switch output 80 PBCTL A / D convertor circuit GND. Parallel output Parallel I / O Parallel I / O and pattern generator output Function Chroma rotary switch output PWM output Parallel I / O Parallel output For connection of oscillator Logic circuit GND Parallel I / O CTL counter pulse output CTL logic output 3 Video ICs BU38603 / BU38703 / BU38803 •Electrical characteristics (unless otherwise noted, Ta = 25°C, V DD Measurement circuit Min. Typ. Max. Unit IDD — 12 19 mA Output high level voltage VH 4.0 4.5 — Output low level voltage VL — 0.5 Max. output low level current ILL 10.0 Input high level voltage VIH 4.0 Input low level voltage VIL — — 1.0 V Input high level current IH — 0 1.0 µA VIN = VDD Fig.2 Input low level current IL – 1.0 0 — µA VIN = 0 Fig.2 Parameter Symbol = 5V and fOSC = 8MHz) Conditions [Logic block] (Logic: pins 24 to 80) Operating supply current No load, when reset Fig.1 V I = 2mA: except pins 66 to 73 I = 1mA: 66 to 73pin Fig.2 1.0 V I = 2mA Fig.2 16.0 — mA — — V 〈Logic I / O〉 66 to 73pin Fig.2 Fig.2 Fig.2 〈Serial I / O〉 Input data hold TSH 0.16 — — µs — Input data setup TSS 0.16 — — µs — Output data delay TD — — 0.3 µs Between CLOCK and DATA — 10 26 mA No load IAD — 0.6 2.0 mA Fig.1 EL –3 0 3 LSB Fig.3 — [Linear block] (Linear: pins 11 to 23) Operating supply current ILI Fig.1 [A / D block] (A / D: pins 1 to 10) Operating supply current Linearity error VADPH 4.0 — — V When P input selected Fig.3 Input low level voltage VADPL — — 1.0 V When P input selected Fig.3 Input high level current IADPH — 0 1.0 µA When P input selected, VIN = VDD Fig.3 IADPL – 1.0 0 — µA When P input selected, VIN = 0 Fig.3 Input high level voltage Input low level current 4 Video ICs BU38603 / BU38703 / BU38803 •Measurement circuits 1k 10 11 22 43 12 1k 14 15 IclkI A A V1 B C I1in A 63 V4 A SW1 B TEST pin SW4 xtal C A B 62 Iclko C A V SW2 24 V2 1 10 V1out I4 64 A Itest A V3 B SW3 Fig.1 Idad 1k Idda Idd A A A 10 22 43 11 12 1k 14 A 15 63 SW2 B xtal SW1 A SW3 18 62 B A B SW4 2-9, 24, 27-36, 46-58 65-75, 77, 78 SW5 1 10 64 Fig.2 5 Video ICs BU38603 / BU38703 / BU38803 10 Iadin A V1 A B 22 43 10 64 SW1 TEST pin (2-9) C D/A 23 1 Fig.3 •Application example Capstan control Control Drum control 8MHz Serial bus Timer CSYNC Pseudo VSYNC Count pulse PI / O PWM CPU ROM / RAM FRC Data shift Head amplifier · chroma Interrupt SI / O VHPULSE Watchdog Pattern generator Servo mode Linear time counter VISSVASS Amplifier gain control CFG. CTL divider A/D RESET DFGAMP DPG CFGAMP REF voltage CTLAMP DFG DPG CFG Fig.4 6 ENVIN Head amplifier SW Chroma rotary SW AHSW VHSW CTL coil Video ICs BU38603 / BU38703 / BU38803 1 4.9 0.9 16 14 12 10 8 6 4 4.8 4.7 4.6 4.5 4.4 4.3 4.2 2 4.1 0 4 – 30 – 10 10 30 50 70 0.7 0.6 0.5 0.4 0.3 0.2 0.1 – 30 – 10 10 30 50 70 0 – 30 – 10 10 30 50 70 TEMPERATURE: Ta (°C) TEMPERATURE: Ta (°C) Fig. 5 Logic circuit current. Fig. 6 Logic “H” output voltage. Fig. 7 Logic “L” output voltage. 2 24 1.8 22 20 18 16 14 12 10 8 6 – 30 0.8 TEMPERATURE: Ta (°C) 26 4 “L” OUTPUT VOLTAGE: VL (V) 5 18 “H” OUTPUT VOLTAGE: VH (V) 20 A / D CIRCUIT CURRENT: IAD (mA) LINEAR CIRCUIT CURRENT: ILI (mA) LOGIC CIRCUIT CURRENT: IDD (mA) •Electrical characteristic curves – 10 10 30 50 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 70 – 30 – 10 10 30 50 70 TEMPERATURE: Ta (°C) TEMPERATURE: Ta (°C) Fig. 8 Linear circuit current. Fig. 9 A / D circuit current. •External dimensions (Units: mm) 24.0 ± 0.3 20.0 ± 0.2 64 41 14.0 ± 0.2 18.0 ± 0.3 80 25 24 2.7 ± 0.1 0.05 1 0.8 0.35 ± 0.1 1.2 40 65 0.15 ± 0.1 0.15 QFP80 7