EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR JANUARY 2008 1.0 INTRODUCTION The XRS10L240 provides the combined advantages of the Serial ATA II Port Selector and Port Multiplier implementations for Serial ATA II systems at 3.0 Gbps and 1.5 Gbps. Combining the capability to address four Serial ATA devices from one external link with support for a failover path from two independent hosts, the XRS10L240 offers a leading solution for propagation of high data rate Serial ATA products in a wide variety of applications. The integration of Serial ATA PHY links, a variety of digital logic capabilities, rate adjust FIFOs, integrated lowcost clock oscillator support, test and loopback features is achieved in a low cost and lower power implementation. The port selector function is used when dual hosts, such as I/O controllers, must access single-port disk drives in high availability storage subsystems where redundancy and load sharing are important. The outputs from the I/O controllers are multiplexed to a Serial ATA drive through the port selector block of the XRS10L240. Active/passive port selector in XRS10L240 allows two different host ports to connect to the same target in order to create a redundant path to that target. In combination with RAID, the XRS10L240 allows system providers to build fully redundant solutions. This avoids the presence of a single point of failure, and enables a fail-over path in the case of host failure. This port multiplier function is used when one active host has to communicate with multiple SATA drives. The XRS10L240 supports up to 4 SATA drives and utilizes the full bandwidth of the host connection. The XRS10L240 includes enhanced features such as staggered HDD spin-up, power management control, hot plug capability and support for legacy software. The XRS10L240 acts as a retimer, maintaining independent signaling domains between the drives, hosts and the external interconnect. The high-speed serial input features selectable equalization adjustment and the high-speed serial output features selectable pre-emphasis to compensate for ISI (Inter-Symbol Interference) and increase maximum cable distances. XRS10L240 meets tight jitter budgets in SATA applications. Exar's serial I/O technology enables reliable data transmission over 1 meter or more of FR-4 and 4 meters or more of unequalized copper cable. REV. 1.01 Host and drive port speeds can be mixed and matched, based upon inherent data rate negotiation present in the SATA II specifications. The MDIO bus allows simple configuration of the XRS10L240. To summarize, the port multiplier functionality in the XRS10L240 allows the system designer to increase the number of serial ATA connections in an enclosure that does not have a sufficient number of serial ATA connections for all of the drives in the enclosure. The port selector functionality in the XRS10L240 allows replacement for expensive Fibre Channel drives with cost effective and high capacity SATA drives in enterprise class applications without compromising on redundancy or performance. STANDARDS COMPLIANCE The XRS10L240 is compliant with the following industry specifications: • Serial ATA, Revision 1.0a • Serial ATA II: Extensions to Serial ATA 1.0a, Revision 1.2 • Serial ATA II PHY Electrical Specifications, Revision 1.0 • Serial ATA II: Port Selector, Revision 1.0 • Serial ATA II: Port Multiplier, Revision 1.2 • Serial ATA II: Revision 2.6 APPLICATIONS • Serial ATA Enclosures • Other Serial ATA link replicator applications • Buffers for externally connected links • High density storage boxes • RAID Subsystems FEATURES GENERAL FEATURES • Six independent 3/1.5G SATA ports. • Supports 3/1.5G rate detection/speed negotiation. • Supports power down modes - Active, partial, slumber and power down. PORT MULTIPLIER/SELECTOR LOGIC FEATURES • Low latency architecture. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR • Supports OOB signaling for SATA applications. REV. 1.01 PHYSICAL FEATURES Internal OOB detectors for COMSAS, COMRESET/ COMINIT and COMWAKE. • CMOS 0.13 Micron Technology • Single 1.2 V Power Supply • -40°C to 85°C Industrial Temperature Range TEST AND CONTROL FEATURES • Supports MDIO Bus. • Outputs for various failure modes. • Built-In self test mode through the MDIO bus. • Supports various loopback modes. • 2000 V ESD Rating on All High Speed I/O Pins • No heatsink or airflow required • 100-Pin LQFP Package APPLICATION EXAMPLE I/O FEATURES The XRS10L240 is ideally suited for use within an external drive enclosure as a means of providing redundant host access to ensure system availability and reliability, while enabling access to up to four target devices per XRS10L240. This application is shown in Figure 1. Other applications for the XRS10L240 include use in fixed-content or network attached storage systems, storage arrays, desktop applications or entry-level servers, RAID storage or disk-to-disk backup. • High speed outputs with selectable pre-emphasis to extend the link budgets. • High speed input equalization for improved signal integrity. • Compliant with SATA Gen2i & Gen2 specification. • Enables reliable data transmission over 1 meter or more of FR-4 and 4 meters or more of unequalized copper cable. • Supports spread spectrum clocking to reduce EMI. FIGURE 1. SYSTEM BLOCK DIAGRAM FOR XRS10L240 IN A DRIVE ENCLOSURE APPLICATION DRIVE ENCLOSURE XRS10L240 Port Selector Port Multiplier 2 SATA SATA SATA SATA EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RESETB DRACT0 DRACT1 DRACT2 DRACT3 VSS SOTN0 SOTP0 VDD SORN0 SORP0 VSS VSSA VDDA VSS SORP1 SORN1 VDD SOTP1 SOTN1 VSS VDD VSS PWRDNB ANTEST FIGURE 2. PINOUT OF THE XRS10L240 XRS10L240 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TRST PORTSEL MDC VSS MDIO VSS SOTN2 SOTP2 VDD SORN2 SORP2 VSS VSSA VDDA VSS SORP3 SORN3 VDD SOTP3 SOTN3 VSS VSS VDD CLKSTN CLKSTP HBACT PS_SIDEBAND_B VSS VDD VSS SiTN1 SiTP1 VDD SiRN1 SiRP1 VSS VDDA VSSA VSS SiRP0 SiRN0 VDD SiTP0 SiTN0 VSS TCK TMS VDD TDO TDI 3 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VDDA RBias VSSA CMU_REFN CMU_REFP VDDA XOG XOD VSSA SCANMODE PTN1 PTP1 VDD PRN1 PRP1 VSS VDDA VSSA VSS PRP0 PRN0 VDD PTP0 PTN0 VSS EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 2.0 PIN DESCRIPTIONS TABLE 1: XRS10L240 PIN DESCRIPTIONS Pin Name Pin Number I/O DESCRIPTION DATA INTERFACE SOTP0/SOTN0 68, 69 SOTP1/SOTN1 57, 56 SOTP2/SOTN2 8, 7 SOTP3/SOTN3 19, 20 SORP0/SORN0 65, 66 SORP1/SORN1 60, 59 SORP2/SORN2 11, 10 SORP3/SORN3 16, 17 SITP0/SITN0 93, 94 SITP1/SITN1 82, 81 SIRP0/SIRN0 90, 91 SIRP1/SIRN1 85, 84 O CML AC Coupled Serial ATA Output Transmitters. These ports communicate from the XRS10L240 to downstream devices I Serial ATA Input Receivers. These ports receive signals from downstream devices O Serial ATA Output Transmitters. These ports communicate from the XRS10L240 to upstream hosts. I Serial ATA Input Receivers. These ports receive signals from upstream hosts. CLOCK INTERFACE CMU_REFP/ CMU_REFN 46, 47 I CML AC Coupled Reference clock input XOD 43 0 Analog Crystal oscillator output XOG 44 I Analog Crystal oscillator input, 1.26V max MDIO INTERFACE SIGNALS MDC 3 I LVCMOS MDIO clock input, +3.3V LVCMOS MDIO 5 I/O LVCMOS MDIO data port, +3.3V LVCMOS. Open drain JTAG Interface Signals TCK 96 I LVCMOS JTAG test clock, +3.3V LVCMOS TDI 100 I JTAG test data in, +3.3V LVCMOS TDO 99 O JTAG test data out, +3.3V LVCMOS. Open drain. If used to daisy chain JTAG devices, pull up externally using 3.3KOhm resistor. TMS 97 I JTAG mode select, +3.3V LVCMOS TRST 1 I JTAG test reset, +3.3V LVCMOS. Pull low externally using 3.3KOhm resistor for normal operation of the device. GENERAL CONTROL AND CONFIGURATION SIGNALS (CMOS) RBIAS 49 I Analog Connection point for calibration termination resistor. RESETB 75 I LVCMOS 4 Active low reset pin, +3.3V LVCMOS. EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 1: XRS10L240 PIN DESCRIPTIONS Pin Name Pin Number I/O DESCRIPTION PWRDNB 52 I LVCMOS Active low power down signal for chip, +3.3V LVCMOS. DRACT[3:0] 71, 72, 73, 74 O LVCMOS Drive activity port for external LED. Active Low, 3.3V LVCMOS, open drain HBACT 76 O LVCMOS 0 = Host 0 selected (status) 1 = Host 1 selected (status) 0-1-0-1 Toggle (with 1 sec stay at each state) indicates no Host is selected. 3.3V LVCMOS PS_SIDEBAND_ B 77 I LVCMOS 0 = When 0 AND p_sel_mthd, (bit 0 of register 0.9A) =0, Host Port is selected by protocol based port selection. 1 = When 1 OR p_sel_mthd, (bit 0 of register 0.9A) = 1, host port is selected by p_side_mthd (bit 1 of register 0.9A) Please refer to Table 2, “Host Port Selection,” on page 6 PORTSEL 2 I LVCMOS Port selector external input pin when this mode is set in the register. Low selects host port 0, otherwise port 1. +3.3V LVCMOS TEST PIN ANTEST 51 O Analog Analog test pin CLKSTN/ CLKSTP 24, 25 O CML AC Coupled Output clock test pin RESERVED PINS PRP0/PRN0 31, 30 I Short with a 100 ohms resistor PRP1/PRN1 36, 37 I Short with a 100 ohms resistor PTP0/PTN0 28, 27 O No Connect PTP1/PTN1 39, 40 O No Connect SCANMODE 41 I LVCMOS For factory use only. connect to ground. POWER AND GROUND SIGNALS VDD 9, 18, 23, 29, 38, 54, 58, 67, 79, 83, 92, 98 I 1.2V supply. VDDA 14, 34, 45, 50, 62, 87 I 1.2V Analog supply. VSS 4, 6, 12, 15, 21, 22, 26, 32, 35, 53, 55, 61, 64, 70, 78, 80, 86, 89, 95 I Ground. VSSA 13, 33, 42, 48, 63, 88 I Analog Ground. 5 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 2: HOST PORT SELECTION HARDWARE PINS PS_SIDEBAND_ B PIN 77 REGISTER SETTINGS - REGISTER 0.009A COMMENTS PORTSEL PIN 2 P_SEL_MTHD P_SIDE_MTHD P_HOST_SEL BIT 0 BIT 1 BIT 2 0 "Selects host port 0 = Host port 0 1 = Host port 1 x 0 x Host port is selected by hardware PORTSEL pin x "Selects host port 0 = Host port 0 1 = Host port 1 1 0 x Host port is selected by hardware PORTSEL pin 0 x x 1 "Selects host port 0 = Host port 0 1 = Host port 1 "Host port is selected by register 0x0.009A bit 2 x x 1 1 "Selects host port 0 = Host port 0 1 = Host port 1 "Host port is selected by register 0x0.009A bit 2 1 x 0 x x Host port is selected by protocol based selection 6 3.3V LVCMOS EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 3.0 FUNCTIONAL DESCRIPTION A top-level view of the XRS10L240 is shown in Figure 3 outlining the interfaces to the device and the required support components. The data path can be seen at the top of the device. This includes the two output transmit and input receive paths at the top left, providing the upstream interface to the host, and the four output transmit and input receive paths at the top right, providing the downstream interface to the target devices. The clocking, control, and configuration interfaces are shown below the dotted line. FIGURE 3. XRS10L240 INTERFACES Serial ATA Upstream SIT_P/N[1:0] SOT_P/N[3:0] Serial ATA Downstream Interface to HBAs SIR_P/N[1:0] SOR_P/N[3:0] Interface to HBAs DRACT[3:0] CMU_REF_P/N Reference Clock HBACT[1:0] Control and configuration Interface XOD RESETB XOG PWRDNB TCK Crystal Oscillator I/O TDI MDC TDO1 JTAG Interface MDIO1 TMS TRST RBIAS VDDA Calibration Resistor 49.9 Ω ± 0.5% The XRS10L240 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This common building block provides a uniform implementation with common characteristics and a common register map, but provides a functional implementation of independent PHY blocks. Digital logic implementations of Serial ATA link layer blocks along with port selector and port multiplier logic provide the remainder of the data path within the XRS10L240. In addition, management and control interfaces including an MDIO interface for register control, a JTAG interface for boundary scan purposes, and a resistor calibration circuit complete the device. A block diagram of the XRS10L240 is shown in Figure 4. FIGURE 4. XRS10L240 BLOCK DIAGRAM SIR 0 SIT0 SIR 1 SIT1 SATA II 3G PH Y SATA II LINK LAYER SATA II 3G PH Y SATA II LINK LAYER SATA II 3G PH Y SOT0 SATA II LINK LAYER SATA II 3G PH Y SOT1 SATA II LINK LAYER SATA II 3G PH Y SOT2 SATA II LINK LAYER SATA II 3G PH Y SOT3 SOR 0 SOR 1 RATE ADJUST FIFO PO RT SELECTOR SOR 2 PO RT MU LTIPLIER 7 SOR 3 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 3.1 REV. 1.01 Out Of Band Feature Each Serial ATA link provides full support for the three Out Of Band (OOB) signals supported by Serial ATA: COMRESET, COMINIT and COMWAKE. These sequences must be separated by idle periods as shown in Figure 5. The sequences are comprised of 106.7ns bursts of activity that are interleaved with varying length stretches of electrical idle. This alternating sequence must be repeated four times to be recognized. FIGURE 5. COMWAKE AND COMRESET/COMINIT SEQUENCES 106.7ns COMWAKE 106.7ns COMRESET COMINIT 320ns An example OOB sequence and the resulting burst and idle widths are shown in Figure 6. If the sequence of burstWidth and idleWidth counts falls within the range specified in the MDIO registers for four consecutive burst/idle sequences, then the link will assert COMINIT or COMWAKE. This OOB signal will remain asserted for as long as the corresponding sequence on the input pins continues. FIGURE 6. EXAMPLE OOB SEQUENCE rxdP, rxdN squelchClock burstWidth idleWidth 15 15 17 15 17 COMINT = (MaxBurstWidth≥burstWidth≥MinBurstWidth) && (MaxInitWidth≥idleWidth≥MinInitWidth) COMWAKE = (MaxBurstWidth≥burstWidth≥MinBurstWidth) && (MaxWakeWidth≥idleWidth³MinWakeWidth) 8 17 EXSTOR - 1 XRS10L240 REV. 1.01 3.2 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR Power Down Modes Each Serial ATA link within the XRS10L240 features independent full support for the 3 defined Serial ATA power modes, as follows: • Active: All parts of the link are active. All power-down signals are de-asserted. • Partial: In partial mode, the input and output pipelines are shut down, but the PLL and the OOB generation circuits are active. • Slumber: In slumber mode, the PLL is also shut down, saving additional power but adding latency on exit. The XRS10L240 also provides full support for power management commands from connected hosts and devices, as outlined by the Serial ATA II port selector and port multiplier specifications. The XRS10L240 will issue a Power Management request to the active host when all devices have entered a power management mode. Also the XRS10L240 willissue Power Management requests to all connected devices when the active host has entered a power management mode. If the PhyRdy signal is not present between the active host and the XRS10L240, the XRS10L240 will power down the PHY connected to that host and squelch the four device transmitters. OOB signals will still be propagated between the host and the XRS10L240. In addition, the XRS10L240 will power down the PHY connected to its inactive host port. Power management requests from a host port, as specified by a PMREQ primitive, will propagate to all active device ports. In such a condition, the XRS10L240 will respond with a PMACK or PMNAK primitive, appropriately modify the power setting of the link with the host, and then propagate the request to each device that has PhyRdy set. The link within the XRS10L240 to each device that responds with a valid PMACK signal will be appropriately modified to reflect the new power setting. Power management requests from a device port, as specified by a PMREQ primitive, will only affect the link between that device and the XRS10L240. In such a condition, the XRS10L240 will respond with a PMACK or PMNAK primitive, and modify the link to reflect the requested power state. 3.3 Speed Negotiation The XRS10L240 will automatically perform speed negotiation with the host and devices in order to verify whether the second generation Serial ATA 3.0 Gbps data rate is available or whether the system will need to fall back upon the first generation Serial ATA 1.5 Gbps data rate. Speed negotiation is performed on an independent basis by each of the dual-channel macros. Speed negotiation is done independently on all host and device ports by default. MDIO configuration can request a common negotiated speed on the host and device ports if such a speed exists. To perform speed negotiation with a downstream device, the XRS10L240 will first perform a COMRESET/COMINIT handshake with the device and then performs a calibrate/ COMWAKE handshake. Following receipt of the device COMWAKE signal, the XRS10L240 will continually send out a D10.2 signal while awaiting receipt of the device ALIGN primitive. Depending on the speed of the ALIGN primitive, the XRS10L240 will be able to determine the PHY generation of the device, and provide the appropriate 1.5 Gbps or 3.0 Gbps ALIGN primitive in return to the device, thus completing speed negotiation. This process is outlined in Figure 7. 9 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 FIGURE 7. SERIAL ATA SPEED NEGOTIATION For speed negotiation with an upstream host, after the COMRESET/COMINIT and COMWAKE handshake is complete, the XRS10L240 will initially send out an ALIGN primitive at the 2nd generation 3.0 Gbps data rate. If no confirming 3.0 Gbps ALIGN primitive is received from the host, the XRS10L240 will then step down and attempt negotiation at the lower 1.5 Gbps data rate. Port selector Implementation 3.4 The XRS10L240 provides full support for the Serial ATA II Port Selector specification. A Serial ATA Port Selector is a mechanism that allows two different host ports to connect to the same device in order to create a redundant path to that device. Only one host connection to the device is active at a time. The two host ports are responsible for coordination of access to the XRS10L240 by one of two separate means: protocol-based port selection or sideband port selection. Each method is described in detail in the next two sections. 3.4.1 Protocol Based Port Selection Protocol-based port selection makes use of a sequence of Serial ATA OOB signals to select the active host port. The port selection signal is based on a pattern of COMRESET OOB signals transmitted from the host to the XRS10L240. The port selection signal is composed of a series of COMRESET signals with the timing from one COMRESET signal to the next as shown in Table 3 and Figure 8. The XRS10L240 selects the port, if inactive, on the de-assertion of COMRESET after receiving two complete back-to-back sequences with this defined inter-burst spacing. This can also be identified as two sequences of two COMRESET intervals comprising a total of five COMRESET bursts with four inter-burst delays. Once a port is designated as active, reception of additional COMRESET signals is propagated directly to the device, even if the COMRESET signals constitute a port selection signal. TABLE 3: PORT SELECTOR SIGNAL INTER-RESET TIMING REQUIREMENTS NOMINAL MIN. MAX UNITS T1 2.0 1.6 2.4 ms Inter-reset assertion delay for first event of the selection sequence T2 8.0 7.6 8.4 ms Inter-reset assertion delay for second event of the selection sequence 10 COMMENTS EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 FIGURE 8. PORT SELECTION SIGNAL - TRANSMITTED COMRESET SIGNALS 3.4.2 Sideband Based Port Selection The XRS10L240 also features support for a sideband port selection mechanism. This is implemented via the MDIO register settings. This feature can also be enabled using pins PS_SIDEBAND_B and PORTSEL. 3.5 Port Multiplier Implementation The XRS10L240 provides full support for the functionality outlined in the Serial ATA II Port Multiplier specification. This Port Multiplier functionality follows the Port Selector implementation, and only one link can be active at any time. A Serial ATA II Port Multiplier is a mechanism for one active host connection to communicate with multiple devices. A Port Multiplier is conceptually a simple multiplexer in which one active host connection is multiplexed to multiple device connections. The XRS10L240 uses four bits, known as the PM Port field in all Serial ATA frame types, to route frames between the selected host and the appropriate device. PM ports 0 through 3 are valid device ports within the 4output XRS10L240, while PM port 15 is designated for communication between the host and the XRS10L240 itself. For host-to-device transactions, the PM Port field is designated by the host in order to specify which device the frame is intended for. For device-to-host transactions, the XRS10L240 fills in the PM Port field with the port address of the device that is transmitting the frame. The PM Port field is defined in the Serial ATA port multiplier specification to be the first 32-bit Dword in the Frame Information Structure (FIS) for all FIS types, as shown in Figure 9. FIGURE 9. PORT SELECTION SIGNAL - TRANSMITTED COMRESET SIGNALS As defined in Serial ATA1.0 3.5.1 PM Port FIS Type Transmission from a host to a device A host indicates the target device for receipt of a transmitted frame by setting the PM Port field in the frame to the device's port address. When an XRS10L240 receives a frame as selected from one of the two available hosts by the port selector, it checks the PM Port field in the frame to determine which port address should be used. If the frame is set for transmission to the control port (15), the XRS10L240 receives the frame and performs the command or operation requested. If the frame is designated for a device port, the XRS10L240 obeys the following procedure: 1. The XRS10L240 first determines if the device port is valid. If the device port is not valid, the XRS10L240 will issue a SYNC primitive to the host and terminate reception of the frame. 2. The XRS10L240 determines if the X bit is set in the device port's PSCR[1] (SError) register. If the X bit is set, the XRS10L240 issues a SYNC primitive to the host and terminates reception of the frame. 3. The XRS10L240 determines if a collision has occurred. A collision occurs when a reception is already in progress from the device that the host wants to transmit to. If a collision has occurred, the XRS10L240 will 11 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 finish receiving the frame from the host and will then issue an R_ERR primitive to the host as the ending status. The XRS10L240 will then discard the frame, but will not return an R_RDY primitive to the host until the frame from the affected device port has been transmitted to the host, thus indicating to the host when it can retry to send the frame. The transmission from the device will proceed as requested, as the device will always take collision precedence over the host. 4. The XRS10L240 initiates a transfer with the device by issuing an X_RDY primitive to the device. A collision may occur as the XRS10L240 is issuing the X_RDY to the device if the device has started transmitting an X_RDY primitive to the XRS10L240, indicating a decision to start a transmission to the host. In this case, the XRS10L240 will finish receiving the frame from the host and then issue an R_ERR primitive to the host to indicate an unsuccessful transmission. The transmission from the device will proceed as requested, as the device will always take collision precedence over the host. 5. After the device issues an R_RDY primitive to the XRS10L240, the XRS10L240 will transmit the frame from the host to the device. The XRS10L240 will not send an R_OK status primitive to the host until the device has issued an R_OK primitive to indicate successful frame reception. In this way, the R_OK status handshake is interlocked from the device to the host. If an error is detected during any part of the frame transfer, the XRS10L240 will ensure that the error condition is propagated to the host and the device. If no error occurs during frame transfer, the XRS10L240 will not alter the contents of the frame, or modify the CRC in any way. 3.5.2 Transmission from a device to a host A device indicates a transmit to a host in the same way as would be done if the host and device were attached directly. This transaction obeys the following procedure: 1. After receiving an X_RDY primitive from the device, the XRS10L240 will determine if the X bit is set in the device port's PSCR[1] (SError) register. The XRS10L240 will not issue an R_RDY primitive to the device until this bit is cleared to zero. 2. The XRS10L240 will then receive the frame from the device. The XRS10L240 will fill in the PM Port field with the port address of the transmitting device. The XRS10L240 will then check the CRC received from the device, and if valid, it will recalculate the CRC based upon the new PM Port field. If the CRC calculated from the device is incorrect, the XRS10L240 will corrupt the CRC sent to the host to ensure propagation of the error condition 3. The XRS10L240 will issue an X_RDY primitive to the host to start the transmission of the frame to the host. After the host issues an R_RDY primitive to the XRS10L240, the frame from the device, with the updated CRC, will then be transmitted to the host. The XRS10L240 will not send an R_OK status primitive to the device until the host has issued an R_OK primitive to indicate successful frame reception. In this way, the R_OK status handshake will be interlocked from the device to the host. If an error is detected during any part of the frame transfer, the XRS10L240 will ensure that the error condition is propagated to the host and the device. 12 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 Clocking 3.6 The XRS10L240 allows the use of either an external reference clock or of a low cost crystal oscillator to act as a reference clock. Separate device inputs are available for each approach, with full rate reference clock inputs provided on pins CMU_REFP and CMU_REFN, and crystal oscillator inputs provided on pins XOD and XOG. Supported data rates and their appropriate PLL divide factors are outlined in Table 4. TABLE 4: PLL DIVIDE FACTORS MODE SYSCLK /REF /FB DINCLK RXCLK SERIAL CLOCK DATA RATE SATA Gen. 2 25MHz 1 60 300MHz 1.5GHz 3.0Gbps SATA Gen. 2 50MHz 1 30 300MHz 1.5GHz 3.0Gbps SATA Gen. 2 75MHz 1 20 300MHz 1.5GHz 3.0Gbps SATA Gen. 2 100MHz 2 30 300MHz 1.5GHz 3.0Gbps SATA Gen. 2 150MHz 1 10 300MHz 1.5GHz 3.0Gbps NOTE: * All link start with 3.0Gbps, then negotiate down to 1.5Gbps for SATA Generation 1 devices. 3.6.1 Spread Spectrum Clocking The XRS10L240 provides full support for receipt and generation of signals that have been configured for Spread Spectrum Clocking (SSC) support. The spread technique is implemented by down-spreading the data rate by 0.5% as a means of reducing EMI. Generation of the down-spread clock is performed within the XRS10L240. An example of the resultant spectral fundamental frequency before and after SSC can be seen in Figure 10. FIGURE 10. SPREAD SPECTRUM CLOCKING 13 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 3.7 REV. 1.01 Test and Loopback Modes The XRS10L240 provides for loopback testing on both the host and device interfaces, and incorporates a number of internal testing features, as outlined in the following subsections. 3.7.1 Host Side Loopback Modes The XRS10L240 supports two forms of host loopback modes: a shallow serial loopback implemented within the host PHY macro, or a deep parallel loopback implemented within the device PHY macros after the port selector and port multiplier functionality. SHALLOW HOST LOOPBACK MODE The shallow host loopback mode is shown in Figure 11. In this mode, the incoming data stream from the host and embedded clock are recovered by an internal CDR, and the deserialized data is retransmitted serially back to the host, as clocked by the recovered clock. In this implementation, the received data is still transmitted to the internal port selector block and will propagate through to the device side output pins. FIGURE 11. SHALLOW HOST LOOPBACK MODE DEEP HOST LOOPBACK MODE The deep host loopback mode is shown in Figure 12. In this mode, the incoming data stream from the host is transmitted through the digital blocks within the XRS10L240, and the loopback path is implemented at the device-side Serial ATA PHY block. Note that once again, the looped back data is still transmitted on the deviceside output pins. The deep host loopback mode is enabled by using the Parallel Loopback registers for the downstream PHYs in Device 2 or 3. This received data must be in the form of valid SATA frames for a deep loopback to be successful. FIGURE 12. DEEP HOST LOOPBACK MODE 14 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 3.7.2 Device Side Loopback Modes The XRS10L240 supports two forms of device-side loopback modes: a shallow serial loopback implemented within the device-side PHY macros, or a deep parallel loopback implemented within the host PHY macro after the port selector and port multiplier functionality. SHALLOW DEVICE LOOPBACK MODE The shallow device loopback mode is shown in Figure 13. In this mode, the incoming data stream from the device and embedded clock are recovered by an internal CDR, and the deserialized data is retransmitted serially back to the designated device, as clocked by the recovered clock. In this implementation, the received data is still transmitted to the internal port multiplier block. FIGURE 13. SHALLOW DEVICE LOOPBACK MODE DEEP DEVICE LOOPBACK MODE The deep device loopback mode is shown in Figure 14. In this mode, the incoming data stream from the device is transmitted through the digital blocks within the XRS10L240, and the loopback path is implemented at the host-side Serial ATA PHY block. Note that once again, the looped back data is still transmitted on the host-side output pins. FIGURE 14. DEEP DEVICE LOOPBACK MODE 3.7.3 PRBS Testers Each Serial ATA link within the XRS10L240 device has the independent ability to generate pseudo random bit sequences (PRBS) on their Tx pins, and to check them on the Rx pins, thus implementing a built-in self test (BIST) feature. This capability is enabled and disabled on an independent basis on a link-by-link basis through the Transmit_Test and Receive_Test registers (N.0000 and N.0020) outlined in Table 11. PRBS PATTERNS of 2^10-1 and 2^31-1 are available. 15 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 4.0 REV. 1.01 ELECTRICAL SPECIFICATIONS This section contains the electrical specifications for the XRS10L240. 4.1 Serial ATA Specifications The XRS10L240 electrical transmit and receive specifications are outlined in this section. The XRS10L240 is fully compliant to the Serial ATA II specification for Gen2i, Gen2x, Gen2m, Gen1i, Gen1x and Gen1m variations at 3.0 and 1.5 Gbps. 4.1.1 Serial ATA Transmitter A simplified version of the output circuit and test fixture for each of the 6 Serial ATA transmit outputs on the XRS10L240 is shown in Figure 15. The output differential pair is terminated to the supply VDD. The circuit is designed to be AC coupled. FIGURE 15. SERIAL ATA EQUIVALENT OUTPUT CIRCUIT The XRS10L240 Serial ATA outputs include a simple one-tap equalizer, that is useful in driving longer printed circuit traces and is a required component in second generation Serial ATA PHYs. This equalizer preemphasizes the output signal whenever there is a data transition. The amount of pre-emphasis can vary between 0 and 45.5%, and is configured via MDIO register settings. Note that pre-emphasis doesn't increase the overall swing, but instead reduces the output amplitude when there is no transition. 16 EXSTOR - 1 XRS10L240 REV. 1.01 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR FIGURE 16. EFFECTS OF TRANSMIT PRE-EMPHASIS The overall swing level can also be modified via MDIO register settings. The XRS10L240 transmit mask is shown in Figure 17. FIGURE 17. TRANSMIT EYE MASK FOR SERIAL ATA OUTPUT 17 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 4.1.2 REV. 1.01 Serial ATA Receiver An equivalent circuit for the XRS10L240 Serial ATA inputs is shown in Figure 18. The device receiver mask is shown in Figure 19. This circuit is designed to be AC coupled. The termination resistors are not connected during power-up FIGURE 18. SERIAL ATA EQUIVALENT INPUT CIRCUIT FIGURE 19. RECEIVE EYE MASK FOR SERIAL ATA INPUT 18 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 5: SERIAL ATA LINK SPECIFICATIONS NAME MIN. NOM MAX UNITS Bit Time 670 - 333 ps JXR1 Input Jitter Tolerance Mask at signal crossover 0.32 - - UI JXR1,DJ Deterministic jitter tolerance at signal crossover 0.18 - - UI Output jitter mask at signal crossover - - 0.15 UI Deterministic output jitter at signal crossover - - 0.07 UI Input signal rise/fall times (20% - 80%) 0.2 - 0.46 UI tQR/tQF Output signal rise/fall times (20% - 80%) 0.2 - 0.41 UI tTOL,RX1 RX to sysclock frequency offset tolerance -5350 0 350 ppm Input swing, differential peak-peak 175 - 1600 mV Output swing, differential peak-peak 800 - 1200 mV VIN,IDLE No swing detection threshold 65 120 155 mV RIN,DIFF Differential mode input resistance 85 100 115 Ω RIN,CM3 Common mode input resistance 40 50 60 Ω RIN,OFF Common mode input resistance, no power 200 - - kΩ RIN,XS Output termination resistance 40 50 60 Ω S11,IN,DIFF Differential input return loss, 50MHz - 1.5GHz 12 - - dB S11,IN,CM Common mode input return loss 50MHz-1.5GHz 6 - - dB S22,OUT,DIFF Differential output return loss 50MHz-1.5GHz 12 - - dB S22,OUT,CM 6 - - dB tBIT,XS JXT1 JXT1,DJ tR/tF VIN VSW2 DESCRIPTION Common mode output return loss 50MHz-1.5GHz tS,REG Setup time for register port 1.5 - - ns tH,REG Hold time for register port 1.5 - - ns tQ,REG Clock to Q time for register port 0 - 2 ns tCYC,REG Register port clock cycle time 10 - - ns tHI,REG R register port clock high time 4 - - ns tLO,REG Register port clock low time 4 - - ns tRF,REG Register port input rise/fall time - - 0.5 ns NOTES: 1. This value includes 0.5% downspread Spread Spectrum clocking, plus 350ppm tolerance around the center frequency. 2. This is measured at the package ball and does not include any board or connector loss. 3. This value can be as low as 5Ω during power on. 19 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR 4.2 REV. 1.01 CMOS Interface AC and DC specifications for the CMOS inputs and outputs are listed in Table 6. Since all these signals are asynchronous, there are no setup or hold times defined. The CMOS pins are defined in the General Control and Configuration portion of Table 1 in Section 3, "Pin Descriptions". TABLE 6: CMOS I/O SPECIFICATIONS NAME tDR/tDF,CMOS DESCRIPTION CMOS input signal rise/fall times (20% - 80%) tQR/tQF,CMOS1 CMOS output signal rise/fall times (20% - 80%) MIN NOM MAX UNITS 0.2 - 5 ns 0.2 - 5 ns VIL,CMOS CMOS input low voltage -0.3 0 0.8 V VIH,CMOS CMOS input high voltage 1.7 3.3 3.6 V VOL,CMOS CMOS output low voltage -0.3 0 0.4 V VPULLUP Open Drain Pull-up Voltage 2.3 - 3.6 V IOL,CMOS Output current for VOL = 0.4V 10 - 20 mA dIOL/dt,CMOS Output current rate of change -10 - 10 mA/ns LI,CMOS CMOS I/O inductance - - 8 nH CI,CMOS CMOS I/O capacitance - - 5 pF 150 uA ILEAKAGE2 CMOS I/O Leakage Current NOTE: .1. This value is measured driving a load of 20pF. NOTE: .2. This values is measured at 2.5 VDC. 4.3 MDIO Interface The Management Data Input/Output (MDIO) port complies with Clause 45 of the IEEE 802.3ae specification. A representative MDIO driver/receiver is shown in Figure 20. MDIO uses an open drain driver with a pullup resistor. 20 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 FIGURE 20. REPRESENTATIVE MDIO CIRCUIT 2.5V/3.3V Pin To other MDIO Devices Open Drain Driver Representative MDIO Read and Write waveforms are shown in Figure 21. The XRS10L240 samples MDIO on the rising edge of MDC for input and drives MDIO after the rising edge of MDC for output. Note that setup, hold, and output timings are defined from the maximum vIL and minimum VIH levels. FIGURE 21. MDIO INPUT AND OUTPUT WAVEFORMS Values for MDIO parameters are shown in Table 7 21 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 7: MDIO DC AND AC CHARACTERISTICS NAME DESCRIPTION MIN NOM MAX UNITS tCYCLE,MDIO MDC cycle time 400 - - ns tLOW,MDC MDC low time 160 - - ns tHIGH,MDC MDC high time 160 - - ns tS,MDIO1 MDIO input to MDC setup time 10 - - ns tH,MDIO2 MDC to MDIO input hold time 10 - - ns tQ,MDIO3 MDC to MDIO output time 0 - 150 ns tDR/tDF,MDIO MDIO input signal rise/fall times (20% - 80%) 0.2 - 100 ns tQR/tQF,MDIO4 MDIO output signal rise/fall times (20% - 80%) 0.2 - 80 ns VIL,MDIO MDIO input low voltage -0.3 0 0.8 V VIH,MDIO MDIO input high voltage 1.7 3.3 3.6 V VOL,MDIO4 MDIO output low voltage -0.3 0 0.4 V VPULLUP Open Drain Pull-up Voltage 2.3 - 3.6 V IOL,MDIO MDIO Output current for VOL = 0.4V 10 - 20 mA dIOL/dt,MDIO MDIO Output current rate of change -10 - 10 mA/ns LI,MDIO MDIO input inductance - - 8 nH CI,MDIO MDIO input capacitance - - 5 pF NOTES: 1. Measured from minimum MDIO VIH to maximum MDC VIL for MDIO rising edge. 2. Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge. Measured from maximum MDIO VIL to maximum MDC VIL for MDIO falling edge. Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge. 3. Measured from minimum MDC VIH to maximum MDIO VIL for MDIO rising edge and MDC rising edge. 4. Measured from minimum MDC VIH to minimum MDIO VIH for MDIO falling edge and MDC rising edge. Measured from maximum MDC VIL to maximum MDIO VIL for MDIO rising edge and MDC falling edge. Measured from maximum MDC VIL to minimum MDIO VIH for MDIO falling edge and MDC falling edge. Measured driving a load of 470pF. TABLE 8: OPERATING CONDITIONS Name Min Nom Max Units Ambient temperature under bias -40 25 85 °C VDD Core power supply voltage 1.14 1.2 1.26 V IDD Core power supply current - 650 800 mA TA Description 22 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 8: OPERATING CONDITIONS Name Description Min Nom Max Units VESD Electrostatic discharge tolerance, Human Body Model All Non-High-Speed I/O Pins 1600 V VESD Electrostatic discharge tolerance, Human Body Model All High-Speed I/O Pins 2000 V θJA Junction-to-ambient thermal resistance 38.5 23 0 C/W EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 5.0 REGISTERS DESCRIPTION The XRS10L240 provides a variety of registers for the purpose of device configuration, testing and monitoring. These registers are accessed through the MDIO interface, outlined in “Section 4.3, MDIO Interface” on page 20. The entire register set is described in this section. 5.1 Register Overview The XRS10L240 port address is hardwired to 0; this field should be set to 0 in all packets.The XRS10L240 contains three identical instantiations of a dual Serial ATA PHY macro. A common set of registers exists within each of these macros, and are outlined in “Section 5.2, Macro Registers” on page 25. MDIO device designations 1-3 are used for each of these three macros as shown in Table 9. Registers relating to the XRS10L240 as a whole are outlined in “Section 5.3, XRS10L240 Device Generic Registers” on page 38 and make use of MDIO device 0. TABLE 9: MDIO DEVICE DESIGNATIONS MDIO DEVICE DESIGNATION MACRO RELEVANT PINS 0 XRS10L240 Device Generic Registers N/A 1 Serial ATA Input Macro SI0, SI1 2 Serial ATA Output Macro 0 SO0, SO1 3 Serial ATA Output Macro 1 SO2, SO3 The XRS10L240 registers are arranged as 8-bit fields with 8-bit addresses. These are mapped into the 16-bit MDIO address and data fields by setting the most significant byte of each to be 0. An example mapping from a macro address/data combination to an MDIO address & data combination is shown in Table 10. TABLE 10: MDIO ADDRESSING MACRO ADDRESS MACRO DATA MDIO ADDRESS MDIO DATA 0x40 abcde 0x0040 00000000000abcde NOTE: The unused upper 3 bits in FBDIV are also set to 0 during MDIO writes and are undefined during MDIO reads. In the description of each register field, there is an entry describing its read/write status. This may fall into one of the following categories: • R/W- register field is read/write • RO - register field is read only • LL - Latching Low - Used with bits that monitor some state internal to the XRS10L240. When the condition for the bit to go low is reached, the bit stays low until the next time it is read. Once it is read, its value reverts to the cur-rent state of the condition it monitors. • LH - Latching High - When the condition for the bit to go high is reached, the bit stays high until the next time it is read. Once it is read, its value reverts to the current state of the condition it monitors. • SC - When an SC bit is set, some action is initiated; once the action is complete, the bit is cleared. 24 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 5.2 Macro Registers The registers outlined in this section are common to each of the three Serial ATA dual PHY macros as described in the previous section. As such, each listed register is present in each of the 1, 2, and 3 MDIO register spaces, and will perform the stated function on the specified Serial ATA lane. The registers within each dual PHY macro are split into three sections: Transmit/Receive lane 0 registers: Address range 000***** Transmit/Receive lane 1 registers: Address range 001***** PLL registers: Address range 010***** Bias generator registers: Address range 011***** TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX N.0000 N.0020 BIT(S) NAME R/W DEFAULT 7 Transmit_TestLbit R/W 0 Test Pattern LONE bit Control 0 = Use input data from DATAIN 1 = Generate LONE bit pattern (1000010000). 6 SATAPCIEXB_G1 R/W 0 Tx output swing booster bit (Gen 1) 0 = boost swing by 15% 1 = nominal swing 5:4 5:4 Receive_Test0[1:0] Receive_Test1[1:0] R/W 00 PRBS checker control 00 = disable PRBS checkers 01 = enable 2^10-1 checker 10 = Reserved 11 = enable 2^31-1 checkers 3:2 3:2 Transmit_Test0[1:0] Transmit_Test1[1:0] R/W 00 Test Pattern Control 00 = Use input data from DATAIN 01 = Generate 2^10-1 PRBS 10 = Generate 1010 Pattern 11 = Generate 2^31-1 PRBS 1 selFourFive R/W 1 0 = Output data is x8 1 = Output data is x10 0 SATAPCIEXB_G2 R/W 0 Tx output swing booster bit (Gen 2) 0 = boost swing by 15% 1 = nominal swing 25 DESCRPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME R/W DEFAULT N.0001 N.0021 7:3 7:3 RiseFall_Coef0[4:0] RiseFall_Coef1[4:0] R/W 00000 2:0 Transmit_Eq0[2:0] Transmit_Eq1[2:0] R/W 011 Transmit equalization control 000 = 0% transmit preemphasis 001 = 6.5% transmit preemphasis 010 = 13% transmit preemphasis 011 = 19.5% transmit preemphasis 100 = 26% transmit preemphasis 101 = 32.5% transmit preemphasis 110 = 39% transmit preemphasis 111 = 45.5% transmit preemphasis 7:6 7:6 mscProg0[1:0] mscProg1[1:0] RW 01 Receive equalization control – boost at 1.5GHz 5:3 5:3 Beacon_Swing0[2:0] Beacon_Swing1[2:0] R/W 100 Transmit swing size for OOB Signals 000 = 800mV 001 = 700mV 010 = 600mV 011 = 500mV 100 = 400mV 101 = 300mV 110 = 200mV 111 = 0mV 2:0 2:0 Output_Swing0[2:0] Output_Swing1[2:0] R/W 100 Transmit swing size in normal operation 000 = 800mV 001 = 700mV 010 = 600mV 011 = 500mV 100 = 400mV 101 = 300mV 110 =200mV 111 = 0mV 7 enEqB R/W 0 6:4 noSigLevel0[2:0] noSigLevel1[2:0] RW 001 Nominal threshold for no signal detect 3:0 hpProgOvrd0[3:0] hpProgOvrd1[3:0] RW 0000 High pole programming override value N.0002 N.0022 N.0003 N.0023 26 DESCRPTION Output rise/fall time coefficient (Gen 2) 00000 = +0ps 11111 = +25ps other = increases rise/fall times monotonically between 0 and 25ps Enable receive equalization 0 = enable equalization 1 = disable equalization EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME R/W DEFAULT N.0004 N.0024 7:0 7:0 xCDROffs_F0[7:0] xCDROffs_F1[7:0] RW 0x40 2’s complement offset for Clock data recovery Offset = CDRoff*tbit/128 Value of xCDROffs0/1 when DIV2CLK=0 N.0005 N.0025 7:0 7:0 Rx_Offset0 Rx_Offset1 R/W 80h 2's complement offset for Clock data recovery Offset = CDRoff*tbit/256 Value of xCDROffs0/1 when DIV2CLK=1 N.0006 N.0026 7 xCDRmetamode RW 0 Selection of clock to use on FSM 6 xCDRrndT RW 1 Randomizes tie breaker 5 xCDRclkmode RW 0 selects clock to use for FSM 4 xCDRrotate RW 0 Enables CDR rotation 3:0 xCDRinc0[3:0] xCDRinc1[3:0] RW 0x2 7:6 Reserved RO 0 5 xCDRupdnsw RW 0 4:0 xCDRincF0[4:0] xCDRincF1[4:0] RW 00010 7 sel_extCDRenF RW 1 0 = 2nd order CDR selected from register 1 = 2nd order CDR selected from outside of eMacro 6 xCDRenF 1 CDR frequency tracking loop enable 5 xCDRmisc R/W 0 4:0 xCDRlimHF0[4:0] xCDRlimHF1[4:0] RW 00111 7 Reserved RO - Reserved 6 xCDRmult2F_F RW 0 Value of xCDRmult2F when DIV2CLK=0 5 xCDRmult2F_H RW 1 Value of xCDRmult2F when DIV2CLK=1 4:0 xCDRlimLF0[4:0] xCDRlimLF1[4:0] RW 0x18 N.000A N.002A 7:6 Reserved RO - 5:0 MinBurstWidth0[5:0] MinBurstWidth1[5:0] R/W N.000B N.002B 7:6 Reserved RO 5:0 MaxBurstWidth0[5:0] MaxBurstWidth1[5:0] R/W N.000C N.002C 7:6 Reserved RO 5:0 5:0 MinInitWidth0[5:0] MinInitWidth1[5:0] RW N.0007 N.0027 N.0008 N.0028 N.0009 N.0029 DESCRPTION Increment for CDR Direction of count on FSM Fast increment size for CDR Reserved 000100 Lower bound count of activity burst for COM FSM - Reserved 000111 Upper bound count of activity burst for COM FSM - Reserved 001100 Lower bound count of idle for COMINIT/COMRESET 27 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME R/W DEFAULT N.000D N.002D 7:6 7:6 Reserved RO - 5:0 5:0 MaxWakeWidth0 MaxWakeWidth1 RW N.000E N.002E 7:6 Reserved RO 5:0 MinWakeWidth0[5:0] MinWakeWidth1[5:0] RW N.000F N.002F 7:6 Reserved RO 5:0 MaxWakeWidth0[5:0] MaxWakeWidth1[5:0] N.0010 N.0030 7:6 Reserved RO - 5:3 rcvRef0[2:0] rcvRef1[2:0] RW 011 Percent of full swing that TX must reach during Receiver Detect to count as receiver present (not applicable to SATA PHY macros) 2:0 squelchdivsel[2:0] 000 Value by which to divide squelch clock 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 6 100 = divide by 8 101 = divide by 10 110 = divide by 12 111 = divide by 14 N.0011 7:0 Reserved R0 0x00 Reserved N.0012 7:5 rcvdetdelayo[10:8] RW 0x04 Reserved 4:0 Reserved RO - Reserved 7:0 rcvdetdelay1[7:0] (lower 8 bits) RO 0x00 N.0031 DESCRPTION Reserved 010110 Upper bound count of idle for COMINIT/COMRESET - Reserved 000100 Lower bound count of idle for COMWAKE - Reserved 000111 Upper bound count of idle for COMWAKE Reserved Number of SYSCLK cycles to wait between assertion of RECDET and clocking comparato NOTE: Not applicable to SATA PHY. N.0032 7:3 Reserved RO - 2:0 rcvdetdelayo[10:8] (upper 3 bits) RO 0x04 Reserved Number of SYSCLK cycles to wait between assertion of RECDET and clocking comparator for receiver detect (not applicable to SATA PHY macros) NOTE: Not applicable to SATA PHY. 28 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX N.0013 N.0033 N.0014 N.0034 N.0015 N.0035 N.0017 N.0016 N.0037 N.0036 BIT(S) NAME R/W DEFAULT 7 orxpclkflip RW 1 Invert outgoing rxpclk for external use 6 irxpclkflip RW 1 Invert incoming rxpclk for internal use 5 rxpclkflip RW 0 line loopback fifo rxpclk flip 4 otxpclkflip RW 0 Invert outgoing txpclk for external use 3 itxpclkflip RW 0 Invert incoming txpclk for internal use 2:0 clkTestSel0[2:0] clkTestSel1[2:0] RW 000 7:6 Reserved RO - 5:3 nidleCmin[2:0] RW 011 2:0 nburstCmin[2:0] RW 0100 7 Reserved RO - 6:4 sysclk25divsel0[2:0] sysclk25divsel1[2:0] RW 000 Divider selection for sysclk-> sysclk25 000 = divide by 1 (sysclk is 25MHz) 001 = divide by 2 (sysclk is 50MHz) 010 = divide by 3 (sysclk is 75MHz) 011 = divide by 4 (sysclk is 100MHz) 100 = divide by 5 (sysclk is 125MHz) 101 = divide by 6 (sysclk is 150MHz) 110 = divide by 10 (sysclk is 250MHz) 111 = divide by 12 (sysclk is 300MHz) 3:0 comburstnum[3:0] RW 0x05 number of bursts in com* sequence 7:0 wec0[15:0] wec1[15:0] RO - 29 DESCRPTION Selection for clock onto clockTest pin 000 = disable 001 = txpclk[0] 010 = rxclk[0] 011 = sysclk 100 = SSCtrig other = reserved Only clkTestSel0 is active; clkTestSel1 is a noconnect Reserved Number of idles required before declaring a COM* match Number of bursts required before declaring a COM* match Reserved PRBS error count Upper byte write clears both upper and lower bytes EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 11: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX N.0018 N.0038 BIT(S) NAME R/W DEFAULT 7:6 Reserved RO - 5:3 txbiasbuffselb0[2:0] txbiasbuffselb1[2:0] RW 100 DESCRPTION Reserved Tx Pre-driver swing size for async beacon 000 = 800mV 001 = 700mV 010 = 600mV 011 = 500mV 100 = 400mV 101 = 300mV 110 = 200mV 111 = 0mV NOTE: This feature is not used for SATA N.0019 N.0039 2:0 txbiasbuffsela0[2:0] txbiasbuffsela1[2:0] RW 100 7 Reserved RO - Reserved 6 enComPulseDet RW 0 0 = Detect COM outputs by level 1 = Revert to detection of COM output by pulse 5 widerCW RW 0 0 = selects normal COMWAKE width detection 1 = Selects detection of wider COMWAKE (for debugging purposes only) 4:0 rcSelH0[4:0] rcSelH1[4:0] RW 111111 30 Tx Predriver swing size in normal operation 000 = 800mV 001 = 700mV 010 = 600mV 011 = 500mV 100 = 400mV (sata default) 101 = 300mV Output rise/fall time coefficient (Gen 1) 00000 = +0ps 11111 = +25ps Other code increases rise/fall times monotonically between 0 and 25ps EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 The Rx_offset registers change the sampling point of the data relative to the bit boundary. The offset value is stored in two's complement format, with bit 0 being the LSB. The step size is a fraction of the bit time; it is constant across process and operating conditions but changes with the operating frequency. The eye diagram in Figure 15 shows graphically the effect of changing the register value. FIGURE 22. EFFECT OF SETTING RECEIVE OFFSET REGISTER Data Eye 64 (0x40) 31 32 (0x20)0 0 (0x00) -32 (0xE0) -64 (0xC0) Register Value EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 12: PLL CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME TYPE DEFAULT N.0040 7:6 Reserved RO - 5:0 FBDIV[5:0] RW 101101 7:6 Reserved RO - 5:0 REFDIV[5:0] RW 010000 7:6 Reserved RO - 5:0 SSCInc RW 0x01 7:6 Reserved RO - 5:0 SSCIncIntrv RW 01100 7:6 Reserved RO - 5:0 SSCMax RW 00000 N.0041 N.0042 N.0043 N.0044 32 DESCRIPTION Reserved Divide value for feedback clock 110000 = divide by 5 100000 = divide by 10 100001 = divide by 15 100010 = divide by 20 100011 = divide by 25 100101 = divide by 30 100111 = divide by 50 101101 = divide by 60 (default for 25MHz Ref)) Other - reserved Reserved Divide values for system clock 010000 = divide by 1 (default for 25MHz Ref)) 000000 = divide by 2 000001 = divide by 3 000010 = divide by 4 000011 = divide by 5 000101 = divide by 6 000110 = divide by 8 000111 = divide by 10 001101 = divide by 12 001110 = divide by 16 001111 = divide by 20 Others - reserved Reserved Step size for SSC increment Reserved Interval between steps for SSC increment Reserved Maximum value for spread (set to 51, [0x33h] when SSC is set to "0") EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 12: PLL CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME TYPE DEFAULT N.0045 7:5 Reserved RO - Reserved 4 SSCmode R/W 0 Selects position of spreading interpolator 0 = Interpolator in feedback path 1 = Interpolator in feedforward path 3 SSCCenter R/W 0 Center spread instead of down/upspread 2 SSCInvert R/W 0 Spread up instead of down 1 SSCPDMBypass R/W 0 Do not use the pulse density modulator 0 SSCBypass R/W 1 Bypass the saw generator and pulse density modulator and get increment from SSCMax (set SSCMax to 51 when SSCBypass is set to 0) 7 PLLQpumpOvrd RW 0 Override for charge pump programmability 0 = use value based on FB divider 1 = use value from PLLQpump N.0046 DESCRIPTION Values based on FB divider: FBDIV[5:0] qpump[6:0] 11XXXX => 1111110 100000 => 0001110 100001 => 0000110 100010 => 0000011 100011 => 0000010 100101 => 0000010 100111 => 0000001 101101 => 0000001 Others => 0000000 6:0 PLLQpump[6:0] R/W R/O 0000011 Charge Pump Programmability 0000001 0000001 = Enable 1 charge pump unit 0000010 = Enable 2 charge pump units 0000011 = Enable 3 charge pump units 0000110 = Enable 4 charge pump units 0000111 = Enable 5 charge pump units 0001110 = Enable 6 charge pump units 0001111 = Enable 7 charge pump units 0011110 = Enable 8 charge pump units 0011111 = Enable 9 charge pump units 0111110 = Enable 10 charge pump units 0111111 = Enable 11 charge pump units NOTE: 33 PLLQpump can be both R/W and R/O depending on the value of PLLQpumpOvrd. On power up the default is RO and the actual value read will be 0000001 (based >on the FBDIV default). EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 12: PLL CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME TYPE DEFAULT N.0047 7:3 Reserved RO - Reserved 2 tdccovrd RW 0 1 = use tdccen bits to activate/disable transmit duty cycle correction ports 0 = use pwrdnTxB bits to activate/disable transmit duty cycle correction ports 1:0 tdccen[1:0] RW 00 When tdccovrd is asserted, tdccen[N] enables/disables duty cycle correction from transmit lane N. 1 = enable duty cycle correction from lane N 0 = disable duty cycle correction from lane N 7:1 Reserved RO - Reserved 0 pllClkDiv5en RW 1 1 = enable pllclkDiv5 0 = disable pllClkDiv5 N.0048 DESCRIPTION TABLE 13: BIAS GENERATOR CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME TYPE RESET VALUE N.0064 7:4 pr100Tx[3:0] RW 0x0 Transmit r bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA 3:0 pr100squelch[3:0] RW 0x0 Squelch 100u r bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA 34 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 13: BIAS GENERATOR CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME TYPE RESET VALUE N.0065 7:6 prcal50spare0[1:0] RW 00 50u spare rcal bias 0 00 = 50uA 01 = 75uA 10 = 25uA 11 = 100uA 5:4 prcal50DCCTx[1:0] RW 00 Transmit rcal bias 00 = 50uA 01 = 75uA 10 = 25uA 11 = 100uA 3:0 prcal100Tx[3:0] RW 0x0 Transmit rcal bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA 7:2 Reserved RO - 1:0 prcal50spare1[1:0] RW 00 50u spare rcal bias 0 00 = 50uA 01 = 75uA 10 = 25uA 11 = 100uA 7:4 pr100ext1[3:0] RW 0x0 100u external bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA 3:0 pr100ext0[3:0] RW 0x0 100u external bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA N.0066 N.0067 35 DESCRIPTION Reserved EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 13: BIAS GENERATOR CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1, 2, 3) ADDRESS HEX BIT(S) NAME TYPE RESET VALUE N.0068 7:4 Reserved RO - 3:0 prcal100pciPreamp [3:0] RW 0x0 DESCRIPTION Reserved 100u external bias 1010=50uA 0010=75uA 0000=100uA 0001=125uA 1100=150uA 0111=175uA 1111=200uA TABLE 14: POWERDOWN REGISTERS (MDIO DEVICES 1, 2 & 3) ADDRESS HEX 1.0080 2.0080 3.0080 1.0081 2.0081 3.0081 BIT(S) NAME TYPE RESET VALUE DESCRIPTION 7:6 SIpwrdnDetB[1:0] SO01pwrdnDetB[1:0] SO23pwrdnDetB[1:0] RW 11 Powers down the signal detector and COM* circuits 1 = normal operation 0 = power down 5:4 SIpwrdnRxB[1:0] SO01pwrdnRxB[1:0] SO23pwrdnRxB[1:0] RW 11 Powers down the receivers and CDR 1 = normal operation 0 = power down 3:2 SIpwrdnTxDrvB[1:0] SO01pwrdnTxDrvB[1:0] SO23pwrdnTxDrvB[1:0] RW 11 Powers down the transmitter 1 = normal operation 0 = power down 1:0 SIpwrdnTxB[1:0] SO01pwrdnTxB[1:0] SO23pwrdnTxB[1:0] RW 11 Powers down the transmit pipes and clock 1 = normal operation 0 = power down 7:2 Reserved RO - Reserved 1 SIpwrdnBiasGen SO01pwrdnBiasGen SO23pwrdnBiasGen RW 0 Powers down the bandgap. 1 = power down 0 = normal operation 0 SIpwrdnPLLB SO01pwrdnPLLB SO23pwrdnPLLB RW 1 Powers down the PLL 1 = normal operation 0 = power down 36 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 15: BLOCK CONTROL SIGNALS (MDIO DEVICES 1, 2&3) ADDRESS HEX BIT(S) NAME TYPE RESET VALUE 7:4 Reserved RO - 3:2 SIselLpbk[1:0] SO01selLpbk[1:0] SO23selLpbk[1:0] RW 00 Serial Loopback Control 1 = Enable Serial Loopback 0 = Normal operation 1:0 SIparLpbk[1:0] SO01parLpbk[1:0] SO23parLpbk[1:0] RW 00 Parallel Loopback Control 1 = Enable Parallel Loopback 0 = Normal operation 7:6 SISendBeacon[1:0] SO01SendBeacon[1:0] SO23SendBeacon[1:0] PSendBeacon[1:0] RW 00 Causes beacon signal to be sent on link 5:4 SItxsigsel1[1:0] SO01txsigsel1[1:0] SO23txsigsel1[1:0] RW 00 Transmitter 1 source selection 00 = transmit data 01 = transmit internally generated beacon 10 = transmit externally generated beacon 11 = transmit idle/COM* 3:2 SItxsigsel0[1:0] SO01txsigsel0[1:0] SO23txsigsel0[1:0] RW 00 Transmitter 0 source selection 00 = transmit data 01 = transmit internally generated beacon 10 = transmit externally generated beacon 11 = transmit idle/COM* 1:0 SIsysClkEn[1:0] SO01sysClkEn[1:0] SO23sysClkEn[1:0] RW 00 Source of txPClk[1:0] SItxsigsel0[1:0] SO01txsigsel0[1:0] 1.0084 2.0084 3.0084 7:2 Reserved RO - 1:0 SIrcvDet[1:0] SO01rcvDet[1:0] SO23rcvDet[1:0] RW/SC 00 1.0085 2.0085 3.0085 7:2 Reserved RO - 1:0 SIDIV2CLK[1:0] SO01DIV2CLK[1:0] SO23DIV2CLK[1:0] RW 00 1.0082 2.0082 3.0082. 1.0083 2.0083 3.0083 37 DESCRIPTION Reserved Reserved Starts receiver detect cycle. Self clearing Reserved Divide reference clock by 2 for corresponding lane EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 15: BLOCK CONTROL SIGNALS (MDIO DEVICES 1, 2&3) ADDRESS HEX 1.0086 2.0086 3.0086 1.0087 2.0087 3.0087 1.0088 2.0088 3.0088 5.3 BIT(S) NAME TYPE RESET VALUE DESCRIPTION 7:6 Reserved RO - 5:4 SIforceidle[1:0] SO01forceidle[1:0] SO23forceidle[1:0] RW 00 Generate forceidle signal to lane 3:2 SIcomtype[1:0] SO01comtype[1:0] SO23comtype[1:0] RW 00 Type of COM sequence to generate when Comstart is asserted 1 = generate WAKE 0 = generate INIT 1:0 SIcomstart[1:0] SO01comstart[1:0] SO23comstart[1:0] RW/SC 00 Comstart signal. Self clearing 7:6 SIcomfinish[1:0] SO01comfinish[1:0] SO23comfinish[1:0] RO/LH 00 Signal generation initiated by comtype has finished 5:4 SIsigValid[1:0] SO01sigValid[1:0] SO23sigValid[1:0] RO/LH 00 Valid signal received on lane 3:2 SICOMWAKE[1:0] SO01COMWAKE[1:0] SO23COMWAKE[1:0] RO/LH 00 COMWAKE Sequence received on lane 1:0 SICOMINIT[1:0] SO01COMINIT[1:0] SO23COMINIT[1:0] RO/LH 00 COMINIT Sequence received on lane 7:6 Reserved RO - 5:4 SIRXErr[1:0] SO01RXErr[1:0] SO23RXErr[1:0] RO/LH 00 PRBS error on lane. Self clearing 3:2 SIrcvAbsent[1:0] SO01rcvAbsent[1:0] SO23rcvAbsent[1:0] RO/LH 00 No Receiver present on lane 1:0 SIrcvPresent[1:0] SO01rcvPresent[1:0] SO23rcvPresent[1:0] RO/LH 00 Receiver detected on lane Reserved Reserved XRS10L240 Device Generic Registers This section outlines generic registers relating to the XRS10L240 as a whole. These registers are accessed through MDIO device 0. 38 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 16: RESET CONTROL SIGNALS ADDRESS HEX BIT(S) NAME TYPE RESET VALUE 0.0000 7:2 Reserved RO - Reserved 1 simflag RW 0 speed up flag for simulation only 0 rseqstart RW/SC 0 setting starts up reset controller. Self clearing 0.0003 0.0002 7:0 override_reg[15:0] RW 0x00 0x00 0.0004 3:0 resetPLLB_reg[3:0] RW 0xf Resets the PLL portion of the macros. 0.0005 7:0 resetDB_reg[7:0] RW 0xff Resets the digital portion of the macros 0 = reset the part 1 = normal operation 0.0006 7:0 resetCDRB_reg[7:0] RW 0xff Resets the CDR portion of the macros. 0.0011 0.0010 7:0 rcon_controlwords0[15:0] RW 0x02 0x00 reset controller microwords 0.0013 0.0012 7:0 rcon_controlwords1[15:0] RW 0x00 0x04 reset controller microwords 0.0015 0.0014 7:0 rcon_controlwords2[15:0] RW 0x00 0x53 reset controller microwords 0.0017 0.0016 7:0 rcon_controlwords3[15:0] RW 0x02 0x40 reset controller microwords 0.0019 0.0018 7:0 rcon_controlwords4[15:0] RW 0x00 0x80 reset controller microwords 0.001B 0.001A 7:0 rcon_controlwords5[15:0] RW 0x01 0x40 reset controller microwords 0.001D 0.001C 7:0 rcon_controlwords6[15:0] RW 0x00 0xc0 reset controller microwords 0.001F 0.001E 7:0 rcon_controlwords7[15:0] RW 0x01 0x20 reset controller microwords 0.0021 0.0020 7:0 rcon_controlwords8[15:0] RW 0x00 0x00 reset controller microwords 39 DESCRIPTION Override register for resets [15] – ebables all overrides [14:9] spares [8] – rcal reset [7] – device macro1 [6] – device macro0 [5] – selector and multiplier [4] – device gasket 1 [3] – device gasket 0 [2] – host gasket [1] – host macro [0] – rcal enable EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 16: RESET CONTROL SIGNALS ADDRESS HEX BIT(S) NAME TYPE RESET VALUE DESCRIPTION 0.0023 0.0022 7:0 rcon_controlwords9[15:0] RW 0x00 0x00 reset controller microwords 0.0025 0.0024 7:0 rcon_controlwordsA[15:0] RW 0x00 0x00 reset controller microwords 0.0027 0.0026 7:0 rcon_controlwordsB[15:0] RW 0x00 0x00 reset controller microwords 0.0030 7:0 revision_id[7:0] R/O 03H Deivice Revision ID 0.0031 7:0 device_id [15:8] R/O 83H Device ID MSB 0.0032 7:0 device_id [7:0 R/O 06H Device ID LSB TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX 0.0080 NAME TYPE RESET VALUE 7 p_rx_areset_h RW 0 Programmable auto reset for transmit elastic fifo (Host link layer) 1 = reset fifo when full or empty 0 = otherwise 6 p_rx_ra_disable_h RW 0 Programmable rate adjust disable for receive elastic fifo (Host link layer) 1 = disable 0 = enable 5 p_tx_feclr_h RW 0 programmable fifo error clear for transmit elastic fifo (Host link layer) 1 = clear sticky error 0 = otherwise 4 p_tx_areset_h RW 0 Programmable auto reset for transmit elastic fifo (Host link layer) 1 = reset fifo when full or empty 0 = otherwise 3 p_tx_ra_disable_h RW 0 Programmable rate adjust disable for transmit elastic fifo 1 = disable 0 = enable 2:1 p_devport_sel[1:0] RW 00 device port select for FIS routing in test mode 0 p_test_mode RW 0 1 = port multiplier in test mode 0 = otherwise 40 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX 0.0081 NAME TYPE RESET VALUE 7 p_rx_areset_d0 RW 0 Programmable auto reset for transmit elastic fifo (Device 0 link layer) 1 = reset fifo when full or empty 0 = otherwise 6 p_rx_ra_disable_d0 RW 0 Programmable rate adjust disable for receive elastic fifo (Device 0 link layer) 1 = disable 0 = enable 5 p_tx_feclr_d0 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 0 link layer) 1 = clear sticky error 0 = otherwise 4 p_tx_areset_d0 RW 0 Programmable auto reset for transmit elastic fifo (Device 0 link layer) 1 = reset fifo when full or empty 0 = otherwise 3 p_tx_ra_disable_d0 RW 0 Programmable rate adjust disable for transmit elastic fifo 1 = disable 0 = enable 2 p_as_mon_h RW 1 Control bit that 1 = monitors for unaligned Dword primitives (Host link layer) 0 = otherwise 1 p_sd_disable_h RW 0 Programmable scrambler/de-scrambler disable (Host link layer) 1 = disable 0 = enable 0 p_rx_feclr_h RW 0 Programmable fifo error clear for transmit elastic fifo (Host link layer) 1 = clear sticky error 0 = otherwise 41 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX 0.0082 NAME TYPE RESET VALUE 7 p_rx_areset_d1 RW 0 Programmable auto reset for transmit elastic fifo (Device 1 link layer) 1 = reset fifo when full or empty 0 = otherwise 6 p_rx_ra_disable_d1 RW 0 Programmable rate adjust disable for receive elastic fifo (Device 1 link layer) 1 = disable 0 = enable 5 p_tx_feclr_d1 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 1 link layer) 1 = clear sticky error 0 = otherwise 4 p_tx_areset_d1 RW 0 Programmable auto reset for transmit elastic fifo (Device 1 link layer) 1 = reset fifo when full or empty 0 = otherwise 3 p_tx_ra_disable_d1 RW 0 Programmable rate adjust disable for transmit elastic fifo (Device 1 link layer) 1 = disable 0 = enable 2 p_as_mon_d0 RW 1 Control bit that 1 = monitors for unaligned Dword primitives (Device 0 link layer) 0 = otherwise 1 p_sd_disable_d0 RW 0 Programmable scrambler/de-scrambler disable (Device 0 link layer) 1 = disable 0 = enable 0 p_rx_feclr_d0 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 0 link layer) 1 = clear sticky error 0 = otherwise 42 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX 0.0083 NAME TYPE RESET VALUE 7 p_rx_areset_d2 RW 0 Programmable auto reset for transmit elastic fifo (Device 2 link layer) 1 = reset fifo when full or empty 0 = otherwise 6 p_rx_ra_disable_d2 RW 0 Programmable rate adjust disable for receive elastic fifo (Device 2 link layer) 1 = disable 0 = enable 5 p_tx_feclr_d2 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 2 link layer) 1 = clear sticky error 0 = otherwise 4 p_tx_areset_d2 RW 0 Programmable auto reset for transmit elastic fifo (Device 2 link layer) 1 = reset fifo when full or empty 0 = otherwise 3 p_tx_ra_disable_d2 RW 0 Programmable rate adjust disable for transmit elastic fifo (Device 2 link layer) 1 = disable 0 = enable 2 p_as_mon_d1 RW 1 Control bit that 1 = monitors for unaligned Dword primitives (Device 1 link layer) 0 = otherwise 1 p_sd_disable_d1 RW 0 Programmable scrambler/de-scrambler disable (Device 1 link layer) 1 = disable 0 = enable 0 p_rx_feclr_d1 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 1 link layer) 1 = clear sticky error 0 = otherwise 43 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX 0.0084 NAME TYPE RESET VALUE 7 p_rx_areset_d3 RW 0 Programmable auto reset for transmit elastic fifo (Device 3 link layer) 1 = reset fifo when full or empty 0 = otherwise 6 p_rx_ra_disable_d3 RW 0 Programmable auto reset for transmit elastic fifo (Device 3 link layer) 1 = reset fifo when full or empty 0 = otherwise 5 p_tx_feclr_d3 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 3 link layer) 1 = clear sticky error 0 = otherwise 4 p_tx_areset_d3 RW 0 Programmable auto reset for transmit elastic fifo (Device 3 link layer) 1 = reset fifo when full or empty 0 = otherwise 3 p_tx_ra_disable_d3 RW 0 Programmable rate adjust disable for transmit elastic fifo (Device 3 link layer) 1 = disable 0 = enable 2 p_as_mon_d2 RW 1 Control bit that 1 = monitors for unaligned Dword primitives (Device 2 link layer) 0 = otherwise 1 p_sd_disable_d2 RW 0 Programmable scrambler/de-scrambler disable (Device 2 link layer) 1 = disable 0 = enable 0 p_rx_feclr_d2 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 2 link layer) 1 = clear sticky error 0 = otherwise 44 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX 0.0085 0.0086 0.0087 0.0088 NAME TYPE RESET VALUE 7:5 Reserved RO - Reserved 4 p_no_req_sig_after_xbit _clr R/W 0 1 = Allows forwarding of commands to the device and re-setting of the x bit immediately after the x bit is cleared. Control FIS are always forwarded 0 = Requires a device to first send its signature before commands can be forwarded to the device or the x bit can be set again. In legacy mode this bit is ignored (as if it were set to "1". 3 p_dvc_prt_en RW 0 1 = enable all port multiplier ports on reset 0 = otherwise 2 p_as_mon_d3 RW 1 Control bit that 1 = monitors for unaligned Dword primitives (Device 3 link layer) 0 = otherwise 1 p_sd_disable_d3 RW 0 Programmable scrambler/de-scrambler disable (Device 3 link layer) 1 = disable 0 = enable 0 p_rx_feclr_d3 RW 0 Programmable fifo error clear for transmit elastic fifo (Device 3 link layer) 1 = clear sticky error 0 = otherwise 7 p_cont_add_duable R/W 0 1 = cont insertion in Tx disabled 0 = cont insertion in Tx enabled 6 Reserved RO - Reserved 5:3 p_dvc1_wght[2:0] RW 000 Device port 1 weight for weighted-round robin arbitration Valid values 1-7 2:0 p_dvc0_wght[2:0] RW 000 Device port 0 weight for weighted-round robin arbitration Valid values 1-7 7:6 Reserved RO - 5:3 p_dvc3_wght[2:0] RW 000 Device port 3 weight for weighted-round robin arbitration Valid values 1-7 2:0 p_dvc2_wght[2:0] RW 000 Device port 2 weight for weighted-round robin arbitration Valid values 1-7 7:0 p_intvl_val[7:0] RW 0xB7 45 DESCRIPTION Reserved programmable communication interval value for hot plug FSM Interval is 27.3us * count EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX NAME TYPE RESET VALUE 7 Reserved RO - 6:3 p_msb_rscnt[3:0] RW 1000 2 p_dlock_err_clr RW 0 1 = clear the stick deadlock error indicator 0 = otherwise 1 p_restart_pm_en RW 1 1 = port multiplier will restart if it enters deadlock 0 = otherwise 0 p_pwrmng_on RW 1 1 = power management turned on in port 0 = power management turned off in port 7 Reserved RO - Reserved 6:4 p_col_ad[2:0] RW 000 Col address of the SRAM in test mode 3:0 p_row_ad[11:0] RW 0x00 Row address of the SRAM in test mode 0.0091 7:0 p_row_ad[11:0] RW 0x00 Row address of the SRAM in test mode 0.0092 7:0 p_wdata[7:0] RW 0x00 Write data for the sram in test mode 0.0093 7:0 p_rdata[7:0] RO 0x00 Read data from the sram in test mode 0.0094 7:2 Reserved RO - Reserved 1 p_wr_en RW 0 1 = write op 0 = read op 0 p_wr_toggle RW 0 initiates an sram op 0.0089 0.0090 46 DESCRIPTION Reserved The 4 MSB’s of the 20 bit timeout value used to decide how long the PM should wait before issuing a restart EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX 0.0095 NAME TYPE RESET VALUE 7 o_rx_ferr_d2 RO 0 Observable receive elastic fifo sticky error (full or empty) (Device 2 link layer) 1 = error 0 = no error 6 o_tx_ferr_d2 RO 0 Observable transmit elastic fifo sticky error (full or empty) (Device 2 link layer) 1 = error 0 = no error 5 o_rx_ferr_d1 RO 0 Observable receive elastic fifo sticky error (full or empty) (Device 1 link layer) 1 = error 0 = no error 4 o_tx_ferr_d1 RO 0 Observable transmit elastic fifo sticky error (full or empty) (Device 1 link layer) 1 = error 0 = no error 3 o_rx_ferr_d0 RO 0 Observable receive elastic fifo sticky error (full or empty) (Device 0 link layer) 1 = error 0 = no error 2 o_tx_ferr_d0 RO 0 Observable transmit elastic fifo sticky error (full or empty)(Device 0 link layer) 1 = error 0 = no error 1 o_rx_ferr_h RO 0 Observable receive elastic fifo sticky error (full or empty) (Host link layer) 1 = error 0 = no error 0 o_tx_ferr_h RO 0 Observable transmit elastic fifo sticky error (full or empty)(Host link layer) 1 = error 0 = no error 47 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 17: SATA PORT MULTIPLIER REGISTERS ADDRES BIT(S) S HEX NAME TYPE RESET VALUE 7 o_dlock_err RO 0 1 = a PM deadlock occurred 0 = otherwise 6 spdmode_d3 RO 0 SPD mode signal from phy 3 1 = 3Gb/s mode 0 = 1.5Gb/s mode 5 spdmode_d2 RO 0 SPD mode signal from phy 2 1 = 3Gb/s mode 0 = 1.5Gb/s mode 4 spdmode_d1 RO 0 SPD mode signal from phy 1 1 = 3Gb/s mode 0 = 1.5Gb/s mode 3 spdmode_d0 RO 0 SPD mode signal from phy 0 1 = 3Gb/s mode 0 = 1.5Gb/s mode 2 pm_ssc_tx_en RO 0 Dynamic SSC transmit enable signal 1 o_rx_ferr_d3 RO 0 Observable receive elastic fifo sticky error (full or empty) (Device 3 link layer) 1 = error 0 = no error 0 o_tx_ferr_d3 RO 0 Observable transmit elastic fifo sticky error (full or empty) (Device 3 link layer) 1 = error 0 = no error 7:6 max_spd_to_dp3[1:0] RO 00 SPD field from the dev 3 SCControl reg 5:4 max_spd_to_dp2[1:0] RO 00 SPD field from the dev 2 SCControl reg 3:2 max_spd_to_dp1[1:0] RO 00 SPD field from the dev 1 SCControl reg 1:0 max_spd_to_dp0[1:0] RO 00 SPD field from the dev 0 SCControl reg 0.0098 7:0 p_vct_fis_size[11:0] RW 0x06 0.0099 7 p_vct_en RW 1 6:4 p_vct_emp_wmark[2:0] RW 0x3 Progammable watermark for VCT read from SRAM 3:0 p_vct_fis_size[11:0] RW 0x0 Programmable FIS size when VCT kicks in 0.0096 0.0097 48 DESCRIPTION Programmable FIS size when VCT kicks in Enable for virtual cut-through EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 18: SATA PORT SELECTOR REGISTERS ADDRESS HEX BIT(S) NAME TYPE RESET VALUE 0.009A 7 Reserved RO - Reserved 6 p_led_revb RW 0 0 = No effect 1 = Change functionality of pin 77 (PS_SideBand) and pin 76 HBACT[0] to original HBACTfunctionality (for backwards compatability) 5 p_nopass_cominit RW 1 1 = Do not pass 1st cominit (Must be set to "1" for normal operation) DESCRIPTION NOTE: In legacy mode, even if set to "1", cominit will be passed from device 0 to the host. 0 = Pass 1st cominit from device(s) to host (for testing Puposes only) 4 p_lcs_spd_sel RW 0 1 = don’t mix speeds; use the slowest 0 = mix speeds based on device abilities 3 p_test_mode_sel RW 0 1 = port selector in test mode 0 = port selector in normal mode 2 p_host_sel RW 0 Side band port selection 1 = Select Host port 2 0 = Select Host port 1 1 p_side_mthd RW 0 1 = p_host_sel based sideband selection 0 = external pin based sideband selection 0 p_sel_mthd RW 0 1 = When 1 or PS_SideBand (pin 77) =1, host port is selected by p_side_method (bit 1). 0 = protocol based port selection. Please refer to Table 2, “Host Port Selection,” on page 6 0.009C 7:0 p_err_thres[14:0] RW 0x00 0.009D 7 p_err_thres_en RW 0 6:0 p_err_thres[14:0] RW 0x00 49 Threshold for high error rate from port multiplier Enable for error counting Threshold for high error rate from port multiplier EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 19: CLOCK CONFIGURATION REGISTER ADDRESS HEX BIT(S) NAME TYPE RESET VALUE 0.0001 7:3 Reserved RO - Reserved 2 refClkSel RW 0 1 = select CMU_REF 0 = select on chip crystal oscillator 1 pwrdnRefClk RW 0 Powers down reference clock 7:4 Reserved RO - Reserved 3:1 clkMacroTestSel[2:0] RW 000 DESCRIPTION 0 0.009B 0 clkTestEn RW 0 000 = disabled 001 = Sata Output Macro 2 010 = Sata Output Macro 0 011 = Sata Input Macro 100 = Reserved 101 = SysClkBotLeft 110 = PLL Output 111 = PLL Test Clock -->ClkTestIn<4> -->ClkTestIn<5> -->ClkTestIn<6> 0 = disable clock test output buffer 1 = enable clock test output buffer TABLE 20: RESERVED DEBUG REGISTERS ADDRESS HEX BIT(S) NAME RW RESET VALUE 0.00A0 7:0 Reserved RW 0x00 Debug Use Only 0.00A1 7:0 Reserved RW 0x00 Debug Use Only 0.00A2 7:0 Reserved RW 0x00 Debug Use Only 0.00A3 7:0 Reserved RW 0x00 Debug Use Only 0.00A4 7:0 Reserved RW 0x0F Debug Use Only 0.00A5 7:0 Reserved RW 0x0F Debug Use Only 0.00A6 7:0 Reserved RW 0x78 Debug Use Only 0.00A7 7:0 Reserved RW 0x00 Debug Use Only 0.00A8 7:0 Reserved RW 0x7C Debug Use Only 0.00A9 7:0 Reserved RW 0x00 Debug Use Only 0.00AA 7:0 Reserved RW 0x7C Debug Use Only 0.00AB 7:0 Reserved RW 0x00 Debug Use Only 0.00AC 7:0 Reserved RW 0x00 Debug Use Only 0.00AD 7:0 Reserved RW 0x00 Debug Use Only 50 -->ClkTestIn<0> -->ClkTestIn<1> -->ClkTestIn<2> DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 20: RESERVED DEBUG REGISTERS ADDRESS HEX BIT(S) NAME RW RESET VALUE 0.00AE 7:0 Reserved RW 0x00 Debug Use Only 0.00B0 7:0 Reserved RW 0x00 Debug Use Only 0.00B1 7:0 Reserved RW 0x00 Debug Use Only 0.00B2 7:0 Reserved RW 0x00 Debug Use Only 0.00B3 7:0 Reserved RW 0x00 Debug Use Only 0.00B4 7:0 Reserved RW 0x00 Debug Use Only 0.00B5 7:0 Reserved RW 0x00 Debug Use Only 0.00B6 7:0 Reserved RW 0x00 Debug Use Only 0.00B7 7:0 Reserved RW 0x00 Debug Use Only 0.00B8 7:0 Reserved RW 0x00 Debug Use Only 0.00B9 7:0 Reserved RW 0x00 Debug Use Only 0.00BA 7:0 Reserved RW 0x00 Debug Use Only 0.00BB 7:0 Reserved RW 0x0F Debug Use Only 0.00BC 7:0 Reserved RW 0x00 Debug Use Only DESCRIPTION TABLE 21: PORT MULTIPLIER SATA STANDARD REGISTERS REGISTER BIT(S) NAME TYPE DEFAULT VALUE GSCR(0) Product Identifier 31 - 16 Device ID R/O 0x8306 Device ID allocated by the vendor. 15 - 0 Vendor ID R/O 0x13A8 Vendor ID allocated by the PCI-SIG of the vendor that produced the Port Multiplier. GSCR(1) Revision Information 31 - 16 Reserved R/O 0x0000 31-16 Reserved 15 - 8 REV_LEV R/O 0x03 15-8 Revision level of the Port Multiplier. 7:4 Reserved R/O 0x0 7-4 Reserved 3 PM_1,2 R/O 1 1=Supports Port Multiplier specification 1.2. 2 PM_1.1 R/O 1 1=Supports Port Multiplier specification 1.1. 1 PM_1.0 R/O 1 1=Supports Port Multiplier specification 1.0. 0 Reserved R/O 0 Reserved 51 DESCRIPTION EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 21: PORT MULTIPLIER SATA STANDARD REGISTERS REGISTER BIT(S) NAME TYPE DEFAULT VALUE GSCR(2) Port Information 7:4 Reserved R/O 0x0 Reserved 3-0 DEV_FAN_OUT_ PORTS R/O 0x4 Number of exposed device fan-out ports. 31 - 15 Reserved R/O 0x0 14 Reserved R/O 0 Unused 13 Reserved R/O 0 Unused 12 Reserved R/O 0 Unused 11 Reserved R/O 0 Unused 10 Reserved R/O 0 Unused 9 Reserved R/O 0 Unused 8 Reserved R/O 0 Unused 7 Reserved R/O 0 Unused 6 Reserved R/O 0 Unused 5 Reserved R/O 0 Unused 4 Reserved R/O 0 Unused 3 OR_PORT-3 R/O 0 OR of selectable bits in Port 3 PSCR[1] (SError) 2 OR_PORT-2 R/O 0 OR of selectable bits in Port 2 PSCR[1] (SError) 1 OR_PORT-1 R/O 0 OR of selectable bits in Port 1 PSCR[1] (SError) 0 OR_PORT-0 R/O 0 OR of selectable bits in Port 0 PSCR[1] (SError) GSCR(33) Error Information Bit Enable 31 - 0 ERR_INFO_EN R/O 0x400FFFF GSCR(64) Port Multiplier Revision 1.X Features Support 31 - 5 Reserved R/O 0x0 4 PHY_EVENT R/O 0 1 = Supports Phy event counters 3 ASYNC R/O 1 1 = Supports asynchronous notification 2 SSC R/O 0 1 = Supports dynamic SSC transmit enable 1 PMREQP R/O 1 1 = Supports issuing PMREQP to host 0 BIST R/O 0 1 = Supports BIST GSCR(32) Error Information 52 DESCRIPTION If set, bit is enabled for use in GSCR[32] Reserved EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 21: PORT MULTIPLIER SATA STANDARD REGISTERS REGISTER BIT(S) NAME TYPE DEFAULT VALUE GSCR(96) Port Multiplier Revision 1.X Features Enable 31 - 4 Reserved R/O 0x0 3 ASYNC_EN R/W 0 1 = Asynchronous notification enabled 2 SSC_EN R/W 0 1 = Dynamic SSC transmit is enabled 1 PMREQP_EN R/W 0 1 = Issuing PMREQP to host is enabled 0 BIST_EN R/W 0 1 = BIST support is enabled DESCRIPTION Reserved TABLE 22: SATA STANDARD REGISTERS - DEVICE PORT (0 TO 3) - STATUS AND CONTROL NOTE: Registers designated as WC are write clear. In order to clear a particular bit or bit field within a WC designated register, write a ‘1’ to that bit or bit field. REGISTER BIT(S) NAME TYPE DEFAULT VALUE PSCR(0) (SStatus) 31 - 12 Reserved R/O 0x0 Reserved 11 - 8 IPM R/O 0x0 The IPM value indicates the current interface power management state 0000b = Device not present or communication not established 0001b = Interface in active state 0010b= Interface in Partial power management state 0110b = Interface in Slumber power management state All other values reserved 7 -4 SPD R/O 0x0 The SPD value indicates the negotiated interface communication speed established 0000b = No negotiated speed (device not present or communication not established) 0001b = Generation 1 communication rate negotiated 0010b = Generation 2 communication rate negotiated All other values reserved 3-0 DET R/O 0x0 The DET value indicates the interface device detection and Phy state. 0000b = No device detected and Phy communication not established 0001b = Device presence detected but Phy communication not established 0011b = Device presence detected and Phy communication established 0100b = Phy in offline mode as a result of the interface being disabled or running in a BIST loopback mode All other values reserved 31 - 16 DIAG R/WC 0x40 See description below 15 - 0 ERR R/WC 0x0 See description below PSCR(1) (SError) DESCRIPTION 53 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 TABLE 22: SATA STANDARD REGISTERS - DEVICE PORT (0 TO 3) - STATUS AND CONTROL NOTE: Registers designated as WC are write clear. In order to clear a particular bit or bit field within a WC designated register, write a ‘1’ to that bit or bit field. REGISTER BIT(S) NAME TYPE DEFAULT VALUE PSCR(2) (SControl) 31 - 19 Reserved R/O 0x0 Reserved All reserved fields shall be cleared to zero. 20 - 16 Reserved R/W 0x0 Reserved All reserved fields shall be cleared to zero 15 - 12 SPM R/W 0x0 See description below 11 - 8 IPM R/W 0x0 See description below 7-4 SPD R/W 0x0 See description below 3-0 DET R/W 0x4 See description below DESCRIPTION SError register SCR(1) The Serial ATA interface Error register - SError - is a 32-bit register that conveys supplemental Interface error information to complement the error information available in the Shadow Register Block Error register. The register represents all the detected errors accumulated since the last time the SError register was cleared (whether recovered by the interface of not). Set bits in the error register are explicitly cleared by a write operation to the SError register, or a reset operation. The value written to clear set error bits shall have 1’s encoded in the bit positions corresponding to the bits that are to be cleared. Host software should clear the Interface SError register at appropriate checkpoints in order to best isolate error conditions and the commands they impact. Bits [31:16] DIAG The DIAG field contains diagnostic error information for use by diagnostic software in validating correct operation or isolating failure modes. The field is bit significant as defined in the following figure. DIAG R R R R A X F T S H C D B W I N A Port Selector presence detected: This bit is set to one when COMWAKE is received while the host is in state HP2: HR_AwaitCOMINIT. On power-up reset this bit is cleared to zero. The bit is cleared to zero when the host writes a one to this bit location. B 10b to 8b Decode error: When set to a one, this bit indicates that one or more 10b to 8b decoding errors occurred since the bit was last cleared to zero. C CRC Error: When set to one, this bit indicates that one or more CRC errors occurred with the Link layer since the bit was last cleared to zero. D Disparity Error: When set to one, this bit indicates that incorrect disparity was detected one or more times since the last time the bit was cleared to zero. F Unrecognized FIS type: When set to one, this bit indicates that since the bit was last cleared one or more FISes were received by the Transport layer with good CRC, but had atype field that was not recognized. I Phy Internal Error: When set to one, this bit indicates that the Phy detected some internal error since the last time this bit was cleared to zero. N PHYRDY change: When set to one, this bit indicates that the PHYRDY signal changed state since the last time this bit was cleared to zero. 54 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 H Handshake error: When set to one, this bit indicates that one or more R_ERRPhandshake response was received in response to frame transmission. Such errors may be the result of a CRC error detected by the recipient, a disparity or 10b/8b decoding error, or other error condition leading to a negative handshake on a transmitted frame. R Reserved bit for future use: Shall be cleared to zero. S Link Sequence Error: When set to one, this bit indicates that one or more Link state machine error conditions was encountered since the last time this bit was cleared to zero. The Link layer state machine defines the conditions under which the link layer detects an erroneous transition. T Transport state transition error: When set to one, this bit indicates that an error has occurred in the transition from one state to another within the Transport layer since the last time this bit was cleared to zero. W COMWAKE Detected: When set to one this bit indicates that a COMWAKE signal was detected by the Phy since the last time this bit was cleared to zero. X Exchanged: When set to one this bit indicates that device presence has changed since the last time this bit was cleared to zero. The means by which the implementation determines that the device presence has changed is vendor specific. This bit may be set to one anytime a Phy reset initialization sequence occurs as determined by reception of the COMINIT signal whether in response to a new device being inserted, in response to a COMRESET having been issued, or in response to power-up. Bits [15:0] ERR The ERR field contains error information for use by host software in determining the appropriate response to the error condition. The field is bit significant as defined in the following figure. ERR R R R R E P C T R R R R R R M I C Non-recovered persistent communication or data integrity error: A communication error that was not recovered occurred that is expected to be persistent. Since the error condition is expected to be persistent the operation need not be retried by host software. Persistent communications errors may arise from faulty interconnect with the device, from adevice that has been removed or has failed, or a number of other causes. E Internal error: The host bus adapter experienced an internal error that caused the operation to fail and may have put the host bus adapter into an error state. Host software should reset the interface before re-trying the operation. If the condition persists, the host bus adapter may suffer from a design issue rendering it incompatible with the attached device. I Recovered data integrity error: A data integrity error occurred that was recovered by the interface through a retry operation or other recovery action. This may arise from a noise burst in the transmission, a voltage supply variation, or from other causes. No action is required by host software since the operation ultimately succeeded, however, host software may elect to track such recovered errors in order to gauge overall communications integrity and potentially step down the negotiated communication speed. M Recovered communications error: Communications between the device and host was temporarily lost but was re-established. This may arise from a device temporarily being removed, from a temporary loss of Phy synchronization, or from other causes and may be derived from the PHYRDYn signal between the Phy and Link layers. No action is required by the host software since the operation ultimately succeeded, however, host software may elect to track such recovered errors in order to gauge overall communications integrity and potentially step down the negotiated communication speed. P Protocol error: A violation of the Serial ATA protocol was detected. This may arise from invalid or poorly formed FISes being received, from invalid state transitions, or from other causes. Host software should reset the interface and retry the corresponding operation. If such an error persists, the attached device may have a design issue rendering it incompatible with the host bus adapter. R Reserved bit for future use: Shall be cleared to zero. 55 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 T Non-recovered transient data integrity error: A data integrity error occurred that was not recovered by the interface. Since the error condition is not expected to be persistent the operation should be retried by host software. SControl register SCR(2) The Serial ATA interface Control register - SControl - is a 32-bit read-write register that provides the interface by which software controls Serial ATA interface capabilities. Writes to the SControl register result in an action being taken by the host adapter or interface. Reads from the register return the last value written to it. Bits [19:16] PMP The Port Multiplier Port (PMP) field represents the 4-bit value to be placed in the PM Port field of all transmitted FISes. This field is ‘0000’ upon power-up. This field is optional and an HBA implementation may choose to ignore this field if the FIS to be transmitted is constructed via an alternative method. Bits [15:12] SPM The Select Power Management (SPM) field is used to select a power management state. Anon-zero value written to this field shall cause the power management state specified to be initiated. A value written to this field is treated as a one-shot. This field shall be read as 0000b. ■ 0000b = No power management state transition requested ■ 0001b = Transition to the Partial power management state initiated ■ 0010b = Transition to the Slumber power management state initiated ■ 0100b = Transition to the active power management state initiated ■ All other values reserved Bits [11:8] IPM The IPM field represents the enabled interface power management states that may be invoked via the Serial ATA interface power management capabilities ■ 0000b = No interface power management state restrictions ■ 0001b = Transitions to the Partial power management state disabled ■ 0010b = Transitions to the Slumber power management state disabled ■ 0011b = Transitions to both the Partial and Slumber power management states disabled ■ All other values reserved Bits [7:4]SPD The SPD field represents the highest allowed communication speed the interface is allowed to negotiate when interface communication speed is established ■ 0000b = No speed negotiation restrictions ■ 0001b = Limit speed negotiation to a rate not greater than Gen 1 communication rate ■ 0010b = Limit speed negotiation to a rate not greater than Gen 2 communication rate ■ All other values reserved Bits [3:0] DET The DET field controls the host adapter device detection and interface initialization. ■ 0000b = No device detection or initialization action requested ■ 0001b = Perform interface communication initialization sequence to establish communication. This is functionally equivalent to a hard reset and results in the interface being reset and communications reinitialized. Upon a write to the SControl register that sets the DET field to 0001b, the host interface shall transition to the HP1: HR_Reset state and shall remain in that state until the DET field is set to a value other than 0001b, by a subsequent write to the SControl register. 56 EXSTOR - 1 XRS10L240 REV. 1.01 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR ■ 0100b = Disable the Serial ATA interface and put Phy in offline mode. ■ All other values reserved 57 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 6.0 FEATURES AND BENEFITS TABLE 23: FEATURES AND BENEFITS DISTINGUISHING FEATURE COMPETITIVE ADVANTAGE SYSTEM BENEFIT Port Multiplier Functionality Available with Port Selector functionality in a single package Expands Number of Addressable Devices Port Selector Functionality Available with Port Multiplier functionality in a Redundant Path For Failover Applications single package Support for 3.0 Gbps and 1.5 Backwards Compatibility to SATA Gen. 1 Gbps Can be used with both SATA Gen. 1 and Gen. 2 drives Equalization and pre-empha- Superior analog front end. Very high signal sis on the receive front end integrity. Meets SATA Gen2i, Gen2x Enables Longer distances on the copper/FR-4 Improved signal integrity Programmable Output Swing Optimizes Power Consumption Provides compliance to both SAS and SATA systems Speed Negotiation Locks to 3/1.5G SATA data without any exter- Reduces system complexity and software nal components. effort to implement auto rate adaptation. Fast Locking & Low Latency Locks to incoming data with in 300 data edges. Latency is <25 clock cycles. Built in Self Test. Includes a PRBS generator and checker for Makes testing of the storage sub-systems self testing. PRBS patterns of 2^10-1, 2^23-1, easier. and 2^31-1 are all available. 2 Wire MDIO Bus Control and monitoring features are managed Minimizes board space and system cost. through a comprehensive register set instead of multiple pins. Power down modes Supports the following modes of operation: Active Mode - 90 mW Partial Mode - <37.5 mW Slumber Mode - <5 mW Power down mode < 0.5mW Enhances the overall system performance. Provides full support of power management commands from the connected hosts and devices. Fully complies with the Serial ATA II port multiplier specification. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet January 2008. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 58 EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRS10L240IV-F 100 Pin LQFP (Lead Free) -40°C to +85°C XRS10L240IV 100 Pin LQFP -40°C to +85°C 100 LEAD LOW-PROFILE QUAD FLAT PACK (14 X 14 X 1.4 mm LQFP, 1.0 mm FORM) D D1 75 51 76 50 D1 100 26 1 β B e C A2 A Seating Plane 25 α A1 L NOTE: The control dimension is in millimeters INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.010 0.014 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.622 0.638 15.80 16.20 59 D EXSTOR - 1 XRS10L240 SERIAL ATA II: PORT MULTIPLIER / PORT SELECTOR REV. 1.01 NOTE: The control dimension is in millimeters INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX D1 0.390 0.555 13.90 14.10 e 0.0197 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° β 7° typ 7° typ REVISIONS REV # DATE 1.00 November 2008 1.01 January 2008 DESCRIPTION OF CHANGES Released. Corrected JTAG TRST, TDO pin desc., part ordering info. 60