NJW1143A AUDIO PROCESSOR Q GENERAL DESCRIPTION The NJW1143A is an audio processor which includes volume, balance, tone control, surround, simulated stereo and AGC function. Also the NJW1143A features high precision characteristics about channel balance, it is less than ±1.0dB at –70dB attenuation. All of internal status and variables are controlled by I2C BUS. Selectable 4-slave address is applicable to multi-speaker system. It is suitable for any TV set. Q PACKAGE OUTLINE NJW1143AV Q FEATURES O Operating Voltage 8 to 13V O I2C BUS Interface (Fast mode applicable, Selectable 4-Slave address, 3V I/F applicable) O Low Output Noise O AGC Circuit (Selectable 4-stage compression level via I2C BUS) O "eala" (NJRC Surround) O Simulated Surround O Bi-CMOS Technology O Package Outline SSOP32 Q BLOCK DIAGRAM SRFIL AGC TONE TONE -Ha -La OUTa CVO CBA VOL1 INa TONE CTH VOL2 2 AGC INb I C Bus Interface eala & Sim ulate Stereo VOL1 CTL CSR AUX0 AUX1 ADR0 ADR1 TONE SCL SDA VOL2 Bias TONE TONE -Hb -Lb OUTb V+ GND Vref -1- NJW1143A Q PIN CONFIGURATION Ach Input 1 IN1a No Connect 2 NC Ach Output 3 OUTa No Connect 4 NC Ach Treble Filter 5 TONE-Ha TONE-Hb 28 Bch Treble Filter Ach Bass Filter 6 TONE-La TONE-Lb 27 Bch Bass Filter AGC Filter 7 AGC SRFIL 26 Surround Filter Pop Noise Reduction for Surround ON/OFF Control 8 CSR CBA 25 Pop Noise Reduction for Volume Control 9 CVO CTL 24 Pop Noise Reduction for BASS Control 10 ADR0 CTH 23 Pop Noise Reduction for Treble Control 11 ADR1 AUX1 22 Auxiliary Output 1 12 SDA AUX0 21 Auxiliary Output 0 13 NC 14 SCL No Connect 15 NC 16 NC 18 Ground 16 GND V+ 2 I C Slave Address Select 0 I2C Slave Address Select 1 SDA Serial Data Input (I2C BUS) No Connect SCL Serial Clock Input (I2C BUS) -2- IN1b 32 Bch Input 31 No Connect OUTb 30 Bch Output NC NC 29 NC 20 Vref 19 17 No Connect Pop Noise Reduction for Balance Control No Connect Reference Voltage No Connect Power Supply NJW1143A Q ABSOLUTE MAXIMUM RATING (Ta=25°C) PARAMETER SYMBOL + Supply Voltage V Power Dissipation PD RATING UNIT 15 800 V NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting mW Operating Temperature Range Topr -20 to +75 °C Storage Temperature Range Tstg -40 to +125 °C Q ELECTRICAL CHARACTERISTICS (Ta=25°C, V+=9V, Rg=600Ω, RL=47kΩ, Vin=100mVrms/1kHz, AGC=OFF, TONE=0dB, Surround=OFF unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT 8.0 9.0 13.0 V Operating Voltage V+ Supply Current ICC No Signal - 13.0 25.0 mA VREF No Signal 4.0 4.5 5.0 V 2.8 3.0 - Vrms - 2.5 - Vrms Reference Voltage Maximum Input Voltage VIM VOL=-20dB,THD=10% Maximum Output Voltage VOM OUTPUT VOL=0dB,THD=1% Channel Balance 1 GCB1 VOL=0dB -1.0 0.0 1.0 dB Channel Balance 2 GCB2 VOL=-70dB, Vin=1Vrms -1.0 0.0 1.0 dB Balance Boost A BABST CHS=”0”, BAL=”11111” -2.0 0.0 2.0 dB Balance Cut A BACUT CHS=”1”, BAL=”11111” Vin = 1Vrms - - -70 dB Balance Boost B BBBST CHS=”1”, BAL=”11111” -2.0 0.0 2.0 dB - - -70 dB - - 0.3 % -2.0 0.0 2.0 dB - -100 -90 dB - -80 -70 dB - -90 (31.6) -106 (5.0) -85 (56.2) dBV (µVrms) dBV (µVrms) Logic Output: High 4.5 - 5.5 Logic Output: Low 0 - 0.5 Balance Cut B Total Harmonic Distortion BBCUT THD CHS=”0”, BAL=”11111” Vin = 1Vrms Vo=0.5Vrms BW=400Hz to 30kHz Maximum Gain GVMAX VOL= 0dB Minimum Gain GVMIN VOL= MUTE, Vin=2Vrms Channel Separation CS Output Noise 1 VNO1 Output Noise 2 VNO2 AUX Output Voltage VAUX Vin = 1Vrms A-weighting VOL = 0dB A-weighting VOL = MUTE A-weighting -96 (15.8) V BW: Band Width -3- NJW1143A Q ELECTRICAL CHARACTERISTICS (Ta=25°C, V+=9V, Rg=600Ω, RL=47kΩ, Vin=100mVrms/1kHz, AGC=OFF, TONE=0dB, Surround=OFF unless otherwise specified) ♦ TONE CONTROL PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT High Frequency Boost HFBST BCT=”1”, TREB=”1111”, f=10kHz 12.0 15.0 18.0 dB High Frequency Flat HFFLT TREB=”0000”, f=10kHz -2.0 0.0 2.0 dB High Frequency Cut HFCUT BCT=”0”, TREB=”1111”, f=10kHz -18.0 -15.0 -12.0 dB Low Frequency Boost LFBST BCB=”1”, BASS=”1111”, f=100Hz 12.0 15.0 18.0 dB Low Frequency Flat LFFLT BASS=”0000”, f=100Hz -2.0 0.0 2.0 dB Low Frequency Cut LFCUT BCB=”0”, BASS=”1111”, f=100Hz -18.0 -15.0 -12.0 dB MIN. TYP. MAX. UNIT ♦ AGC CONTROL (AGC-ON) PARAMETER SYMBOL TEST CONDITION AGC Boost AGCBST Vin=50mVrms, f=1kHz 1.5 3.5 5.5 dB AGC Flat1 AGCFLT1 Vin=125mVrms, f=1kHz -2.5 0.0 2.5 dB AGC Flat2 AGCFLT2 Vin=250mVrms, f=1kHz -2.5 0.0 2.5 dB AGC Flat3 AGCFLT3 Vin=300mVrms, f=1kHz -2.5 0.0 2.5 dB AGC Flat4 AGCFLT4 Vin=400mVrms, f=1kHz -2.5 0.0 2.5 dB AGC Cut AGCCUT Vin=2Vrms, f=1kHz -14 -10 -6.0 dB MIN. TYP. MAX. UNIT 2.0 4.0 6.0 dB -6.5 -4.5 -2.5 dB 6.0 8.0 10.0 dB 1.5 3.5 5.5 dB 1.0 3.0 5.0 dB 1.0 3.0 5.0 dB ♦ SURROUND (SURROUND-ON) PARAMETER SYMBOL Surround Gain1 SRGAIN1 Surround Gain2 SRGAIN2 Surround Gain3 SRGAIN3 Surround Gain4 SRGAIN 4 Simulated Surround Gain1 SRSIM1 Simulated Surround Gain2 SRSIM2 -4- TEST CONDITION Ain→Aout, f=100Hz SUR0=”1”, SUR=”1” Ain→Bout, f=100Hz SUR0=”1”, SUR=”1” Ain→Aout, f=100Hz SUR0=”0”, SUR=”1” Ain→Bout, f=100Hz SUR0=”0”, SUR=”1” Ain+Bin→Aout, f=1kHz SUR0=”1”, SUR=”0” Ain+Bin→Bout, f=1kHz SUR0=”1”, SUR=”0” NJW1143A TIMING ON THE I2C BUS (SDA,SCL) SDA tf tr tf tHD:ST A tBUF tr tSP tSU:DAT SCL tHD:STA S tLOW tSU:STA tHD:DAT tSU:ST O tHIGH Sr S P CHARACTERISTICS OF I/O STAGES FOR I2C BUS (SDA,SCL) I2C BUS Load Conditions STANDARD MODE : Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND) FAST MODE : Pull up resistance 4kΩ (Connected to +5V), Load capacitance 50pF (Connected to GND) PARAMETER SYMBOL Standard mode Fast mode MIN. TYP. MAX. MIN. TYP. MAX. UNIT Low Level Input Voltage VIL 0.0 - 1.5 0.0 - 1.5 V High Level Input Voltage VIH 2.7 - 5.0 2.7 - 5.0 V Low level output voltage (3mA at SDA pin) VOL 0 - 0.4 0 - 0.4 V Ii -10 - 10 -10 - 10 µA Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax -5- NJW1143A CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I2C-BUS DEVICES PARAMETER Standard mode SYMBOL Fast mode UNIT MIN. TYP. MAX. MIN. TYP. MAX. fSCL - - 100 - - 400 kHz tHD:STA 4.0 - - 0.6 - - µs Low period of the SCL clock tLOW 4.7 - - 1.3 - - µs High period of the SCL clock tHIGH 4.0 - - 0.6 - - µs tSU:STA 4.7 - - 0.6 - - µs tHD:DAT 0 - - 0 - - µs tSU:DAT 250 - - 100 - - ns Rise time of both SDA and SCL signals tr - - 1000 - - 300 ns Fall time of both SDA and SCL signals tf - - 300 - - 300 ns tSU:STO 4.0 - - 0.6 - - µs Bus free time between a STOP and START condition tBUF 4.7 - - 1.3 - - µs Capacitive load for each bus line Cb - - 400 - - 400 pF Noise margin at the Low level VnL 0.5 - - 0.5 - - V Noise margin at the High level VnH 1 - - 1 - - V SCL clock frequency Hold time (repeated) START condition. Set-up time for a repeated START condition Data hold time NOTE) Data set-up time Set-up time for STOP condition Cb ; total capacitance of one bus line in pF. NOTE). Data hold time : tHD:DAT Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge. The SDA block in the NJW1143A does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not providing a hold time of at least 300nsec for the SDA in the master device. The time-consists of the data-delay-circuit of the SDA terminal are as follows. TLH ≈ RP*CD THL ≈ RD*CD (a) Low level Æ High level : (b) High level Æ Low level : In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward voltage (Vf) as much as possible. VDD RP RP SCL MASTER SBD SDA RD -6- CD NJW1143A NJW1143A TERMINAL DESCRIPTION No. SYMBOL FUNCTION 1 INa Ach Input terminal 32 INb Bch Input terminal EQUIVALENT CIRCUIT VOLTAGE V+/2 100k REF 3 OUTa Ach Output terminal 30 OUTb Bch Output terminal V+/2 FB 50 32k 5 TONE-Ha Ach Treble Filter terminal 28 TONE-Hb Bch Treble Filter terminal V+/2 32k 12k 6 TONE-La Ach Bass Filter terminal 27 TONE-Lb Bch Bass Filter terminal 7 AGC Capacitor connection terminal for AGC attack and recovery time setting FB 12k V+/2 12k 400 1.4V 400 -7- NJW1143A TERMINAL DESCRIPTION No. SYMBOL FUNCTION 8 CSR Pop Noise Reduction for Surround ON/OFF Control EQUIVALENT CIRCUIT VOLTAGE V+/2 32k 9 CVO Pop Noise Reduction for Volume Control 10 ADR0 I2C Slave Address Select 0 11 ADR1 I2C Slave Address Select 1 8k V+/2 - 4k 12 SDA SDA Serial Data Input (I2C BUS) 14 SCL SDA Serial Clock Input (I2C BUS) 16 GND Ground terminal - - 17 V+ Power Supply terminal - - -8- 12k NJW1143A TERMINAL DESCRIPTION No. SYMBOL FUNCTION 19 Vref Reference Voltage terminal EQUIVALENT CIRCUIT VOLTAGE V+/2 200k AUX0 Auxiliary 2 values voltage Output terminal 0 22 AUX1 Auxiliary 2 values voltage Output terminal 1 23 CTH Pop Noise Reduction for Bass Control 24 CTL Pop Noise Reduction for Treble Control 25 CBA Pop Noise Reduction for Balance Control 21 50 36k V+/2 12k 26 SRFIL Surround filter terminal FB 4k V+/2 -9- NJW1143A Q APPLICATION CIRCUIT 0.1µF + 1 INa INb 32 2 NC NC 31 3 OUTa 4 NC 0.1µF + OUTb 30 NC 29 2.2nF 2.2nF 5 TONE-Ha TONE-Hb 28 100nF 100nF 1 µF 1 µF + 1 µF + 6 TONE-La 7 AGC TONE-Lb 27 8 CVO CBA 25 9 CSR CTL 24 10 ADR0 CTH 23 11 ADR1 AUX1 22 12 SDA AUX0 21 13 NC NC 14 SCL Vref 19 13 NC NC 16 GND 3.9kΩ 3.9kΩ 22nF SR FIL 26 1 µF + 1 µF + 1µF + 20 1 µF + 20 V+ 17 + 22 µF (NOTE) Separate the I2C bus line from the following terminals for avoiding digital noise problem. Pin No. Symbol Pin No. Symbol Pin No. Symbol 5 TONE-Ha 26 SR FIL 28 TONE-Hb 6 TONE-La 27 TONE-Lb - - 10 - NJW1143A Q DEFINITION OF I2C REGISTER O I2C BUS FORMAT MSB S LSB Slave Address 1bit 8bit MSB LSB MSB A Select Address 1bit 8bit A 1bit LSB Data 8bit A P 1bit 1bit S: Starting Term A: Acknowledge Bit P: Ending Term O SLAVE ADDRESS MSB LSB 1 0 0 0 0 ADR1 ADR0 R/W ADR0, ADR1: Hardware pin programmable address bits ADR1 ADR0 Address 0 0 1 1 0 1 0 1 80H 82H 84H 86H R/W=0: Write mode for register setting R/W=1: Not available O CONTROL REGISTER TABLE The select address sets each function (Volume, Balance, AGC, Tone Control, Surround etc.). The auto-increment function cycles the select address as follows. 00H→01H→02H→03H→00H Select Address BIT D7 D6 D4 D5 D3 D2 D1 D0 VOL 00H 01H CHS BAL SUR 02H BCB BASS AGC-SW 03H BCT TREB Don’t Care AUX1 AUX0 AGC-FLAT O CONTROL REGISTER DEFAULT VALUE Control register default value is all “0”. Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 00H 0 0 0 0 0 0 0 0 01H 0 0 0 0 0 0 0 0 02H 0 0 0 0 0 0 0 0 03H 0 0 0 0 0 0 0 0 - 11 - NJW1143A Q I2C CONTROL COMMAND DESCRIPTION OMASTER VOLUME CONTROL Select Address BIT D7 D6 D5 D4 D3 D2 D1 D0 VOL 00H The volume controls both Ach and Bch by the 0.5dB step. The volume is consisted of volume1 and volume2. The level is divided into half to each volume1 and volume2. OBALANCE, AGC AND INPUT SELECTOR SETTINGS BIT Select Address D7 01H CHS D6 D5 D4 D3 D2 D1 BAL D0 SUR •CHS: Channel select for balance control “0”: Ach “Bch is attenuated” “1”: Bch “Ach is attenuated” •BAL: Balance control for both Ach and Bch (1dB/Step) The balance is consisted of volume2 alone. Volume1 does not operate on balance. •SUR : Surround Setting SUR Surround Setting Remarks D1 D0 Surround OFF 0 0 Input through Simulated Stereo mode 0 1 For monaural signal input only "eala" High mode 1 0 Surround Effect Small (4.0dB typ.) "eala" Low mode 1 1 Surround Effect Large (8.0dB typ.) OTONE CONTROL (Bass) and AGC SETTINGS BIT Select Address D7 02H BCB D6 D5 D4 D3 BASS AGC-SW •BCB : Bass Boost or Cut “0” : Cut “1” : Boost •BASS : BASS Level Cut Level : -15 to 0dB(1dB/Step) Boost Level : 0 to +15dB(1dB/Step) •AGC-SW : AGC ON/OFF Switch “0” : AGC OFF “1” : AGC ON (Default : 125mVrms) •AGC-FLAT : AGC Flat Level AGC Flat Level 125mVrms 250mVrms 375mVrms 500mVrms - 12 - AGC-FLAT D1 0 0 1 1 D2 D0 0 1 0 1 D1 D0 AGC-FLAT NJW1143A OTONE CONTROL (Treble) and FOCUS EFFECT SETTINGS BIT Select Address D7 03H BCT D6 D5 D4 TREB D3 D2 D1 D0 Don't Care AUX1 AUX0 •BCT : Treble Boost or Cut “0” : Cut “1” : Boost •TREB : Treble Level Cut Level : -15 to 0dB(1dB/Step) Boost Level : 0 to +15dB(1dB/Step) •AUX1/AUX0: Auxiliary port High/Low “0”: Logic output ”Low” “1”: Logic output ”High” - 13 - NJW1143A Q Master Volume (Select Address: 00H) VOL Gain(dB) HEX D7 D6 D5 D4 D3 D2 D1 D0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 FF FD FB F9 F7 F5 F3 F1 EF ED EB E9 E7 E5 E3 E1 DF DD DB D9 D7 D5 D3 D1 CF CD CB C9 C7 C5 C3 C1 BF BD BB B9 B7 B5 B3 B1 AF AD AB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 14 - NJW1143A MASTER VOLUME (Cont'd) VOL Gain(dB) HEX D7 D6 D5 D4 D3 D2 D1 D0 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -90 -100 Mute A9 A7 A5 A3 A1 9F 9D 9B 99 97 95 93 91 8F 8D 8B 89 87 85 83 81 7F 7D 7B 79 77 75 73 71 6F 6D 6B 69 67 65 63 61 5F 4B 37 00 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 - 15 - NJW1143A Q Balance (Select Address: 01H) CHS Channel Setting D7 Attenuated Bch Gain Attenuated Ach Gain D6 D5 BAL D4 D3 D2 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 -23 -24 1 1 0 1 1 0 1 0 1 0 -25 -26 -27 -28 -29 -30 MUTE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Gain(dB) - 16 - 0 1 NJW1143A Q Tone Control Bass (Select Address: 02H) Bass Cut or Boost BCB D7 Cut 0 Boost 1 BASS Cut Gain(dB) Boost Gain(dB) D6 D5 D4 D3 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Q Tone Control Treble (Select Address: 03H) Treble Cut or Boost BCT D7 Cut Boost 0 1 TREB Cut Gain(dB) Boost Gain(dB) D6 D5 D4 D3 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 17 -