R1EX24064ASAS0A R1EX24064ATAS0A Two-wire serial interface 64k EEPROM (8-kword × 8-bit) REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Description R1EX24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MONOS memory technology and CMOS process and low voltage circuitry technology. They also have a 32-byte page programming function to make their write operation faster. Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology’s sales office before using industrial applications such as automotive systems, embedded controllers, and meters. Features • • • • • • • • Single supply: 1.8 V to 5.5 V Two-wire serial interface (I2C serial bus) Clock frequency: 400 kHz Power dissipation: Standby: 2 µA (max) Active (Read): 1 mA (max) Active (Write): 3.0 mA (max) Automatic page write: 32-byte/page Write cycle time: 5 ms Endurance: 1,000k Cycles @ 25°C Data retention: 100 Years @ 25°C REJ03C0332-0200 Page 1 of 22 Rev.2.00 Oct.26, 2009 R1EX24064AxxS0A Small size packages: SOP-8pin, TSSOP-8pin • Shipping tape and reel TSSOP 8-pin: 3,000 IC/reel SOP 8-pin: 2,500 IC/reel • Temperature range: −40 to +85°C • Lead free products. Ordering Information Type No. Internal organization Operating voltage Frequency Package R1EX24064ASAS0A 64k bit (8192 × 8-bit) 1.8 V to 5.5 V 400 kHz 150 mil 8-pin plastic SOP PRSP0008DF-B (FP-8DBV) Lead free R1EX24064ATAS0A 64k bit (8192 × 8-bit) 1.8 V to 5.5 V 400 kHz 8-pin plastic TSSOP PTSP0008JC-B (TTP-8DAV) Lead free Pin Arrangement 8-pin SOP /8-pin TSSOP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (Top view) Pin Description Pin name Function A0 to A2 Device address SCL Serial clock input SDA Serial data input/output WP Write protect VCC Power supply VSS Ground REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 2 of 22 R1EX24064AxxS0A Block Diagram High voltage generator Control logic A0, A1, A2 SCL X decoder WP Address generator VSS Memory array Y decoder VCC Y-select & Sense amp. SDA Serial-parallel converter Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC −0.6 to +7.0 Vin −0.5* to +7.0* V Operating temperature range* Topr −40 to +85 °C Storage temperature range Tstg −55 to +125 °C Input voltage relative to VSS 1 Unit 2 V 3 Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): −3.0 V for pulse width ≤ 50 ns. 3. Should not exceed VCC + 1.0 V. DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 1.8 5.5 V VSS 0 0 0 V Input high voltage VIH VCC × 0.7 VCC + 0.5 V Input low voltage VIL −0.3*1 VCC × 0.3 V Operating temperature Topr −40 +85 °C Notes: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns. REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 3 of 22 R1EX24064AxxS0A DC Characteristics (Ta = −40 to +85°C, VCC = 1.8 V to 5.5 V) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current ILI 2.0 µA VCC = 5.5 V, Vin = 0 to 5.5 V Output leakage current ILO 2.0 µA VCC = 5.5 V, Vout = 0 to 5.5 V Standby VCC current ISB 1.0 2.0 µA Vin = VSS or VCC Read VCC current ICC1 1.0 mA VCC = 5.5 V, Read at 400 kHz Write VCC current ICC2 3.0 mA VCC = 5.5 V, Write at 400 kHz Output low voltage VOL2 0.4 V VCC = 2.7 to 5.5 V, IOL = 3.0 mA VOL1 0.2 V VCC = 1.8 to 2.7 V, IOL = 1.5 mA Capacitance (Ta = +25°C, f = 1 MHz) Parameter Symbol Min Typ Max Unit Test conditions Input capacitance (A0 to A2, SCL, WP) Cin*1 6.0 pF Vin = 0 V CI/O*1 6.0 pF Vout = 0 V Output capacitance (SDA) Note: 1. Not 100% tested. Memory cell characteristics (VCC = 1.8 V to 5.5 V) Ta=25°C Ta=85°C Endurance 1,000k Cycles min. 100k Cycles min 1 Data retention 100 Years min. 10 Years min. 1 Notes: 1. Not 100% tested. REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 4 of 22 Notes R1EX24064AxxS0A AC Characteristics (Ta = −40 to +85°C, VCC = 1.8 to 5.5 V) Test Conditions • Input pules levels: VIL = 0.2 × VCC VIH = 0.8 × VCC • Input rise and fall time: ≤ 20 ns • Input and output timing reference levels: 0.5 × VCC • Output load: TTL Gate + 100 pF Parameter Symbol Min Typ Max Unit Clock frequency fSCL 400 kHz Clock pulse width low tLOW 1200 ns Clock pulse width high tHIGH 600 ns Noise suppression time tI 50 ns Access time tAA 100 900 ns Bus free time for next mode tBUF 1200 ns Notes 1 Start hold time tHD.STA 600 ns Start setup time tSU.STA 600 ns Data in hold time tHD.DAT 0 ns Data in setup time tSU.DAT 100 ns Input rise time tR 300 ns 1 Input fall time tF 300 ns 1 Stop setup time tSU.STO 600 ns Data out hold time tDH 50 ns Write protect hold time tHD.WP 1200 ns Write protect setup time tSU.WP 0 ns Write cycle time tWC 5 ms Notes: 1. Not 100% tested. 2. tWC is the time from a stop condition to the end of internally controlled write cycle. REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 5 of 22 2 R1EX24064AxxS0A Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) tSU.WP tHD.WP WP Write Cycle Timing Stop condition Start condition SCL SDA D0 in Write data (Address (n)) ACK REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 6 of 22 tWC (Internally controlled) R1EX24064AxxS0A Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output Data (SDA) The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during the SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high change of SDA should be done during the SCL low period. REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 7 of 22 R1EX24064AxxS0A Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to VCC or VSS. When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. These pins are internally pulled-down to VSS. The device reads these pins as Low if unconnected. Pin Connections for A0 to A2 Pin connection Max connect Memory size number A2 A1 A0 64k bit VCC/VSS VCC/VSS VCC/VSS Note: 8 Note 1. During floating, “VCC/VSS” are fixed to VSS. Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write data, acknowledgment "1""(NO ACK) is outputted. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. The WP pin is internally pulled-down to VSS. Write operations for all memory array are allowed if unconnected. Write Protect Area Write protect area WP pin status 64k bit VIH Full (64k bit) VIL Normal read/write operation REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 8 of 22 R1EX24064AxxS0A Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start condition and stop condition). Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in a internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode (See write cycle timing). Start Condition and Stop Condition SCL SDA (in) Start condition REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 9 of 22 Stop condition R1EX24064AxxS0A Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL 1 SDA IN SDA OUT REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 10 of 22 2 8 9 Acknowledge out R1EX24064AxxS0A Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of all devices which are connected to the bus. This means that the device is selected if the inputted 3-bit device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond hard-wired device address pins A0 to A2. Device Address Word Device address word (8-bit) Device code (fixed) 64k Note: 1 0 R/W code*1 Device address code 1 0 1. R/W=“1” is read and R/W = “0” is write. REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 11 of 22 A2 A1 A0 R/W R1EX24064AxxS0A Write Operations(WP=Low) Byte Write: (Write operation during WP=Low status) A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 64kbit EEPROM receives 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. Byte Write Operation 2nd Memory address (n) Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 1st Memory address (n) 64k 1010 Start a12 a11 a10 a9 a8 *1 *1 *1 Device address a7 a6 a5 a4 a3 a2 a1 a0 WP W ACK R/W Note: 1. Don't care bit REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 12 of 22 ACK ACK ACK Stop R1EX24064AxxS0A Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 32 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop condition. The a0 to a4 address bits are automatically incremented upon receiving write data (Dn+1). The EEPROM can continue to receive write data up to 32 bytes. If the a0 to a4 address bits reaches the last address of the page, the a0 to a4 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Page Write Operation WP 1st Memory address (n) 2nd Memory address (n) Write data (n) Write data (n+m) Start ACK R/W Note: 1. Don't care bit REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 13 of 22 ACK ACK D5 D4 D3 D2 D1 D0 W D7 D6 D5 D4 D3 D2 D1 D0 1010 a7 a6 a5 a4 a3 a2 a1 a0 64k a12 a11 a10 a9 a8 *1 *1 *1 Device address ACK ACK Stop R1EX24064AxxS0A Write Operations(WP=High) Byte Write: (Write operation during WP=High status) A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 64kbit EEPROM receives 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0". After receipt of 8-bit write data, the EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed. Byte Write Operation 2nd Memory address (n) Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 1st Memory address (n) No ACK 64k 1010 Start a12 a11 a10 a9 a8 *1 *1 *1 Device address a7 a6 a5 a4 a3 a2 a1 a0 WP W ACK R/W Note: 1. Don't care bit REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 14 of 22 ACK ACK Stop R1EX24064AxxS0A Page Write: The page write is the same sequence as the byte write. The page write is initiated by a start condition, device address word and memory address(n) with every ninth bit acknowledgment"0". But after inputting write data(Dn) , the EEPROM outputs acknowledgment "1"(NO ACK). Then the EEPROM write operations are not allowed. Page Write Operation WP 1st Memory address (n) 2nd Memory address (n) Write data (n) No ACK No ACK Write data (n+m) Start ACK R/W Note: 1. Don't care bit REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 15 of 22 ACK ACK D5 D4 D3 D2 D1 D0 W D7 D6 D5 D4 D3 D2 D1 D0 1010 a7 a6 a5 a4 a3 a2 a1 a0 64k a12 a11 a10 a9 a8 *1 *1 *1 Device address Stop R1EX24064AxxS0A Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK. Write Cycle Polling Using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation Send memory address Send start condition Proceed random address read operation Send stop condition REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 16 of 22 Send stop condition R1EX24064AxxS0A Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit current address data from the most significant bit following acknowledgment “0”. If the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation Device address 1010 Start REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 17 of 22 Read data (n+1) R D7 D6 D5 D4 D3 D2 D1 D0 64k ACK R/W No ACK Stop R1EX24064AxxS0A Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 × 8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “1”(no acknowledgment) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation Start Device address W ACK R/W ACK 1010 Start ACK Dummy write Notes: 1. Don't care bit 2. 2nd device address code (#) should be same as 1st (@). REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 18 of 22 Read data (n) # # # R R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 2nd Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 1010 @@@ a12 a11 a10 a9 a8 64k 1st Memory address (n) *1 *1 *1 Device address No ACK Stop Current address read R1EX24064AxxS0A Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgment “1” (no acknowledgment) and a following stop condition. Sequential Read Operation ACK R/W REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 19 of 22 ACK ACK ACK D5 D4 D3 D2 D1 D0 R Read data (n+1) Read data (n+2) Read data (n+m) D7 D6 D5 D4 D3 D2 D1 D0 Start 1010 D7 D6 D5 D4 D3 D2 D1 D0 64k Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 Device address No ACK Stop R1EX24064AxxS0A Notes Data Protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. • SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. • VCC should be turned off after the EEPROM is placed in a standby state. • VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional programming mode. • VCC turn on rate should be longer than 2 µs/V. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 20 of 22 R1EX24064AxxS0A Package Dimensions R1EX24064ASAS0A (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code P-SOP8-3.9x4.89-1.27 RENESAS Code PRSP0008DF-B *1 Previous Code FP-8DBV MASS[Typ.] 0.08g D 8 F NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 5 *2 c E HE bp Index mark Terminal cross section ( Ni/Pd/Au plating ) Reference Dimension in Millimeters Symbol 4 1 Z e *3 bp x M A L1 A1 θ L y Detail F REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 21 of 22 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 4.89 5.15 3.90 0.102 0.14 0.254 1.73 0.35 0.40 0.45 0.15 0.20 0.25 0° 8° 5.84 6.02 6.20 1.27 0.25 0.10 0.69 0.406 0.60 0.889 1.06 R1EX24064AxxS0A R1EX24064ATAS0A (PTSP0008JC-B / Previous Code: TTP-8DAV) JEITA Package Code P-TSSOP8-4.4x3-0.65 RENESAS Code PTSP0008JC-B *1 Previous Code TTP-8DAV MASS[Typ.] 0.034g D 8 F 5 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c *2 E HE bp Terminal cross section ( Ni/Pd/Au plating ) Reference Dimension in Millimeters Symbol Index mark L1 1 e *3 bp x M θ A1 A Z 4 L Detail F y REJ03C0332-0200 Rev.2.00 Oct. 26, 2009 Page 22 of 22 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 3.00 3.30 4.40 0.03 0.07 0.10 1.10 0.15 0.20 0.25 0.10 0.15 0.20 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.805 0.40 0.50 0.60 1.00 Revision History Rev. Date R1EX24064AxxS0A Data Sheet Contents of Modification Page Description 0.01 Nov. 05, 2007 Initial issue 1.00 April. 21, 2008 Deletion preliminary 1.01 Jan.13, 2009 P1 Features Power dissipation Active(write) change 3.5mA to 3.0mA. 6 Endurance cycles change 10 cycles to 1,000k cycles @ 25°C. Data retentions years change 10 years to 100 years @ 25°C. P4 DC characteristics Write Vcc current change 3.5 mA to 3.0 mA. Memory cell characteristics new is described. P5 AC characteristics Erase/Write endurance is deleted. Notes1. change Not 100% tested. Notes3 deleted. 2.00 Oct.26, 2009 P8 Addition of device address description These pins are internally pulled-down to Vss. The device reads these pins as Low if unconnected. Addition of write protect description The WP pin is internally pulled-down to Vss. Write operations for all memory array are allowed if unconnected. P20 Change of Vcc turn on description ·Vcc turn on speed should be longer than 10 µs . to ·Vcc turn on rate should be longer than 2 µs/V. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. 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