Slide 1 Extracting RF Mosfet Spice Models MTT 1998 - Baltimore Md. by S. K. Leong Polyfet Rf Devices www.polyfet.com This presentation is available on our web site Slide 2 Why simulate? n n n n n n n Simulation - It’s the only way! Fast accurate results. What if analysis. Too time consuming to do it by hand or by Smith chart. S-Parameters - Linear simulation only. Spice simulates - power, gain, efficiency and harmonics (IMD). Non Linear parameters. Takes harmonic loading into consideration. Generate large signal impedance data, Zin and Zout, without building test fixtures. With today’s simulation tools available, high power rf design does not have to be a tedious task anymore. The days of trail and error are passe and soon too will be manual graphing on the Smith Chart. Unlike linear designs using S parameters, the lack of good high power transistor models has hampered the industry from using simulation for non-linear designs. Polyfet RF Devices supplies Spice Models for all their transistors. For other manufacturers, it might be necessary to extract models for your own use. The following graphs show simulation vs. actual measured results demonstrating the usefulness of simulation. Unlike using S parameters or Zin Zout, using Spice provides the advantage of analyzing non-linear behavior and efficiency. With today’s requirements in designing for digital radios linearity and efficiency are critical parameters and simulation using Spice enable accurate results. Slide 3 Sim. Vs Meas. Pout and Gain Pout F=300MHZ, VDS=7.5V, Idq=.6A 5 12 4.5 11 10 4 3.5 9 Gain Pout 3 8 2.5 7 2 6 1.5 5 1 4 0.5 3 2 0 0 0.2 0.4 0.6 0.8 1 1.2 P IN IN W A T T S POUT S imulated Pout G A IN S imulated Gain Demonstration of Accuracy in simulating Power output and gain of amplifier. Slide 4 Sim. Vs Meas. Gain & Effic. F re q v s G a i n , P i n = 4 0 0 m w , V D S = 7 . V , I d q = . 6 A 16 80% 70% Efficiency 14 60% 50% 12 40% 30% Gain 10 20% 10% 8 0% 225 250 275 300 325 350 375 400 Fre q i n M H z G A IN S imula te d G a in E fficie n c y S i m E ffic ie n c y Demonstration of accuracy in simulating gain and efficiency over a broad bandwidth. Slide 5 Sim. Vs Meas. Harmonics Mo d u l e F r e q v s H a r m o n i c s , P i n = 4 0 0 m w , V D S = 7 . V , Idq=.6A 0 -10 -20 -30 -40 -50 -60 225 250 275 300 325 Fre q in MHz Me a s u r e d Demonstration of simulation of 2nd Harmonic 350 S imulated 375 400 Slide 6 Steps for Spice Extraction DC Model. IV curve matching n AC model - Generate Power Dependent S parameters. n Final model - Device and Package Parasitics. Optimize to match S parameters. n Procedures to extract Spice models Reference Books:Semiconductor Device Modeling - Palo Antognetti and Giuseppe Massobrio Spice-Practical Device Modeling - Ron Kielkowski “Spicing-up SPICE II Software for Power Mosfet Modeling” Dolny et el. RCA Application Note AN-8160 “Device Modeling High Power DMOS Transistor Amplifiers” Steve Hamilton and Octavius Pitzalis Jr. EEsof Application Note. Need to measure DC characteristics, capacitances and S parameters in order to generate Spice models Slide 7 DC Model n n n n Good to know Gate Length (channel length) and Gate Width (Perimeter) Measure IV curves. Curve fit model to IV data. Mosfet in series with Jfet. Spice - Berkeley 2G.6 Level 1. 6 5 4 ID IN AMPS n 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 22 VDS IN VOLTS vg=2v Vg=4v Vg=6v vg=8v vg=10v vg=12v Device design information is needed from Manufacturer. - gate length and gate Width. If not, set L/W=1 and adjust Kp to fit. Use Curve tracer or equivalent to measure I-V curves. Curve fit IV plot. Vt, Kp can be extracted by measuring Id Vs Vgs. Slide 8 Circuit Representation Schematic representation of Spice Model showing Mosfet and Jfet. Applies to both VDMOS and LDMOS. Slide 9 Why JFET Ldmos Cross section view of VDMOS showing parasitic Jfet in the vertical drain region. LDMOS has a horizontal drain drift region which is modeled by using the Jfet. Slide 10 AC Model Take capacitance measurements of Coss, Ciss and Crss Vs bias voltage. n Develop Body Diode parameters - M, Vj and Rs. n Generate Power Dependent S parameters. Bias at S-para S-para Idq. n Breakdown voltage of Body Diode is important. n Measure the 3 parasitic capacitances. Use the Coss curve Vs bias voltage to obtain Vj and m for the body diode. Set bias current at the current level used to measure S parameters. Generate Power Dependent S parameters. Body Diode BV setting is important. Power Dependent S parameter is generated from the 3 active elements - MOSFET, JFET and DBODY Slide 11 Final Model n n n Measure S parameters of device at highest possible Idq - limited by Bias Tee and bandwidth. Add parasitic inductances and capacitances to model. Optimize to match S parameters. Finalize the Spice model with package capacitances. A linear simulator is used to match measured data to simulated data. Simulation programs with optimization capability is necessary in order to perform this operation. Using the optimizer, parasitic capacitances and inductances are varied so simulated Sparameter best match measured S-parameters data. Slide 12 Validate and Verify Simulate and build amp. n Watch out for optimizer limitations. n Watch out for harmonics loading. n Practice and build on experience. n It is not expected to have the simulated data and the built up amplifier to be identical. Since transistors vary from lot to lot, fine tuning at the amplifier level is expected. The values of inductance and capacitance can vary from simulation to final can be off as much as 25%. However, without simulation, we wouldn’t even be this close. Often manual tuning is required as Optimizer has limitations. It is also found useful to simulate Zin Zout values and use those as loads to optimize the matching network, rather than letting the Optimizer match the matching network to the transistor.