PDF Spec - Raltron Electronics Corporation

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VE/VC8825A-LZ-100-FREQ-CF-EL
VE/VC8925A-LZ-100-FREQ-CF-EL (3.3V)
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Specifically designed for OC192; FEC applications
Meets SONET Jitter requirement
Available at 3.3V***** (Shall use 9 in the 2nd figure P/N location… Example; VC8925A…)
Enable/Disable – optional Feature
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MECHANICAL SPECIFICATION
OUTLINE TOLERANCE:
±0.015” / 0.4mm
PIN FUNCTIONS:
[1] CONTROL VOLTAGE
[2] ENABLE / DISABLE
[3] CASE / GROUND
[4] OUTPUT
[5] COMP. OUTPUT
[6] SUPPLY VOLTAGE
MARKING:
VE8825A-LZ-100
FREQ-CF-EL
RAL D/C
DIMENSION:
A: 0.031~0.039” / 0.8~1.0mm
B: 0.031~0.039” / 0.8~1.0mm
C: 0.047~0.059” / 1.2~1.5mm
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ELECTRICAL SPECIFICATION
PARAMETER
Frequency, nom
Supply voltage, nom.
Supply current, max.
SYMBOL
fo
Vcc
Is
PECL output level
Duty cycle
VOH / VOL
DC
Rise- / fall time, max.
Jitter, rms, max.
Freq. stability vs. temperature,
max.
Freq. stability vs. supply, max.
Freq. stability vs. load, max.
Aging characteristics, max.
tr / tf
J
∆f/fc(Ta)
Control voltage range
Freq. pulling range, min.
Settability
Linearity, max.
Input impedance, min.
Modulation freq. bandwidth, min.
Vc
∆f/fc
Vfo
∆f/V
Zin
MBW(-3dB)
Enable option
Disable option
En
Dis
Pin 2=Low, Vcc-1.620 (max.)
Pin 2=High, Vcc-1.025 (min.)
Enabled
Operating temperature range
Storage temperature range
Absolute voltage ranges
Ta
T(stg)
Vcc, Vc(abs)
Non-destructive, DC
0…+70
-40…+90
-0.5…+7.0
∆f/fc(∆Vcc)
∆f/fc(∆load)
∆f/fc(∆t)
CONDITIONS
VALUE
622.08; 666.5143; 669.3266
+5.0; +3.3
135.0
Vcc±5%
Vcc=nom, Vc=0.5*Vcc,
Ta=+25°C, 50Ω to Vcc-2.0VDC load
Vcc=nom, load=50Ω to Vcc-2.0VDC
load=50Ω to Vcc-2.0VDC / @ 50%Vcc,
Ta=+25°C
20%~80% Vout, 80%~20% Vout, max
1σ, Fj= 12kHz…20MHz
Ta=0°C…+70°C, (ref. to +25°C)
± 5% Supply change
± 10%Load change
∆t=1st year
∆t=per year thereafter
DC
over the control voltage range
Ta=+25°C ±1°C
Positive slope
Vcc=nom, Vc=0.5*Vcc,
Ta=+25°C, 50Ω to Vcc-2.0VDC load
RALTRON ELECTRONICS CORP. ! 10651 N.W . 19
th
Vcc-1.025/Vcc-1.62
40…60
UNIT
MHz
V
mA
V
%
0.550
1.0
±25.0
ns
ps
ppm
±5.0
±3.0
±4.0
±2.0
+0.5…+4.5 (0…3.3 @Vcc-=3.3V)
±100.0
+2.5 ± 0.5 (+1.65±0.25 @ Vcc=3.3V)
± 10.0
10.0
10.0
ppm
ppm
ppm
ppm
V
ppm
V
%
KΩ
KHz
Pin 4 will assume a fixed level of logic “0”,
and pin 5 will assume a fixed level of logic“1”
St ! Miami, Florida 33172 ! U.S.A.
phone: +001(305) 593-6033 ! fax: +001(305)594-3973 ! e-mail: [email protected] ! internet: http:/www.raltron.com
°C
°C
V
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TIMING DIAGRAM
PECL WAVEFORM
+5.0 VDC
+3.975 VDC
+3.5 VDC
+3.38 VDC
GND
TIME
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ELECTRICAL TEST DIAGRAM
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REFLOW SOLDER
RALTRON ELECTRONICS CORP. ! 10651 N.W . 19
th
St ! Miami, Florida 33172 ! U.S.A.
phone: +001(305) 593-6033 ! fax: +001(305)594-3973 ! e-mail: [email protected] ! internet: http:/www.raltron.com