micrf507

MICRF507
470MHz to 510MHz Low-Power FSK
Transceiver with +10dBm Power Amplifier
General Description
The MICRF507 is a fully-integrated FSK transceiver with
+10dBm power amplifier and transmit/receive switch. The
device is targeted at automated meter reading (AMR)
applications in the China Short Range Device (SRD)
frequency band of 470MHz to 510MHz. The device
supports data rates up to 20kbps with PLL divider
modulation and up to 200kbps with VCO modulation. The
receiver achieves a sensitivity of -113dBm at a data rate of
2.4kbps while only consuming 12mA of supply current.
The integrated power amplifier (PA) delivers +10dBm of
output power while only consuming 21.5mA of supply
current. Power down supply current is a low 0.2µA while
retaining register information and a low 280µA in standby
mode where only the crystal oscillator is enabled.
The receiver of the MICRF507 utilizes a Zero IF (ZIF) I/Q
architecture, integrating a low-noise amplifier (LNA) with
bypass mode, I/Q quadrature mixers, three-pole SallenKey IF channel pre-filters, and six-pole elliptic switched
capacitor IF filters, providing excellent selectivity, adjacent
channel rejection and blocking performance. FSK
demodulation is implemented digitally and a synchronizer,
when enabled, recovers the received bit clock. A receive
signal strength indicator (RSSI) circuit indicates the
received signal level over a 50dB range. An integrated
Frequency Error Estimator (FEE) and crystal tuning
capability allow fine tuning of the RF frequency.
The transmitter of the MICRF507 consists of an FSK
modulator and power amplifier with output power
adjustable from +10dBm to -3.5dBm in seven steps.
Modulation can be achieved by applying two sets of PLL
divider ratios or through direct VCO modulation by varying
VCO tank capacitance.
The MICRF507 requires a 2.0V to 2.5V supply voltage,
operates over the -40˚C to +85˚C temperature range, and
is available in a 32-pin QFN package.
RadioWire®
Features
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-113dBm sensitivity at 2.4kbps encoded bit rate
+10dBm power amplifier with seven gain steps
12mA receive supply current
21.5mA transmit supply current at +10dBm
0.2μA power down current (registers retain settings)
280µA standby current (crystal oscillator enabled)
Data rates up to 20kbps with PLL divider modulation
Data rates up to 200kbps with VCO modulation
Integrated transmit and receive (T/R) switch
LNA with bypass mode
Zero IF I/Q receiver architecture
IF pre-amplifiers with DC-offset removal
Three-pole Sallen-Key IF channel low-pass pre-filter
Six-pole elliptic switched capacitor IF low-pass filter
50kHz to 350kHz programmable baseband bandwidth
59dB blocking at ±1MHz offset
53dB adjacent channel rejection at ±500kHz offset
FSK digital demodulator with clock recovery
50dB Received Signal Strength Indicator (RSSI)
Frequency Error Estimator (FEE)
Reference crystal tuning capability
2.0 to 2.5V supply voltage range
-40˚C to +85˚C operating temperature range
Available in 32-pin QFN package
(5.0mm × 5.0mm × 0.85mm)
Applications
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China Short Range Device (SRD) Communications
Automated Meter Reading (AMR)
Advanced Metering Infrastructure (AMI)
Wireless Remote Meter Reading
RadioWire is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2, 2013
Revision 2.2
Micrel, Inc.
MICRF507
®
RadioWire FSK Transceiver Selection Guide ................................................................................................................ 4
Ordering Information ......................................................................................................................................................... 4
Pin Configuration ............................................................................................................................................................... 4
Pin Description ................................................................................................................................................................... 4
Block Diagram .................................................................................................................................................................... 6
Absolute Maximum Ratings .............................................................................................................................................. 7
Operating Ratings .............................................................................................................................................................. 7
Electrical Characteristics .................................................................................................................................................. 7
Functional Description .................................................................................................................................................... 10
Control (3-wire) Interface ...................................................................................................................................... 10
Reading ................................................................................................................................................................. 13
Control Interface Timing ........................................................................................................................................ 14
Power-on Reset .................................................................................................................................................... 14
Clock Generation ............................................................................................................................................................. 15
Crystal Oscillator (XCO) .................................................................................................................................................. 16
BITSYNC_CLK (Receiver Bit Synchronization Clock) .......................................................................................... 17
BITRATE_CLK (Transmitter Bit Rate Clock) ........................................................................................................ 17
MODULATOR_CLK (VCO Modulator Clock) ........................................................................................................ 17
Data Interface and Bit Synchronization ......................................................................................................................... 17
Sync_en = 0 .......................................................................................................................................................... 19
Sync_en = 1 .......................................................................................................................................................... 19
Additional Considerations in the Use of Synchronizer (Sync_en = 1) .................................................................. 19
Frequency Synthesizer .................................................................................................................................................... 20
VCO....................................................................................................................................................................... 22
Charge Pump ........................................................................................................................................................ 22
PLL Filter ............................................................................................................................................................... 22
Lock Detect ........................................................................................................................................................... 23
Receiver ............................................................................................................................................................................ 24
Front End............................................................................................................................................................... 24
Sallen-Key Filters .................................................................................................................................................. 25
Switched Capacitor Filter ...................................................................................................................................... 25
RSSI ...................................................................................................................................................................... 25
FEE ....................................................................................................................................................................... 26
XCOtune Procedure Example ......................................................................................................................................... 27
Transmitter........................................................................................................................................................................ 28
Power Amplifier ..................................................................................................................................................... 28
Frequency Modulation........................................................................................................................................... 29
Divider Modulation ................................................................................................................................................ 30
VCO Modulation and the Modulator ...................................................................................................................... 30
Modulator Filter ..................................................................................................................................................... 32
System Modes and Initialization ..................................................................................................................................... 33
Start-up and Initialization....................................................................................................................................... 33
Modes of Operation ............................................................................................................................................... 33
Mode Transitions ................................................................................................................................................... 33
Message Coding and Formatting ................................................................................................................................... 34
DC Balanced Line Coding ..................................................................................................................................... 34
Message Formatting: Preamble ............................................................................................................................ 34
Typical Application .......................................................................................................................................................... 35
October 2, 2013
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Revision 2.2
Micrel, Inc.
MICRF507
Bill of Materials ................................................................................................................................................................. 36
Layout Considerations .................................................................................................................................................... 37
Layer Definition ..................................................................................................................................................... 37
Grounding.............................................................................................................................................................. 37
RF Traces.............................................................................................................................................................. 37
Supply Routing ...................................................................................................................................................... 37
PLL Loop Filter ...................................................................................................................................................... 37
Overview of Programming Bits....................................................................................................................................... 38
Detailed Description of Programming Bits .................................................................................................................... 39
Package Information and Recommended Landing Pattern ......................................................................................... 46
October 2, 2013
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Revision 2.2
Micrel, Inc.
MICRF507
RadioWire® FSK Transceiver Selection Guide
Part Number
Frequency Range
Maximum Data
Rate
Receive
Current
Supply Voltage
Transmit Current
Package
MICRF505
850MHz to 950MHz
200kbps
13.5mA
2.0 to 2.5V
28mA
QFN-32
MICRF505L
850MHz to 950MHz
200kbps
13.5mA
2.25 to 5.5V
28mA
QFN-32
MICRF506
410MHz to 450MHz
200kbps
12mA
2.0 to 2.5V
21.5mA
QFN-32
MICRF507
470MHz to 510MHz
200kbps
12mA
2.0 to 2.5V
21.5mA
QFN-32
Ordering Information
Part Number
MICRF507YML TR
Junction Temperature Range
Package
-40° to +85°C
Pb-Free 32-Pin QFN
Pin Configuration
32-Pin QFN
Pin Description
Pin Number
Pin Name
Type
Pin Function
1
RFGND
2
PTATBIAS
3
RFVDD
LNA and PA power supply.
4
RFGND
LNA and PA ground.
LNA and PA ground.
O
5
ANT
6
RFGND
LNA and PA ground.
7
RFGND
LNA and PA ground.
October 2, 2013
I/O
Connection for bias resistor.
Antenna Input/Output.
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Revision 2.2
Micrel, Inc.
MICRF507
Pin Description (Continued)
Pin Number
Pin Name
8, 16, 17, 32
NC
9
CIBIAS
10
IFVDD
Type
Pin Function
No connect. Leave these pins floating.
O
Connection for bias resistor.
IF/mixer power supply.
11
IFGND
12
ICHOUT
O
Test pin.
IF/mixer ground.
13
QCHOUT
O
Test pin.
14
RSSI
O
Received signal strength indicator.
15
LD
O
PLL lock indicator.
18
DATACLK
O
RX/TX data clock output.
19
DATAIXO
I/O
RX/TX data input/output.
20
IO
I/O
3-wire interface data in/output
21
SCLK
I
3-wire interface serial clock.
22
CS
I
3-wire interface chip select.
23
XTALIN
I
24
XTALOUT
I/O
25
DIGVDD
Digital power supply.
26
DIGGND
Digital ground.
27
CPOUT
28
GND
29
VARIN
30
VCOGND
VCO ground.
31
VCOVDD
VCO power supply.
Exposed Paddle
October 2, 2013
O
Crystal oscillator input.
Crystal oscillator output or external reference input.
PLL charge pump output.
Substrate ground.
I
VCO varactor tune voltage input.
Ground.
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Revision 2.2
Micrel, Inc.
MICRF507
Block Diagram
October 2, 2013
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Revision 2.2
Micrel, Inc.
MICRF507
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD) ................................................... +2.7V
Voltage on any pin (GND = 0V). ............. -0.3V to +2.7V
Lead Temperature (soldering, 4sec.) ......................... 300°C
Storage Temperature (Ts) .......................... -55°C to +150°C
(3)
ESD Rating .................................................................. 2kV
Supply Voltage (VIN).................................. +2.0V to +2.5V
RF Frequencies ................................ 470MHz to 510MHz
Encoded Bit Rate .................................................200kbps
Ambient Temperature (TA) ....................... –40°C to +85°C
Package Thermal Resistance
32-Pin QFN (θJA) ......................................... 41.7°C/W
Electrical Characteristics(4)
fRF = 490MHz, fXTAL = 16MHz, MICRF507 Development Board, Modulation type = closed-loop VCO modulation, Sync_en bit = 1,
VDD = 2.5V; TA = 25°C, the term “bit rate” refers to encoded bit rate throughout the EC table (see Figure 24), bold values indicate
–40°C< TA < +85°C, unless noted.
Symbol
Parameter
fRF
RF Frequency Operating Range
VDD
Power Supply
Condition
Min
Typ
470
Max
Units
510
MHz
2.5
Power Down Current
0.2
Standby Current
280
V
3
µA
µA
VCO and PLL Section
4
Reference Frequency
PLL Lock Time, 3kHz Bandwidth
PLL Lock Time, 20kHz Bandwidth
Switch Time, 3kHz Loop Bandwidth
Crystal Oscillator Start-Up Time
Charge Pump Current
40
MHz
490MHz to 490.5MHz
0.7
ms
485MHz to 495MHz
1.3
ms
490MHz to 490.5MHz
0.3
ms
Rx – Tx
1.0
Tx – Rx
1.0
Standby to Rx
1.0
Standby to Tx
1.0
With MICRF507 development
board BOM
1.0
ms
ms
VCPOUT = 1.1V, CP_HI = 0
100
125
170
µA
VCPOUT = 1.1V, CP_HI = 1
420
500
680
µA
Transmit Section
POUT
Output Power
Output Power Variation Relative to
VDD = 2.5V, TA = 25°C
Transmit Mode Current
Consumption
RLOAD = 50Ω, PA[2:0] = 111
10
dBm
RLOAD = 50Ω, PA[2:0] = 001
-3.5
dBm
Over temperature range
±1
dB
VDD = 2.0V
-2
dB
RLOAD = 50Ω, PA[2:0] = 111
21.5
mA
RLOAD = 50Ω, PA[2:0] = 001
10.5
mA
RLOAD = 50Ω, PA[2:0] = 000
8.0
mA
Notes:
1.
Exceeding the absolute maximum rating may damage the device.
2.
The device is not guaranteed to function outside its operating rating.
3.
Devices are ESD sensitive. Handling precautions recommended. Human body model; 1.5k in series with 100pF.
4.
Specification for packaged product only.
October 2, 2013
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Revision 2.2
Micrel, Inc.
MICRF507
Electrical Characteristics(4) (Continued)
fRF = 490MHz, fXTAL = 16MHz, MICRF507 Development Board, Modulation type = closed-loop VCO modulation, Sync_en bit = 1,
VDD = 2.5V; TA = 25°C, the term “bit rate” refers to encoded bit rate throughout the EC table (see Figure 24), bold values indicate
–40°C< TA < +85°C, unless noted.
Symbol
Parameter
Condition
Min
Single-Sided Frequency
(5)
Deviation
10
Maximum Bit Rate
Occupied Bandwidth
Typ
(5)
Max
Units
250
kHz
VCO modulation
200
kbps
Divider modulation
20
kbps
38.4kbps, β = 2, 20dBc
140
kHz
125kbps, β = 2, 20dBc
550
kHz
200kbps, β = 2, 20dBc
800
kHz
nd
(5)
-43
-36
dBm
rd
(5)
-59
-36
dBm
2 Harmonic
3 Harmonic
Spurious Emission in Restricted
(5)
Bands < 1GHz
-54
dBm
(5)
-36
dBm
(5)
-30
dBm
Spurious Emission < 1GHz
Spurious Emission > 1GHz
Receive Section
All Functions on
Rx Current Consumption
Rx Current Consumption Variation
-3
Receiver Sensitivity (BER 10 )
Receiver Maximum Input Power
Receiver Sensitivity Tolerance
12
LNA bypassed
10.3
Switch cap filter bypassed, LNA on
9.8
Both switch cap filter and LNA
bypassed
8
Over temperature
2
-113
4.8kbps, β = 16
-111
19.2kbps, β = 4
-107
38.4kbps, β = 4
-104
76.8kbps, β = 2
-101
125kbps, β = 2
-100
200kbps, β = 2
-97
125kbps, 125kHz deviation, LNA on
+7
125kbps, 125kHz deviation, LNA
bypassed
+12
20kbps, 40kHz deviation
+2
Over temperature
2
dB
Over power supply range
1
dB
50
-3
mA
2.4kbps, β = 16
Receiver Baseband Bandwidth
Co-Channel Rejection, BER = 10
mA
19.2kbps, β = 6, PF_FC[1:0] = 01,
fCUT = 133kHz
dBm
dBm
350
-8
kHz
dB
Note:
5.
Guaranteed by design.
October 2, 2013
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Revision 2.2
Micrel, Inc.
MICRF507
Electrical Characteristics(4) (Continued)
fRF = 490MHz, fXTAL = 16MHz, MICRF507 Development Board, Modulation type = closed-loop VCO modulation, Sync_en bit = 1,
VDD = 2.5V; TA = 25°C, the term “bit rate” refers to encoded bit rate throughout the EC table (see Figure 24), bold values indicate
–40°C< TA < +85°C, unless noted.
Symbol
P1dB
Parameter
Condition
Adjacent Channel Rejection, both
interferer and desired signal are
modulated at 19.2 kbps encoded
bit rate, β = 6, PF_FC[1:0] = 01,
-3
fCUT = 133kHz, BER = 10
±500kHz spacing
Min.
53
dB
±1MHz spacing
58
dB
CW Blocking above desired
signal, desired signal is modulated
at 19.2kbps, β = 6, 3dB above
sensitivity, PF_FC[1:0] = 01,
-3
fCUT = 133kHz, BER = 10
±1MHz
59
dB
±2MHz
60
dB
±5MHz
47
dB
±10MHz
60
dB
-34
dBm
2 tones with 1MHz separation
-25
dBm
-90
dBm
1dB Compression
Input IP3
LO Leakage
Spurious Emission
(5)
Max.
Units
<1GHz
-57
dBm
>1GHz
-47
dBm
Input Impedance with no matching
components
33+7j
Ω
50
dB
PIN = -110dBm
0.9
V
PIN = -60dBm
2
V
RSSI Dynamic Range
RSSI Output Range
Typ.
Digital Inputs/Outputs
VIH
Logic Input High
VIL
Logic Input Low
0.7*VDD
VDD
0
0.3*VDD
V
10
MHz
55
%
(5)
Clock/Data Frequency
Clock/Data Duty Cycle
October 2, 2013
(5)
45
9
V
Revision 2.2
Micrel, Inc.
MICRF507
Functional Description
Control (3-wire) Interface
General
The MICRF507 operation is controlled through a set of 8bit registers. The chip has a total of 23 readable registers
(addresses 0-22) of which 22 (addresses 0-21) are
writeable. Through this register set, the user can set the
MICRF507 in transmit or receive mode, program the
carrier frequency, and select a bit rate, among other
options.
Table 1 identifies all register bits. Table 26 gives more
detail and Table 27 shows the register fields grouped by
category, with don’t-care and mandatory bits omitted.
Some bits shown as ‘0’ or ‘1’ are mandatory bits and must
always be written with the values given. Other bits marked
as “-“ are “don’t care” bits.
Registers are accessed serially through the control
interface consisting of the CS, IO, and SCLK pins.
Positive-going pulses at SCLK serve to clock bits in and
out of IO at a rate determined by the user. When IO is an
input, falling edges of SCLK strobe each bit in; when IO is
an output, each bit appears at IO after the rising edge of
SCLK.
October 2, 2013
The IO is an input for entry of starting addresses, the R/W
bit, and bytes being written to registers, and an output for
bytes read from registers.
CS enables transactions at the control interface, active
high. Transitions at the other two pins are ignored when
CS is low. This allows the MICRF507 to share SCLK and
IO with other devices as long as they have separate CS
lines.
To start a transaction (with SCLK and CS initially low),
bring CS high. To end a transaction (with SCLK low), bring
CS low.
To write a bit into IO (when IO is an input); first bring SCLK
high and drive IO with the bit level to be input (in either
order, or simultaneously). Then bring SCLK low.
To read a bit out of IO (when IO is an output); first bring
SCLK high and read the level on IO. Then bring SCLK low
(in either order, or simultaneously).
The first byte to be clocked in during a transaction is made
of seven bits (MSB first) of register address followed by
the R/W bit, 0 for write, 1 for read. Then, one or more
bytes to be written to or read from registers are clocked in
or out respectively, always MSB first.
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Revision 2.2
Micrel, Inc.
MICRF507
Adr
Data Field
A6…A0
D7
D6
D5
D4
D3
D2
D1
D0
0000000
LNA_by
PA2
PA1
PA0
Sync_en
Mode1
Mode0
’1’
0000001
Modulation1
Modulation0
‘0’
‘0’
RSSI_en
LD_en
PF_FC1
PF_FC0
0000010
CP_HI
SC_by
‘0’
PA_By
OUTS3
OUTS2
OUTS1
OUTS0
0000011
‘1’
‘1’
‘0’
VCO_IB2
VCO_IB1
VCO_IB0
VCO_freq1
VCO_freq0
0000100
Mod_F2
Mod_F1
Mod_F0
Mod_I4
Mod_I3
Mod_I2
Mod_I1
Mod_I0
0000101
-
-
‘0’
‘1’
Mod_A3
Mod_A2
Mod_A1
Mod_A0
0000110
-
Mod_clkS2
Mod_clkS1
Mod_clkS0
BitSync_clkS2
BitSync_clkS1
BitSync_clkS0
BitRate_clkS2
0000111
BitRate_clkS1
BitRate_clkS0
RefClk_K5
RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
0001000
‘1’
‘1’
‘0’
ScClk4
ScClk3
ScClk2
ScClk1
ScClk0
0001001
‘0’
‘0’
‘1’
XCOtune4
XCOtune3
XCOtune2
XCOtune1
XCOtune0
0001010
-
-
A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
0001011
-
-
-
-
N0_11
N0_10
N0_9
N0_8
0001100
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
0001101
-
-
-
-
M0_11
M0_10
M0_9
M0_8
0001110
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
0001111
-
-
A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
0010000
-
-
-
-
N1_11
N1_10
N1_9
N1_8
0010001
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
0010010
-
-
-
-
M1_11
M1_10
M1_9
M1_8
0010011
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
0010100
‘1’
‘0’
‘1’
‘0’
‘0’
‘0’
‘1’
‘1’
0010101
-
-
-
-
FEEC_3
FEEC_2
FEEC_1
FEEC_0
0010110
FEE_7
FEE_6
FEE_5
FEE_4
FEE_3
FEE_2
FEE_1
FEE_0
Names of programming bits. Unused bits (“-“) and mandatory bits (“1” or “0”) are shown. Changes to mandatory bits may cause
malfunction.
Table 1. Control Registers
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MICRF507
Writing
This method is used to write either to one register (see
Figure 1), or any number of registers with consecutive
addresses up to all 22 writeable registers (see Figure 2) in
a single transaction.
Procedure:
•
Bring CS active (high). IO is initially an input (and
remains so for the duration of the transaction).
•
Clock in a byte consisting of the address bits and
the R/W bit. The first seven bits are the address
(starting with MSB) of the register, or the first
register if more than one, to be written. The eighth
bit is the R/W bit, which is 0 as this is a write
operation.
•
Clock in one or more bytes, MSB of each byte
first.
•
Bring CS low to end the transaction.
Bits passing through IO are clocked serially into prebuffers, then transferred in parallel to the actual registers
upon de-assertion of CS.
Figure 1. Writing a Byte into a Register
Figure 2. Writing Bytes into n+1 Registers at Consecutive Addresses Starting with Address i
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Micrel, Inc.
MICRF507
•
Reading
Any number of registers with consecutive addresses, from
one up to all 23, can be read.
Procedure:
•
Bring CS active (high). IO is initially an input.
•
Clock in a byte consisting of the address bits and
the R/W bit. The first seven bits are the address
(starting with MSB) of the register, or the first
register if more than one, to be read. The eighth
bit is the R/W bit, which is 1 as this is a read
operation. After the R/W bit is clocked in (falling
edge of SCLK), the next rising edge on SCLK will
enable IO as an output for the duration of the
transaction.
Clock out 8 bits per register (one or more) to be
read through IO, MSB first. Rising edges of SCLK
bring each bit to IO. The user can then
conveniently sample the bit at the next falling edge
of SCLK.
•
Bring CS low to end the transaction. IO reverts to
being an input.
Figure 3 shows how to read one register. To read more
registers at consecutive addresses, continue pulsing SCLK
eight times for each register to be read before de-asserting
CS.
Figure 3. Reading a Byte from a Register
Figure 4. Definitions of Control Interface Timing Parameters
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Revision 2.2
Micrel, Inc.
MICRF507
Control Interface Timing
Figure 4 and Table 2 give the timing specifications for the
control interface.
When in Receive or Transmit mode (but not Power-down
or Standby mode), an additional timing constraint applies:
elapsed time between falling edges of CS must be a
minimum of 2/fc, where fc is the synthesizer’s comparison
frequency (also called phase detector frequency). fc =
fXCO/M,
fc =
fXCO
M
Power-on Reset
The power-on reset time (tPOR), given in Table 2, is defined
as the time from application of supply voltage to
completion of power on reset.
To determine when the chip has completed its power-on
without waiting for the worst-case time (maximum tPOR), do
the following:
•
Write hex 03 (binary 00000011) to Register 0.
This puts the chip in Standby mode.
•
min time =
2M
fXCO
where M = M0 when receiving or transmitting with VCO
modulation, and M = max{M0, M1} when transmitting with
divider modulation.
Read Register 0. If the value read is binary
00000011, then exit; power-on is complete. If not,
go to previous step and repeat.
Because registers are initially in an unknown state after
power-on (exception: Mode[1:0] initializes to 00), always
enter a complete set of register values as the first
transaction, and always enter only nonzero values for N
and M.
Values
Units
Symbol
Parameter
Thigh
Min. high time of
SCLK
20
ns
Tlow
Min. low time of
SCLK
20
ns
tfall
Fall time of SCLK
1
µs
trise
Rise time of SCLK
1
µs
Tcsr
Time from rising
edge of CS to
falling edge of
SCLK
50
ns
Tcsf
Min. delay from
rising edge of CS
to rising edge of
SCLK
25
ns
Twrite
Min. delay from
valid IO to falling
edge of SCLK
during a write
operation
20
ns
Tread
Min. delay from
rising edge of
SCLK to valid IO
during a read
operation
(assuming load
capacitance of IO
is 25pF)
75
ns
tPOR
Power on Reset
time
Min.
Typ.
Max.
4.6
9
Figure 5. Power-On Programming Flowchart
ms
Table 1. Control Interface Timing
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MICRF507
Clock Generation
The MICRF507’s crystal oscillator:
•
Serves as the reference for the synthesizer that is
the carrier and local oscillator source.
•
Is divided down to clock the switched-capacitor IF
filter.
•
Is divided down to generate three other clocks: bit
rate clock, bit synchronization clock, and
modulator clock
Figure 6 shows the oscillator with its frequency-shifting
capacitor bank (controlled by the register field XCOtune)
and the frequency dividers that derive the latter three
clocks from its output. This division occurs in two stages.
First, the XCO output is divided by the 6-bit field Refclk_K,
which has allowable values between 1 and 63. Then, for
each of the three clocks, another field (BitSync_clkS,
BitRate_ClkS, and ModClkS, respectively) selects the
number of further divisions by 2. Complete relationships of
field values and resultant frequencies are given below for
each clock.
Number
of bits
Location
of bits
XCOtune
5
Reg9[4:0]
Crystal oscillator trimming.
RefClk_K
6
Reg7[5:0]
Reference clock divider.
BitRate_clkS
3
Reg6[0],
Reg7[7:6]
Transmitter Bit rate clock setting. See Figure 9 and “Data
Interface and Bit Synchronization” section for more details.
Mod_clkS
3
Reg6[6:4]
VCO Modulator clock setting, set the modulator clock to
either 8x or 16x the bit rate clock.
Reg6[3:1]
Receiver Bit Synchronization clock setting, always set bit
synchronization clock to 16x the bit rate clock. See Figure 9
and “Data Interface and Bit Synchronization” section for more
details.
Field Name
BitSync_clkS
3
Description
Table 3. Register Bit Fields for Clock Generation
Figure 6. MICRF507 Clock Sources
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MICRF507
To achieve 9pF load capacitance required to center
TN4-26011 at 16MHz, set the external capacitors to
1.5pF and XCOtune=16dec. Figure 8 shows the tuning
range for two different capacitor values, 1.5pF and zero
(external capacitors omitted). External capacitor values
will strongly affect the tuning range. Using 1.5pF with the
above crystal gives a tuning range that is approximately
symmetrical about the center frequency.
Crystal Oscillator (XCO)
The crystal oscillator’s role as the synthesizer reference
demands very good phase and frequency stability. As
shown in Figure 7, the external components required for
the oscillator are a crystal, connected between pins 23
and 24, and loading capacitors.
Y1
TN4-26011
Pin 24
XtalOut
C9
1.5pF
Pin 23
XtalIn
C8
1.5pF
Figure 7. Crystal Oscillator Circuit
The load capacitance CL seen between the crystal
terminals is:
CL =
1
1
1
+
C8 C9
+ C XCOtune + Cpin
Figure 8. XCO Tuning with the XCOtune Field
The start-up time of the cystal oscillator, given in Table
4, is about a millisecond and increases with capacitance.
When the MICRF507’s main mode is switched from
Power down mode to Transmit mode via Standby mode,
or to Receive mode via Standby mode, only the XCO is
energized at first. Current consumption during this
prestart period is approximately 280μA (the same as for
Standby mode). After the XCO amplitude is sufficient to
trigger the M-counter and produce two pulses at its
output, the remaining circuits on the chip are powered
on.
Where CXCOtune is the capacitance of the internal
adjustable capacitor bank, and Cpin is defined as the
internal chip capacitance when XCOtune bits are all
zeros, plus PCB stray capacitance across pins 23 and
24. The value of Cpin is about 6pF. The loading capacitor
values required depend on the total CL specified for the
crystal for oscillation at the desired frequency.
It is possible to tune the crystal oscillator internally by
giving the 5-bit register field XCOtune a non-zero value,
which causes internal capacitors to be switched across
the crystal. As this capacitance increases, frequency
decreases. When XCOtune is set to its maximum value
of 31, approximately 4.5pF additional capacitance is
connected across the crystal pins.
The XCO tuning can be used to cancel crystal resonant
frequency error, both initial and with temperature. It can
be used in combination with the Frequency Error
Estimator (FEE). See “FEE” section.
The crystal used is a TN4-26011 from Toyocom.
Specification:
•
Package TSX-10A,
•
Nominal frequency 16.000000MHz
•
Frequency tolerance ±10ppm
•
Frequency stability ±9ppm, load capacitance
9pF
•
Pulling sensitivity 15ppm/pF
October 2, 2013
XCOtune
Start-up Time (µs)
0
590
1
590
2
700
4
700
8
810
16
1140
31
2050
Table 4. Typical Crystal Oscillator Start-up Time
with C8 = C9 = 1.5pF
16
Revision 2.2
Micrel, Inc.
MICRF507
An external reference clock, when used instead of a
crystal, should be applied to pin 24 (XTALOUT) with pin
23 (XTALIN) not connected. To maintain proper DC
biasing within the chip, use AC-coupling between the
external reference and the XTALOUT-pin.
The modulator clock is used if VCO modulation method
is selected. Set the modulator clock frequency to either
8x or 16x the bit rate. See “VCO Modulation and the
Modulator” subsection for more information.
BitRate_clkS[2:0]
BITSYNC_CLK (Receiver Bit Synchronization Clock)
The frequency of the bit synchronization clock
is a function of the crystal oscillator
fBITSYNC_CLK,
frequency fXCO and the values of the register fields
Refclk_K and BitSync_clkS:
fBITSYNC_CLK
fXCO
=
Refclk_K × 2 (7-BitSync_clkS )
The bit synchronizer uses a clock that needs to be
programmed to 16 times the actual bit rate. As an
example, a bit rate of 20kbps needs a bit synchronizer
clock with frequency of 320kHz. Refer to Figure 9 and
“Data Interface and Bit Synchronization” section for more
details.
(fXCO is crystal frequency)
000
fXCO/(128xRefClk_K)
001
fXCO/(64xRefClk_K)
010
fXCO/(32xRefClk_K)
011
fXCO/(16xRefClk_K)
100
fXCO/(8xRefClk_K)
101
fXCO/(4xRefClk_K)
110
fXCO/(2xRefClk_K) (*)
111
fXCO /RefClk_K (*)
Data Interface and Bit Synchronization
fXCO
=
Refclk_K × 2(7-BitRate_clkS)
Transmitted and received data bits are coupled to the
MICRF507 serially through the Data Interface. This Data
Interface consists of the DATAIXO and DATACLK pins.
This is a separate interface from the Control Interface
(CS, IO, and SCLK), for which see Control (3-wire)
Interface.
Figure 9 shows the data interface circuitry aboard the
MICRF507. DATAIXO is an input during transmission,
whereas during reception a driver is enabled and it
becomes an output. DATACLK is always an output.
A rule that applies when using VCO modulation is: after
commanding the MICRF507 to enter transmit mode, the
microcontroller shall tri-state the driver connected to
DATAIXO to leave that pin floating until the
microcontroller begins sending data. See “Mode
Transitions” section for more details.
The data interface can be programmed for synchronous
and non-synchronous operation according to the setting
of the Sync_en bit; see Table 7.
MODULATOR_CLK (VCO Modulator Clock)
The frequency fMOD_CLK of MODULATOR_CLK is a
function of the crystal oscillator frequency fXCO and the
values of the register fields Refclk_K and Mod_clkS:
October 2, 2013
Mod_clkS[2:0]
Table 5. Generation of Bitrate_clk, BitSync_clk
and Mod_clk
In transmit mode, when Sync_en = 1, BITRATE_CLK
appears on the DATACLK pin. Its frequency is equal to
the bit rate. Example; a bit rate of 20 kbit/sec requires an
fBITRATE_CLK of 20kHz. Refer to Figure 9 and the “Data
Interface and Bit Synchronization” subsection for more
details.
fMOD_CLK =
Corresponding Clock
Frequency
(*) Can not be used as BitRate_clk.
BITRATE_CLK (Transmitter Bit Rate Clock)
The frequency fBITRATE_CLK of BITRATE_CLK is a function
of the crystal oscillator frequency fXCO and the values of
the register fields Refclk_K and BitRate_clkS:
fBITRATE_CLK
BitSync_clkS[2:0]
fXCO
Refclk_K × 2 (7-Mod_clkS )
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MICRF507
Field Name
Number
of bits
Location
of bits
Sync_en
1
Reg0[3]
Reference
Description
Synchronizer Mode bit
Table 7
Table 6. Register Bit Fields for Data Interface and Bit Synchronization
Sync_en
State
Comments
0
RX: Bit
synchronization off
Transparent reception of data
0
TX: DataClk pin off
Transparent transmission of data
1
RX: Bit
synchronization on
Bit clock is generated by transceiver
1
TX: DataClk pin on
Bit clock is generated by transceiver
Table 7. Synchronizer Mode Bit
DATAIXO
19
RECEIVE
DATA PATH
TRANSMIT
DATA PATH
RECEIVE
MODE
Sync_en = 0
Sync_en = 0
Sync_en = 1
ENABLE
TO
TRANSMITTER
D Q
Sync_en = 1
D Q
TRANSMIT
BITRATE_CLK
18
RECEIVE
DATACLK
Sync_en
FROM
DEMOD
Filter &
data slicer
Bit
Sync
RECOVERED
CLOCK
BITSYNC_CLK
Figure 9. Data Interface and Synchronization
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Revision 2.2
Micrel, Inc.
Mode
MICRF507
Sync_en
DATACLK
Direction
DATAIXO
Signal
0
Output
0
1
Output
BitRate clock
0
Output
0
1
Output
Clock recovered by bit
synchronizer
Transmit
Receive
Direction
Signal/Function
Input
Modulates carrier directly
(asynchronously)
Input
Sampled at rising edge of BitRate
clock; latched output modulates
carrier
Output
Raw output from demodulator
Output
Filtered and latched demodulator
output; transitions occur at rising
edge of DATACLK
Table 8. Synchronizer Mode and Data Interface
In sync mode (Sync_en bit set to 1), the transmitted bit
stream is clocked with the precision of the MICRF507’s
crystal oscillator, which relaxes timing accuracy
requirements on the data source. During reception, the
synchronizer ensures that transitions of DATAIXO occur
only at rising edges of DATACLK, without edge jitter or
internal glitches. Receiver sensitivity values given in the
Electrical Characteristics table are measured with Sync_en
= 1; with Sync_en = 0, as much as 3-6 dB of sensitivity
could be lost.
recovered clock. DATAIXO (an output during reception)
brings out the synchronized data stream, which has its
transitions at rising edges of DATACLK. See Figure 11.
Sync_en = 0
When Sync_en = 0, the input signal at DATAIXO
modulates the transmitter directly during transmission and
the output signal from DATAIXO is the raw demodulator
output. DATACLK remains fixed at a logic low level during
both transmission and reception.
By being in control of bit timing, the MICRF507 is
effectively the “master.” For maximum timing margin, the
microcontroller, as the “slave,” can present or sample
(during transmit and receive, respectively) each new bit at
the DATAIXO pin at falling edges of DATACLK.
Sync_en = 1
During transmission when Sync_en = 1 the data bit stream
entering DATAIXO is buffered with a flip-flop strobed at the
rising edge of BITRATE_CLK, and the output of the flipflop modulates the transmitter. BITRATE_CLK is brought
out at the DATACLK output. Figure 10 shows the
relationship of DATACLK and DATAIXO transitions.
Figure 10. Data Interface in Transmit Mode
During reception, the bit synchronizer recovers the
received signal’s clock. This recovered clock strobes a flipflop that samples in mid-bit-period the demodulated and
filtered bit stream. The DATACLK output brings out the
October 2, 2013
Figure 11. Data Interface in Receive Mode
Additional Considerations in the Use of Synchronizer
(Sync_en = 1)
Two clock signals, BITRATE_CLK and BITSYNC_CLK,
must be properly programmed when using the
synchronizer. BITRATE_CLK, used in transmission, must
be set to a frequency equal to the bit rate.
BITSYNC_CLK, used in reception, must have a frequency
16 times the bit rate. These frequencies are controlled by
the crystal oscillator frequency and the settings of register
fields, as described in the “Clock Generation” section. Bit
clocking of the incoming signal must agree with the
receiver’s local clocking within ±2.5% (easily met with 100
PPM or better crystals). For example, if fBITSYNC_CLK is
16x19.231kbps, the incoming bit rate can be between
0.975x19.231kbps to 1.025x19.231kbps.
All incoming messages must start with a 0101… preamble
so that the synchronizer can acquire the incoming clock. A
24-bit preamble is typically used; a minimum of 22 bits is
required.
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MICRF507
Frequency Synthesizer
The MICRF507 frequency synthesizer is an integer-N
phase-locked loop consisting of:
•
a reference source, made of an M-divider
clocked by the crystal oscillator
•
a voltage controlled oscillator (VCO)
•
a programmable frequency divider made of an
N-divider, an A-divider, and a dual modulus
prescaler
• a phase/frequency detector
The loop filter is external for flexibility and can be a
simple passive circuit.
The phase/frequency detector compares the reference
frequency (from the M-divider) with the VCO output fed
through the programmable frequency divider. The
charge pump output of the phase/frequency detector,
after filtering, controls the VCO, closing the loop and forcing
the error between the reference frequency and the divided
VCO frequency to zero.
The block diagram, Figure 12, shows the basic elements and
arrangement of a PLL-based frequency synthesizer. The
MICRF507 has a dual modulus prescaler for increased
frequency resolution. In a dual modulus prescaler the main
divider is split into two parts, the main part N and an
additional divider A, where A < N. Both dividers are clocked
from the output of the dual-modulus prescaler, but only the
output of the N divider is fed into the phase detector. The
prescaler will first divide by 16. Both N and A count down
until A reaches zero, at which point the prescaler is switched
to a division ratio 16+1. At this point, the divider N has
completed A counts. Counting continues until N reaches
zero, which is an additional N-A counts. At this point, the
cycle repeats.
Number
of bits
Location of bits
M0
12
Reg13[3:0],
Reg14[7:0]
M0 counter
A0
6
Reg10[5:0]
A0 counter
N0
12
Reg11[3:0],
Reg12[7:0]
N0 counter
M1
12
Reg18[3:0],
Reg19[7:0]
M1 counter
A1
6
Reg15[5:0]
A1 counter
N1
12
Reg16[3:0],
Reg17[7:0]
N1 counter
CP_HI
1
Reg2[7]
VCO_Freq
2
Reg3[1:0]
Frequency setting of VCO (see Table 11)
VCO_IB
3
Reg3[4:2]
VCO bias current setting (see Table 11)
LD_en
1
Reg1[2]
Field Name
Description
High charge pump current (1= 500μA, 0 = 125µA)
Lock detect function on/off
Table 9. Register Bit Fields for Frequency Synthesizer
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Micrel, Inc.
MICRF507
Loop filter
Downconverter
A-Divider
VCO
N-Divider
Prescaler
Charge pump
Div 2
Phase
detector
PA
Div 2
M-Divider
XCO
Figure 12. PLL Block Diagram
D7
D6
D5
D4
D3
D2
D1
D0
0001010
A6…A0
-
-
A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
0001011
-
-
-
-
N0_11
N0_10
N0_9
N0_8
0001100
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
0001101
-
-
-
-
M0_11
M0_10
M0_9
M0_8
0001110
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
0001111
-
-
A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
0010000
-
-
-
-
N1_11
N1_10
N1_9
N1_8
0010001
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
0010010
-
-
-
-
M1_11
M1_10
M1_9
M1_8
0010011
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
Table 10. Register Bit Fields for PLL
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Micrel, Inc.
MICRF507
N, M, and A are numbers of length 12, 12 and 6 bits,
respectively The synthesizer’s output frequency can be
calculated from the following equation:
fPD =
fXCO
fVCO
fRF × 2
=
=
(
)
(
16 × N + A × 2 16 × N + A )
M
The input capacitance at the varactor pin must be taken
into consideration when designing the PLL loop filter. This
is most critical when designing a loop filter with high
bandwidth, which gives relatively small component values.
The input capacitance is approximately 6pF.
M≠0
RF Frequency vs Varactor Input Voltage
1 ≤ A ≤ 16
530
16 × N + A
= fXCO
2M
RF Frequency (MHz)
fRF
540
where
fPD: Phase detector comparison frequency
fXCO: Crystal oscillator frequency
fVCO: Voltage controlled oscillator frequency
fRF: RF carrier frequency
11
500
10
490
01
480
470
450
0
0.4
0.8
1.2
1.6
2
2.4
VARIN Voltage (V)
VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0
470482MHz
1
0
1
0
1
482497MHz
1
0
0
1
0
497510MHz
0
1
1
1
1
Table 11. VCO Bit Setting
The tuning range, the RF frequency versus VCO tune
voltage (varactor input, pin 29), depends on the VCO
frequency setting as shown in as shown in Figure 13.
When the tuning voltage is in the range from 0.9V to 1.4V,
the VCO gain (as seen by the PLL) is at its maximum,
approximately 64 to 70MHz/V. Note that the RF frequency
is half of the PLL frequency. It is recommended that the
VCO tune voltage stays in this range.
October 2, 2013
510
460
The MICRF507 has two sets of register fields controlling
the synthesizer’s frequency multiplication ratio; A0/N0/M0
and A1/N1/M1. During transmission using divider
modulation (see “Divider Modulation” section), bit values of
‘0’ and ‘1’ respectively select the 0 and 1 register field set.
During reception and during transmission using VCO
modulation, only the 0 set is used.
VCO
The VCO has no external components.
The three-bit field VCO_IB controls VCO bias current to
optimize phase noise. The two bit field VCO_freq controls
a capacitor bank which determines the VCO frequency
range. These five bits are set according to the RF
frequency as follows:
RF
Freq
520
Figure 13. RF Frequency vs. Varactor Voltage
and VCO_ Freq bits (VDD = 2.5V)
Charge Pump
The charge pump current can be set to either 125µA or
500µA by CP_HI (‘1’ → 500µA). This will affect the loop
gain and, consequently, filter component values. For
applications using high phase detector frequency and high
PLL bandwidth, use 500µA charge pump current.
PLL Filter
The design of the PLL filter strongly affects the
performance of the frequency synthesizer. Key parameters
in PLL filter design are loop bandwidth, the modulation
method (VCO modulation or divider modulation) and the
bit rate. Filter design also affect the switching time
(important when frequency hopping) and phase noise.
Divider modulation requires the PLL to lock on a new
carrier frequency for every new data bit. As a rule of
thumb, the PLL loop bandwidth should be at least twice as
high as the bit rate. In such cases it is recommended to
use a third order filter to suppress the phase detector
frequency.
For VCO modulation, the PLL loop bandwidth should be
less than 1/10 of the bit rate. If the loop bandwidth is high
relative to the bit rate, the PLL will keep the VCO at a fixed
frequency, preventing it from being modulated.
The recommended third-order loop filter (made with
external components) is shown in Figure 14. When R2=0
and C3 is omitted, this reduces to a second-order loop
filter.
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Micrel, Inc.
MICRF507
Figure 14. Second and Third Order Loop Filter
Table 12 shows three different loop filter designs, the first
two for VCO modulation and the last one for modulation
using the internal dividers. The component values are
calculated with RF frequency = 490MHz, VCO gain =
67MHz/V as seen by the PLL, and desired phase margin =
56º. Other settings are shown in the table. The VARIN pin
capacitance (pin 29) of 6pF can be neglected for the two
filters with lowest bandwidth (which have R2=0 and
relatively large values of C1). For other loop bandwidth
and phase detector values, use the loop filter calculation
tool in RF Testbench software available on Micrel’s
website.
Lock Detect
A lock detector can be enabled by setting LD_en = 1.
When pin LD is high, it indicates that the PLL is in lock.
After a control word is loaded LD will (typically) go low,
then high again when the synthesizer has locked. LD also
goes low initially when the PA (power amplifier) is turning
on.
After the transceiver has been put into Receive or
Transmit mode, or after the power amplifier has been
turned on, a low-to-high transition at LD can serve as an
indicator that the synthesizer frequency has stabilized.
Encoded
Bit Rate
(kbps)
PLL
BW
(kHz)
Charge
Pump
(μA)
Phase
Detector
Freq. (kHz)
C1
C2
R1
R2
C3
VCO
>8
0.8
125
100
10nF
100nF
6.2kΩ
0
NC
VCO
>32
3.2
125
100
680pF
6.8nF
22kΩ
0
NC
Divider
<6.5
13
500
500
390pF
8.2nF
5kΩ
68kΩ
18pF
Table 12. Loop Filter Component Values
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MICRF507
Receiver
Number
of bits
Location
of bits
By_LNA
1
Reg0[7]
PF_FC
2
Reg1[1:0]
SC_by
1
Reg2[6]
ScClk
5
Reg8[4:0]
Field Name
Description
Reference
LNA bypass on/off
Pre-filter corner frequency
Table 14
Bypass of switched capacitor filter on/off
Switched Cap clock divider
RSSI_en
1
Reg1[3]
FEEC
4
Reg21[3:0]
FEE control bits
RSSI function on/off
FEE
8
Reg22[7:0]
FEE value (read only)
Table 15
Table 13. Register Bit Fields for Receiver
The receiver is a zero intermediate frequency (ZIF) type
employing low-power, fully integrated low-pass filters.
A low noise amplifier (LNA) drives a quadrature mixer pair.
The mixer outputs feed two identical signal channels.
Each channel’s signal path has a pre-amplifier, a third
order Sallen-Key RC low-pass pre-filter, a six-pole
switched-capacitor filter (which determines actual
selectivity), and finally a limiter.
The limiter outputs then enter a demodulator which detects
the relative phase of the baseband I and Q signals. If the I
channel signal lags the Q channel, the FSK tone frequency
lies above the LO frequency (data ‘1’). If the I channel
leads the Q channel, then the FSK tone lies below the LO
frequency (data ‘0’). The output of the demodulator is
available on the DATAIXO pin; in either raw form or
latched with the recovered clock according to the setting of
Sync_en bit. An RSSI (receive signal strength indicator)
circuit indicates the received signal level.
available at pins IchOut and QchOut. The output
impedance of each mixer is about 8kΩ.
Front End
The MICRF507’s low-noise amplifier boosts the incoming
signal prior to frequency conversion in order to prevent
mixer noise from degrading overall front-end noise
performance. The LNA is a two-stage amplifier and has a
nominal gain of approximately 23dB at 490MHz. The front
end has a gain of about 31dB to34dB. The gain varies by
1-1.5dB over a 2.0V to 2.5V variation in power supply.
The LNA can be bypassed by setting bit LNA_by to ‘1’.
This can be useful for very strong input signal levels. The
front-end gain with the LNA bypassed is about 12dB. The
mixers have about 10dB of gain at 490MHz. With
appropriate setting of the OUTS field (register 2, bits D3 to
D0), the differential outputs of the mixers can be made
October 2, 2013
MARKER
1
2
3
MHz
470
490
510
RESISTANCE
32.4Ω
33.4Ω
34.4Ω
REACTANCE
7.9Ω
7.4Ω
6.4Ω
Figure 15. LNA Input Impedance
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Micrel, Inc.
MICRF507
The front end’s input impedance, with no matching
network, is close to 50Ω as shown in Figure 15. This gives
an input reflection coefficient of about -13dB. Although the
receiver does not require a matching network to optimize
the gain, a matching network is recommended for
harmonic suppression during transmission and for
improved selectivity in reception.
Sallen-Key Filters
Each IF channel includes a pre-amplifier and a pre-filter.
The preamplifier has a gain of 22dB. The IF amplifier also
removes DC offset. Gain varies by less than 0.5dB over a
2.0V to 2.5V variation in power supply.
The pre-filter is implemented as a three-pole Sallen-Key
low-pass filter. It protects the switched-capacitor filter that
follows it from strong adjacent channel signals and also
serves as an anti-aliasing filter. It is programmable to four
different cut-off frequencies as shown in Table 14.
PF_FC1
PF_FC0
Cutoff (3dB filter corner)
0
0
100kHz
0
1
150kHz
1
0
230kHz
1
1
340kHz
The pre-filter and switched-capacitor filters in cascade
must pass the full IF bandwidth of the received signal. In a
zero-IF receiver such as the MICRF507 this bandwidth is
as follows:
fBW = fOFFSET + fDEV +
rb
2
where
fBW : Needed receiver bandwidth; fCUT above should
not be smaller than fBW [Hz]
fOFFSET: Total frequency offset between receiver and
transmitter [Hz]
fDEV: Single-sided frequency deviation [Hz]
rb: The bit rate in bits/sec
RSSI
Table 14. Pre-Filter Bit Field
Switched Capacitor Filter
The main IF channel filter is a switched-capacitor
implementation of a six-pole elliptic low pass filter. This
meets selectivity and dynamic range requirements with
minimum total capacitance. The cut-off frequency of the
switched-capacitor filter is adjustable by changing the
clock frequency.
A 6-bit frequency divider, programmed by the ScClk[5:0]
field, is clocked by the crystal oscillator. Its output, which is
20 times the filter’s cutoff frequency, is then divided by 4 to
generate the correct non-overlapping clock phases needed
by the filter. The cut-off frequency of the filter is given by:
fCUT =
fXCO
40 ⋅ ScClk
fCUT: Filter cutoff frequency
fXCO: Crystal oscillator frequency
ScClk: Switched capacitor filter clock, bits ScClk[4:0]
(bit 0 has a mandatory value of ‘0’).
For instance, for a crystal frequency of 16MHz and if the 6
bit divider divides the input frequency by 4, the cut-off
frequency of the SC filter is 16MHz/(40 x 4) = 100kHz. A
first-order RC low-pass filter removes clock frequency
components from the signal at the switched-capacitor filter
output.
October 2, 2013
Figure 16. RSSI Voltage
Figure 17. RSSI Network
Figure 16 shows a typical plot of the RSSI voltage as a
function of input power. The RSSI termination network is
shown in Figure 17. The RSSI has a dynamic range of
about 50dB from about -110dBm to -60dBm input power.
When an RF signal is received, the RSSI output increases
and can serve as a signal presence indicator. It could be
used to wake up external circuitry that conserves battery
life while in a sleep mode. Note that RSSI only functions in
Receive mode.
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Micrel, Inc.
MICRF507
Another use for RSSI is to determine that transmit power
can be reduced in a system. If the RSSI detects a strong
signal, the transmitter could be alerted to reduce its
transmit power and so reduce current consumption.
FEE
The Frequency Error Estimator (FEE) counts pulses from
inside the demodulator to measure the frequency offset
between it’s receive frequency and the transmitter’s
frequency. The maximum offset that FEE can correctly
report a frequency difference is about ±20ppm. The output
of the FEE can be used to tune the XCO frequency, both
for production calibration and to compensate for crystal
temperature drift and aging.
The FEE is enabled when FEEC[1:0] = 11, and is off when
FEEC[1:0] = 00 (do not use other values). It has two
counters. One counter determines the measurement
period by generating a trigger every time it has counted up
the number of bit periods selected by the setting of
FEEC[3:2] as given in Table 15. A second counter
accumulates the net tally of UP and DN pulses from the
demodulator. For each incoming ‘1’ bit, UP carries an
average number of pulses that is twice the modulation
index (β), and likewise for each incoming ‘0’ bit and DN.
The trigger transfers the contents of the second counter to
the FEE register and clears it, after which it begins
accumulating again.
FEEC_1
FEEC_0
FEE Mode
0
0
Off
0
1
Do not use
1
0
Do not use
1
1
Counting UP and DN pulses. UP
increments the counter, DN
decrements it.
FEEC_3
FEEC_2
0
0
8
0
1
16
1
0
Do not use
1
1
Do not use
The result of the measurement, read from the FEE register
at address 22 (16 hex, 0010110 binary), is actually an
eight-bit two’s complement signed number, which can
have values from -128 to 127. Reading FEE gives the
most recently transferred value. The raw FEE value,
treated as an unsigned number ranging from 0 to 255, can
be converted into a signed integer as follows:
If FEE < 128 then {FEESIGNED = FEE}
Else {FEESIGNED = (FEE - 256)},
For a straightforward measurement of frequency offset, the
incoming signal has to have an equal number of ones and
zeros, such as a 1010… preamble. The frequency offset
can then be calculated:
fOFFSET =
rb
FEE SIGNED
4P
where FEE is the value read from the FEE register (treated
as a signed number), P is the number of data bits over
which the count is taken, and rb is the bit rate. When
fOFFSET is zero, the transmitter and receiver are perfectly
aligned. A positive fOFFSET means that the received signal
has a higher frequency than the carrier frequency to which
the receiver is tuned. To compensate for this, the
receiver’s XCO frequency should be increased by reducing
XCO_tune bits as detailed in the “Crystal Oscillator (XCO)”
section.
Counting a larger number of symbols (higher P) improves
the accuracy of the measurement. Beware, however, of
overflow, which can cause the FEE value to jump from
+127 to -128 after only one excessive count.
If the frequency offset is too large for the chosen P, then P
must be reduced. P = 8 or P = 16 is safest.
No. of bits used for the
measurement
Table 15. FEEC (Frequency Error Estimator Control) Bits
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MICRF507
XCOtune Procedure Example
A procedure such as the algorithm given below can be
called during production (storing the calibrated XCO_tune
value), at regular intervals, or implemented in the
communication protocol when the frequency has changed.
The MICRF507 measures the frequency offset between
the demodulated signal and the LO, and a micro-controller
programs the XCO_tune bits to tune the XCO so the LO
frequency is equal to received carrier frequency.
Procedure description: A transmitter is assumed to be
sending a 1010… pattern at the correct frequency and bit
rate. The FEE is enabled (FEEC[1:0] = 11) and the
number P of bit periods used in the measurement is 8 or
16. Only the sign of FEE is used.
Objective: The best XCO_tune value (giving the lowest
IFEEI). The desired frequency of the receiver’s PLL is
midway between the “0” and “1” frequencies.
Local variables:
XCO_Present: (5-bit) holds current value in XCO_tune
field
XCO_Step: (4-bit) holds amount by which XCO_tune will
be incremented or decremented
XCO_Sign: (1 bit) has a value of either POS or NEG,
determining respectively whether XCOtune is to be
incremented or decremented (reducing XCOtune
increases LO frequency)
Registers properly set for reception;
LOOP:
XCO_Step = XCO_Step/2;
If (XCO_Sign == POS) then
// If POS then increase LO frequency:
{XCO_present = XCO_present - XCO_Step}
Else
// If NEG then decrease LO frequency:
{XCO_present = XCO_present + XCO_Step}
;
XCO_tune_bits = XCO_Present;
ProgramRFChip;
Wait for > P bit periods;
Read FEE;
If (FEE > 0?) then
{XCO_Sign = POS}
else
{XCO_Sign = NEG} // negative or 0
;
If (XCO_Step > 1) then
{Branch to LOOP}
Else
{If(XCO_Sign == POS) then
{XCO_Present = XCO_Present – 1;
Return (XCO_Present)}; \\ done
}
;
XCO_tune_bits is a buffer, which is written to the XCOtune
field when ProgramRFChip is called.
XCO TUNE PROCEDURE
Initialization:
XCO_Present = 16;
XCO_Step = 16;
XCO_Sign = NEG;
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MICRF507
Transmitter
Power Amplifier
The maximum output power of the power amplifier (PA) is
approximately 10dBm with a 50Ω load. For maximum
output power, the load seen by the PA must be resistive.
Higher output power can be obtained by decreasing the
load impedance, but this will conflict with impedance
matching to the LNA.
The output power is programmable in seven levels by
means of the PA[2:0] field, with approximately 2.5dB
between steps; see Table 17. The power amplifier is
turned off when PA[2:0] = 000. Otherwise the PA is on and
output power increases with the value of the PA[2:0] field
and is maximum when PA[2:0] = 111.
Setting PA_by=1 causes the PA to be bypassed and
output power to drop by ~22dB. It is still possible to control
the power with PA[2:0] bits.
The LC filter shown in Figure 18 reduces harmonic
emission when placed between the ANT pin and antenna.
Number
of bits
Location
of bits
Modulation
2
Reg1[7:6]
Modulation selection
Mod_I
5
Reg4[4:0]
Modulator current setting
Mod_A
4
Reg5[3:0]
Modulator attenuator setting
Mod_F
3
Reg4[7:5]
Modulator filter setting
PA
3
Reg0[6:4]
Power amplifier level
Table 17
PA_by
1
Reg2[4]
Bypass of PA stage on/off
Table 17
Field Name
Description
Reference
Table 18
Table 16. Register Bit Fields for Transmitter and VCO Modulation
PA2
PA1
PA0
0
0
0
State (approximate attenuation)
PA off
0
0
1
15dB attenuation
0
1
0
12.5dB attenuation
0
1
1
10dB attenuation
1
0
0
7.5dB attenuation
1
0
1
5dB attenuation
1
1
0
2.5dB attenuation
1
1
1
Max output
PA_By
0
Power Amplifier Enabled
1
Power Amplifier bypassed, approx 20dB reduced output power.
Table 17. Register Bit Fields for Power Amplifier
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MICRF507
C5
39pF
Modulation1 Modulation0
L1
12nH
ANT (pin 5)
C6
12pF
C4
12pF
State
0
0
Closed loop VCO-modulation
0
1
Not in use
1
0
Modulation by A,M and N
1
1
Not in use
Table 18. Modulation Field
Figure 18. LC Filter
This filter is designed for the 490MHz band with 50Ω
terminations. Component values may have to be tuned to
compensate for layout parasitics.
Frequency Modulation
The MICRF507 supports two methods of FSK modulation,
selected with the Modulation field as shown in Table 18:
VCO modulation (enabled when Modulation1 is bit set to
0) and divider modulation (Modulation1 bit set to 1). The
Modulation0 bit must always remain 0.
Bits from the microcontroller to be transmitted enter at the
DATAIXO pin. See Table 19.
The modulation index ß must be a minimum of 2. It is
given by
β=2
fDEV
rb
in which fDEV is the single-sided deviation and rb is the bit
rate. Another constraint on fDEV is
fDEV ≥ rb + fOFFSET
where fOFFSET is the total frequency offset between the
receiver and the transmitter:
The calculated fDEV should be used to calculate the needed
receiver bandwidth, see “Switched Capacitor Filter”
section.
VCO Modulation
Frequency Divider Modulation
Set Modulation[1:0] to
00
10
Means of modulation
VCO modulation using modulator
Divider modulation by switching between
A0/M0/NO and A1/M1/N1
Register fields to set
Refclk_K, Mod_clkS, Mod_I, Mod_A,
Mod_F
A0, M0, N0, A1, M1, N1
PLL bandwidth required
Lower than 1/10 of bit rate
Higher than 2x bit rate
Bitstream constraints
DC balance required
None
Instantaneous frequency
waveform (spectrum)
determined by
Register fields affecting modulator
PLL transient response
Table 19. Modulation Modes
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MICRF507
Divider Modulation
When Modulation[1:0] = 10, two sets of divider values
need to be programmed. The divider values stored in the
M0, N0, and A0 registers are selected to transmit a ‘0’ and
the M1, N1, and A1 registers are selected to transmit a ‘1’.
fRF0 = fXCO
16 × N0 + A0
2M0
fRF1 = fXCO
16 × N1 + A1
2M1
The carrier frequency that a receiver must be set to in
order to receive the above transmitted signal is:
fRF =
fRF0 + fRF1
2
and the single-sided deviation is:
fDEV =
fRF1 − fRF0
2
as to “round” the waveform and reduce the transmission
spectral width.
The amplitude of the modulating waveform, and therefore
frequency deviation, is determined by the modulation clock
frequency (controlled by the crystal oscillator frequency
and the register fields Refclk_K, and Mod_ClkS), the
charge/discharge current (controlled by the register field
Mod_I), and the setting of an attenuator (controlled by the
register field Mod_A). The effects of these factors are
explained and quantified belo. A filter is provided to
optimize transmit bandwidth, the proper setting of which is
also explained below.
The synthesizer is a negative feedback loop that
suppresses perturbations inside the loop (including the
modulating varactor control voltage) below its bandwidth.
The PLL will not allow modulation unless its transient
response is slower than the bitstream pulses. Frequency
deviation is a high-pass response to modulation. This
means that when VCO modulation is used, the loop
bandwidth must be less than the lowest baseband spectral
component of the bitstream. It also means that the
bitstream must be DC-free (have an equal number of ones
and zeros). See “DC Balanced Line Coding” section.
The PLL must lock to a new frequency upon every
transition in the transmitted bitstream and therefore, needs
a high bandwidth, at least twice the bit rate.
VCO Modulation and the Modulator
VCO Modulation is selected when Modulation[1:0] = 00.
The modulator generates a waveform with programmable
amplitude and shape. This waveform is fed into a
modulation varactor in the VCO, which performs the
desired frequency modulation. The synthesizer operates
with A=A0, M=M0, and N=N0.
To create the modulating waveform the modulator charges
and discharges a capacitor, controlled by a modulator
clock. As shown in Figure 19, each transition of the
waveform takes four periods of the modulator clock.
Charge/discharge current, and therefore slope, varies so
October 2, 2013
Figure 19. Modulator Waveform and Clock
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MICRF507
Frequency Deviation under VCO Modulation
Three factors determine the deviation at which the data
stream is modulated: modulator clock frequency, capacitor
charge/discharge current, and modulator attenuator
setting. After each is presented in turn, the complete
formula for deviation is given.
The modulator clock frequency is determined by the
crystal oscillator frequency and the settings of the
Refclk_K and Mod_clkS fields:
fMOD_CLK =
To avoid saturation in the modulator, it is important not to
exceed maximum Mod_I. Maximum Mod_I for a given
fMOD_CLK is given by:
Mod_IMAX = INT(fMOD_CLK ⋅ 28 × 10 -6 ) - 1
where INT() returns the integer part of the argument.
fXCO
Refclk_K × 2 (7-Mod_clkS)
Set the modulator clock frequency to either 8x or 16x the
frequency deviation rate.
Figure 21. Two Different Modulator Current Settings
A third factor determining deviation is the modulator
attenuator, controlled by the Mod_A field. The attenuator is
used when the bit rate is small and/or the BT is small,
which gives a relatively slow modulator clock and therefore
long rise- and fall times, leading in turn to large frequency
deviations unless the signal is attenuated. Additionally, the
attenuator will improve the resolution in the modulator.
Figure 20. Two Different Modulator Clock Settings
Having fMOD_CLK set at 8 times the bit rate corresponds to a
baseband data signal filtered in a Gaussian filter with a
bandwidth-period product (BT) of 1. When BT is increased,
the waveform will be less filtered. Figure 20 shows two
waveforms with BT=1 (the minimum, with fMOD_CLK at 8
times the bitrate) and BT=2 (with fMOD_CLK at 16 times the
bit rate). Changing BT changes the charge-and discharge
times and therefore the frequency deviation, as seen in
Figure 20.
The capacitor charge/discharge current, set with the Mod_I
field, affects deviation, as shown in Figure 21, where
Mod_Ia>Mod_Ib. Higher current will give a higher
frequency deviation and vice versa. The effect of
modulator clock and Mod_I is as follows:
fDEV
Figure 22. Two Different Modulator Attenuator Settings
The effect of the attenuator is given by:
fDEV ∝
Mod_I
∝
fMOD_CLK
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1 + Mod_A
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Micrel, Inc.
MICRF507
Figure 22 shows two waveforms with different attenuator
setting: Mod_Aa < Mod_Ab . If Mod_A is increased, the
frequency deviation is lowered and vice versa.
The resulting frequency deviation in terms of the
parameters discussed above is given in the following
equations:
fMOD_CLK =
fDEV =
fXCO
Refclk_K × 2 (7−Mod_clkS)
Mod_I
1
×
× (C1 + C 2 × fRF )
fMOD_CLK 1 + Mod_A
where:
fDEV:
fXCO:
fRF:
Refclk_K:
Mod_clkS:
fMOD_CLK:
Mod_I:
Mod_A:
C1:
C2:
Figure 23. Modulator Waveform with and without Filtering
in which rb is the bit rate in bits/sec. Mod_F=0 disables the
modulator filter and Mod_F=7 provides the most filtering.
Figure 23 shows a waveform with and without the filter.
The modulator filter will not influence the frequency
deviation as long as the programmed cut-off frequency is
above the actual bit rate.
Single sided frequency deviation [Hz]
Crystal oscillator frequency [Hz]
Center frequency [Hz]
6 bit divider, values between 1 and 63
Modulator clock setting, values
between 0 and 7
Modulator clock frequency, derived
from the crystal frequency, Refclk_K
and Mod_clkS
Modulator current setting, values
between 0 and 31
Modulator attenuator setting, values
between 0 and 15
10
-2.72 x 10
85.2
Note that the constants C1 and C2 are empirically derived.
Actual frequency deviation may differ by a few percent.
Modulator Filter
To reduce the high-frequency components in the
generated waveform, a filter with programmable cut-off
frequency can be enabled. This is done using Mod_F[2:0],
bit 0 being LSB. The Mod_F field should be set according
to the formula:
Mod_F =
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150x10 3 bps
rb
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MICRF507
System Modes and Initialization
Start-up and Initialization
After supply voltage is applied to the MICRF507, a power
on reset period elapses during which it should be
considered to be in an unknown state. The microcontroller
should wait until power on reset is completed. See
“Power-On Reset” subsection within the “Control (3-wire)
Interface” section. After power-on is completed, all 22
writeable registers must be correctly initialized before
operation of the MICRF507. Write only non-zero values to
the M0, N0, M1, and N1 fields.
When using VCO modulation; after MICRF507 has been
put in transmit mode, the microcontroller will tri-state the
driver connected to DATAIXO pin to leave that pin floating
until the microcontroller begins sending data. This is
because in transmit mode, the modulator is disabled while
the DATAIXO pin is floating (a weak voltage divider sets its
level at Vdd/2) in order to prevent a performancedegrading transient when message transmission begins.
Below, “write to registers” means writing a complete
control word, or writing just to registers that need to
change.
Transition to transmit mode:
Modes of Operation
Mode1
Mode0
State
Comments
0
0
Power
down
Keeps register configuration
0
1
Standby
Only crystal oscillator
running
1
0
Receive
Full receive
Transmit
Full transmit except PA
state
1
1
•
Write to registers setting PA on (this requires
updating Register 0 only).
•
Wait for LD.
•
Enable the microcontroller’s pin as an output
driving DATAIXO and begin sending the transmit
bitstream.
After the last bit is transmitted return the
microcontroller’s pin to being an input.
Transition to receive mode:
Mode Transitions
To go from power down mode to either receive or transmit
mode, the MICRF507 needs to go through the standby
mode first. This is to ensure that the crystal oscillator starts
up correctly. Once the crystal oscillator settles, the
MICRF507 can go to receive or transmit mode.
When the mode has been changed to Transmit or
Receive, or when the power amplifier has been enabled,
the synthesizer must be allowed to stabilize. See “Lock
Detect” section.
Number
of bits
Write to registers, setting transmit mode, and other
changes as needed; set/keep PA off (to reduce
spurious emissions). This makes DATAIXO an
input.
•
Table 20. Main Mode Bits
Field Name
•
Location
of bits
•
Have the
disabled.
•
Write to registers setting receive mode and other
changes as needed.
•
Wait for LD. Or, if desired, commence checking
the received bitstream for a valid message without
waiting.
microcontroller’s
Description
DATAIXO
driver
Reference
Mode
2
Reg0[2:1]
Main mode selection
Table 20
OUTS
4
Reg2[3:0]
Test pins output
Table 28
Table 21. Register Bit Fields for System Functions
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MICRF507
Message Coding and Formatting
DC Balanced Line Coding
Line coding, diagrammed in Figure 24, is used when a
communication channel imposes constraints on bit
sequences. An encoding stage that ensures DC balance
(equal numbers of ‘1’ and ‘0’ bits and no long consecutive
runs of either) in the encoded bit stream allows the use of
VCO modulation without restrictions on the message bit
stream. Of the coding schemes which meet this need,
Manchester encoding and 3B4B are among the most
commonly used. Programming and performance of the
MICRF507 are based on the encoded bit rate.
In Manchester encoding, each message bit maps to a
word made of two encoded bits as shown in Table 22. The
encoded bit rate is twice the message bit rate so the
encoding overhead is 100%. When selecting PLL loop
filter it is important to note that frequency content of the
encoded bit stream extends down to one-fourth of the
encoded bit rate. That is the case of a 0101… message
bit sequence, which results in a 100110011001… encoded
bit sequence.
Data
Word
“0”
“10”
“1”
“01”
Table 22. Manchester Encoding
Another encoding method, which is much more efficient
than Manchester coding, is 3B4B, where three message
data bits are encoded into a four-line-bit word. The
encoded bit rate is three-quarter times the message bit
rate. For perfect DC balance, a four bit word would have to
have two ‘1’ line bits and two ‘0’ line bits. Only six such
words are possible. Special steps are therefore needed to
deal with the remaining two encodings: whenever 000 and
111 data appear, toggle a flag that remembers whether the
last encoded word was taken from the “Word A” column
and select the respective word from the other column
shown in Table 23.
Data
Word A
Word B
000
1011
0100
001
1100
010
0011
011
1010
100
0101
101
1001
110
0110
111
1101
0010
Table 23. 3B4B Encoding
Data bits
Encoded words
Comments
000 000 000 000
000
1011 0100 1011
0100 1011
A Flag indicates
if “Word A” has
been used
111 111 010 110
000
1101 0010 0011
0110 1011
A Flag indicates
if “Word A” has
been used
Table 24. Example of 3B4B Encoding
Message Formatting: Preamble
Messages are typically preceded by a header consisting of
24 bits in an alternating pattern: 0101… Such a header
can permit the following actions by the receiver prior to the
arrival of information-carrying bits:
•
Reading of RSSI
•
Bit synchronizer lock-up
•
Using the FEE to null out frequency offset
Figure 24. Link Architecture with Encoding
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Micrel, Inc.
MICRF507
Typical Application
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MICRF507
Bill of Materials
Item
Part Number
C1
GRM188R71C103K
C2
GRM219R71C104K
Manufacturer
Murata
(6)
Murata
C3
Description
Qty.
0.01µF, 16V Capacitor, X7R ±10%, Size 0603
1
0.1µF, 16V Capacitor, X7R ±10%, Size 0805
1
No Connect
0
C4
GRM1885C1H120J
Murata
12pF, 50V Capacitor, COG ±5%, Size 0603
1
C5
GRM1885C1H390J
Murata
39pF, 50V Capacitor, COG ±5%, Size 0603
1
C6
GRM1885C1H120J
Murata
12pF, 50V Capacitor, COG ±5%, Size 0603
1
C7
GRM155R61A102K
Murata
Optional 1000pF
1
C8, C9
GRM1555C1H1R5C
Murata
1.5pF, 50V Capacitor, COG ±0.25pF, Szie 0402
2
C10
GRM155R61A102K
Murata
1000pF, 10V Capacitor, X5R ±10%, Size 0402
1
C11
GRM155R71H221K
Murata
220pF, 50V Capacitor, X7R ±10%, Size 0402
1
C12, C13
GRM155R61A102K
Murata
1000pF, 10V Capacitor, X5R ±10%, Size 0402
2
6.2k Resistor, ±5%, Size 0402
1
(7)
R1
CRCW04026200RJK
Vishay
R2
CRCW04020RJK
Vishay
0Ω Resistor, ±5%, Size 0402
1
R3
CRCW040227KJK
Vishay
27k Resistor, ±5%, Size 0402
1
R5
CRCW040282KJK
Vishay
82k Resistor, ±5%, Size 0402
1
R6
CRCW040233KJK
Vishay
33K Resistor, ±5%, Size 0402
1
R7
CRCW04020RJK
Vishay
0Ω Resister, ±5% Size 0402
1
12nH, ±5%, Size 0603
1
16MHz, 9pF, 10/10ppm
1
470MHz to 510MHz Low-Power FSK Transceiver
with +10dBm Power Amplifier
1
(8)
L1
0603CS-12NXJB
Coilcraft
Y1
TSX-10A16.0000MHz:
TN4-26011
Toyocom
U1
MICRF507
(9)
(10)
Micrel, Inc.
Notes:
6.
Murata: www.murata.com
7.
Vishay: www.vishay.com
8.
Coilcraft: www.coilcraft.com
9.
Toyocom: www.epsontoyocom.co.jp/english
10. Micrel, Inc.: www.micrel.com
October 2, 2013
36
Revision 2.2
Micrel, Inc.
Layout Considerations
To ensure the best RF performance, a carefully planned
layout is essential. Grounding, RF path geometry, supply
routing, and layer definition all play a role in an optimal
design. These are discussed below, and a recommended
layout can be found on the Micrel website at:
www.micrel.com.
Layer Definition
A typical MICRF507 PCB design consists of four layers,
with the following stack-up:
Layer1 – Component and RF routing
Layer2 – Ground
Layer3 – VDD Routing
Layer 4 – Non-RF Routing
While not the only acceptable definition, this example
provides a good foundation for the general techniques
discussed below.
Grounding
Design the layout to provide the shortest possible return
path for signals and noise sources. Place ground vias
close to all critical items such as ground pins on the RF IC,
decoupling capacitors, and matching components.
October 2, 2013
MICRF507
RF Traces
The ANT pin impedance is approximately 50Ω. To
minimize reflection due to impedance mismatch, RF traces
should be a controlled impedance of 50Ω as well. Refer to
the Micrel Development Board layout, or a transmission
line impedance calculator to verify a specific geometry’s
characteristic impedance.
Supply Routing
The radio system is sensitive to supply noise and signals
coupled from one section to another. Routing the supply
lines on an internal layer (below the ground layer)
separates them from potential noise sources such as the
reference oscillator, PA, charge pump, etc. Route supplies
separately and place bypass capacitors as close as
possible to the associated pin.
PLL Loop Filter
Place loop filter components close to each other and near
pins 27 and 29. Connection of the loop filter to VDD should
occur very close to VCOVDD, pin 31. Avoid routing
potentially noisy busses or traces near the loop filter.
37
Revision 2.2
Micrel, Inc.
MICRF507
Overview of Programming Bits
Address
Field
Data Field
A6..A0
D7
D6
D5
D4
D3
D2
D1
D0
0000000
LNA_by
PA2
PA1
PA0
Sync_en
Mode1
Mode0
Load_en
0000001
Modulation1
Modulation0
RSSI_en
LD_en
PF_FC1
PF_FC0
0000010
CP_HI
SC_by
PA_by
OUTS3
OUTS2
OUTS1
OUTS0
IFBias_s
IFA_HG
VCO_BIAS_s
(“1”)
(“1”)
(“0”)
VCO_IB2
VCO_IB1
VCO_IB0
VCO_freq
1
VCO_freq0
0000100
Mod_F2
Mod_F1
Mod_F0
Mod_I4
Mod_I3
Mod_I2
Mod_I1
Mod_I0
0000101
-
-
Mod_FHG
Mod_shape
(“0”)
(“1”)
Mod_A3
Mod_A2
Mod_A1
Mod_A0
0000110
-
Mod_clkS2
0000011
0000111
BitRate_clkS1 BitRate_clkS0
OL_opamp_en PA_LDc_en
(“0”)
VCO_by
(“0”)
(”0”)
Mod_clkS1
Mod_clkS0 BitSync_clkS2 BitSync_clkS1
BitSync_cl
BitRate_clkS2
kS0
RefClk_K5
RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
ScClk4
ScClk3
ScClk2
ScClk1
ScClk0
XCOtune4
XCOtune3
XCOtune2
XCOtune1
XCOtune0
SC_HI
ScClk_X2
ScSW_en
(“1”)
(“1”)
(“0”)
PrescalMode_s
Prescal_s
XCOAR_en
(“0”)
(“0”)
(”1”)
0001010
-
-
A0_5
A0_4
A0_3
A0_2
A0_1
A0_0
0001011
-
-
-
-
N0_11
N0_10
N0_9
N0_8
0001100
N0_7
N0_6
N0_5
N0_4
N0_3
N0_2
N0_1
N0_0
0001000
0001001
0001101
-
-
-
-
M0_11
M0_10
M0_9
M0_8
0001110
M0_7
M0_6
M0_5
M0_4
M0_3
M0_2
M0_1
M0_0
0001111
-
-
A1_5
A1_4
A1_3
A1_2
A1_1
A1_0
0010000
-
-
-
-
N1_11
N1_10
N1_9
N1_8
0010001
N1_7
N1_6
N1_5
N1_4
N1_3
N1_2
N1_1
N1_0
0010010
-
-
-
-
M1_11
M1_10
M1_9
M1_8
0010011
M1_7
M1_6
M1_5
M1_4
M1_3
M1_2
M1_1
M1_0
Div2_HI
LO_IB1
LO_IB0
PA_IB4
PA_IB3
PA_IB2
PA_IB1
PA_IB0
(“1”)
(“0”)
(“1”)
(”1”)
(”0”)
(”1”)
(”0”)
(“1”)
0010101
-
-
-
-
FEEC_3
FEEC_2
FEEC_1
FEEC_0
0010110
FEE_7
FEE_6
FEE_5
FEE_4
FEE_3
FEE_2
FEE_1
FEE_0
0010100
Table 25. Overview of Register Bits
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Revision 2.2
Micrel, Inc.
MICRF507
Detailed Description of Programming Bits
ADR #
BIT #
0000000
0000001
0000010
0000011
0000100
Name
Description
7
By_LNA
LNA bypass on/off
6
PA2
Power amplifier level, 3.bit
Reference Table 17
5
PA1
Power amplifier level, 2.bit
Reference Table 17
4
PA0
Power amplifier level, 1.bit
Reference Table 17
3
Sync_en
Synchronizer Mode bit
Reference Table 7
2
Mode1
Main Mode selection 2.bit
Reference Table 20
1
Mode0
Main Mode selection 1.bit
Reference Table 20
0
Load_en
“1” mandatory
Comments
7
Modulation1
Modulation selection 2.bit
Reference Table 18
6
Modulation0
Modulation selection 1.bit
Reference Table 18
5
OL_opamp_en
“0” mandatory
4
PA_LDc_en
“0” mandatory. PA on/off controlled by Lock Detect pin
if this bit is 1
3
RSSI_en
RSSI function on/off
2
LD_en
Lock detect function on/off
1
PF_FC1
Pre-filter corner frequency 2.bit
Reference Table 14
0
PF_FC0
Pre-filter corner frequency 1.bit
Reference Table 14
7
CP_HI
High charge-pump current (4x=500uA) on/off
6
SC_by
Bypass of Switched Capacitor filter on/off
5
VCO_by
“0” mandatory. Bypass of VCO stage on/off
4
PA_by
Bypass of PA stage on/off
3
OUTS3
Test pins output 4.bit
Reference Table 28
2
OUTS2
Test pins output 3.bit
Reference Table 28
1
OUTS1
Test pins output 2.bit
Reference Table 28
0
OUTS0
Test pins output 1.bit
Reference Table 28
7
IFBias_s
“1” mandatory.
6
IFA_HG
“1” mandatory.High gain setting in preamplifier
5
VCO_Bias_s
“0” mandatory.Select separate bias for VCO on
VCOBias pin
4
VCO_IB2
VCO bias current setting, 3. bit (111 = highest current)
Reference Table 11
3
VCO_IB1
VCO bias current setting, 2. bit (100 = typical current)
Reference Table 11
2
VCO_IB0
VCO bias current setting, 1. bit
Reference Table 11
1
VCO_freq1
Frequency setting of VCO, 2. bit (11=highest
frequency)
Reference Table 11
0
VCO_freq0
Frequency setting of VCO, 1.bit
Reference Table 11
7
Mod_F2
Modulator filter setting, MSB
6
Mod_F1
Modulator filter setting
5
Mod_F0
Modulator filter setting, LSB
4
Mod_I4
Modulator current setting, MSB
3
Mod_I3
Modulator current setting
2
Mod_I2
Modulator current setting
1
Mod_I1
Modulator current setting
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Revision 2.2
Micrel, Inc.
ADR #
MICRF507
BIT #
0
0000101
0000110
0000111
0001000
0001001
Name
Description
Mod_I0
Modulator current setting, LSB
Comments
7
---------
Reserved/not in use
6
---------
Reserved/not in use
5
Mod_FHG
“0” mandatory. Modulator Test bit.
4
Mod_shape
“1” mandatory.Modulator shape enable
3
Mod_A3
Modulator attenuator setting, LSB
2
Mod_A2
Modulator attenuator setting
1
Mod_A1
Modulator attenuator setting
0
Mod_A0
Modulator attenuator setting, MSB (=0: Attenuator
active)
7
---------
Reserved/not in use
6
Mod_clkS2
Modulator clock setting 3.bit
5
Mod_clkS1
Modulator clock setting 2.bit
4
Mod_clkS0
Modulator clock setting 1.bit
3
BitSync_clkS2
BitSync clock setting 3.bit
2
BitSync_clkS1
BitSync clock setting 2.bit
1
BitSync_clkS0
BitSync clock setting 1.bit
0
BitRate_clkS2
Bitrate clock setting 3.bit
7
BitRate_clkS1
Bitrate clock setting 2.bit
6
BitRate_clkS0
Bitrate clock setting 1.bit
5
RefClk_K5
Reference clock divider 6.bit
4
RefClk_K4
Reference clock divider 5.bit
3
RefClk_K3
Reference clock divider 4.bit
2
RefClk_K2
Reference clock divider 3.bit
1
RefClk_K1
Reference clock divider 2.bit
0
RefClk_K0
Reference clock divider 1.bit
7
SC_HI
“1” mandatory. Switced Cap filter high current setting
on/off
6
ScClk_X2
“1” mandatory. Switced Cap clock mulitplied by two
5
ScSw_EN
“0” mandatory. Switch cap switch enable
4
ScClk4
SwitchCap clock divider 5.bit
3
ScClk3
SwitchCap clock divider 4.bit
2
ScClk2
SwitchCap clock divider 3.bit
1
ScClk1
SwitchCap clock divider 2.bit
0
ScClk0
SwitchCap clock divider 1.bit
7
PrescalMode_s
“1” mandatory. Select external control of prescal mode
(div32/33)
6
Prescale_s
“0” mandatory. Select external control of prescale mode
(div 32/33)
5
XCOAR_en
“1” mandatory. XCO amplitude regulation on/off
4
XCOtune4
Crystal oscillator trimming, LSB
3
XCOtune3
Crystal oscillator trimming
2
XCOtune2
Crystal oscillator trimming
1
XCOtune1
Crystal oscillator trimming
October 2, 2013
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Revision 2.2
Micrel, Inc.
ADR #
MICRF507
BIT #
0
0001010
0001011
0001100
0001101
0001110
0001111
Name
Description
XCOtune0
Crystal oscillator trimming, MSB
7
---------
Reserved/not in use
6
---------
Reserved/not in use
5
A0_5
A0-counter 6.bit
4
A0_4
A0-counter 5.bit
3
A0_3
A0-counter 4.bit
2
A0_2
A0-counter 3.bit
1
A0_1
A0-counter 2.bit
0
A0_0
A0-counter 1.bit
7
---------
Reserved/not in use
6
---------
Reserved/not in use
5
---------
Reserved/not in use
4
---------
Reserved/not in use
3
N0_11
N0-counter 12.bit
2
N0_10
N0-counter 11.bit
1
N0_9
N0-counter 10.bit
0
N0_8
N0-counter 9.bit
7
N0_7
N0-counter 8.bit
6
N0_6
N0-counter 7.bit
5
N0_5
N0-counter 6.bit
4
N0_4
N0-counter 5.bit
3
N0_3
N0-counter 4.bit
2
N0_2
N0-counter 3.bit
1
N0_1
N0-counter 2.bit
0
N0_0
N0-counter 1.bit
7
---------
Reserved/not in use
6
---------
Reserved/not in use
5
---------
Reserved/not in use
4
---------
Reserved/not in use
3
M0_11
M0-counter 12.bit
2
M0_10
M0-counter 11.bit
1
M0_9
M0-counter 10.bit
0
M0_8
M0-counter 9.bit
7
M0_7
M0-counter 8.bit
6
M0_6
M0-counter 7.bit
5
M0_5
M0-counter 6.bit
4
M0_4
M0-counter 5.bit
3
M0_3
M0-counter 4.bit
2
M0_2
M0-counter 3.bit
1
M0_1
M0-counter 2.bit
0
M0_0
M0-counter 1.bit
7
---------
Reserved/not in use
6
---------
Reserved/not in use
October 2, 2013
Comments
41
Revision 2.2
Micrel, Inc.
ADR #
0010000
0010001
0010010
0010011
0010100
MICRF507
BIT #
Name
Description
5
A1_5
A1-counter 6.bit
4
A1_4
A1-counter 5.bit
3
A1_3
A1-counter 4.bit
2
A1_2
A1-counter 3.bit
1
A1_1
A1-counter 2.bit
0
A1_0
A1-counter 1.bit
7
---------
Reserved/not in use
6
---------
Reserved/not in 7use
5
---------
Reserved/not in use
4
---------
Reserved/not in use
3
N1_11
N1-counter 12.bit
2
N1_10
N1-counter 11.bit
1
N1_9
N1-counter 10.bit
0
N1_8
N1-counter 9.bit
7
N1_7
N1-counter 8.bit
6
N1_6
N1-counter 7.bit
5
N1_5
N1-counter 6.bit
4
N1_4
N1-counter 5.bit
3
N1_3
N1-counter 4.bit
2
N1_2
N1-counter 3.bit
1
N1_1
N1-counter 2.bit
0
N1_0
N1-counter 1.bit
Comments
7
---------
Reserved/not in use
6
---------
Reserved/not in use
5
---------
Reserved/not in use
4
---------
Reserved/not in use
3
M1_11
M1-counter 12.bit
2
M1_10
M1-counter 11.bit
1
M1_9
M1-counter 10.bit
0
M1_8
M1-counter 9.bit
7
M1_7
M1-counter 8.bit
6
M1_6
M1-counter 7.bit
5
M1_5
M1-counter 6.bit
4
M1_4
M1-counter 5.bit
3
M1_3
M1-counter 4.bit
2
M1_2
M1-counter 3.bit
1
M1_1
M1-counter 2.bit
0
M1_0
M1-counter 1.bit
7
Div2_HI
“1” mandatory. High bias current setting in Div2 circuit
on/off
6
LO_IB1
“0 mandatory. Bias current setting of LObuffer, 2. bit
(11 = highest current)
October 2, 2013
42
Revision 2.2
Micrel, Inc.
ADR #
0010101
0010110
MICRF507
BIT #
Name
Description
5
LO_IB0
“1” mandatory. Bias current setting of LObuffer, 1. bit
(01 = typical current)
4
PA_IB4
“0” mandatory. Bias current setting of PA, 2. bit (11 =
highest current)
3
PA_IB3
“0 mandatory. Bias current setting of PA, 1. bit (01 =
typical current)
2
PA_IB2
“0” mandatory. Bias current setting of PAbuffer, 3. bit
1
PA_IB1
“1”mandatory. Bias current setting of PAbuffer, 2. bit
Comments
0
PA_IB0
“1” mandatory. Bias current setting of PAbuffer, 1. bit
7
---------
Reserved/not in use
6
---------
Reserved/not in use
5
---------
Reserved/not in use
4
---------
Reserved/not in use
3
FEEC_3
FEE control bit
Reference Table 15
2
FEEC_2
FEE control bit
Reference Table 15
1
FEEC_1
FEE control bit
Reference Table 15
0
FEEC_0
FEE control bit
Reference Table 15
7
FEE_7
FEE value, bit 7, MSB
6
FEE_6
FEE value, bit 6
5
FEE_5
FEE value, bit 5
4
FEE_4
FEE value, bit 4
3
FEE_3
FEE value, bit 3
2
FEE_2
FEE value, bit 2
1
FEE_1
FEE value, bit 1
0
FEE_0
FEE value, bit 0, LSB
Table 26. Detailed Description of Programming Bits
October 2, 2013
43
Revision 2.2
Micrel, Inc.
Clocking
Category
Field Name
Number
of Bits
Location
of Bits
Description
XCOtune
5
Reg9[4:0]
Crystal oscillator trimming
RefClk_K
6
Reg7[5:0]
Reference clock divider
BitRate_clkS
3
Reg6[0],
Reg7[7:6]
Bitrate clock setting
Mod_clkS
3
Reg6[6:4]
Modulator clock setting
BitSync_clkS
3
Reg6[3:1]
BitSync clock setting
Sync_en
1
Reg0[3]
M0
12
Reg13[3:0],
Reg14[7:0]
M0 counter
A0
6
Reg10[5:0]
A0 counter
N0
12
Reg11[3:0],
Reg12[7:0]
N0 counter
M1
12
Reg18[3:0],
Reg19[7:0]
M1 counter
A1
6
Reg15[5:0]
A1 counter
N1
12
Reg16[3:0],
Reg17[7:0]
N1 counter
Transmit/VCO
modulation
Receive
Synthesizer
DataI/F
MICRF507
System
Synchronizer Mode bit
Reference
Table 7
High charge pump current (500 μA = 4x) on/off
CP_HI
1
Reg2[7]
VCO_Freq
2
Reg3[1:0]
Frequency setting of VCO (highest frequency at 11)
VCO_IB
3
Reg3[4:2]
VCO bias current setting (highest current at 111, 100
typical)
LD_en
1
Reg1[2]
Lock detect function on/off
By_LNA
1
Reg0[7]
LNA bypass on/off
PF_FC
2
Reg1[1:0]
SC_by
1
Reg2[6]
Pre-filter corner frequency
Table 14
Bypass of switched capacitor filter on/off
ScClk
5
Reg8[4:0]
RSSI_en
1
Reg1[3]
Switched Cap clock divider
FEEC
4
Reg21[3:0]
FEE control bits
FEE
8
Reg22[7:0]
FEE value (read only)
Modulation
2
Reg1[7:6]
Modulation selection
RSSI function on/off
Mod_I
5
Reg4[4:0]
Modulator current setting
Mod_A
4
Reg5[3:0]
Modulator attenuator setting
Mod_F
3
Reg4[7:5]
Modulator filter setting
PA
3
Reg0[6:4]
Power amplifier level
PA_by
1
Reg2[4]
Table 15
Table 18
Table 17
Bypass of PA stage on/off
Mode
2
Reg0[2:1]
Main mode selection
Table 20
OUTS
4
Reg2[3:0]
Test pins output
Table 28
Table 27. Register Fields
October 2, 2013
44
Revision 2.2
Micrel, Inc.
MICRF507
OutS3
OutS2
OutS1
OutS0
IchOut
QchOut
Ichout2 / RSSI
QchOut2 / NC
0
0
0
0
Gnd
Gnd
Gnd
Gnd
0
0
0
1
Ip mixer
In mixer
Ip IFamp
In IFamp
0
0
1
0
Qp mixer
Qn mixer
Qp IFamp
Qn IFamp
0
0
1
1
Ip IFamp
In IFamp
Ip SC-filter
In SC-filter
0
1
0
0
Qp IFamp
Qn IFamp
Qp SC-filter
Qn SC-filter
0
1
0
1
Ip SC-filter
In SC-filter
Gnd
I limiter
0
1
1
0
Qp SC-filter
Qn SC-filter
Gnd
Q limiter
0
1
1
1
Ip mixer
In mixer
Ip SC-filter
In SC-filter
1
0
0
0
Qp mixer
Qn mixer
Qp SC-filter
Qn SC-filter
1
0
0
1
Ip mixer
In mixer
Gnd
I limiter
1
0
1
0
Qp mixer
Qn mixer
Gnd
Q limiter
1
0
1
1
Ip mixer
Qp mixer
ModIn
PrescalMode
1
1
0
0
Ip IFamp
Qp IFamp
TI1
TQ1
1
1
0
1
Ip SC-filter
Qp SC-filter
DemodUp
DemodDn
1
1
1
0
I limiter
Q limiter
Demod
MAout
1
1
1
1
N-div
M-div
Phi1n
Phi2n
Table 28. Test Signals
October 2, 2013
45
Revision 2.2
Micrel, Inc.
MICRF507
Package Information(11) and Recommended Landing Pattern
32-Pin QFN (ML)
Note:
11. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
October 2, 2013
46
Revision 2.2
Micrel, Inc.
MICRF507
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2010 Micrel, Incorporated
October 2, 2013
47
Revision 2.2