ADC Application Note
ADC Application Note
1
适用产品：
1.1. SM59R16A2 / SM59R08A2
1.2. SM59R16A5/ SM59R09A5/ SM59R05A5/ SM59R16A3/ SM59R09A3/ SM59R05A3
1.3. SM59R04A2/ SM59R04A1/ SM59R03A1/ SM59R02A1
文件说明：SM59R 系列注意 ADC 因架构差异，各型号说明请参考以下相对章节。
2
3
SM59R16A5/ SM59R09A5/ SM59R05A5/ SM59R16A3/ SM59R09A3/ SM59R05A3/ SM59R04A2/
SM59R04A1/ SM59R03A1/ SM59R02A1 ADC 使用说明：
3.1 ADC 规格概述：
3.1.1 提供8组独立的10-bit ADC。
3.1.2 提供ADC中断向量于0x53H。
3.1.3 ADC为SAR架构。
3.1.4 ADC clock(Hz)不可大于500KHz，提供32组预除设定（请参考SFR ADCCS设定）。
3.2 SFR 特殊控制缓存器及特殊状态缓存器介绍：
Mnemonic
Description
Dire
ct
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESE
T
ADC
ADCC1
ADCC2
ADCDH
ADCDL
ADCCS
IEN1
IRCON
ADC Control register
1
ADC Control register
2
ADC data high byte
ADC data low byte
ADC clock select
Interrupt Enable 1
register
Interrupt request
register
ABh
ACh
ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN
Start
ADJUST
-
-
-
ADCCH[2:0]
ADCDH [7:0]
ADCDL [7:0]
00H
00H
ADh
AEh
AFh
00H
00H
00H
-
-
-
B8h
EXEN2
-
IEIIC
IELVI
IEKBI
IEADC
IESPI
IEPWM
00h
C0H
EXF2
TF2
IICIF
LVIIF
KBIIF
ADCIF
SPIIF
PWMIF
00H
ADCCS[4:0]
Mnemonic: ADCC1
Address: ABh
7
6
5
4
3
2
1
0
Reset
ADC7EN ADC6EN ADC5EN ADC4EN ADC3EN ADC2EN ADC1EN ADC0EN
00H
ADC7EN: ADC channels 7 enable.
ADC7EN = 1 – Enable ADC channel 7
ADC6EN: ADC channels 6 enable.
ADC6EN = 1 – Enable ADC channel 6
ADC5EN: ADC channels 5 enable.
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
1
Ver. A 2010/06
ADC Application Note
ADC5EN = 1 – Enable ADC channel 5
ADC4EN: ADC channels 4 enable.
ADC4EN = 1 – Enable ADC channel 4
ADC3EN: ADC channels 3 enable.
ADC3EN = 1 – Enable ADC channel 3
ADC2EN: ADC channels 2 enable.
ADC2EN = 1 – Enable ADC channel 2
ADC1EN: ADC channels 1 enable.
ADC1EN = 1 – Enable ADC channel 1
ADC0EN: ADC channels 0 enable.
ADC0EN = 1 – Enable ADC channel 0
Mnemonic: ADCC2
7
6
5
Start ADJUST
-
4
-
3
-
2
1
ADCCH[2:0]
Address: ACh
0
Reset
00H
Start: When this bit is set, the ADC will be start conversion.
ADJUST: Adjust the format of ADC conversion DATA.
ADJUST = 0: (default value)
ADC data high byte ADCD [9:2] = ADCDH [7:0].
ADC data low byte ADCD [1:0] = ADCDL [1:0].
ADJUST = 1:
ADC data high byte ADCD [9:8] = ADCDH [1:0].
ADC data low byte ADCD [7:0] = ADCDL [7:0].
ADCCH[2:0]: ADC channel select.
ADCCH [2:0]
Channel
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
ADJUST = 0:
Mnemonic: ADCDH
Address: ADh
7
6
5
4
3
2
1
0
Reset
ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2]
00H
Mnemonic: ADCDL
7
6
ADJUST = 1:
Mnemonic: ADCDH
7
6
Mnemonic: ADCDL
5
-
5
-
4
-
4
-
3
-
2
-
3
-
1
ADCD[1]
2
-
Address: AEh
0
Reset
ADCD[0]
00H
Address: ADh
1
0
Reset
ADCD[9] ADCD[8]
00H
Address: AEh
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
2
Ver. A 2010/06
ADC Application Note
7
6
5
4
3
2
1
0
ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0]
Reset
00H
ADCD[9:0]: ADC data register.
Mnemonic: ADCCS
7
6
-
5
-
Address: AFh
4
3
2
1
0
Reset
ADCCS[4] ADCCS[3] ADCCS[2] ADCCS[1] ADCCS[0]
00H
ADCCS[4:0]: ADC clock select.
*The ADC clock maximum 12.5MHz.
*The ADC Conversion rate maximum 500KHz
ADCCS[4:0]
ADC Clock(Hz)
Clocks for ADC Conversion
00000
Fclk/2
46
00001
Fclk/4
92
00010
Fclk/6
138
00011
Fclk/8
184
00100
Fclk/10
230
00101
Fclk/12
276
00110
Fclk/14
322
00111
Fclk/16
368
01000
Fclk/18
414
01001
Fclk/20
460
01010
Fclk/22
506
01011
Fclk/24
552
01100
Fclk/26
598
01101
Fclk/28
644
01110
Fclk/30
690
01111
Fclk/32
736
10000
Fclk/34
782
10001
Fclk/36
828
10010
Fclk/38
874
10011
Fclk/40
920
10100
Fclk/42
966
10101
Fclk/44
1012
10110
Fclk/46
1058
10111
Fclk/48
1104
11000
Fclk/50
1150
11001
Fclk/52
1196
11010
Fclk/54
1242
11011
Fclk/56
1288
11100
Fclk/58
1334
11101
Fclk/60
1380
11110
Fclk/62
1426
11111
Fclk/64
1472
.
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
3
Ver. A 2010/06
ADC Application Note
Fclk
2 × ( ADCCS + 1)
ADC_Clock
ADC _ Conversion _ Rate =
23
ADC _ Clock =
Mnemonic: IEN1
7
6
EXEN2
5
IEIIC
4
IELVI
3
IEKBI
2
IEADC
1
IESPI
Address: B8h
0
Reset
IEPWM
00h
1
SPIIF
Address: C0h
0
Reset
PWMIF
00H
IEADC: A/D converter interrupt enable
IEADC = 0 – Disable ADC interrupt.
IEADC = 1 – Enable ADC interrupt.
Mnemonic: IRCON
7
6
5
EXF2
TF2
IICIF
4
LVIIF
3
KBIIF
2
ADCIF
ADCIF: A/D converter end interrupt flag. Must be cleared by software.
3.3 以下是 ADC 相对应的中断向量表：
Interrupt Vector
Address
Interrupt Number
*(use Keil C Tool)
IE0 – External interrupt 0
0003h
0
TF0 – Timer 0 interrupt
000Bh
1
IE1 – External interrupt 1
0013h
2
TF1 – Timer 1 interrupt
001Bh
3
RI0/TI0 – Serial channel 0 interrupt
0023h
4
TF2/EXF2 – Timer 2 interrupt
002Bh
5
PWMIF – PWM interrupt
(The SM59R16A2/SM59R08A2 haven’t)
0043h
8
SPIIF – SPI interrupt
004Bh
9
ADCIF – A/D converter interrupt
0053h
10
KBIIF – keyboard Interface interrupt
005Bh
11
LVIIF – Low Voltage Interrupt
(The SM59R16A2/SM59R08A2 haven’t)
0063h
12
IICIF – IIC interrupt
006Bh
13
RI1/TI1 – Serial channel 1 interrupt
0083h
16
008Bh
17
0093h
18
Interrupt Request Flags
RTC/ALARM interrupt
(Only SM59R16A5/SM59R09A5/SM59R05A5 have)
Comparator interrupt
(Only SM59R16A5/SM59R09A5/SM59R05A5 have)
*See Keil C about C51 User’s Guide about Interrupt Function description
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
4
Ver. A 2010/06
ADC Application Note
3.4 ADC 应用流程图：
3.5 ADC 程序范例：
Describe:
main
Program:
//====================================================================
//
//
S Y N C M O S T E C H N O L O G Y
//
//====================================================================
#include "..\h\SM59R04A2.h"
void main(void)
{
unsigned char temp_H,temp_L;
//ADCC1
ADCC1 =
//ADCC2
ADCC2 =
= 0xFF;
0x01;
= 0x40;
0x00;
//ADC
//ADC
//ADC
//ADC
Chanel
Chanel
Chanel
Chanel
all enable
0 enable
0 is analog input, Adjust=1
0 is analog input, Adiust=0
while(1)
{
ADCC2 |=0x80;
//sbit ADC START = 1, will auto clear after finish
while(!IRCON && 0x04); //finish if ADCIF=1, converting if ADCIF=0
temp_L = ADCDL; //ADC result, the Adjust=0, the ADCDL[1:0]=ADCD[1:0]
temp_H = ADCDH; //the ADCDH[7:0]=ADCD[9:2]
IRCON &= 0xFB; //Clear ADCIF flag for next ADC conversion
}
}
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
5
Ver. A 2010/06
ADC Application Note
4
SM59R16A2 / SM59R08A2 使用说明：
4.1 ADC 规格概述：
4.1.1 提供4组独立的ADC
4.1.2 10-bit或8-bit模式选择
4.1.3 ADC为SAR架构
4.1.4 ADC clock(Hz)不可大于500KHz，提供四组预除设定（请参考SFR ADCCS设定）
4.1.5 当VDD=3.3，可侦测电压为0V~3.3V
4.1.6 当VDD=5.0 应用，说明如下：
4.1.6.1
在ADC START之前，Port4[7:4]必须先输出”0000”调校
4.1.6.2
ADC IP是3.3V，应用在Analog IN=5V时，要接分压电阻（如下图），总电阻不可超
过50KΩ，建议为17KΩ及33KΩ即可 (Analog IN=3.3V则不用)
SM59R16A2
ADC
Analog
Voltage In
17KΩ
CH0~3
33KΩ
4.2 SFR 特殊控制缓存器及特殊状态缓存器介绍：
Mnemonic
ADCC1
ADCC2
ADCDH
ADCDL
Description
Direct
Bit 7
Bit 6
ADC Control 1
ADC Control 2
ADC data high
byte
ADC data low
byte
ABh
ACh
COM
START
Bit 5
ADC
ADC8B
ADh
-
Bit 3
Bit 2
ADC3E ADC2E
ADCCH[1:0]
-
AEh
Mnemonic: ADCC1
7
6
-
Bit 4
Bit 1
Bit 0
ADC1E ADC0E
ADCCS[1:0]
00h
00h
ADCDH [1:0]
00h
ADCDL[7:0]
5
-
4
-
3
ADC3E
2
ADC2E
1
ADC1E
RESET
00h
Address: ABh
0
Reset
ADC0E
00h
ADC3E: ADC Chanel 3 致能旗标
=0 : 禁能（预设）
=1 : 致能
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
6
Ver. A 2010/06
ADC Application Note
ADC2E: ADC Chanel 2 致能旗标
=0 : 禁能（预设）
=1 : 致能
ADC1E: ADC Chanel 1 致能旗标
=0 : 禁能（预设）
=1 : 致能
ADC0E: ADC Chanel 0 致能旗标
=0 : 禁能（预设）
=1 : 致能
Mnemonic: ADCC2
7
6
COM
START
5
ADC8B
4
-
3
2
ADCCH[1:0]
Address: ACh
1
0
Reset
ADCCS[1:0]
00h
COM: ADC 转换完成旗标（只读）
= 0：当 ADC module 转换启动时，该旗标由硬件自动设置为”0”
= 1：当 ADC module 转换完成时，该旗标由硬件自动设置为”1”
START: 开始（停止）转换旗标
= 0：表示 ADC modul 停止执行（预设）
= 1：由软件设定 ADC module 开始执行，完成后该旗标由硬件自动清除为”0”
ADC8B: 8-bit 模式旗标
= 0：选择 10-bit 模式（预设）；转换后数据存在缓存器 ADCD[9:0]
（High Byte: ADCD [9:8] = ADCDH [1:0]，Low Byte: ADCD [7:0] = ADCDL [7:0]）
= 1：选择 8-bit 模式；转换后数据存在缓存器（ADCD[7:0] = ADCDL [7:0] ）
ADCCH[1:0] 模拟输入通道选择旗标（The analog input signal can be chosen with it）：
ADCC1.ADCxE
ADCCH[1:0]
Note
对应 MCU 引脚
ADC0E
00
P4.4/ADC0
(default)
ADC1E
01
P4.5/ADC1
ADC2E
10
P4.6/ADC2
ADC3E
11
P4.7/ADC3
PS. ADC 致能与模拟输入通道必定要相对应才可正确地转换
ADCCS[1:0]: ADC除频选择旗标
= 00 : ADC clock 由系统频率除 8
= 01 : ADC clock 由系统频率除 16
= 10 : ADC clock 由系统频率除 32
= 11 : ADC clock 由系统频率除 64
为符合 spec，以下表格为设定 ADCCS 的建议值：
ADCCS[1:0]
ADC clock
00
Fclk/8
(Fclk: 1MHz ~ 4MHz)
01
Fclk/16
(Fclk: 4MHz ~ 8MHz)
10
Fclk/32
(Fclk: 8MHz ~ 16MHz)
11
Fclk/64
(Fclk: 16MHz ~ 32MHz)
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
7
Ver. A 2010/06
ADC Application Note
Fclk
8 × 2 ADCCS
ADC Clock =
(ADC 输入频率频率，单位：Hz，ADC clock 不可大于 500KHz)
20
ADC Clock
ADC Conversion Time =
(ADC 取样率，单位：Hz，每次转换需要 20 个 ADC clock 时间)
ADC Sample Rate =
Mnemonic: ADCDH
7
6
5
1
ADC Conversion Time
4
3
2
Address: ADh
1
0
Reset
ADCDH[1:0]
00h
ADCDH[1:0]: 高位数据储存缓存器 The high bits of digital output of this ADC
Mnemonic: ADCDL
7
6
5
4
3
ADCDL[7:0]
2
1
Address: AEh
0
Reset
00h
ADCDL[7:0]: 低位数据储存缓存器 The low bits of digital output of this ADC
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
8
Ver. A 2010/06
ADC Application Note
4.3 ADC 应用流程图：
4.4 ADC 程序范例：
Describe:
main
Program:
//====================================================================
//
//
S Y N C M O S T E C H N O L O G Y
//
//====================================================================
#include "..\h\SM59R16A2.h"
void main(void)
{
unsigned char temp_H,temp_L;
//ADCC1
ADCC1 =
//ADCC2
ADCC2 =
= 0x0F;
0x01;
= 0x20;
0x03;
//ADC
//ADC
//ADC
//ADC
Chanel
Chanel
8-bit
10-bit
all enable
0 enable
mode, Chanel 0 is analog input, Div=8
mode, Chanel 0 is analog input, Div=64
while(1)
{
ADCC2 |=0x40;
//sbit ADC START = 1, will auto clear after finish
while(!ADCC2 && 0x80); //finish if COM=1, converting if COM=0
temp_L = ADCDL; //ADC result
temp_H = ADCDH;
}
}
MSpecifications subject to change without notice, contact your sales representatives for the most recent information.
ISSFA-0204
9
Ver. A 2010/06