Low Power CMOS Output VCXO Family (17MHz to 130MHz)

Low Power CMOS Output VCXO Family (17MHz to 130MHz)
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VCXO output for the 17MHz to 130MHz range
- PLL500-17B: 17MHz to 36MHz
- PLL500-27B: 27MHz to 65MHz
- PLL500-37B: 65MHz to 130MHz
Low phase noise.
CMOS output with OE tri-state control.
Selectable output drive
- Standard: 8mA drive capability.
- High: 24mA drive capability.
Fundamental crystal input.
Integrated high linearity variable capacitors.
+/- 150 ppm pull range, max 5% linearity.
Low jitter (RMS): 2.5ps period jitter.
2.5V ~ 3.3V operation.
Available in 8-Pin SOP or Die.
XIN
1
OE^
2
VCON
3
GND
4
XOUT
8
P500-x7B

PIN CONFIGURATION
7
DRIVSEL^
6
VDD
5
CLK
^: Denotes internal Pull-up
DIE PAD LAYOUT
32 mil
(812,986)
8
1
XIN
XOUT
DRIVSEL^ 7
2
39 mil
FEATURES
OE^
VDD 6
3 VCON
DESCRIPTION
CLK 5
4 GND
The PLL500-17B/27B/37B are a low cost, high performance, low phase noise, and high linearity VCXO
family for the 17 to 130MHz range, providing less
than -130dBc/Hz at 10kHz offset. The very low jitter
(2.5 ps RMS period jitter) makes these chips ideal
for applications requiring voltage controlled frequency sources. The IC’s are designed to accept
fundamental resonant mode crystals.
DIE ID:PLL500-17B: C500A-0505-05P
PLL500-27B: C500A-0505-05Q
PLL500-37B: C500A-0505-05R
Y
(0,0)
X
Note: ^ Denotes internal pull up
DIE SPECIFICATIONS
FREQUENCY RANGE
PART #
MULTIPLIER
FREQUENCY
Name
Value
PLL500-17B
No PLL
17 – 36 MHz
Size
39 x 32 mil
PLL500-27B
No PLL
27 – 65 MHz
Reverse side
GND
PLL500-37B
No PLL
65 – 130 MHz
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
BLOCK DIAGRAM
XIN
XOUT
XTAL
OSC
VARICAP
CLK
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 1
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PIN AND PAD DESCRIPTION
Name
Pin#
XIN
Die Pad Position
Type
Description
X (m)
Y (m)
1
94.183
768.599
I
Crystal input pin.
OE
2
94.157
605.029
I
Output Enable input pin. Disables the output when pulled
to “0”. Internal pull-up enables output by default if pin is
not connected.
VCON
3
94.183
331.756
I
Frequency control voltage input pin.
GND
4
94.193
140.379
P
Ground pin.
CLK
5
715.472
203.866
O
Clock output pin.
VDD
6
715.307
455.726
P
VDD power supply pin.
DRIVSEL
7
715.472
626.716
I
Output drive select pin. High drive if set to ‘0’. Standard
drive if set to ‘1’. Internal pull-up.
XOUT
8
476.906
888.881
I
Crystal output pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
SYMBOL
MIN.
V DD
MAX.
UNITS
4.6
V
Input Voltage, DC
VI
-0.5
V DD +0.5
V
Output Voltage, DC
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
C
Ambient Operating Temperature*
TA
-40
85
C
Junction Temperature
TJ
125
C
Lead Temperature (soldering, 10s)
260
C
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 2
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
2. AC Electrical Specifications
PARAMETERS
SYMBOL
Input Crystal Frequency
Output Clock Rise/Fall Time
CONDITIONS
MIN.
TYP.
PLL500-17B
17
36
PLL500-27B
27
65
PLL500-47B
65
130
T R /T F
0.8V ~ 2.0V with 10 pF load
0.8
T R /T F
0.3V ~ 3.0V with 15 pF load
2.5
Output Clock Duty Cycle
MAX.
Measured @ 1.4V (3.3V)
45
50
MHz
ns
55
50
Short Circuit Current
UNITS
%
mA
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
SYMBOL
T VCXOSTB
CONDITIONS
MIN.
From power valid
VCXO Tuning Range
XTAL C 0 /C 1 < 250
0V  VCON  3.3V
CLK output pullability
VCON=1.65V, 1.65V
UNITS
10
ms
ppm
150
ppm
100
Pull range linearity
PWSRR
Frequency change with
VDD varied +/- 10%
VCON pin input impedance
VCON modulation BW
MAX.
300
VCXO Tuning Characteristic
Power Supply Rejection
TYP.
-1
2000
0V < VCON < 3.3V, -3dB
-17B
-27B
-37B
18
18
25
ppm/V
5
%
+1
ppm
k
kHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 3
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
4. Jitter and Phase Noise Specifications
PARAMETERS
CONDITIONS
RMS Period Jitter
(1 sigma – 10,000 samples)
With capacitive decoupling
between VDD and GND.
MIN
TYP
MAX
UNITS
2.5
ps
PLL500-17B
Phase Noise relative to carrier at 27MHz
@100Hz offset
-100
dBc/Hz
Phase Noise relative to carrier at 27MHz
@1kHz offset
-125
dBc/Hz
Phase Noise relative to carrier at 27MHz
@10kHz offset
-142
dBc/Hz
Phase Noise relative to carrier at 27MHz
@100kHz offset, and 1MHz
-150
dBc/Hz
PLL500-27B
Phase
Phase
Phase
Phase
Noise
Noise
Noise
Noise
relative
relative
relative
relative
to
to
to
to
carrier
carrier
carrier
carrier
at
at
at
at
61.44MHz
61.44MHz
61.44MHz
61.44MHz
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset, and 1MHz
-100
-125
-142
-150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
relative
relative
relative
relative
relative
to
to
to
to
to
carrier
carrier
carrier
carrier
carrier
at
at
at
at
at
77.76MHz
77.76MHz
77.76MHz
77.76MHz
77.76MHz
@100Hz offset
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
-100
-125
-142
-150
-152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL500-37B
Phase
Phase
Phase
Phase
Phase
Noise
Noise
Noise
Noise
Noise
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 4
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
5. DC Specifications
PARAMETERS
Supply Current,
Dynamic, with
Loaded Outputs
Allowable output load
capacitance
SYMBOL
I DD
CL
(Output)
CONDITIONS
TYP.
MAX.
27MHz, 15pF output load, 3.3V
3.7
5
35MHz, 15pF output load, 3.3V
4.2
6
78MHz, 15pF output load, 3.3V
7.2
9
27MHz, 15pF output load, 2.5V
2.4
3.5
35MHz, 15pF output load, 2.5V
2.8
4
78MHz, 15pF output load, 2.5V
5.2
7
pF
PLL500-27B
20
pF
PLL500-37B Std drive <100MHz
15
pF
PLL500-37B High drive
10
pF
3.63
V
Output High Voltage
V OH
I OH = -8mA, 3.3V Supplies
Output Low Voltage
V OL
I OL = 8mA, 3.3V Supplies
2.25
I OH = -4mA, 3.3V Supplies
2.4
V
0.4
V DD – 0.4
8
9.5
High drive, 3.3V
24
27
mA
50
VCON
0
V
V
Standard drive, 3.3V
Short Circuit Current
VCXO Control Voltage
mA
30
V DD
Output drive current
UNITS
PLL500-17B
Operating Voltage
Output High Voltage
at CMOS level
MIN.
mA
V DD
V
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 5
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
6. Crystal Specifications
PARAMETERS
SYMBOL
Crystal Loading Rating (VCON = 1.65V, PLL500-17B)
Crystal Loading Rating (VCON = 1.65V, PLL500-27B)
Crystal Loading Rating (VCON = 1.65V, PLL500-37B)
Crystal Loading Rating (VCON = 1.25V, PLL500-17B)
Crystal Loading Rating (VCON = 1.25V, PLL500-27B)
MIN.
TYP.
MAX.
UNITS
7.8
C L (xtal)
(see note
below)
Crystal Loading Rating (VCON = 1.25V, PLL500-37B)
6.3
5.1
pF
8.9
7.2
5.7
Maximum Sustainable Drive Level
200
Operating Drive Level
W
W
50
Max C0 for PLL500-17B
5
Max C0 for PLL500-27B
3.5
Max C0 for PLL500-37B
2.5
C0/C1
250
-
30
Ω
ESR
RS
pF
Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above.
If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
Note that the Cload values above are for the IC only, and do not include PCB parasitics. Crystal specifications for Cload include PCB parasitics.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 6
Low Power CMOS Output VCXO Family (17MHz to 130MHz)
PACKAGE INFORMATION
SOP 8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
C
e
L
b
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
R=Tape & Reel
Blank=Normal Package
L=GREEN Package
D=Die
S=SOP-8L
Order Number
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Marking
Package Option
PLL500-X7BDC
No marking on die
Die (Waffle Pack)
PLL500-X7BSC
P500-X7B
8-Pin SOP (Tube)
PLL500-X7BSC-R
P500-X7B
8-Pin SOP (Tape and Reel)
PLL500-X7BSCL
P500-X7B
8-Pin SOP (Tube), GREEN
PLL500-X7BSCL-R
P500-X7B
8-Pin SOP (Tape and Reel) , GREEN
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 10/30/07 Page 7