NEC UPD30181AF1-131-GA3

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30181A, 30181AY
TM
VR4181A
64-/32-BIT MICROPROCESSOR
DESCRIPTION
The µPD30181A and 30181AY (VR4181A), which are high-performance 64-/32-bit microprocessors employing the
TM
TM
RISC (reduced instruction set computer) architecture developed by MIPS , are products in the VR Series of
microprocessors manufactured by NEC.
The VR4181A includes as its CPU the VR4120™ core, an ultra-low-power-consumption core featuring cache
memory, a high-speed product-sum operation unit, and a memory management unit. Other on-chip components
include an LCD controller, CompactFlash controller, USB host/function controller, DMA controller, SDRAM controller,
2
2
PWM controller, AC97/I S audio interface, full-duplex asynchronous serial interface, IrDA interface, I C serial
interface, keyboard interface, touch panel interface, real-time clock, A/D converter, D/A converter, and other
controllers and interfaces required for battery-driven mobile information devices, fixed compact information devices,
car navigation systems, and compact embedded devices.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
• VR4181A Hardware User’s Manual (U16049E)
TM
• VR4100 Series Architecture User’s Manual (U15509E)
FEATURES
{ VR4120 core (64-bit RISC core) on chip as CPU
{ Pipeline clock: 131 MHz
{ Conforms to MIPS III (except for FPU, LL and SC
instructions) and MIPS16 instruction sets
{ Supports MACC and DMACC high-speed product-sum
operation instructions
{ On-chip cache memory
Capacity includes 8 KB instruction cache and 8 KB
data cache
{ Employs a writeback cache
{ Physical addresses: 32 bits
Virtual addresses: 40 bits
{ On-chip 32 double-entry TLB
{ Effective power management using four modes:
Fullspeed, Standby, Suspend, and Hibernate
{ Employs a high-performance internal system bus (Tbus)
{ DRAM controller supporting 64 Mb, 128 Mb, and 256
Mb SDRAMs
{ External system bus interface supporting ROM, page
ROM, flash memory, SRAM, ISA devices, IDE (ATA)
devices, and SyncFlash™ memory
{ UMA type LCD controller (supports STN and TFT
panels)
{ ExCA register-compatible CompactFlash interface (2
slots)
{ USB host controller (Rev1.1, OHCI Rev1.0)
controller
{ USB function (Rev1.1) controller
2
{ AC97 and I S audio interfaces (1 channel each)
{ Clocked serial interface (1 channel)
{ NS16550-compatible serial interface (3 channels)
{ IrDA (SIR) interface (1 channel)
2
{ I C bus interfaces (2 channels, µPD30181AY only)
{ PWM controller (3 channels)
{ DMA controller supporting chain mode (4 channels)
{ Keyboard scan interface (supports 8 × 12 key matrix)
{ X-Y coordinate auto scan touch panel interface
{ On-chip A/D converter and D/A converter
{ On-chip watchdog timer unit
{ RTC unit (total of 3 timer and counter channels)
{ On-chip PLL and clock generators
{ Power supplies: 2.5 V for core, 3.3 V for I/O block
{ Package: 240-pin plastic FBGA
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U16277EJ1V0DS00 (1st edition)
Date Published October 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
©
2002
1997
µPD30181A, 30181AY
APPLICATIONS
{ Car navigation systems
{ Digital consumer devices (digital information home equipment)
{ Battery-driven mobile information devices
{ Controllers for embedded devices
ORDERING INFORMATION
Part Number
µPD30181AF1-131-GA3
µPD30181AF1-131-GA3-A
I C Bus
Internal Maximum
Interface
Operating Frequency
None
131 MHz
240-pin plastic FBGA (16 × 16)
None
131 MHz
240-pin plastic FBGA (16 × 16)
On chip
131 MHz
240-pin plastic FBGA (16 × 16)
On chip
131 MHz
240-pin plastic FBGA (16 × 16)
Note
µPD30181AYF1-131-GA3
µPD30181AYF1-131-GA3-A
Note
2
Package
Note
Lead-free product
PIN CONFIGURATION
• 240-pin plastic FBGA (16 × 16)
Bottom view
Top view
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V U T R P N M L K J H G F E D C B A
A B C D E F G H J K L M N P R T U V
Index mark
2
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(1/3)
No.
Power
Supply
A1
3.3 V
A2
3.3 V
A3
A4
Name
No.
Power
Supply
Name
D6
C5
3.3 V
D26
D5
C6
3.3 V
D24
3.3 V
D3
C7
3.3 V
D23
3.3 V
D1
C8
3.3 V
D22
A5
3.3 V
D8
C9
3.3 V
D20
A6
3.3 V
D10
C10
3.3 V
D18
A7
3.3 V
D12
C11
3.3 V
UHDP
A8
3.3 V
D14
C12
3.3 V
UOC
A9
3.3 V
D16
C13
3.3 V
NMI#
A10
3.3 V
D17
C14
3.3 V
DQM2/LBE2#
A11
3.3 V
UDP
C15
3.3 V
PCS0#
A12
3.3 V
CLK48
C16
3.3 V
SYSEN#
A13
3.3 V
SDCS2#
C17
3.3 V
IORDY
A14
3.3 V
SDCS3#
C18
3.3 V
UBE#
A15
3.3 V
MEMWR#
D1
3.3 V
CAS#
A16
3.3 V
PCS4#
D2
3.3 V
RAS#
A17
3.3 V
PCS1#
D3
3.3 V
D29
A18
3.3 V
IORD#
D4
2.5 V
VDD2
B1
3.3 V
D7
D5
3.3 V
D25
B2
3.3 V
DQM1/LBE1#
D6
2.5 V
GND2
B3
3.3 V
D4
D7
2.5 V
VDD2
B4
3.3 V
D2
D8
3.3 V
D21
B5
3.3 V
D0
D9
3.3 V
D19
B6
3.3 V
D9
D10
3.3 V
GNDU
B7
3.3 V
D11
D11
3.3 V
VDDU
B8
3.3 V
D13
D12
3.3 V
GND3
B9
3.3 V
D15
D13
3.3 V
VDD3
B10
3.3 V
UDN
D14
2.5 V
GND2
B11
3.3 V
UHDN
D15
3.3 V
MEMRD#
B12
3.3 V
UPON
D16
3.3 V
PWM1/KSCAN6/GPIO9
B13
3.3 V
DQM3/LBE3#
D17
3.3 V
IOCS16#
B14
3.3 V
PCS3#
D18
3.3 V
PWM0/KSCAN7/GPIO8
B15
3.3 V
ROMCS#
E1
3.3 V
SDCLK
B16
3.3 V
PCS2#
E2
3.3 V
SDCS1#
B17
3.3 V
SYSDIR
E3
3.3 V
D30
B18
3.3 V
IOWR#
E4
3.3 V
VDD3
C1
3.3 V
DQM0/LBE0#
E8
3.3 V
VDD3
C2
3.3 V
WE#
E9
3.3 V
GND3
C3
3.3 V
D28
E10
2.5 V
GND2
C4
3.3 V
D27
E11
2.5 V
VDD2
Remark # indicates active low.
Data Sheet U16277EJ1V0DS
3
µPD30181A, 30181AY
(2/3)
No.
Power
Supply
Name
No.
Power
Supply
E15
3.3 V
VDD3
K2
3.3 V
A12
E16
3.3 V
KPORT0/GPIO4
K3
3.3 V
A19/GPIO58
E17
3.3 V
PWM2/KSCAN5/GPIO10
K4
3.3 V
A20/GPIO59
E18
3.3 V
KPORT1/GPIO5
K5
3.3 V
VDD3
F1
3.3 V
SDCS0#
K14
3.3 V
VDD3
F2
3.3 V
CKE0
K15
3.3 V
SO/KSCAN9/GPIO21
F3
3.3 V
D31
K16
3.3 V
SCK/KSCAN11/GPIO23
F4
3.3 V
GND3
K17
3.3 V
FRM/KSCAN8/GPIO20
F15
2.5 V
GNDP
K18
3.3 V
CF1_VCCEN#/KSCAN4/GPIO37
F16
3.3 V
CF1_DIR/KPORT4/GPIO39
L1
3.3 V
A11
F17
3.3 V
KPORT2/GPIO6
L2
3.3 V
A9
F18
3.3 V
CLKX1
L3
3.3 V
A17/GPIO56
G1
3.3 V
A13
L4
3.3 V
A18/GPIO57
G2
3.3 V
A14
L5
2.5 V
VDD2
G3
3.3 V
TC0#/GPIO52
L14
2.5 V
GND2
G4
3.3 V
TC1#/GPIO53
L15
3.3 V
JTMS
G15
2.5 V
VDDP
L16
3.3 V
JTDO
G16
3.3 V
KPORT3/GPIO7
L17
3.3 V
SI/KSCAN10/GPIO22
G17
3.3 V
CF1_EN#/KPORT5/GPIO38
L18
3.3 V
JTCK
G18
3.3 V
CLKX2
M1
3.3 V
A8
H1
3.3 V
SA10
M2
3.3 V
A7
H2
3.3 V
A0
M3
3.3 V
A15/GPIO54
H3
3.3 V
A23/RP#
M4
3.3 V
A16/GPIO55
H4
3.3 V
A24/CKE1
M15
3.3 V
JTRST#
H5
2.5 V
GND2
M16
3.3 V
CF0_IOIS16#/GPIO34
H14
3.3 V
VDDO
M17
3.3 V
JTDI/RMODE#
H15
3.3 V
GNDO
M18
3.3 V
BKTGIO#
H16
3.3 V
KSCAN0/GPIO0
N1
3.3 V
A6
H17
3.3 V
KSCAN3/GPIO3
N2
3.3 V
A5
H18
3.3 V
RTCX2
N3
3.3 V
A10
J1
3.3 V
A1
N4
2.5 V
GND2
J2
3.3 V
A2
N15
2.5 V
VDD2
J3
3.3 V
A21/GPIO60
N16
3.3 V
CF0_CD2#/GPIO36
J4
3.3 V
A22/GPIO61
N17
3.3 V
CF0_CD1#/GPIO35
J5
3.3 V
GND3
N18
3.3 V
CF_WAIT#/GPIO33
J14
2.5 V
VDD2
P1
3.3 V
A4
J15
3.3 V
GND3
P2
3.3 V
DAK1#
J16
3.3 V
KSCAN1/GPIO1
P3
3.3 V
DRQ1#
J17
3.3 V
KSCAN2/GPIO2
P4
3.3 V
GNDAD
J18
3.3 V
RTCX1
P8
2.5 V
VDD2
K1
3.3 V
A3
P9
2.5 V
GND2
Remark # indicates active low.
4
Name
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(3/3)
No.
Power
Supply
P10
2.5 V
P11
3.3 V
P15
Name
No.
Power
Supply
Name
GND2
T16
3.3 V
FPD2
GND3
T17
3.3 V
I.C. (GND3)Note 2
3.3 V
CF0_CE2#/GPIO32
T18
3.3 V
CF0_EN#/GPIO26
P16
3.3 V
CF0_DIR/GPIO27
U1
3.3 V
MPOWER
P17
3.3 V
CF0_READY/GPIO29
U2
3.3 V
AIN0
P18
3.3 V
CF0_CE1#/GPIO31
U3
3.3 V
TPX0
R1
3.3 V
DRQ0#
U4
3.3 V
TPY0
R2
3.3 V
POWER
U5
3.3 V
TxD0/CLKSEL2Note 1
R3
3.3 V
RSTSW#
U6
3.3 V
RTS0#/GPIO19/CLKSEL1Note 1
R4
3.3 V
GNDTP
U7
3.3 V
RxD2/IRDIN
R5
3.3 V
VDDTP
U8
3.3 V
CTS2#/BITCLK/SCLK
R6
3.3 V
VDDAD
U9
3.3 V
I.C. (GND3)Note 2
R7
3.3 V
VDD3
U10
3.3 V
SCL0/KPORT7/GPIO12
R8
3.3 V
GND3
U11
3.3 V
VSYNC/FLM/BMODE1Note 1
R9
3.3 V
DCD2#/SDATAIN/SDI
U12
3.3 V
FPD15/CF1_READY/GPIO51
R10
3.3 V
SDA0/KPORT6/GPIO11
U13
3.3 V
FPD12/CF1_CE1#/GPIO48
R11
3.3 V
VPBIAS/GPO63
U14
3.3 V
FPD10/CF1_CD1#/GPIO46
R12
3.3 V
VPLCD/GPO62
U15
3.3 V
FPD6/GPIO42
R13
3.3 V
VDD3
U16
3.3 V
FPD4/GPIO40
R14
2.5 V
VDD2
U17
3.3 V
CF1_RESET/DBUS32Note 1
R15
3.3 V
GND3
U18
3.3 V
CF0_VCCEN#/GPIO24
R16
3.3 V
CF_REG#/GPIO25
V1
3.3 V
TPY1
R17
3.3 V
CF0_RESET/GPIO28
V2
3.3 V
AIN1
R18
3.3 V
CF0_STSCHG#/GPIO30
V3
3.3 V
AIN3
T1
3.3 V
RTCRST#
V4
3.3 V
AOUT
T2
3.3 V
POWERON
V5
3.3 V
RxD0
T3
3.3 V
DAK0#
V6
3.3 V
CTS0#/GPIO18
T4
3.3 V
TPX1
V7
3.3 V
DTR0#/RTS1#/GPIO17/CLKSEL0Note 1
T5
3.3 V
AIN2
V8
3.3 V
TxD2/IRDOUT/MIPS16ENNote 1
T6
3.3 V
DCD0#/GPIO16
V9
3.3 V
DSR2#/SRESET#
T7
3.3 V
DSR0#/CTS1#/GPIO15
V10
3.3 V
RxD1/SCL1/GPIO14
T8
3.3 V
RTS2#/SYNC/WS/DIVMODE1Note 1
V11
3.3 V
DCLK/SHCLK
Note 1
T9
3.3 V
DTR2#/SDATAOUT/SDO/DIVMODE0
V12
3.3 V
HSYNC/LOCLK/NWIREENNote 1
T10
3.3 V
TxD1/SDA1/GPIO13
V13
3.3 V
FPD11/CF1_CD2#/GPIO47
T11
3.3 V
ENAB/M/BMODE0Note 1
V14
3.3 V
FPD9/GPIO45
T12
3.3 V
FPD14/CF1_STSCHG#/GPIO50
V15
3.3 V
FPD7/GPIO43
T13
3.3 V
FPD13/CF1_CE2#/GPIO49
V16
3.3 V
FPD5/GPIO41
T14
3.3 V
FPD8/GPIO44
V17
3.3 V
FPD3
T15
3.3V
FPD0
V18
3.3 V
FPD1
Notes 1. These pins are used for mode settings. A mode setting is made according to the status of these pins
at the rising edge of the RTCRST# signal. Use pull-up/pull-down resistors to set the pin statuses.
2. Be sure to connect these pins to GND3.
Remark # indicates active low.
Data Sheet U16277EJ1V0DS
5
µPD30181A, 30181AY
PIN INDENTIFICATION (1/2)
A(24:0):
Address bus
DRQ(1:0)#:
AIN(3:0):
Analog data Input
DSR0#, DSR2#: 16550 data set ready
AOUT:
Analog data output
DTR0#, DTR2#: 16550 data terminal ready
BITCLK:
AC97 bit clock
ENAB:
TFT display enable
BKTGIO#:
N-wire break trigger I/O
FLM:
STN first line clock
BMODE(1:0):
Boot mode
FPD(15:0):
LCD display data
CAS#:
SDRAM column address strobe
FRM:
CSI frame input
CF_REG#:
CompactFlash register memory access
GND2:
Internal ground
CF_WAIT#:
CompactFlash wait input
GND3:
I/O ground
CF0_CD(2:1)#:
CompactFlash card detect
GNDAD:
A/D and D/A converter ground
CF0_CE(2:1)#:
CompactFlash card enable
GNDO:
Oscillator ground
CF0_DIR:
CompactFlash data direction
GNDP:
PLL ground
CF0_EN#:
CompactFlash buffer enable
GNDTP:
Touch panel ground
CF0_IOIS16#:
CompactFlash I/O is 16 bits
GNDU:
USB transceiver ground
CF0_READY:
CompactFlash ready
GPIO(61:0):
General-purpose I/O
CF0_RESET:
CompactFlash reset
GPO(63:62):
General-purpose output
CF0_STSCHG#:
CompactFlash status change
HSYNC:
TFT horizontal sync
CF0_VCCEN#:
CompactFlash VCC enable
I.C.:
Internally connected
CF1_CD(2:1)#:
CompactFlash card detect
IOCS16#:
I/O 16-bit bus sizing
CF1_CE(2:1)#:
CompactFlash card enable
IORD#:
I/O read
CF1_DIR:
CompactFlash data direction
IORDY:
I/O ready
CF1_EN#:
CompactFlash buffer enable
IOWR#:
I/O write
CF1_READY:
CompactFlash ready
IRDIN:
IrDA data input
CF1_RESET:
CompactFlash reset
IRDOUT:
IrDA data output
CF1_STSCHG#:
CompactFlash status change
JTCK:
N-wire clock
CF1_VCCEN#:
CompactFlash VCC enable
JTDI:
N-wire data input
CKE0:
SDRAM Clock enable
JTDO:
N-wire data output
CKE1:
SyncFlash memory clock enable
JTMS:
N-wire mode select
CLK48:
USB clock input
JTRST#:
N-wire reset
CLKSEL(2:0):
Pipeline clock select
KPORT(7:0):
Key Scan input
CLKX(2:1):
Clock input
KSCAN(11:0):
Key Scan output
CTS0#, CTS1#, CTS2#: 16550 clear to send
LOCLK:
STN load clock
D(31:0):
Data bus
LBE(3:0)#:
System bus byte enable
DAK(1:0)#:
DMA acknowledge
M:
STN modulation clock
DBUS32:
ROM data bus mode
MEMRD#:
Memory read
DCD0#, DCD2#:
16550 data carrier detect
MEMWR#:
Memory write
DCLK:
TFT dot clock
MIPS16EN:
MIPS16 enable
DIVMODE(1:0):
Divide-by mode
MPOWER:
Main power control
DQM(3:0):
SDRAM byte enable
NMI#:
Non maskable interrupt
Remark # indicates active low.
6
Data Sheet U16277EJ1V0DS
DMA request
µPD30181A, 30181AY
PIN INDENTIFICATION (2/2)
NWIREEN:
N-Wire enable
SO:
CSI data output
PCS(4:0)#:
Programmable chip select
SRESET#:
AC97 reset
POWER:
Power switch
SYNC:
AC97 synchronous clock
POWERON:
Power on state
SYSDIR:
System data direction
PWM(2:0):
Pulse width modulation
SYSEN#:
System data enable
RAS#:
SDRAM row address strobe
TC(1:0)#:
Terminal counter
RMODE#:
N-wire reset mode select
TPX(1:0):
Touch panel X coordinate data
ROMCS#:
Chip select for ROM
TPY(1:0):
Touch panel Y coordinate data
RP#:
SyncFlash memory
TxD0, TxD1, TxD2: 16550 transmit data
reset/power-down
UBE#:
RSTSW#:
Reset switch
UDN:
USB function negative data
RTCRST#:
Real-time clock reset
UDP:
USB function positive data
RTCX(2:1):
Real-time clock input
Upper byte enable for system bus
UHDN:
USB host negative data
RTS0#, RTS1#, RTS2#: 16550 data request to send
UHDP:
USB host positive data
RxD0, RxD1, RxD2:
16550 receive data
UOC:
USB host root hub port over current
SA10:
SDRAM address 10-bit
UPON:
USB host root hub port power control
2
2
SCLK:
I S continuous clock
VDD2:
Internal power supply
SCL1, SCL0:
I C clock
VDD3:
I/O power supply
SCK:
CSI serial clock
VDDAD:
A/D and D/A converter power supply
SDA1, SDA0:
I C data
VDDO:
Oscillator power supply
SDATAIN:
AC97 serial codec data input
VDDP:
PLL power supply
SDATAOUT:
AC97 serial codec data output
VDDTP:
Touch panel power supply
SDCLK:
SDRAM clock
VDDU:
USB transceiver power supply
SDCS(3:2)#:
SyncFlash memory chip select
VPBIAS:
Bias power control
SDCS(1:0)#:
SDRAM chip select
SDI:
I S serial codec data input
2
VPLCD:
Logic power control
2
VSYNC:
TFT vertical sync
2
SDO:
I S serial codec data output
WE#:
SDRAM write enable
SHCLK:
STN shift clock
WS:
I S word select
SI:
CSI data input
2
Remark # indicates active low.
Data Sheet U16277EJ1V0DS
7
µPD30181A, 30181AY
INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS
PC
CompactFlash/ Communication
PC Card
STN/TFT LCD Panel
Color/Monochrome
SDRAM/
SyncFlash
ROM/Flash
memory
HDD, CD-ROM
ISA I/O
Devices
32/16-bit
Bus Buf
SDRAM
Control
Buf
Bus
Control
Card/IDE
Control
2 slots
DMA
In-circuit
emulator
Debug
I/F
VR4120
CPU Core
CPU I/F
Bridge
Printer
BluetoothTM
Baseband
USB
Host
Control
USB
Func.
Control
AC97
Control
Interrupt Watchdog
Control
Timer
PCM Sound
Stereo
CODEC
Bridge
LCD
Control
Mouse
RTC/
Timer
Power
Management
I2S
Control
Audio Input
N-Wire
32.768 kHz
18.432 MHz
Clock
Generator
Key
Scan
I/F
PWM
Control
3ch
GPIO
64 MAX.
Serial
(UART)
3ch
Serial
(I2C)
2ch
Serial
(CSI)
Port
Control
IrDA/
RS-232-C
Driver,
Bluetooth
Baseband,
etc.
CCD Module,
Serial
EEPROMTM
etc.
MCU,
CODEC
Control,
etc.
Touch
Panel
Control
D/A
Analog
Control
Touch
Panel
A/D
VR4181A
LED
LCD Backlight
Contrast
Battery Monitor
CPU CORE INTERNAL BLOCK DIAGRAM
Virtual address bus
Internal data
bus
Control (o)
Control (i)
Bus
interface
Data
cache
(8 KB)
Instruction
cache
(8 KB)
Address/Data (o)
TLB
Address/Data (i)
Clock
generator
Internal clock
8
CP0
Data Sheet U16277EJ1V0DS
CPU
µPD30181A, 30181AY
CONTENTS
1. PIN FUNCTIONS .................................................................................................................................. 10
1.1
Pin Functions ......................................................................................................................................... 10
1.2
Pin Status in Specific Status ................................................................................................................ 26
1.3
Pin I/O Circuit Types and Recommended Connection of Unused Pins............................................ 33
1.4
Pin I/O Circuits ....................................................................................................................................... 36
2. ELECTRICAL SPECIFICATIONS ........................................................................................................ 37
3. PACKAGE DRAWING .......................................................................................................................... 68
4. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 69
Data Sheet U16277EJ1V0DS
9
µPD30181A, 30181AY
1. PIN FUNCTIONS
Remark # indicates active low.
1.1 Pin Functions
(1) System bus interface signals
(1/3)
Signal Name
I/O
Function
Address bus
These pins are used to specify system bus addresses.
They are used to access ROM, flash memory, SRAM, ISA devices, PC
Cards, IDE (ATA) devices, and general-purpose devices.
Alternate Function
A24
O
A23
O
A(22:15)
O
SA10
O
Address bit 10 for SDRAM or SyncFlash memory
Instead of connecting to A10, connect this pin (SA10) to address bit 10 in
SDRAM or SyncFlash memory.
–
A(14:0)
O
Address bus
These pins are used to specify system bus addresses.
They are used to access SDRAM, SyncFlash memory, ROM, flash
memory, SRAM, ISA devices, CompactFlash/PC Cards, IDE (ATA)
devices, and general-purpose devices.
–
D(31:0)
I/O
Data bus
These pins are used to transfer data to the VR4181A and SDRAM,
SyncFlash memory, ROM, flash memory, SRAM, ISA devices,
CompactFlash/PC Cards, IDE (ATA) devices, and general-purpose
devices.
–
PCS(4:0)#
O
Programmable chip select
These pins can be set as active when the VR4181A accesses ROM, flash
memory, SRAM, and general-purpose devices. They can be connected
only to devices that are not subject to bus sizing via the IOCS16# pin.
–
ROMCS#
O
Boot ROM chip select
This pin can be set as active when the VR4181A accesses boot ROM or
flash memory. When the BMODE(1:0) pin status is 01 and the RTCRST#
signal has been cleared, the VR4181A fetches the boot code from a
device connected to the ROMCS# pin to activate this pin.
–
MEMRD#
O
System bus memory read
This pin becomes active when the VR4181A reads data from any of the
following devices.
• ROM, flash memory, SRAM, or general-purpose devices controlled by
the ROMCS# pin or PCS# pin
• External ISA bus memory space devices and CompactFlash/PC Card
memory space devices
–
10
Data Sheet U16277EJ1V0DS
CKE1
RP#
GPIO(61:54)
µPD30181A, 30181AY
(2/3)
Signal Name
I/O
Function
Alternate Function
MEMWR#
O
System bus memory write
This pin becomes active when the VR4181A writes to any of the following
devices.
• ROM, flash memory, SRAM, or general-purpose devices controlled by
the ROMCS# pin or PCS# pin
• External ISA bus memory space devices and CompactFlash/PC Card
memory space devices
–
IORD#
O
System bus I/O read
This pin becomes active when the VR4181A reads data from the external
ISA bus I/O space devices or CompactFlash/PC Card I/O ports. It is
valid only when accessing the external ISA bus I/O space.
–
IOWR#
O
System bus I/O write
This pin becomes active when the VR4181A writes data to external ISA
bus I/O space devices or CompactFlash/PC Card I/O ports. It is valid
only when accessing the external ISA bus I/O space.
–
IORDY
I
System bus I/O channel ready
This pin (IORDY) is set as inactive in relation to read/write strobes from
the VR4181A in order to extend the access time for a device connected to
the system bus. It is set as active once the device is in a mode that
supports access from the VR4181A. It can be used to access a device
connected to the ROMCS# pin or PCS# pin or a device connected to the
external ISA space.
–
IOCS16#
I
System bus sizing request
Set this signal as active when an ISA device connected to the system
bus accesses data in 16-bit width. Bus sizing that uses this pin IOCS16#
is enabled only when accessing the external ISA space.
–
UBE#
O
System bus higher byte enable
This pin becomes active during system bus access if the higher bytes of
the 16-bit data bus are valid. It can be used if a device connected to the
ROMCS# or PCS# pin or a device connected to the external ISA space
uses 16-bit width.
–
LBE(3:0)#
O
System bus byte enable
The LBE(3:0)# signal pins used for 32-bit general-purpose devices are
shared as the DQM(3:0) signal pins for SDRAM and SyncFlash memory,
so the function of this pin changes based on time division. When the
VR4181A accesses a device that uses the ROMCS# pin or PCS# pin, the
LBE(3:0)# signals become valid only when the SYSEN# signal is at low
level. This signal indicates the data bus’s valid byte lane. If the device
connected to the ROMCS# pin or PCS# pin has 32-bit width, this pin can
be used. When the SYSEN# pin is at high level, this pin operates as the
DQM(3:0) pins that are referenced by SDRAM.
DQM(3:0)
Data Sheet U16277EJ1V0DS
11
µPD30181A, 30181AY
(3/3)
Signal Name
I/O
Function
Alternate Function
SYSDIRNote
O
Data bus isolation buffer direction control
This signal is valid only when accessing devices other than SDRAM or
SyncFlash memory devices. The signal is at high level during read
cycles and at low level during write cycles.
–
SYSEN#Note
O
Enables data bus isolation buffer connection
This signal is set to high level during SDRAM and SyncFlash memory
cycles and is at low level when accessing any other devices.
–
DRQ(1:0)#
I
DMA service request signal
The DRQ(1:0)# signals are sampled at the rising edge of TClock. Be
sure to hold this signal at active level until a DMA request is
acknowledged. Set this signal as inactive when not using the DRQ(1:0)#
signals.
–
DAK(1:0)#
O
Enables DMA service request
This signal goes to active level when access to the target device occurs
via DMA transfer.
–
TC(1:0)#
I/O
DMA transfer completion signal (open drain)
This signal is driven at active level when a DMA transfer is completed.
During a transfer, this signal operates as a DMA stop request input
signal.
NMI#
I
GPIO(53:52)
Non-maskable interrupt input
This is an interrupt request signal that cannot be masked in relation to the
CPU core. When the VR4181A starts normally and the MPOWER signal
is at high level, input from the NMI# pin is connected to the CPU core via
the ICU. While the MPOWER signal is at low level, input to the NMI# pin
is monitored by the PMU as a source of NMI shutdowns.
–
Note The SYSEN# and SYSDIR signals are buffer control signals used to isolate the SDRAM and SyncFlash
memory buses from other low-speed device buses. Isolating high-speed memory access paths from other
devices reduces the load on the system bus between the VR4181A and the SDRAM or SyncFlash
memory. When using the system bus isolation buffer, the correspondence between the SYSEN# and
SYSDIR signals and the data bus isolation status is as shown below.
12
SYSEN#
SYSDIR
Bus Operation
0
0
Enables connection via data bus isolation buffer
• Write cycle for ROM, flash memory, SRAM, ISA device, CompactFlash/PC
Card, or other general-purpose device
• Hibernate mode
0
1
Enables connection via data bus isolation buffer
• Read cycle for ROM, flash memory, SRAM, ISA device, CompactFlash/PC
Card, or general-purpose device
1
0
Disables connection via data bus isolation buffer
Read/write cycle for SDRAM or SyncFlash memory
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2) Memory interface signals
Signal Name
I/O
Function
Alternate Function
–
SDCLK
O
Operating clock for SDRAM and SyncFlash memory
This signal can also be set (via register settings) to stop clock output
when not accessing SDRAM or SyncFlash memory.
CKE1
O
Operating clock enable signal for SyncFlash memory
CKE0
O
Operating clock enable signal for SDRAM
–
SDCS(3:2)#
O
Chip select signal for SyncFlash memory
–
SDCS(1:0)#
O
Chip select signal for SDRAM
–
RAS#
O
Row address strobe signal for SDRAM and SyncFlash memory
–
CAS#
O
Column address strobe signal for SDRAM and SyncFlash memory
–
DQM(3:0)
O
Byte enable signal for SDRAM and SyncFlash memory
The DQM(3:0) signals for SDRAM and SyncFlash memory shares pins
with the LBE(3:0)# signals for 32-bit general-purpose devices, so the
function of these pins change based on time division. When the SYSEN#
signal is at high level, the pin operates as the DQM(3:0) signals which are
referenced by SDRAM.
WE#
O
Write enable signal for SDRAM and SyncFlash memory
RP#
O
SyncFlash memory initialization/power down signal
Data Sheet U16277EJ1V0DS
A24
LBE(3:0)#
–
A23
13
µPD30181A, 30181AY
(3) Initialization interface signals
Signal Name
I/O
Function
Alternate Function
POWER
I
VR4181A activation request (power switch) signal
When the rising edge of this signal is detected in Hibernate mode, an
activation factor occurs (the VR4181A restores to Fullspeed mode).
–
RSTSW#
I
VR4181A reset signal
This signal initializes the internal statuses of all resettable devices except
the RTC timer, PMU, GIU, and PWMU channels 0 and 1.
–
RTCRST#
I
VR4181A RTC reset signal
This signal initializes the internal statuses of all resettable devices,
including the RTC timer. When supplying power to a device for the first
time, be sure to set this signal as active for external circuits.
–
POWERON
O
VR4181A activation indication
When an activation factor has been detected, this signal becomes active
(high level) for a specified amount of time.
–
MPOWER
O
VR4181A operation in progress indication
When 2.5 V circuits are operating, this signal becomes active (high level).
In Hibernate mode, it is inactive (low level). When this signal is inactive,
the 2.5 V power supply can be stopped.
–
Remarks 1. Activation factors are used to restore from Hibernate mode to Fullspeed mode.
2. For further description of the operation of initialization interface signals, see Hardware User’s
Manual.
(4) Clock interface signals
Signal Name
I/O
Function
Alternate Function
RTCX(2:1)
–
32.768 kHz crystal resonator connection pin
–
CLKX(2:1)
–
18.432 MHz crystal resonator connection pin
–
14
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(5) LCD interface signals
Signal Name
I/O
Function
Alternate Function
DCLK/SHCLK
O
Dot clock (DCLK) for TFT/shift clock (SHCLK) for STN
–
HSYNC/LOCLK
O
Horizontal sync signal for TFT/load clock for STN
NWIREEN
VSYNC/FLM
O
Vertical sync signal for TFT/first line clock for STN
BMODE1
ENAB/M
O
Display enable signal for TFT/M clock for STN
BMODE0
FPD15
O
LCD display data
CF1_READY,
GPIO51
FPD14
O
LCD display data
CF1_STSCHG#,
GPIO50
FPD(13:12)
O
LCD display data
CF1_CE(2:1)#,
GPIO(49:48)
FPD(11:10)
O
LCD display data
CF1_CD(2:1)#,
GPIO(47:46)
FPD(9:4)
O
LCD display data
GPIO(45:40)
FPD(3:0)
O
LCD display data
VPBIAS
O
LED bias power control
This signal can be used as a general-purpose output when not using the
LCD controller.
GPO63
VPLCD
O
LCD logic power control
This signal can be used as a general-purpose output when not using the
LCD controller.
GPO62
–
Caution The connection between the FPD(15:0) of the VR4181A and LCD panel data line corresponds to
the panel data width, as shown below.
VR4181A
STN Panel Data
(4 Bits)
STN Panel Data
(8 Bits)
TFT Panel Data
(12 Bits)
TFT Panel Data
(16 Bits)
FPD0
Data line 0
Data line 0
Data line (B0)
Data line (B0)
FPD1
Data line 1
Data line 1
Data line (B1)
Data line (B1)
FPD2
Data line 2
Data line 2
Data line (B2)
Data line (B2)
FPD3
Data line 3
Data line 3
Data line (B3)
Data line (B3)
FPD4
–
Data line 4
Data line (G0)
Data line (B4)
FPD5
–
Data line 5
Data line (G1)
Data line (G0)
FPD6
–
Data line 6
Data line (G2)
Data line (G1)
FPD7
–
Data line 7
Data line (G3)
Data line (G2)
FPD8
–
–
Data line (R0)
Data line (G3)
FPD9
–
–
Data line (R1)
Data line (G4)
FPD10
–
–
Data line (R2)
Data line (G5)
FPD11
–
–
Data line (R3)
Data line (R0)
FPD12
–
–
–
Data line (R1)
FPD13
–
–
–
Data line (R2)
FPD14
–
–
–
Data line (R3)
FPD15
–
–
–
Data line (R4)
Data Sheet U16277EJ1V0DS
15
µPD30181A, 30181AY
(6) CompactFlash/PC Card/IDE (ATA) interface signal
Signal Name
I/O
Function
Alternate Function
CF1_CD(2:1)#
I
CompactFlash/PC Card (slot 1) detection signal
FPD(11:10),
GPIO(47:46)
CF1_CE(2:1)#
O
CompactFlash/PC Card (slot 1) enable signal
FPD(13:12),
GPIO(49:48)
CF1_STSCHG#
I
CompactFlash/PC Card (slot 1) status change signal
FPD14, GPIO50
CF1_READY
I
CompactFlash/PC Card (slot 1) ready signal
FPD15, GPIO51
CF1_RESET
O
CompactFlash/PC Card (slot 1) reset signal
DBUS32
CF1_DIR
O
CompactFlash/PC Card (slot 1) data bus direction control signal
KPORT4,
GPIO39
CF1_EN#
O
CompactFlash/PC Card (slot 1) buffer enable signal
KPORT5,
GPIO38
CF1_VCCEN#
O
CompactFlash/PC Card (slot 1) VCC enable signal
KSCAN4,
GPIO37
CF0_CD(2:1)#
I
CompactFlash/PC Card (slot 0) detection signal
GPIO(36:35)
CF0_IOIS16#
I
CompactFlash/PC Card (slot 0) I/O 16-bit bus signal
GPIO34
CF_WAIT#
I
CompactFlash/PC Card (slots 0, 1) wait signal
GPIO33
CF0_CE(2:1)#
O
CompactFlash/PC Card (slot 0) enable signal
GPIO(32:31)
CF0_STSCHG#
I
CompactFlash/PC Card (slot 0) status change signal
GPIO30
CF0_READY
I
CompactFlash/PC Card (slot 0) ready signal
GPIO29
CF0_RESET
O
CompactFlash/PC Card (slot 0) reset signal
GPIO28
CF0_DIR
O
CompactFlash/PC Card (slot 0) data bus direction control signal
GPIO27
CF0_EN#
O
CompactFlash/PC Card (slot 0) buffer enable signal
GPIO26
CF_REG#
O
CompactFlash/PC Card (slots 0, 1) register select signal
GPIO25
CF0_VCCEN#
O
CompactFlash/PC Card (slot 0) VCC enable signal
GPIO24
Cautions 1. Be sure to use MEMRD#, MEMWR#, IORD#, and IOWR# respectively as CompactFlash/PC
Card access strobe signals OE#, WE#, IORD#, and IOWR#.
2. The CF0_EN#, CF1_EN#, CF0_DIR, and CF1_DIR signals are used to control the buffer that
isolates the CompactFlash/PC Card’s bus from other device’s buses. This isolation of the
CompactFlash/PC Card’s bus enables hot plug-in support. The following table lists the
correspondence between the CF0_EN#, CF1_EN#, CF0_DIR, and CF1_DIR signals and data
bus isolation statuses when using the data bus isolation buffer.
16
CF0_EN#,
CF1_EN#
CF0_DIR,
CF1_DIR
Operation of Bus
0
0
Enable connection via data bus isolation buffer
• Write cycle to CompactFlash/PC Card
0
1
Enable connection via data bus isolation buffer
• Read cycle to CompactFlash/PC Card
1
– (Undefined)
Disable connection via data bus isolation buffer
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(7) USB (host/function) interface signals
Signal Name
I/O
CLK48
I
UHDP
Function
Alternate Function
USB clock (48 MHz)
–
I/O
USB host serial data (+) signal
Be sure to connect a 22 Ω resistor in series for impedance matching.
–
UHDN
I/O
USB host serial data (–) signal
Be sure to connect a 22 Ω resistor in series for impedance matching.
–
UPON
O
USB host route hub power control signal
–
UOC
I
USB host route hub overcurrent input signal
–
UDP
I/O
USB function serial data (+) signal
Be sure to connect a 22 Ω resistor in series for impedance matching.
–
UDN
I/O
USB function serial data (–) signal
Be sure to connect a 22 Ω resistor in series for impedance matching.
–
2
(8) AC97/I S stereo audio interface signals
Signal Name
I/O
Function
Alternate Function
2
BITCLK/SCLK
I/O
Bit clock input (12.288 MHz) for AC97/input or output of I S clock
(maximum frequency during input: 6.144 MHz).
When used as the SCLK signal, this signal is output by the VR4181A
when the I2SU is in master mode and is input from an external source in
slave mode.
CTS2#
SYNC/WS
I/O
Synchronous clock output for AC97/input or output of I2S word select
signal
When used as the WS signal, this signal is output by the VR4181A when
the I2SU is in master mode and is input from an external source in slave
mode.
RTS2#,
DIVMODE1
SDATAOUT/SDO
O
Serial data output signal for AC97/serial data output signal for I2S
DTR2#,
DIVMODE0
SDATAIN/SDI
I
Serial data input signal for AC97/serial data input signal for I2S
DCD2#
SRESET#
O
Reset signal for AC97
DSR2#
Data Sheet U16277EJ1V0DS
17
µPD30181A, 30181AY
(9) Clocked serial interface signals
Signal Name
SCK
I/O
Function
Alternate Function
I/O
Serial clock (maximum frequency for input and output: 4.6 MHz)
This signal is output by the VR4181A in master mode and is input from an
external source in slave mode.
KSCAN11,
GPIO23
SI
I
Serial data input signal
KSCAN10,
GPIO22
SO
O
Serial data output signal
This signal is set to high impedance when the value of the FRMEN bit
and FRMMD bit is 1 in the CSIMODE register, and the FRM signal is at
high level.
KSCAN9 ,
GPIO21
FRM
I
Serial frame signal
This signal determines the data direction (transmit/receive), or it can be
used to enable (low level) or disable (high level) transfers.
KSCAN8,
GPIO20
18
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(10) 16550 (UART) serial interface signals
Signal Name
I/O
Function
Alternate Function
RxD0
I
Serial (channel 0) receive data
–
TxD0
O
Serial (channel 0) transmit data
CLKSEL2
RTS0#
O
Serial (channel 0) transmit request signal
GPIO19,
CLKSEL1
CTS0#
I
Serial (channel 0) transmit enable signal
GPIO18
DTR0#/RTS1#
O
Serial (channel 0) terminal ready signal/serial (channel 1) transmit
request signal
GPIO17,
CLKSEL0
DCD0#
I
Serial (channel 0) carrier detection signal
GPIO16
DSR0#/CTS1#
I
Serial (channel 0) data set ready signal/serial (channel 1) transmit enable
signal
GPIO15
RxD1
I
Serial (channel 1) receive data
SCL1, GPIO14
TxD1
O
Serial (channel 1) transmit data
SDA1, GPIO13
RxD2
I
Serial (channel 2) receive data
IRDIN
TxD2
O
Serial (channel 2) transmit data
IRDOUT,
MIPS16EN
RTS2#
O
Serial (channel 2) transmit request signal
SYNC, WS,
DIVMODE1
CTS2#
I
Serial (channel 2) transmit enable signal
BITCLK, SCLK
DTR2#
O
Serial (channel 2) terminal ready signal
SDATAOUT,
SDO,
DIVMODE0
DCD2#
I
Serial (channel 2) carrier detection signal
SDATAIN, SDI
DSR2#
I
Serial (channel 2) data set ready signal
SRESET#
(11) IrDA interface signals
Signal Name
I/O
Function
Alternate Function
IRDIN
I
IrDA receive data input
RxD2
IRDOUT
O
IrDA transmit data output
TxD2, MIPS16EN
(12) I C serial interface signals (µPD30181AY only)
2
Signal Name
SCL1
SDA1
I/O
I/O
I/O
Function
2
Serial clock (open drain) for I C (channel 1)
2
Serial I/O data (open drain) for I C (channel 1)
2
Alternate Function
RxD1, GPIO14
TxD1, GPIO13
SCL0
I/O
Serial clock (open drain) for I C (channel 0)
KPORT7,
GPIO12
SDA0
I/O
Serial I/O data (open drain) for I2C (channel 0)
KPORT6,
GPIO11
Data Sheet U16277EJ1V0DS
19
µPD30181A, 30181AY
(13) PWM interface signals
Signal Name
I/O
Function
Alternate Function
PWM2
O
PWM output (channel 2)
KSCAN5,
GPIO10
PWM1
O
PWM output (channel 1)
KSCAN6, GPIO9
PWM0
O
PWM output (channel 0)
KSCAN7, GPIO8
(14) Keyboard interface signals
Signal Name
I/O
Function
Alternate Function
KPORT7
I
Key scan input data
SCL0, GPIO12
KPORT6
I
Key scan input data
SDA0, GPIO11
KPORT5
I
Key scan input data
CF1_EN#,
GPIO38
KPORT4
I
Key scan input data
CF1_DIR,
GPIO39
KPORT(3:0)
I
Key scan input data
GPIO(7:4)
KSCAN11
O
Key scan output data
SCK, GPIO23
KSCAN10
O
Key scan output data
SI, GPIO22
KSCAN9
O
Key scan output data
SO, GPIO21
KSCAN8
O
Key scan output data
FRM, GPIO20
KSCAN7
O
Key scan output data
PWM0, GPIO8
KSCAN6
O
Key scan output data
PWM1, GPIO9
KSCAN5
O
Key scan output data
PWM2, GPIO10
KSCAN4
O
Key scan output data
CF1_VCCEN#,
GPIO37
KSCAN(3:0)
O
Key scan output data
GPIO(3:0)
(15) Touch panel/analog interface signals
Signal Name
I/O
Function
Alternate Function
TPX(1:0)
I/O
Touch panel X coordinate data
This signal is used to detect the X coordinate of the touch panel location
that has been pressed when the supply voltage is applied to the X
coordinates and Y coordinates.
–
TPY(1:0)
I/O
Touch panel Y coordinate data
This signal is used to detect the Y coordinate of the touch panel location
that has been pressed when the supply voltage is applied to the Y
coordinates and X coordinates.
–
AIN(3:0)
I
General-purpose A/D data input
–
AOUT
O
General-purpose D/A data output
–
20
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(16) Debug interface signals
Signal Name
I/O
Function
Alternate Function
JTCK
I
N-Wire clock
–
JTMS
I
N-Wire mode select signal
This signal selects N-Wire serial transfer mode.
–
JTDI/RMODE#
I
N-Wire input data/N-Wire reset mode select signal
This pin functions alternately as RMODE# and JTDI. When JTRST# is
active it functions as RMODE#, and when JTRST# is inactive it functions
as JTDI.
• RMODE# input
When JTRST# is active, this pin is the reset mode pin. The initial value
for a debug reset is determined by the level of this signal. A debug
reset is a reset of the processor, and there are two types: a debug cold
reset and a debug soft reset. This serves the same function as Cold
Reset input and Soft Reset input from various target systems.
0: Sets debug reset as valid and resets CPU core
1: Sets debug reset as invalid and does not reset CPU core
• JTDI input
When the JTRST# signal is inactive, this pin operates as the N-Wire
serial data input.
–
JTDO
O
N-Wire serial data output
–
JTRST#
I
N-Wire reset signal
–
N-Wire break trigger I/O
• BKTGIO#: When used for input setting
When JTRST# is inactive and BKTGIO# is used for input setting, this
pin is the event trigger/break request input pin. When break requests
are valid, setting BKTGIO# to low level stops execution of user
programs in normal mode and forcibly shifts the processor to debug
mode. After BKTGIO# goes to low level in debug mode, break requests
are retained until the processor is restored to normal mode.
0: Requests break and forcibly shifts processor to debug mode
1: Retains current status of processor
• BKTGIO#: When used for output setting
When JTRST# is inactive and BKTGIO# is used for output setting, this
pin is the event trigger/break output pin. When the processor is
operating in normal mode and an event is detected that meets any of
the conditions for a hardware breakpoint (instruction address breakpoint
or data access breakpoint), an event trigger is output from BKTGIO# as
a low level signal (one pulse) and detection of the event is reported to
the external debugging tool. Finally, after the event trigger is output, all
detected events are reported as one event trigger. When the processor
is shifted to debug mode, output continues at low level and all
previously non-reported events are not reported.
0: Hardware breakpoint was detected
The processor is shifted to debug mode.
1: The processor is in normal mode.
–
BKTGIO#
I/O
Data Sheet U16277EJ1V0DS
21
µPD30181A, 30181AY
(17) General-purpose I/O signals
(1/2)
Signal Name
I/O
Function
General-purpose output ports
Alternate Function
GPO63
O
GPO62
O
GPIO(61:54)
I/O
GPIO(53:52)
I/O
TC(1:0)#
GPIO51
I/O
FPD15,
CF1_READY
GPIO50
I/O
FPD14,
CF1_STSCHG#
GPIO(49:48)
I/O
FPD(13:12),
CF1_CE(2:1)#
GPIO(47:46)
I/O
FPD(11:10),
CF1_CD(2:1)#
GPIO(45:40)
I/O
FPD(9:4)
GPIO39
I/O
CF1_DIR,
KPORT4
GPIO38
I/O
CF1_EN#,
KPORT5
GPIO37
I/O
CF1_VCCEN#,
KSCAN4
GPIO(36:35)
I/O
CF0_CD(2:1)#
GPIO34
I/O
CF0_IOIS16#
GPIO33
I/O
CF_WAIT#
GPIO(32:31)
I/O
CF0_CE(2:1)#
GPIO30
I/O
CF0_STSCHG#
GPIO29
I/O
CF0_READY
GPIO28
I/O
CF0_RESET
GPIO27
I/O
CF0_DIR
GPIO26
I/O
CF0_EN#
GPIO25
I/O
CF_REG#
GPIO24
I/O
CF0_VCCEN#
GPIO23
I/O
SCK, KSCAN11
GPIO22
I/O
SI, KSCAN10
GPIO21
I/O
SO, KSCAN9
GPIO20
I/O
FRM, KSCAN8
GPIO19
I/O
RTS0#/
CLKSEL1
GPIO18
I/O
CTS0#
22
VPBIAS
VPLCD
General-purpose I/O ports
Data Sheet U16277EJ1V0DS
A(22:15)
µPD30181A, 30181AY
(2/2)
Signal Name
I/O
Function
General-purpose I/O ports
Alternate Function
GPIO17
I/O
GPIO16
I/O
DCD0#
GPIO15
I/O
DSR0#, CTS1#
GPIO14
I/O
RxD1, SCL1
GPIO13
I/O
TxD1, SDA1
GPIO12
I/O
SCL0, KPORT7
GPIO11
I/O
SDA0, KPORT6
GPIO10
I/O
PWM2, KSCAN5
GPIO9
I/O
PWM1, KSCAN6
GPIO8
I/O
PWM0, KSCAN7
GPIO(7:4)
I/O
KPORT(3:0)
GPIO(3:0)
I/O
KSCAN(3:0)
Data Sheet U16277EJ1V0DS
DTR0#, RTS1#,
CLKSEL0
23
µPD30181A, 30181AY
(18) Mode setting signals
These signals are used to set various modes.
These signals are sampled only when the RTCRST# signal has changed to high level. At all other times, they
can be used as alternate-function pins.
In order to disconnect a pull-up or pull-down resistor for mode setting during normal operation, use a switch
linked to the RTCRST# signal.
Signal Name
I/O
Function
Alternate Function
BMODE1
I
BMODE0
I
NWIREEN
I
N-Wire use enable signal
0: Disabled
1: Enabled
HSYNC, LOCLK
DBUS32
I
Boot ROM bus width specification
0: 16 bits
1: 32 bits
CF1_RESET
CLKSEL2
I
TxD0
CLKSEL1
I
CLKSEL0
I
Set frequency of CPU core’s pipeline reference clock (AClock)
CLKSEL(2:0) = 111: Setting prohibited (147.4 MHz)
CLKSEL(2:0) = 110: 131.1 MHz
CLKSEL(2:0) = 101: 118.0 MHz
CLKSEL(2:0) = 100: 98.3 MHz
CLKSEL(2:0) = 011: 90.7 MHz
CLKSEL(2:0) = 010: 84.1 MHz
CLKSEL(2:0) = 001: 78.5 MHz
CLKSEL(2:0) = 000: 73.7 MHz
DIVMODE1
I
DIVMODE0
I
MIPS16EN
I
24
Boot ROM type setting
BMODE(1:0) = 01: ROM/flash memory
BMODE(1:0) = 10: SyncFlash memory
BMODE(1:0) = 00 or 11: Setting prohibited
Set division ratio of AClock and internal system bus reference clock
(TClock)
DIVMODE(1:0) = 10: AClock/2 (DIV2 mode)
DIVMODE(1:0) = 01: AClock/3 (DIV3 mode)
DIVMODE(1:0) = 11, 00: Setting prohibited
Enables use of MIPS16 instruction set
0: Use disabled
1: Use enabled
Data Sheet U16277EJ1V0DS
VSYNC, FLM
ENAB, M
RTS0#, GPIO19
DTR0#, RTS1#,
GPIO17
RTS2#, SYNC,
WS
DTR2#, SDO,
SDATAOUT
TxD2, IRDOUT
µPD30181A, 30181AY
(19) Dedicated VDD/GND signals
Signal Name
Power Supply
Function
VDD2
2.5 V
Power supply for internal logic
GND2
2.5 V
GND for internal logic
VDD3
3.3 V
Power supply for I/O buffers (except for I/O buffer of USB transceiver)
GND3
3.3 V
GND for I/O buffers (except for I/O buffer of USB transceiver)
VDDU
3.3 V
Dedicated power supply for USB transceiver
GNDU
3.3 V
Dedicated GND for USB transceiver
VDDP
2.5 V
Dedicated power supply for PLL (analog unit)
GNDP
2.5 V
Dedicated GND for PLL (analog unit)
VDDO
3.3 V
Dedicated power supply for oscillator
GNDO
3.3 V
Dedicated GND for oscillator
VDDAD
3.3 V
Dedicated power supply for the A/D and D/A converters.
The voltage applied to this pin becomes the maximum voltage value for the A/D and
D/A converters’ interface signals.
GNDAD
3.3 V
Dedicated GND for the A/D and D/A converters.
The voltage applied to this pin becomes the minimum voltage value for the A/D and
D/A converters’ interface signals.
VDDTP
3.3 V
Dedicated power supply for touch panel interface
GNDTP
3.3 V
Dedicated GND for touch panel interface
Caution The VR4181A includes two power supply systems, a 2.5 V system and a 3.3 V system. When
applying a voltage, be sure to apply it to the 3.3 V power supply system first. Apply voltage to
the 2.5 V power supply system according to the status of the MPOWER pin.
Data Sheet U16277EJ1V0DS
25
µPD30181A, 30181AY
1.2 Pin Statuses in Specific Status
(1/7)
Pin Name
(Signal Name)
AlternateFunction Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
A24
CKE1
0
0
0
Note 1
0
A23
RP#
0
0
0
Note 1
0
A(22:15)
GPIO(61:54)
0
0
0
Note 1
0
A(14:0)
–
0
0
0
Note 1
0
SA10
–
0
0
0
Note 1
0
D(31:0)
–
0
0
0
Note 1
0
IORD#
–
Hi-Z
Hi-Z
1
Note 1
Hi-Z
IOWR#
–
Hi-Z
Hi-Z
1
Note 1
Hi-Z
IORDY
–
Hi-Z
Hi-Z
–
–
Hi-Z
IOCS16#
–
Hi-Z
Hi-Z
–
–
Hi-Z
UBE#
–
0
0
1/0
Note 1
0
PCS(4:0)#
–
Hi-Z
Hi-Z
1
Note 1
Hi-Z
SYSDIR
–
0
0
0
Note 1
0
SYSEN#
–
0
0
1/0
Note 1
0
DRQ(1:0)#
–
Hi-Z
Hi-Z
–
–
Hi-Z
DAK(1:0)#
–
Hi-Z
Hi-Z
1
Note 1
Hi-Z
Hi-Z
Hi-Z
–
Note 1
Hi-Z
–
–
–
–
–
TC(1:0)#
GPIO(53:52)
NMI#
–
ROMCS#
–
Hi-Z
Hi-Z
1
Note 1
Hi-Z
MEMRD#
–
Hi-Z
Hi-Z
1
Note 1
Hi-Z
MEMWR#
–
Hi-Z
Hi-Z
1
Note 1
Hi-Z
0
0
1
Note 1
0
0
Operating
Operating
0
0
0
1
1
Note 1
0
RP#
A23
SDCLK
–
CKE1
A24
CKE0
–
0
1
Note 2
0
0
SDCS(3:2)#
–
0
1
1/0
1/0
0
SDCS(1:0)#
–
0
1
1/0
1/0
0
RAS#
–
0
1
1/0
1/0
0
Notes 1. The status in the previous Fullspeed mode is retained.
2. Changes according to the setting in the SDRAMACT register in the GIU.
When SDACT bit = 0: 1
When SDACT bit = 1: 0
Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance
2. When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
26
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2/7)
Pin Name
(Signal Name)
AlternateFunction Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
CAS#
–
0
1
1/0
1/0
0
DQM(3:0),
LBE(3:0)#
–
0
0
1/0
1/0
0
WE#
–
0
1
1/0
1/0
0
POWER
–
–
–
–
–
–
RSTSW#
–
–
–
–
–
–
RTCRST#
–
–
–
–
–
–
POWERON
–
0
0
0
0
0
MPOWER
–
0
0
1
1
0
RTCX(2:1)
–
–
–
–
–
–
CLKX(2:1)
–
–
–
–
–
–
DCLK, SHCLK
–
0
0
0
Note 1
0
HSYNC, LOCLK NWIREEN
Note 2
0
0
Note 1
0
VSYNC, FLM
BMODE1
Note 3
0
0
Note 1
0
ENAB, M
BMODE0
Note 3
0
0
Note 1
0
FPD15
CF1_READY,
GPIO51
Hi-Z
Hi-Z
0
Note 1
Hi-Z
FPD14
CF1_STSCHG#,
GPIO50
Hi-Z
Hi-Z
0
Note 1
Hi-Z
FPD(13:12)
CF1_CE(2:1)#,
GPIO(49:48)
Hi-Z
Hi-Z
0
Note 1
Hi-Z
FPD(11:10)
CF1_CD(2:1)#,
GPIO(47:46)
Hi-Z
Hi-Z
0
Note 1
Hi-Z
FPD(9:4)
GPIO(45:40)
Hi-Z
Hi-Z
0
Note 1
0
0
0
0
Note 1
0
FPD(3:0)
–
VPLCD
GPO62
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VPBIAS
GPO63
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Notes 1. The status in the previous Fullspeed mode is retained. If the LCD panel’s voltage drops during
Suspend mode, enter settings in the LCU register to stop output operations and set the pin’s value to
0.
2. The input level is sampled when the RTCRST# signal has changed to high level in order to enable or
disable use of the N-Wire.
3. The input level is sampled when the RTCRST# signal has changed to high level in order to set the
boot ROM type.
Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance
2. When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
Data Sheet U16277EJ1V0DS
27
µPD30181A, 30181AY
(3/7)
Pin Name
(Signal Name)
AlternateFunction Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
CF1_CD(2:1)#
FPD(11:10),
GPIO(47:46)
Hi-Z
Hi-Z
–
–
Hi-Z
CF1_CE(2:1)#
FPD(13:12) ,
GPIO(49:48)
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF1_STSCHG#
FPD14, GPIO50
Hi-Z
Hi-Z
–
–
Hi-Z
CF1_READY
FPD15, GPIO51
Hi-Z
Hi-Z
–
–
Hi-Z
CF1_RESET
DBUS32
Note 2
Hi-Z
Hi-Z
Note 1
Note 3
CF1_DIR
KPORT4,
GPIO39
Hi-Z
Hi-Z
0
Note 1
Hi-Z
CF1_EN#
KPORT5,
GPIO38
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF1_VCCEN#
KSCAN4,
GPIO37
Hi-Z
Hi-Z
1
Note 1
Hi-Z
CF0_CD(2:1)#
GPIO(36:35)
Hi-Z
Hi-Z
–
–
Hi-Z
CF0_IOIS16#
GPIO34
Hi-Z
Hi-Z
–
–
Hi-Z
CF_WAIT#
GPIO33
Hi-Z
Hi-Z
–
–
Hi-Z
CF0_CE(2:1)#
GPIO(32:31)
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF0_STSCHG#
GPIO30
Hi-Z
Hi-Z
–
–
Hi-Z
CF0_READY
GPIO29
Hi-Z
Hi-Z
–
–
–
CF0_RESET
GPIO28
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF0_DIR
GPIO27
Hi-Z
Hi-Z
0
Note 1
Hi-Z
CF0_EN#
GPIO26
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF_REG#
GPIO25
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF0_VCCEN#
GPIO24
Hi-Z
Hi-Z
1
Note 1
Hi-Z
CLK48
–
Hi-Z
Hi-Z
Note 3
Note 3
Hi-Z
UHDP
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
UHDN
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
UPON
–
0
0
0
0
0
UOC
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
UDP
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Notes 1. The status in the previous Fullspeed mode is retained.
2. The input level is sampled when the RTCRST# signal has changed to high level in order to set the
boot ROM bus width.
3. The registers in the GIU can be used to set 1, 0, or high impedance.
Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance
2. When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
28
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(4/7)
Pin Name
(Signal Name)
AlternateFunction Pin
Name (Alternate
Signal Name)
UDN
During RTC
Reset
–
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
WS, RTS2#,
DIVMODE1
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDATAOUT
SDO, DTR2#,
DIVMODE0
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDATAIN
SDI, DCD2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SRESET#
DSR2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCLK
BITCLK, CTS2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
WS
SYNC, RTS2#,
DIVMODE1
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDO
SDATAOUT,
DTR2#,
DIVMODE0
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDI
SDATAIN,
DCD2#
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
KSCAN11,
GPIO23
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SI
KSCAN10,
GPIO22
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SO
KSCAN9,
GPIO21
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
FRM
KSCAN8,
GPIO20
Hi-Z
Hi-Z
–
Note 2
Hi-Z
BITCLK
SCLK, CTS2#
SYNC
RxD0
Hi-Z
Hi-Z
–
–
Hi-Z
TxD0
CLKSEL2
–
Note 3
Hi-Z
1
Note 2
1
RTS0#
GPIO19,
CLKSEL1
Note 3
Hi-Z
1
Note 2
1
CTS0#
GPIO18
Hi-Z
Hi-Z
–
–
Hi-Z
Notes 1. The input level is sampled when the RTCRST# signal has changed to high level in order to set the
division ratio for the CPU core’s pipeline reference clock (AClock) and the peripheral system bus’s
reference clock (TClock).
2. The status in the previous Fullspeed mode is retained.
3. The input level is sampled when the RTCRST# signal has changed to high level in order to set the
frequency of the CPU core’s pipeline reference clock (AClock).
Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance
2. When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
Data Sheet U16277EJ1V0DS
29
µPD30181A, 30181AY
(5/7)
AlternateFunction Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
DTR0#
RTS1#, GPIO17,
CLKSEL0
Note 1
Hi-Z
1
Note 2
Hi-Z
DCD0#
GPIO16
–
–
–
–
–
DSR0#
CTS1#, GPIO15
–
–
–
–
Hi-Z
RxD1
SCL1, GPIO14
Hi-Z
Hi-Z
−
−
Hi-Z
TxD1
SDA1, GPIO13
Hi-Z
Hi-Z
1
Note 2
Hi-Z
RTS1#
DTR0#, GPIO17,
CLKSEL0
Note 1
Hi-Z
1
Note 2
Hi-Z
CTS1#
DSR0#, GPIO15
–
–
–
–
Hi-Z
RxD2
IRDIN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TxD2
IRDOUT,
MIPS16EN
Note 3
Hi-Z
1
Note 2
Hi-Z
RTS2#
SYNC, WS,
DIVMODE1
Note 4
Hi-Z
1
Note 2
Hi-Z
CTS2#
SCLK, BITCLK
Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
DTR2#
SDO,
SDATAOUT,
DIVMODE0
Note 4
Hi-Z
1
Note 2
Hi-Z
DCD2#
SDI, SDATAIN
Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
DSR2#
SRESET#
Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
IRDIN
RxD2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IRDOUT
TxD2,
MIPS16EN
Note 3
Hi-Z
0
Note 2
Hi-Z
Pin Name
(Signal Name)
Notes 1. The input level is sampled when the RTCRST# signal has changed to high level in order to set the
frequency of the CPU core’s pipeline reference clock (AClock).
2. The status in the previous Fullspeed mode is retained.
3. The input level is sampled when the RTCRST# signal has changed to high level in order to set
whether to use the MIPS16 instruction set or not.
4. The input level is sampled when the RTCRST# signal has changed to high level in order to set the
division ratio for the CPU core’s pipeline reference clock (AClock) and the peripheral system bus’s
reference clock (TClock).
Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance
2. When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
30
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(6/7)
Pin Name
(Signal Name)
AlternateFunction Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
SCL1Note 1
RxD1, GPIO14
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SDA1Note 1
TxD1, GPIO13
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
Note 1
SCL0
KPORT7,
GPIO12
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SDA0Note 1
KPORT6,
GPIO11
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
PWM2
KSCAN5,
GPIO10
Hi-Z
Hi-Z
0
Note 2
Hi-Z
PWM1
KSCAN6,
GPIO9
Hi-Z
Hi-Z
Note 2
Note 2
Note 2
PWM0
KSCAN7,
GPIO8
Hi-Z
Hi-Z
Note 2
Note 2
Note 2
KPORT7
SCL0, GPIO12
Hi-Z
Hi-Z
–
–
Hi-Z
KPORT6
SDA0, GPIO11
Hi-Z
Hi-Z
–
–
Hi-Z
KPORT5
CF1_EN#,
GPIO38
Hi-Z
Hi-Z
–
–
Hi-Z
KPORT4
CF1_DIR,
GPIO39
Hi-Z
Hi-Z
–
–
Hi-Z
KPORT(3:0)
GPIO(7:4)
Hi-Z
Hi-Z
–
–
Hi-Z
KSCAN11
SCK, GPIO23
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN10
SI, GPIO22
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN9
SO, GPIO21
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN8
FRM, GPIO20
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN7
PWM0, GPIO8
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN6
PWM1, GPIO9
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN5
PWM2, GPIO10
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN4
CF1_VCCEN#,
GPIO37
Hi-Z
Hi-Z
0
Note 2
Hi-Z
KSCAN(3:0)
GPIO(3:0)
Hi-Z
Hi-Z
0
Note 2
Hi-Z
TPX(1:0)
–
1
1
1
Note 2
1
TPY(1:0)
–
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
AIN(3:0)
–
–
–
–
–
–
AOUT
–
0
0
0
Note 2
0
Notes 1. µPD30181AY only
2. The status in the previous Fullspeed mode is retained.
Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance
2. When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
Data Sheet U16277EJ1V0DS
31
µPD30181A, 30181AY
(7/7)
AlternateFunction Pin
Name (Alternate
Signal Name)
During RTC
Reset
After RTC Reset
After Reset by
RSTSW or
Watchdog Timer
In Suspend
Mode
In Hibernate
Mode or During
Shutdown by
HALTimer
JTCKNote 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTMSNote 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTDI ,
RMODE#
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
JTDONote 1
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
–
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
VPBIAS
Hi-Z
HI-Z
Hi-Z
Hi-Z
Hi-Z
VPLCD
HI-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
A(22:15)
Hi-Z
Hi-Z
Note 3
Note 3
Note 3
Hi-Z
Note 3
Note 3
Note 3
Pin Name
(Signal Name)
Note 1
Note 1
JTRST#
Note 1
BKTGIO#
GPO63
GPO62
Note 2
GPIO(61:54)
GPIO(53:0)
Note 4
Hi-Z
Note 5
Notes 1. This is the pin status when the N-Wire function has been set to use prohibit status via a setting for the
NWIREEN pin.
2. When SyncFlash memory has been selected as the boot ROM, this pin can be used as the GPIO pin.
3. The registers in the GIU can be used to set 1, 0, or high impedance.
4. See the other pin names and alternate-function pin names.
5. The GPIO19 and GPIO17 signals are sampled as CLKSEL(1:0) when the RTCRST# signal has
changed to high level in order to set the frequency of the CPU core’s pipeline reference clock
(AClock).
Caution After an RTC reset, the GPIO pins are set in the input direction and input disable status is set.
Input enable status can be set by software after an RTC reset. Accordingly, there is no need to
externally add elements such as pull-up or pull-down resistors for unused GPIO pins in order to
determine the signal status. However, GPIO(61:54), which are shared with A(22:15), function as
GPIO pins only when SyncFlash memory has been selected.
The status of output pins in
Hibernate mode can be specified by using software to enter the required settings in internal
registers in advance.
Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance
2. When a pin has high impedance, the buffer’s input enable setting is OFF. Leakage current will not
occur even when an intermediate level is applied.
32
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
1.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins
(1/3)
Pin Name
I/O
I/O Circuit Type
Recommended Connection of Unused Pins
A24/CKE1
O
A
Leave open
A23/RP#
O
A
Leave open
A(22:15)/GPIO(61:54)
I/O
A
Leave open
A(14:0)
O
A
Leave open
SA10
O
A
Leave open
D(31:0)
I/O
A
Connect to VDD3 or GND3 via a resistor
IORD#
O
A
Leave open
IOWR#
O
A
Leave open
IORDY
I
A
Connect to VDD3
IOCS16#
I
A
Connect to VDD3
UBE#
O
A
Leave open
PCS(4:0)#
O
A
Leave open
SYSDIR
O
A
Leave open
SYSEN#
O
A
Leave open
DRQ(1:0)#
I
A
Connect to VDD3
DAK(1:0)#
O
A
Leave open
TC(1:0)#/GPIO(53:52)
I/O
A
Leave open
NMI#
I
A
Connect to VDD3
ROMCS#
O
A
Leave open
MEMRD#
O
A
Leave open
MEMWR#
O
A
Leave open
SDCLK
O
A
Leave open
CKE0
O
A
Leave open
SDCS(3:0)#
O
A
Leave open
RAS#
O
A
Leave open
CAS#
O
A
Leave open
DQM(3:0)/LBE(3:0)#
O
A
Leave open
WE#
O
A
Leave open
POWER
I
B
Connect to VDD3
RSTSW#
I
B
Connect to VDD3
RTCRST#
I
B
–
POWERON
O
A
Leave open
MPOWER
O
A
Leave open
O
A
Leave open
I/O
A
Connect to VDD3 or GND3 via a resistor
I/O
A
Connect to VDD3 or GND3 via a resistor
DCLK/SHCLK
Note
HSYNC/LOCLK/NWIREEN
Note
VSYNC/FLM/BMODE1
Note The signal level is sampled when the RTCRST# signal has changed to high level.
Data Sheet U16277EJ1V0DS
33
µPD30181A, 30181AY
(2/3)
Pin Name
I/O
I/O Circuit Type
Recommended Connection of Unused Pins
ENAB/M/BMODE0Note
I/O
A
Connect to VDD3 or GND3 via a resistor
FPD15/CF1_READY/GPIO51
I/O
A
Leave open
FPD14/CF1_STSCHG#/GPIO50
I/O
A
Leave open
FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48)
I/O
A
Leave open
FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46)
I/O
A
Leave open
FPD(9:4)/GPIO(45:40)
I/O
A
Leave open
FPD(3:0)
O
A
Leave open
VPLCD/GPO62
O
A
Leave open
O
A
Leave open
CF1_RESET/DBUS32
I/O
B
Connect to VDD3 or GND3 via a resistor
CF1_DIR/KPORT4/GPIO39
I/O
B
Leave open
CF1_EN#/KPORT5/GPIO38
I/O
B
Leave open
CF1_VCCEN#/KSCAN4/GPIO37
I/O
B
Leave open
CF0_CD(2:1)#/GPIO(36:35)
I/O
B
Leave open
VPBIAS/GPO63
Note
CF0_IOIS16#/GPIO34
I/O
B
Leave open
CF_WAIT#/GPIO33
I/O
B
Leave open
CF0_CE(2:1)#/GPIO(32:31)
I/O
B
Leave open
CF0_STSCHG#/GPIO30
I/O
B
Leave open
CF0_READY/GPIO29
I/O
B
Leave open
CF0_RESET/GPIO28
I/O
B
Leave open
CF0_DIR/GPIO27
I/O
B
Leave open
CF0_EN#/GPIO26
I/O
B
Leave open
CF_REG#/GPIO25
I/O
B
Leave open
CF0_VCCEN#/GPIO24
I/O
B
Leave open
SCK/KSCAN11/GPIO23
I/O
B
Leave open
SI/KSCAN10/GPIO22
I/O
B
Leave open
SO/KSCAN9/GPIO21
I/O
B
Leave open
FRM/KSCAN8/GPIO20
I/O
B
Leave open
RxD2/IRDIN
I
B
Leave open
TxD2/IRDOUT/MIPS16ENNote
I/O
B
Connect to VDD3 or GND3 via a resistor
RTS2#/SYNC/WS/DIVMODE1Note
I/O
B
Connect to VDD3 or GND3 via a resistor
I/O
B
Leave open
I/O
B
Connect to VDD3 or GND3 via a resistor
I
B
Leave open
I/O
B
Leave open
I
B
Connect to VDD3
I/O
B
Connect to VDD3 or GND3 via a resistor
I/O
B
Connect to VDD3 or GND3 via a resistor
CTS2#/BITCLK/SCLK
Note
DTR2#/SDATAOUT/SDO/DIVMODE0
DCD2#/SDATAIN/SDI
DSR2#/SRESET#
RxD0
Note
TxD0/CLKSEL2
Note
RTS0#/GPIO19/CLKSEL1
Note The signal level is sampled when the RTCRST# signal has changed to high level.
34
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(3/3)
Pin Name
I/O
I/O Circuit Type
CTS0#/GPIO18
I/O
B
Leave open
DTR0#/RTS1#/GPIO17/CLKSEL0Note
I/O
B
Connect to VDD3 or GND3 via a resistor
DCD0#/GPIO16
I/O
B
Leave open
DSR0#/CTS1#/GPIO15
I/O
B
Leave open
RxD1/SCL1/GPIO14
I/O
B
Leave open
TxD1/SDA1/GPIO13
I/O
B
Leave open
SCL0/KPORT7/GPIO12
I/O
B
Leave open
SDA0/KPORT6/GPIO11
I/O
B
Leave open
PWM2/KSCAN5/GPIO10
I/O
B
Leave open
PWM1/KSCAN6/GPIO9
I/O
B
Leave open
PWM0/KSCAN7/GPIO8
I/O
B
Leave open
KPORT(3:0)/GPIO(7:4)
I/O
B
Leave open
KSCAN(3:0)/GPIO(3:0)
I/O
B
Leave open
CLK48
I
A
Leave open
UHDP
I/O
G
Leave open
UHDN
I/O
G
Leave open
UPON
O
A
Leave open
UOC
I
B
Connect to GND3
UDP
I/O
G
Leave open
UDN
I/O
G
Leave open
TPX(1:0)
I/O
C
Leave open
TPY0
I/O
C
Leave open
TPY1
I/O
D
Leave open
AIN(3:0)
I
E
Leave open
AOUT
O
F
Leave open
JTCK
I
A
Leave open
JTMS
I
A
Leave open
JTDI/RMODE#
I
A
Leave open
JTDO
O
A
Leave open
JTRST#
I
A
Leave open
I/O
A
Leave open
BKTGIO#
Recommended Connection of Unused Pins
Note The signal level is sampled when the RTCRST# signal has changed to high level.
Data Sheet U16277EJ1V0DS
35
µPD30181A, 30181AY
1.4 Pin I/O Circuits
Type A
Type D
VDD3
Data
VDDTP
Data
P-ch
P-ch
IN/OUT
Output
disable
IN/OUT
Output
disable
N-ch
N-ch
P-ch
+
−
Input
enable
N-ch
Vref
Type B
VDD3
Data
Input
enable
P-ch
N-ch
IN/OUT
Open drain
Output
disable
N-ch
Type E
IN
P-ch
+
−
N-ch
Input
enable
Vref
Type C
Type F
Analog
output
voltage
VDDTP
Data
P-ch
OUT
IN/OUT
Type G
Output
disable
N-ch
P-ch
+
−
Data
−IN/OUT
Output
disable
N-ch
Vref
+IN/OUT
+
−
Input
enable
Remark Type A: Low slew-rate output
Type B: Schmitt-triggered input, low slew-rate output
Type G: Differential I/O
36
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Symbol
Supply voltage
Input voltage
Storage temperature
Condition
Rating
Unit
VDD25
2.5 V (VDD2, VDDP pins)
–0.5 to +3.6
V
VDD33
3.3 V (VDD3, VDDU, VDDTP, VDDAD, VDDO pins)
–0.5 to +4.0
V
VI
VDD33 ≥ 3.7 V
–0.5 to +4.0
V
VDD33 < 3.7 V
–0.5 to VDD33 + 0.3
V
–65 to +125
°C
Tstg
Cautions 1. Do not short-circuit two or more output pins simultaneously.
2. If even one of the above parameters exceeds the absolute maximum ratings even
momentarily, the quality of the product may be degraded. The absolute maximum ratings,
therefore, specify the value exceeding which the product may be physically damaged. Use
the product well within these ratings.
The specifications and conditions shown in DC Characteristics and AC Characteristics are
the ranges for normal operation and quality assurance of the product.
3. VI can be –1.5 V if the input pulse is less than 10 ns.
Operating Conditions
Parameter
Symbol
Supply voltage
Ambient temperature
Oscillation start voltageNote 1
Condition
MIN.
MAX.
Unit
VDD25
2.5 V (VDD2, VDDP pins)
2.3
2.7
V
VDD33
3.3 V (VDD3, VDDU, VDDTP, VDDAD, VDDO pins)
3.0
3.6
V
TA
When operating at 131.1 MHz
–40
+85
°C
VDDS
3.0
V
Note 2
VDDH1
2.5
V
Note 3
VDDH2
3.0
V
Oscillation hold voltage
Oscillation hold voltage
Notes 1. This is a voltage at which oscillation is always started after power application, and is applied to
oscillators of 32.768 kHz and 18.432 MHz.
2. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 32.768 kHz.
3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal
operation level, and is applied to an oscillator of 18.432 MHz.
Remark The VR4181A has two types of power supplies. The 3.3 V power supply should be turned on at first.
Turn on/off the 2.5 V power supply depending on the status of the MPOWER pin.
Capacitance (TA = –40 to +85°°C, VDD33 = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
Unmeasured pins returned to 0 V.
MIN.
MAX.
Unit
10
pF
Note 1
CI_USB
20
pF
Note 2
CIO
10
pF
I/O capacitance
I/O capacitance
Notes 1. Applies to the UHDP, UHDN, UDP, and UDN pins.
2. Applies to I/O pins other than the UHDP, UHDN, UDP, and UDN pins.
Data Sheet U16277EJ1V0DS
37
µPD30181A, 30181AY
DC Characteristics (TA = –40 to +85°°C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V)
(1) Pins of I/O circuit types A, C, and D
Parameter
Output voltage, high
Symbol
VOH
Conditions
Pins of types A
MIN.
Note 1
Note 2
Note 3
Note 1
Note 2
Note 3
,C
, and D
TYP.
MAX.
0.8VDD33
,
Unit
V
IOH = −2 mA
Output voltage, low
VOL
Pins of types A
,C
, and D
0.4
V
2.0
VDD33 + 0.3
V
0.75VDD33
VDD33 + 0.3
V
−0.3
0.25VDD33
V
−0.3
0.5
V
,
IOL = 2 mA
Input voltage, high
VIH
Pins of types A
Note 1
(excluding GPIO pin of
Note 2
edge triggered interrupt), C
VIH1E
Pins of type A
VIL
Pins of type A
Note 4
Note 3
, and D
(GPIO pin of edge
triggered interrupt)
Input voltage, low
Note 1
(excluding GPIO pin of
Note 2
edge triggered interrupt), C
VIL1E
Pins of type A
Note 4
Note 3
, and D
(GPIO pin of edge
triggered interrupt)
Notes 1. Applies to the following pins.
D(31:0), IORDY, IOCS16#, DRQ(1:0)#, TC(1:0)#/GPIO(53:52), NMI#, HSYNC/LOCLK/NWIREEN,
ENAB/M/BMODE0, VSYNC/FLM/BMODE1, FPD15/CF1_READY/GPIO51,
FPD14/CF1_STSCHG#/GPIO50, FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48),
FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46), FPD(9:4)/GPIO(45:40), CLK48, JTCK, JTMS, JTDI/RMODE#,
JTRST#, BKTGIO#, A(14:0), A23/RP#, A24/CKE1, CAS#, CKE0, DAK(1:0)#, DCLK/SHCLK, DQM(3:0),
FPD(3:0), IORD#, JTDO, MEMRD#, MEMWR#, MPOWER, PCS(4:0)#, POWERON, RAS#, ROMCS#,
SA10, SDCLK, SDCS(3:0)#, SYSDIR, SYSEN#, UBE#, UPON, VPBIAS/GPO63, VPLCD/GPO62, WE#
2. Applies to the TPX(1:0) and TPY0 pins.
3. Applies to the TPY1 pin.
4. Applies to the following pins.
FPD(9:4)/GPIO(45:40), FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46),
FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48), FPD14/CF1_STSCHG#/GPIO50,
FPD15/CF1_READY/GPIO51, TC(1:0)#/GPIO(53:52), A(22:15)/GPIO(61:54)
Remark For details of the I/O circuits, refer to 1.4 Pin I/O Circuits
38
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(2) Pins of I/O circuit types B and G
Parameter
Output voltage, high
Output voltage, low
Symbol
Input voltage, low
MIN.
VOH2
Pins of type BNote 1, IOH = –2 mA
0.8VDD33
VOH_USB
Pins of type GNote 2, RPD = 15 kΩ
2.8
VOL2
Pins of type BNote 1, IOL = 2 mA
VOL_USB
Input voltage, high
Conditions
Pins of type G
, RPU = 1.5 kΩ
0.75VDD33
Note 1
Pins of type B
VIH_USB
Pins of type GNote 2, single end
Pins of type B
Unit
3.6
V
0.4
V
0.3
V
VDD33 +
0.3
V
2.0
V
−0.3
Note 1
MAX.
V
Note 2
VIH2
VIL2
TYP.
Note 2
0.6
V
0.8
V
VIL_USB
Pins of type G
Hysteresis voltageNote 3
VH
Pins of type BNote 1
Output cross levelNote 4
VCRS_USB
Pins of type GNote 2
1.3
Differential input
sensitivityNote 4
VDI_USB
Pins of type GNote 2
0.2
Differential input common
mode rangeNote 4
VCM_USB
Pins of type GNote 2, VDI < 200 mV
0.8
2.5
V
External pull-up resistor
RPU
Pins of type GNote 2
1.425
1.575
kΩ
External pull-down resistor
RPD
Note 2
Pins of type G
14.25
15.75
kΩ
External resistor for
impedance adjustmentNote 5
RS
Pins of type GNote 2
20.9
23.1
Ω
, single end
0.17VDD33
V
2.0
V
V
Notes 1. Applies to the following pins.
POWER, RSTSW#, RTCRST#, CF1_RESET/DBUS32, RxD0, TxD0/CLKSEL2, RxD2/IRDIN,
TxD2/IRDOUT/MIPS16EN, CTS2#/BITCLK/SCLK, DTR2#/SDATAOUT/SDO/DIVMODE0,
RTS2#/SYNC/WS/DIVMODE1, DCD2#/SDATAIN/SDI, DSR2#/SRESET#, UOC,
CF1_DIR/KPORT4/GPIO39, CF1_EN#/KPORT5/GPIO38, CF1_VCCEN#/KSCAN4/GPIO37,
CF0_CD2#/GPIO36, CF0_CD1#/GPIO35, CF0_IOIS16#/GPIO34, CF_WAIT#/GPIO33,
CF0_CE2#/GPIO32, CF0_CE1#/GPIO31, CF0_STSCHG#/GPIO30, CF0_READY/GPIO29,
CF0_RESET/GPIO28, CF0_DIR/GPIO27, CF0_EN#/GPIO26, CF_REG#/GPIO25,
CF0_VCCEN#/GPIO24, SCK/KSCAN11/GPIO23, SI/KSCAN10/GPIO22, SO/KSCAN9/GPIO21,
FRM/KSCAN8/GPIO20, RTS0#/GPIO19/CLKSEL1, CTS0#/GPIO18, DTR0#/RTS1#/GPIO17/CLKSEL0,
DCD0#/GPIO16, DSR0#/CTS1#/GPIO15, RxD1/SCL1/GPIO14, TxD1/SDA1/GPIO13,
SCL0/KPORT7/GPIO12, SDA0/KPORT6/GPIO11, PWM(2:0)/KSCAN(5:7)/GPIO(10:8),
KPORT(3:0)/GPIO(7:4), KSCAN(3:0)/GPIO(3:0)
2. Applies to the UHDP, UHDN, UDP, and UDN pins
3. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input
signal is not recognized when the signal goes from low to high and the maximum voltage at which the
low level is not recognized when the signal goes from high to low.
4. Precision tests have not been performed. Only guaranteed as design characteristics.
5. The recommended value is 22 Ω.
Remark
For details of the I/O circuits, refer to 1.4 Pin I/O Circuits.
Data Sheet U16277EJ1V0DS
39
µPD30181A, 30181AY
Connection example of external resistor
(a) When pulled down
UHDP, UHDN,
UDP, UDN
DUT
RS
RPD
GNDU
(b) When pulled up
VDDU
RPU
RS
UHDP, UHDN,
UDP, UDN
40
DUT
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(3) Common
Parameter
Symbol
Power supply currentNote 1
IDD25Note 2
Conditions
Fullspeed mode
Unit
350
mA
mA
Fullspeed mode, program using cache
operating, DMA controller operating
100
mA
Fullspeed mode, program not using cache
operating, all peripheral bus masters
stopped, all clocks of unused units stopped
80
mA
Standby mode, peripheral bus master
operating continuously
70
90
mA
Standby mode, all peripheral bus masters
stopped, all clocks of unused unit stopped
45
53
mA
Suspend mode
10
20
mA
Hibernate mode, VDD25 = 0 V
0
0
mA
Fullspeed mode
32-bit bus
45
58
mA
16-bit bus
40
50
mA
32-bit bus
45
58
mA
16-bit bus
40
50
mA
Standby mode, all peripheral bus masters
stopped, all clocks of unused units stopped
2
4
mA
Suspend mode
2
4
mA
Hibernate mode, PWMU channel 0 operating
2
4
mA
Hibernate mode, PWMU channel 0 stopped
25
50
µA
IDDAD
A/D, D/A converters operating
3
9
mA
ILI
VDD33 = 3.6 V, VI = VDD33, 0 V
±5
µA
ILO
VDD33 = 3.6 V, VI = VDD33, 0 V
±5
µA
Standby mode,
peripheral bus master
operating continuously
Note 4
Output leakage current
MAX.
165
IDD33
Input leakage current
TYP.
Fullspeed mode, program using cache
operating, DMA controller operating, clock
supplied to PCI unit
Note 3
Note 5
MIN.
Notes 1. Value when AClock = 131.1 MHz, TClock = 65.55 MHz, Div2 mode.
2. IDD25 is the total current flowing to the VDD2 and VDDP pins.
3. IDD33 is the total current flowing to the VDD3, VDDU, VDDTP, and VDDO pins.
4. IDDAD is the current flowing to the VDDAD pin when Vref is supplied to the A/D and D/A converters.
5. Excluding the I.C. pin.
Remarks 1. In Suspend mode, the internal LCD controller does not operate because the memory controller
(MCU) clock and LCD controller (LCU) clock are stopped.
2. Each current value is the average value that flows under the specified conditions. Design the power
supply so that the current under the MAX. condition can be supplied stably (so that voltage drop or
ripple do not occur in the whole system).
3. The peripheral bus master indicates the following peripheral units.
LCU, DCU, IOPCIU, USBHU, USBFU, AC97U
Data Sheet U16277EJ1V0DS
41
µPD30181A, 30181AY
Data Retention Characteristics (TA = −40 to +85°°C)
Parameter
Symbol
Conditions
Data retention voltage
VDDDR3
Hibernate mode, 3.3 V power supply
Data retention high-level input voltage
VIHDR
Hibernate mode, RTCRST# pin
MIN.
MAX.
Unit
2.5
3.6
V
0.9VDDDR3
V
The data retention voltage and data retention high-level input voltage are the voltages that guarantee the
operation of ElapsedTime counter in the RTC and the data retention of the registers (using a 3.3 V power supply) of
the following peripheral units. These voltages do not apply to the data in the CPU core (using a 2.5 V power supply).
PMU:
PMUINTREG, PMUCNTREG, PMUWAITREG, PMUDIVREG
RTC:
ETIMELREG, ETIMEMREG, ETIMEHREG, ECMPLREG, ECMPMREG, ECMPHREG
GIU:
GPMODE0, GPMODE1, GPMODE2, GPMODE3, GPMODE4, GPMODE5, GPMODE6, GPMODE7,
GPDATA0, GPDATA1, GPDATA2, GPDATA3, GPINEN0, GPINEN1, GPINEN2, GPINEN3, GPINTMSK0,
GPINTMSK1, GPINTMSK2, GPINTMSK3, GPINTTYP0, GPINTTYP1, GPINTTYP2, GPINTTYP3,
GPINTTYP4, GPINTTYP5, GPINTTYP6, GPINTTYP7, GPINTSTAT0, GPINTSTAT1, GPINTSTAT2,
GPINTSTAT3, PINMODE, SDRAMACT, NVREG0, NVREG1, NVREG2, NVREG3
PWMU: PWM0ATSREG, PWM0IATSREG, PWM0CNTREG, PWM0ASTCREG, PWM0INTREG, PWM1CTRL,
PWM1BUF
42
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
AC Characteristics (TA = –40 to +85°°C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V)
AC test input test points
(a) D(31:0), IORDY, IOCS16#, DRQ(1:0)#, TC(1:0)#/GPIO(53:52), NMI#, HSYNC/LOCLK/NWIREEN,
VSYNC/FLM/BMODE1, FPD15/CF1_READY/GPIO51, FPD14/CF1_STSCHG#/GPIO50,
FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48), FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46), FPD(9:4)/GPIO(45:40),
CLK48, JTCK, JTMS, JTDI/RMODE#, JTRST#, BKTGIO#, TPX(1:0), TPY(1:0)
VDD33
2.0 V
2.0 V
Test points
Input pins
0.25VDD33
0.25VDD33
0V
(b) A(22:15)/GPIO(61:54), POWER, RSTSW#, RTCRST#, CF1_RESET/DBUS32, RxD0, TxD0/CLKSEL2,
RxD2/IRDIN, TxD2/IRDOUT/MIPS16EN, CTS2#/BITCLK/SCLK, DTR2#/SDATAOUT/SDO/DIVMODE0,
RTS2#/SYNC/WS/DIVMODE1, DCD2#/SDATAIN/SDI, DSR2#/SRESET#, UOC, CF1_DIR/KPORT4/GPIO39,
CF1_EN#/KPORT5/GPIO38, CF1_VCCEN#/KSCAN4/GPIO37, CF0_CD(2:1)#/GPIO(36:35),
CF0_IOIS16#/GPIO34, CF_WAIT#/GPIO33, CF0_CE(2:1)#/GPIO(32:31), CF0_STSCHG#/GPIO30,
CF0_READY/GPIO29, CF0_RESET/GPIO28, CF0_DIR/GPIO27, CF0_EN#/GPIO26, CF_REG#/GPIO25,
CF0_VCCEN#/GPIO24, SCK/KSCAN11/GPIO23, SI/KSCAN10/GPIO22, SO/KSCAN9/GPIO21,
FRM/KSCAN8/GPIO20, RTS0#/GPIO19/CLKSEL1, CTS0#/GPIO18, DTR0#/RTS1#/GPIO17/CLKSEL0,
DCD0#/GPIO16, DSR0#/CTS1#/GPIO15, RxD1/SCL1/GPIO14, TxD1/SDA1/GPIO13, SCL0/KPORT7/GPIO12,
SDA0/KPORT6/GPIO11, PWM(2:0)/KSCAN(5:7)/GPIO(10:8), KPORT(3:0)/GPIO(7:4), KSCAN(3:0)/GPIO(3:0)
VDD33
0.75VDD33
0.75VDD33
Test points
Input pins
0.25VDD33
0.25VDD33
0V
Data Sheet U16277EJ1V0DS
43
µPD30181A, 30181AY
AC test output test points
VDD33
All output pins
Test points
0.5VDD33
0.5VDD33
0V
Load condition
All output pins
DUT
CL = 50 pF
44
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(1) Clock parameters
Parameter
CPU core operating
Symbol
fAClock
frequency
Conditions
MIN.
Note
TYP.
fTClock
frequency
147.4
MHz
CLKSEL(2:0) = 110
131.1
MHz
CLKSEL(2:0) = 101
118.0
MHz
CLKSEL(2:0) = 100
98.3
MHz
CLKSEL(2:0) = 011
90.7
MHz
CLKSEL(2:0) = 010
84.1
MHz
CLKSEL(2:0) = 001
78.5
MHz
73.7
Note
18.432
fAClock/1
65.55
MHz
DIVMODE(1:0) = 10
18.432
fAClock/2
65.55
MHz
18.432
fAClock/3
65.55
MHz
18.432
fAClock/4
65.55
MHz
Note
DIVMODE(1:0) = 00
fMasterOut
PCIClock frequency
tPCIClock
fTClock/4
fLClock
fTClock/8
32.78
MHz
PCICLKDIV(1:0) = 01
fTClock/4
32.78
MHz
Note
fTClock/2
32.78
MHz
Note
PCICLKDIV(1:0) = 11
fTClock/1
32.78
LCLKDIV(1:0) = 11
Note
fTClock/1
MHz
LCLKDIV(1:0) = 01
fTClock/2
MHz
LCLKDIV(1:0) = 10
fTClock/3
MHz
LCLKDIV(1:0) = 00
PClock frequency
fPClock
fTClock/4
MHz
18.432
fTClock/1
32.78
MHz
PCLKDIV(1:0) = 01
18.432
fTClock/2
32.78
MHz
18.432
fTClock/4
32.78
MHz
18.432
fTClock/8
32.78
MHz
fECU_SysClock ECUSYSCLKDIV(1:0) = 00
fTClock/1
32.78
MHz
ECUSYSCLKDIV(1:0) = 01
fTClock/2
32.78
MHz
ECUSYSCLKDIV(1:0) = 10
fTClock/4
32.78
MHz
ECUSYSCLKDIV(1:0) = 11
fTClock/8
32.78
MHz
Note
PCLKDIV(1:0) = 11
frequency
MHz
PCLKDIV(1:0) = 00
PCLKDIV(1:0) = 10
ECU_SysClock
MHz
PCICLKDIV(1:0) = 00
PCICLKDIV(1:0) = 10
LClock frequency
MHz
DIVMODE(1:0) = 11
DIVMODE(1:0) = 01
MasterOut frequency
Unit
CLKSEL(2:0) = 111
CLKSEL(2:0) = 000
TClock, SDCLK
MAX.
Note
Note These values cannot be set in the current VR4181A.
Remarks 1. The settings of the CLKSEL(2:0) and DIVMODE(1:0) signals are sampled when the RTCRST# signal
changes to high level.
2. PCICLKDIV(1:0): Bits 9 and 8 of the CLKDIVCTRL register in the CCU. Set these bits before
starting use of the on-chip peripheral PCI unit.
3. LCLKDIV(1:0): Bits 5 and 4 of the EXIBUCFG register in the EXIBU. Set these bits before setting
the timing parameters for each register of the EXIBU.
4. PCLKDIV(1:0): Bits 1 and 0 of the CLKDIVCTRL register in the CCU.
5. ECUSYSCLKDIV(1:0): Bits 5 and 4 of the CLKDIVCTRL register in the CCU. Set these bits before
starting use of the ECU.
Data Sheet U16277EJ1V0DS
45
µPD30181A, 30181AY
(2) Reset parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RTC reset input low-level width
tWRSL
Applies to RTCRST# signal
600
ms
RSTSW reset input low-level width
tWRSWL
Applies to RSTSW# signal
100
µs
Remark If the low-level width of reset input is the MIN. value or lower, a reset sequence may not be started.
RTCRST#
(input)
tWRSL
RSTSW#
(input)
tWRSWL
(3) Initial setting parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Setup time (to RTCRST#↑)
tSS
91.6
µs
Hold time (from RTCRST#↑)
tSH
–10
µs
RTCRST#
(input)
NWIREEN, BMODE(1:0),
DBUS32, CLKSEL(2:0),
MIPS16EN, DIVMODE(1:0)
(input)
Hi-Z
Normal operation
tSS
tSH
Remark The circles indicate the sampling timing.
46
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(4) SDRAM, SyncFlash interface (MCU) parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
65.55
MHz
SDCLK frequency
fSDCLK
SDCLK cycle
tSDCLK
15.26
ns
SDCLK high-level width
tSDCH
3.5
ns
SDCLK low-level width
tSDCL
3.5
ns
Output delay time (from SDCLK↑)
tSDDP
1.5
Data setup time
tSDS
6.2
ns
Data hold time
tSDH
2.9
ns
11.7
ns
tSDCLK
tSDCL
tSDCH
SDCLK
(output)
tSDDP
A(14:11), SA10, A(9:0)
(output)
CKE(1:0), SDCS(3:0)#,
DQM(3:0), RAS#,
CAS#, WE#
(output)
D(31:0)
(write)
D(31:0)
(read)
Hi-Z
Hi-Z
tSDS
tSDH
Remark The circles indicate the sampling timing.
Data Sheet U16277EJ1V0DS
47
µPD30181A, 30181AY
(5) ROM, flash memory, SRAM, ISA interface (EXIBU) parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
65.55
MHz
TClock frequency
fTClock
TClock cycle
tTClock
LClock frequency
fLClock
LClock cycle
tLClock
Output delay time
tEXD
0
Data input setup time
tEXS
5
ns
Data input hold time
tEXH
0
ns
15.26
ns
32.78
30.52
MHz
ns
12
10
ns
Data output float delay time
tEXZ
Data output setup time
tEXCL
0
ns
ns
IORDY input hold time
tEXRDYH
0
ns
IOCS16# input hold time
tEXCS16H
0
ns
DRQn# input inactive setup time
tDRQNEG
20
ns
(from command signal↓)
Remarks 1. n = 0, 1
2. TClock is generated by dividing AClock in accordance with the setting of the DIVMODE(1:0) signals
when the RTCRST# signal changes to high level.
After releasing the RTC reset, the division ratio of TClock can be changed by setting the
PMUDIVREG register.
3. LClock is generated by dividing Tclock in accordance with the setting of the LCLKDIV(1:0) bits of the
EXIBUCFG register in the EXIBU.
4. The MEMRD#, MEMWR#, IORD#, and IOWR# signals are called as command signals for the
external system bus interface.
48
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(a) Non-READY mode timing
CONSET+tEXD
CONWID+tEXD
CSOFF
+tEXD
BUSIDLE
+tEXD
A(24:0), UBE#
(output)
ROMCS#, PCS(4:0)#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
tEXD
tEXD
SYSEN#
(output)
SYSDIR
(output)
tTClock
+tEXD
D(31:0)
(read)
Note
Hi-Z
tTClock
+tEXD
Hi-Z
Input
Note
tEXZ
tEXS
tEXD
tEXH
tEXD
D(31:0)
(write)
tEXCL
Note Output
Remarks 1. CONSET, CONWID, CSOFF, and BUSIDLE are the timing parameters that can be changed by
setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles.
2. The circles indicate the sampling timing.
Data Sheet U16277EJ1V0DS
49
µPD30181A, 30181AY
(b) Page access timing (CONSET = 0, CSOFF = 0)
CONWID+tEXD
SUBCWID SUBCWID SUBCWID
+tEXD
+tEXD
+tEXD
A(24:0), UBE#
(output)
ROMCS#, PCS(4:0)#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
tEXD
tEXD
SYSEN#
(output)
SYSDIR
(output)
tTClock
+tEXD
D(31:0)
(read)
Output
Note
Note
Note
Note
tEXS tEXH
tEXS tEXH
tEXS tEXH
tEXS tEXH
tEXD
tEXD
tEXD
tEXD
tEXZ
D(31:0)
(write)
tEXD
Note Input
Remarks 1. CONWID and SUBCWID are the timing parameters that can be changed by setting registers of
the EXIBU. Each timing parameter is defined as the number of LClock cycles.
2. The circles indicate the sampling timing.
3. The broken lines indicate high impedance.
50
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(c) READY mode timing (RDYSYN = 1)
CONSET
+tEXD
RMINWID
+tEXD
CONOFF
+tEXD
CSOFF
+tEXD
BUSIDLE
+tEXD
A(24:0), UBE#
(output)
ROMCS#, PCS(4:0)#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
tEXD
tEXD
SYSEN#
(output)
SYSDIR
(output)
tTClock
+tEXD
tTClock
+tEXD
D(31:0)
(read)
Note
Hi-Z
Hi-Z
Input
Note
tEXZ
tEXS
tEXH
tEXD
tEXD
D(31:0)
(write)
tEXCL
IORDY
(input)
2tTClock+tLClock+tEXD
tEXRDYH
Note Output
Remarks 1. CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters that can be
changed by setting registers of the EXIBU. Each timing parameter is defined as the number of
LClock cycles.
2. The circles indicate the sampling timing.
Data Sheet U16277EJ1V0DS
51
µPD30181A, 30181AY
(d) External ISA bus space access (READY mode) timing (RDYSYN = 1)
IOCS16SET CONSET RMINWID CONOFF
+tEXD
+tEXD
+tEXD
+tEXD
CSOFF
+tEXD
BUSIDLE
+tEXD
A(24:0), UBE#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
tEXD
tEXD
tEXD
SYSEN#
(output)
SYSDIR
(output)
tTClock
+tEXD
D(15:0)
(read)
Note
Hi-Z
tTClock
+tEXD
Hi-Z
Input
Note
Hi-Z
tEXZ
tEXS
tEXH
tEXD
tEXD
D(15:0)
(write)
tEXCL
IORDY
(input)
2tTClock+tLClock+tEXD
tEXRDYH
IOCS16#
(input)
tLClock+tEXD
tEXCS16H
Note Output
Remarks 1. IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters
that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the
number of LClock cycles.
2. The circles indicate the sampling timing.
52
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(e) DMA transfer timing
CONSET+tEXD
CONWID+tEXD
CSOFF
+tEXD
BUSIDLE
+tEXD
A(24:0), UBE#
(output)
ROMCS#, PCS(4:0)#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
tEXD
tEXD
SYSEN#
(output)
SYSDIR
(output)
DRQn#
(input)
tDRQNEG
tTClock
+tEXD
tTClock
+tEXD
DAKn#
(output)
D(31:0)
(read)
Note
Hi-Z
Hi-Z
Input
Note
tEXZ
tEXS
tEXD
tEXH
tEXD
D(31:0)
(write)
tEXCL
Note Output
Remarks 1. CONSET, CONWID, CSOFF, and BUSIDLE are the timing parameters that can be changed by
setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles.
2. The circles indicate the sampling timing.
3. n = 0, 1
Data Sheet U16277EJ1V0DS
53
µPD30181A, 30181AY
(6) CompactFlash/PC Card/ATA (IDE) interface (ECU) parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
65.55
MHz
TClock frequency
fTClock
TClock cycle
tTClock
LClock frequency
fLClock
LClock cycle
tLClock
ECU_SysClock frequency
fECU_SysClock
ECU_SysClock cycle
tECU_SysClock
Output delay time (EXIBU)
tEXD
0
12
ns
Output delay time (ECU)
tECUD
0
TBD
ns
Data input setup time
tEXS
5
ns
Data input hold time
tEXH
0
ns
15.26
ns
32.78
30.52
MHz
ns
32.78
30.52
MHz
ns
Data output float delay time
tEXZ
Data output setup time
tEXCL
0
10
ns
ns
CF_WAIT# input hold time
tECURDYH
0
ns
CF0_IOIS16# input hold time
tECUCS16H
0
ns
(to command signal↓)
Remarks 1. TClock is generated by dividing AClock in accordance with the setting of the DIVMODE(1:0) signals
when the RTCRST# signal changes to high level. After releasing the RTC reset, the division ratio of
TClock can be changed by setting the PMUDIVREG register.
2. LClock is generated by dividing TClock in accordance with the setting of the LCLKDIV(1:0) bits of
the EXIBUCFG register in the EXIBU.
3. ECU_SysClock is generated by dividing TClock in accordance with the setting of the
ECUSYSCLKDIV(1:0) bits of the CLKDIVCTRL register in the CCU.
4. MEMRD#, MEMWR#, IORD#, and IOWR# signals are called as command signals for the external
system bus interface.
(a) Relationship between ECU bus cycle type and ECUWAIT
Bus Cycle
Number of Wait
ECUWAIT Value (ns)
Cycles
MIN.
16-bit I/O cycle (IOnWT = 1)
2
tECU_SysClock × 2
16-bit I/O cycle(IOnWT = 0)
3
tECU_SysClock × 3
8-bit I/O cycle (Wn_IOWS = 1)
4
tECU_SysClock × 4
8-bit I/O cycle (Wn_IOWS = 0)
5
tECU_SysClock × 5
16-bit memory cycle
0
(ZWSEN = 1 and M16W(1:0) = 0)
16-bit memory cycle
N+1
tECU_SysClock × (N + 1)
(ZWSEN = 0 and M16W(1:0) = N)
8-bit memory cycle (ZWSEN = 1)
0
0
8-bit memory cycle (ZWSEN = 0)
5
tECU_SysClock × 4
Remarks 1. IOnWT, Wn_IOWS, ZWSEN, and M16W(1:0) are bits of the register in the ECU.
2. n = 0, 1
54
Data Sheet U16277EJ1V0DS
MAX.
µPD30181A, 30181AY
(b) External ISA bus space access (READY mode) timing (RDYSYN = 1)
IOCS16SET CONSET RMINWID ECUWAIT
+tEXD
+tEXD
+tEXD
+tECUD
CONOFF
+tEXD
CSOFF
+tEXD
BUSIDLE
+tEXD
A(24:0), UBE#
(output)
tTClock
+tECUD
tTClock
+tECUD
CFn_CE(2:1)#,
CF_REG#
(output)
IORD#, IOWR#,
MEMRD#, MEMWR#
(output)
tEXD
tEXD
tEXD
SYSEN#
(output)
SYSDIR
(output)
tTClock
+tEXD
CFn_EN#
(output)
tTClock
+tECUD
tECUD
tECUD
tTClock
+tECUD
CFn_DIR
(output)
D(15:0)
(read)
Note
Hi-Z
tTClock
+tEXD
Hi-Z
Input
Note
Hi-Z
tEXZ
tEXS
tEXD
tEXH
tEXD
D(15:0)
(write)
tEXCL
CF_WAIT#
(input)
tTClock+tLClock+tECU_SysClock+tECUD
tECURDYH
CF0_IOIS16#
(input)
tLClock+tECUD
tECUCS16H
Note Output
Remarks 1. IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters
that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the
number of LClock cycles.
2. The circles indicate the sampling timing.
3. n = 0, 1
Data Sheet U16277EJ1V0DS
55
µPD30181A, 30181AY
(7) USB interface (USBHU, USBFU) parameters
Parameter
Symbol
Note 1
Rise time
Note 1
Fall time
Notes 1, 2
Vp-p output potential width
Conditions
MIN.
Fullspeed (12 Mbps) mode
4
20
ns
tR_LUSB
Low speed (1.5 Mbps) mode
75
300
ns
tF_FUSB
Fullspeed (12 Mbps) mode
4
20
ns
tF_LUSB
Low speed (1.5 Mbps) mode
75
300
ns
tRFM_FUSB
Fullspeed (12 Mbps) mode
90
111
%
tRFM_LUSB
Low speed (1.5 Mbps) mode
80
125
%
2. Indicated by the following expressions.
tRFM_FUSB = tR_FUSB/tF_FUSB
tRFM_LUSB = tR_LUSB/tF_LUSB
90%
90%
10%
10%
tR_FUSB
tR_LUSB
56
Unit
tR_FUSB
Notes 1. Precision tests have not been performed. Only guaranteed as design characteristics.
UHDP, UHDN
UDP, UDN
(I/O)
MAX.
Data Sheet U16277EJ1V0DS
tF_FUSB
tF_LUSB
µPD30181A, 30181AY
(8) AC97 interface (AC97U) parameters
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
BITCLK frequency
fBITCLK
12.288
MHz
BITCLK cycle
tBITCLK
81.4
ns
BITCLK high-level width
tBITCLKH
36
40.7
45
ns
BITCLK low-level width
tBITCLKL
36
40.7
45
ns
SYNC frequency
fSYNC
48
kHz
SYNC cycle
tSYNC
20.8
µs
SYNC high-level width
tSYNCH
1.3
µs
µs
SYNC low-level width
tSYNCL
SDATAIN input setup time
tSDATS
10
19.5
ns
tSDATH
10
ns
(to BITCLK↓)
SDATAIN input hold time
(to BITCLK↓)
SDATAOUT output delay time
tSDATD
25
ns
(to BITCLK↑)
tBITCLK
tBITCLKH
tBITCLKL
BITCLK
(input)
tSDATS
tSDATH
SDATAIN
(input)
tSDATD
tSDATD
SDATAOUT
(output)
tSYNC
tSYNCH
tSYNCL
SYNC
(output)
Data Sheet U16277EJ1V0DS
57
µPD30181A, 30181AY
2
(9) I S interface (I2SU) parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
6.114
MHz
SCLK frequency
fSCLK
SCLK cycle
tSCLK
SCLK high-/low-level width
tSCLKHL
SDI input setup time (to SCLK↑)
tSDIS
30
SDI input hold time (from SCLK↑)
tSDIH
30
SDO output delay time (from SCLK↓)
tSDOD
30
ns
WS delay time (from SCLK↓)
tWSD
30
ns
163
tSCLK/2 – 20 tSCLK/2 + 20
tSCLK
tSCLKHL
tSCLKHL
SCLK
(I/O)
tWSD
WS
(I/O)
tSDIS
tSDIH
SDI
(input)
tSDOD
tSDOD
SDO
(output)
58
ns
Data Sheet U16277EJ1V0DS
ns
ns
ns
µPD30181A, 30181AY
(10) Serial interface (SIU) parameters
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
N + 0.1
µs
TxD0, TxD1, TxD2 output pulse width
tTXD
N – 0.1
RxD0, RxD1, RxD2 input pulse width
tRXD
(9/16) × N
IRDOUT high-level output pulse width
tIRDOUT
(3/16) × N
(3/16) × N +
– 0.1
0.1
IRDIN input pulse width
tIRDIN
µs
1
µs
µs
Remark N is the data transfer cycle per bit determined by the divisor of the baud rate generator set in the
SIUDLL and SIUDLM registers.
Baud Rate
Divisor
(bps)
(DLM(7:0)||DLL(7:0))
N (µs)
50
23040
20000.00
75
15360
13333.33
110
10473
9090.91
134.5
8565
7434.94
150
7680
6666.67
300
3840
3333.33
600
1920
1666.67
1200
960
833.33
1800
640
555.56
2000
576
500.00
2400
480
416.67
3600
320
277.78
4800
240
208.33
7200
160
138.89
9600
120
104.17
19200
60
52.08
38400
30
26.04
57600
20
17.36
115200
10
8.68
128000
9
7.81
144000
8
6.94
192000
6
5.21
230400
5
4.34
288000
4
3.47
384000
3
2.60
576000
2
1.74
1152000
1
0.868
Remark Baud rate = (18.432 MHz/16)/(value set in the SIUDLM or SIUDLL register)
Data Sheet U16277EJ1V0DS
59
µPD30181A, 30181AY
TxDn
(output)
tTXD
RxDn
(input)
tRXD
IRDOUT
(output)
tIRDOUT
IRDIN
(input)
tIRDIN
Remark n = 0 to 2
60
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(11) I C bus interface (I2CU) parameters (µPD30181AY only)
2
Parameter
Symbol
Condition
Normal Mode
High-Speed Mode
MIN.
MAX.
MIN.
MAX.
0
100
0
400
Unit
SCLn frequency
fSCL
Start condition hold time
tHD:STA
4.0
0.6
µs
SCLn low-level width
tLOW
4.7
1.3
µs
SCLn high-level width
tHIGH
4.0
0.6
µs
Rise time
tRC
1.0
0.3
µs
Fall time
tFC
0.3
0.3
µs
Data setup time
tSU:DAT
0.25
0.1
µs
Data retention time
tHD:DAT
0
0
µs
Repeat start setup time
tSU:STA
4.7
0.6
µs
Stop condition setup time
tSU:STO
4.0
0.6
µs
Bus release time
tBUF
4.7
1.3
µs
tFC
tRC
kHz
tSU:STA
SDAn
(I/O)
tSU:STO
tHD:STA
tRC
tBUF
tFC
SCLn
(I/O)
tLOW
tHIGH
tSU:DAT
tHD:DAT
Remark n = 0, 1
Data Sheet U16277EJ1V0DS
61
µPD30181A, 30181AY
(12) Clocked serial interface (CSI) parameters
Parameter
Symbol
SCK frequency
fSCK
SCK cycle
tSCK
SCK high-/low-level width
tSCKHL
Note
SI input setup time (to SCK edge
)
Note
SI input hold time (from SCK edge
SO output delay time (from SCK
)
Condition
MIN.
MAX.
Unit
4.608
MHz
217
tSCK/2 − 20
ns
tSCK/2 + 20
ns
tSIS
50
ns
tSIH
50
ns
tSOD
50
ns
Note
edge
)
Note The SCK edge used differs depending on the settings of the CKMD and CKPOL bits of the CSIMODE
register.
tSCK
tSCKHL
tSCKHL
SCK
(I/O)
tSIS
tSIH
SI
(input)
tSOD
SO
(output)
Remark This diagram shows the timing when using the SCK rising edge (CKMD = 0 and CKPOL = 0,
or CKMD = 1 and CKPOL = 1).
62
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(13) LCD interface (LCU) parameters
Parameter
Symbol
DCLK/SHCLK frequency
fDCLK
DCLK/SHCLK cycle
tDCLK
DCLK/SHCLK high-/low-level width
tDCLKHL
Output delay time
tLCDD
Note
(from DCLK/SHCLK edge
)
Condition
MIN.
MAX.
Unit
32.775
MHz
30
tDCLK/2 − 5
Applies to HSYNC/LOCLK,
ns
tDCLK/2 + 5
ns
30
ns
VSYNC/FLM, ENAB/M, and FPD(15:
0) signals
Note The DCLK/SHCLK edge used differs depending on the setting of the SCLKPOL bit of the LCDCTRLREG
register.
tDCLK
tDCLKHL
tDCLKHL
DCLK/SHCLK
(output)
tLCDD
HSYNC/LOCLK,
VSYNC/FLM,
ENAB/M,
FPD(15:0)
(output)
Remark This diagram shows the timing when using the DCLK/SHCLK rising edge (SCLKPOL = 1).
Data Sheet U16277EJ1V0DS
63
µPD30181A, 30181AY
(14) GPIO interface (GIU) parameters
Parameter
GPIO input level width
Symbol
tGPIN1
Condition
MIN.
MAX.
Unit
100
µs
(tTClock × 4)
ns
Restoring from Hibernate mode when
level trigger is selected.
tGPIN2
Interrupt input when level trigger is
×3
selected.
Note
GPIO input rise time
Note
GPIO input fall time
tGPINR
GPIO(61:40) pins
10
ns
tGPINR2
GPIO pins other than above
200
ns
tGPINF
GPIO(61:40) pins
10
ns
tGPINF2
GPIO pins other than above
200
ns
Note Precision tests have not been performed. Only guaranteed as design characteristics.
(a) GPIO input level width
tGPIN1, tGPIN2
GPIOn
(input)
Remark n = 0 to 61
(b) GPIO input rise/fall time
tGPINF,
tGPINF2
tGPINR,
tGPINR2
GPIOn
(input)
Remark n = 0 to 61
64
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
(15) NMI parameters
Parameter
NMI# input low-level width
Symbol
Condition
tNMI
MIN.
100
MAX.
Unit
µs
NMI#
(input)
tNMI
Data Sheet U16277EJ1V0DS
65
µPD30181A, 30181AY
A/D Converter Characteristics (TA = –40 to +85°°C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V)
Parameter
Symbol
Notes 1, 2
Zero-scale error
Notes 1, 2
Full-scale error
Notes 1, 2
Integral linearity error
Notes 1, 2
Differential linearity error
Note 1
Analog input voltage
Condition
MIN.
Note 1
MAX.
Unit
ZSE
±4.0
LSB
RSE
±5.0
LSB
INL
±3.0
LSB
DNL
±3.0
LSB
−0.3
VIAN
Analog input equivalent resistance
TYP.
VDDAD + 0.3
V
RAIN
1.53
kΩ
Analog input equivalent capacitance
CAIN
6.5
pF
Analog signal source allowable output
REXOUT
Note 1
Note 1
3.5
When pin input
capacitance CI = 3 pF
impedance
Notes 1. Applies to TPX(1:0), TPY(1:0), and AIN(3:0) pins.
2. Excluding quantization error.
Remark LSB:
Least significant bit
VDDAD: Voltage supplied to VDDAD pin
A/D converter input equivalent circuit
VR4181A
REXOUT
AINn
RAIN
CI
Remark n = 0 to 3
66
Data Sheet U16277EJ1V0DS
CAIN
kΩ
µPD30181A, 30181AY
D/A Converter Characteristics (TA = –40 to +85°°C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
INL
±3.0
LSB
Differential linearity error
DNL
±3.0
LSB
String unit resistor
RST
4
Ω
String output equivalent resistor
RSTOUT
1110
Ω
Notes 1, 2
Integral linearity error
Notes 1, 2
Notes 1. Applies to AOUT pin.
2. Excluding quantization error.
Remark LSB: Least significant bit
Cautions 1. The output impedance of the D/A converter is too large to latch the current from AOUT pin. If
the load input impedance is small, insert a buffer amplifier between the load and the AOUT
pin. Make the wiring between the buffer amplifier and load as short as possible.
If the wiring is long, processing is required such as enclosing the wiring in a with ground
pattern.
2. The output voltage of the D/A converter changes in steps, so use the output signal from the
D/A converter after passing it through a low pass filter.
D/A converter output equivalent circuit
VR4181A
VDDAD
1/2 RST
1023
RST
Series
resistor
string
Tap
selector
RSTOUT
AOUT
0
1/2 RST
GNDAD
Remark The series resistor string is connected between the reference voltage for the A/D converter (VDDAD)
and GND (GNDAD) for the A/D converter. To make the 1024 equivalent voltage steps between the
two pins, this circuit consists of 1023 equivalent unit resistors (RST) and two resistors with a
resistance of half RST. The equivalent output impedance of the AOUT pin is the value calculated by
adding RSTOUT to the total RST value corresponding to the selected voltage step.
Data Sheet U16277EJ1V0DS
67
µPD30181A, 30181AY
3. PACKAGE DRAWING
240-PIN PLASTIC FBGA (16x16)
E
w S B
ZD
ZE
B
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
D
V U T R P NM L K J HG F E D C B A
INDEX MARK
w S A
(UNIT:mm)
A
y1
A2
S
S
y
e
S
φb
φx
A1
M
S AB
ITEM
D
DIMENSIONS
16.00±0.10
E
16.00±0.10
w
0.20
A
1.48±0.10
A1
0.35±0.06
A2
1.13
e
0.80
b
0.50 +0.05
–0.10
x
0.08
y
0.10
y1
0.20
ZD
1.20
ZE
68
Data Sheet U16277EJ1V0DS
1.20
P240F1-80-GA3
µPD30181A, 30181AY
4. RECOMMENDED SOLDERING CONDITIONS
The µPD30181A and 30181AY should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales
representative.
Table 4-1. Soldering Conditions for Surface-Mount Type
(a) µPD30181AF1-131-GA3: 240-pin plastic FBGA (16 × 16)
µPD30181AYF1-131-GA3: 240-pin plastic FBGA (16 × 16)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds or less (210°C or higher),
Count: two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
20 hours)
Symbol
IR35-203-2
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
(b) µPD30181AF1-131-GA3-A
: 240-pin plastic FBGA (16 × 16)
Note
µPD30181AYF1-131-GA3-A
: 240-pin plastic FBGA (16 × 16)
Note
For soldering methods and conditions, contact an NEC sales representative.
Note Lead-free product
Data Sheet U16277EJ1V0DS
69
µPD30181A, 30181AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
2
2
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these
2
2
components in an I C system, provided that the system conforms to the I C Standard Specification as
defined by Philips.
Reference document
Electrical Characteristics for Microcomputer (U15170J)
Note
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.
EEPROM, VR4120, VR4181A, VR Series, and VR4100 Series are trademarks of NEC Corporation.
MIPS is a registered trademark of MIPS Technologies, Inc. in the United States.
SyncFlash is a trademark of Micron Technology, Inc.
Bluetooth is a trademark of Bluetooth SIG, Inc.
70
Data Sheet U16277EJ1V0DS
µPD30181A, 30181AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
NEC Electronics Hong Kong Ltd.
• Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
NEC Electronics (Europe) GmbH Fax: 08-63 80 388
Duesseldorf, Germany
• United Kingdom Branch
Tel: 0211-65 03 01
Milton Keynes, UK
Fax: 0211-65 03 327
Tel: 01908-691-133
Fax: 01908-670-290
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Fax: 091-504 28 60
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
J02.4
Data Sheet U16277EJ1V0DS
71
µ
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
• The information in this document is current as of July, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
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• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
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Customers must check the quality grade of each semiconductor product before using it in a particular
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4