High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit GENERAL DESCRIPTION The WS628128 is a high performance; high speed and super low power CMOS Static Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of 4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide high speed, super low power features and maximum access time of 55/ 70ns in 5.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1, CE2) and active LOW output enable (/OE). The WS628128 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The WS628128 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) , SOP (450 mil) and PDIP (600 mil) packages. FEATURES Wide operation voltage: 4.5~5.5V Ultra low power consumption : 2mA＠1MHz (Max.) , Vcc=5.0V. 1.5 uA (Typ.) CMOS standby current High speed access time: 55/70ns. Automatic power down when chip is deselected. Three state outputs and TTL compatible. Data retention supplies voltage as low as 2.0V. Easy expansion with (/CE1, CE2) and /OE options. Product Family Part No. Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type 32 SOP 32 STSOP 0~70oC 70 1.5uA (Vcc = 5.0V) 32 TSOP 32 TSOP (II) 32 PDIP WS628128 4.5~5.5 32 SOP 32 STSOP -40~85oC 70 2uA (Vcc= 5.0V) 32 TSOP 32 TSOP (II) 32 PDIP 1 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM 128K-Word By 8 Bit WS628128 PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM 2 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit PIN DESCRIPTIONS Type Function Input Address inputs for selecting one of the 131,072 x 8 bit words in the RAM Name A0 – A16 /CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is /CE1, CE2 Input not active, the device is deselected and in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write /WE Input operations. With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active /OE Input while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. These 8 bi-directional ports are used to read data from or write data into DQ0~DQ7 I/O Vcc Power Power Supply Gnd Power Ground the RAM. No connection NC TRUTH TABLE MODE /CE1 CE2 /WE /OE H X X X X L X X Output Disable L H H Read L H Write L H Standby DQ0~7 Vcc Current High Z ICCSB, ICCSB1 H High Z ICC H L DOUT ICC L X DIN ICC 3 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter VTERM Rating Terminal Voltage with Respect to GND TBIAS Unit -0.5 to Vcc+0.5 Temperature Under Bias V -40 to +125 O -60 to +150 O C TSTG Storage Temperature PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA C 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Ambient Temperature o Vcc Commercial 0~70 C 4.5~5.5V Industrial -40~85oC 4.5~5.5V 1. Overshoot: Vcc +2.0V in case of pulse width ≦20ns. 2. Undershoot: - 2.0V in case of pulse width ≦20ns. 3. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. 4 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit DC ELECTRICAL CHARACTERISTICS Name VIL VIH IIL Parameter Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current o o (TA = 0 ~70 C, Vcc = 5.0V) Test Condition MIN TYP(1) MAX Unit Vcc=5.0V -0.5 0.8 V Vcc=5.0V 2.2 Vcc+0.5 V VCC=MAX, VIN=0 to VCC -1 1 uA -1 1 uA 0.4 V VCC=MAX, /CE1=VIh, or IOL Output Leakage Current CE2= VIL, or /OE=VIh, or /WE= VIL VIO=0V to VCC VOL Output Low Voltage VCC=MAX, IOL =2.1mA VOH Output High Voltage VCC=MIN, IOH = -1.0mA Operating Power Supply /CE1=VIL, IDQ=0mA, Current F=FMAX =1/ tRC ICCSB TTL Standby Supply /CE1=VIH, IDQ=0mA, ICCSB1 CMOS Standby Current ICC /CE1≧VCC-0.2V, CE2= 0.2V, VIN≧VCC-0.2V or VIN≦0.2V, 2.4 V 1.5 30 mA 1.0 mA 10 uA o 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. 5 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit DATA RETENTION CHARACTERISTICS (TA = 0o ~70oC, Vcc =5.0V) Name VDR ICCDR TCDR tR Parameter Test Condition VCC for Data Retention /CE1≧VCC-0.2V, VIN≧VCC-0.2V or VIN≦0.2V MIN Operation Recovery Unit V 0.5 VIN≦0.2V Retention Time MAX 2.0 Data Retention Current VCC=2.0V, /CE1≧VCC-0.2V, VIN≧VCC-0.2V or Chip Deselect to Data TYP(1) 5 uA 0 ns tRC (2) ns Refer to Retention Waveform Time o 1.TA = 25 C 2. tRC= .Read Cycle Time LOW Vcc DATA RETENTION WAVEFORM (1) (/CE1 Controlled) VC C CE1 tCDR D a ta R e te n tio n M o d e V D R > 2 .0 V C E 1 > V C C - 0 .2 V VI H tR VI H 6 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit LOW Vcc DATA RETENTION WAVEFORM (2) (CE2 Controlled) VC C t CDR D ata R eten tio n M o d e VD R > 2 .0 V C E 2 < 0 .2 v VIL CE2 AC TEST CONDITIONS Input Pulse Levels Vcc/0V Input Rise and Fall Times Input and Output Timing Reference Level Output Load tR VIL KEY TO SWITCHING WAVEFORMS WAVEFORMS 5ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY 0.5Vcc See FIGURE 1A MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON’T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE and 1B 7 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit AC TEST LOADS AND WAVEFORMS FIGURE 1A FIGURE 1B AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oC；Vcc=5.0V ) < READ CYCLE > JEDEC Name Symbol tAVAX tRC Read Cycle Time tAVQV tAA Address Access Time 55 70 ns tELQV tACE Chip Select Access Time 55 70 ns tGLQV tOE Output Enable to Output Valid 25 35 ns tELQX tCLZ(5) Chip Select to Output Low Z 10 10 ns tGLQX tOLZ(5) Output Enable to Output in Low Z 5 5 ns tEHQZ tCHZ(5) Chip Deselect to Output in High Z 0 20 0 25 ns tGHQZ tOHZ(5) Output Disable to Output in High Z 0 20 0 25 ns tAXOX tOH Address Change to Out Disable 10 Description -55 MIN -70 MAX 55 MIN Unit MAX 70 ns 10 8 WS reserves the right to change product or specification without notice. ns Rev. 1.0 High Speed Super Low Power SRAM 128K-Word By 8 Bit WS628128 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 [1,2,4] READ CYCLE 2 [1,3,4] READ CYCLE 3 [1,4] 9 Rev. 1. 0 WS reserves the right to change product or specification without notice. High Speed Super Low Power SRAM WS628128 128K-Word By 8 Bit NOTES: 1. /WE is high in read Cycle. 2. Device is continuously selected when /CE1 = VIL and CE2=VIH. 3. Address valid prior to or coincident with /CE1 transition low and /or CE2 transition high. 4. /OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. AC ELECTRICAL CHARACTERISTICS (TA = 0o ~70oC；Vcc=5.0V ) < WRITE CYCLE > JEDEC Name Symbol Description -55 -70 MIN MAX MIN MAX Unit tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 45 60 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 45 60 ns tWLWH tWP Write Pulse Width 40 50 ns tWHAX tWR Write Recovery Time 0 0 ns tWLQZ tWHZ(10) tDVWH tDW Data to Write Time Overlap 25 30 ns tWHDX tDH Data Hold for Write End 0 0 ns tGHQZ tOHZ(10) Output Disable to Output in 0 Write to Output in High Z 20 30 20 0 30 ns ns High Z tWHOX tOW(10) End of Write to Output Active 5 5 ns 10 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM 128K-Word By 8 Bit WS628128 SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (Write Enable Controlled) WRITE CYCLE2 (Chip Enable Controlled) 11 WS reserves the right to change product or specification without notice. Rev. 1.0 High Speed Super Low Power SRAM 128K-Word By 8 Bit WS628128 NOTES: 1. TAS is measured from the address valid to the beginning of write. 2. The internal write time of the memory is defined by the overlap of /CE1 and CE2 active and /WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of /CE1 or /WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the /CE1 low transition or CE2 high transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state. 6. /OE is continuously low (/OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If /CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of /CE1 going low or CE2 going high to the end of write. 12 WS reserves the right to change product or specification without notice. Rev. 1.0 WS628128 13 WS WS628128 14 WS WS628128 15 WS WS628128 16 WS WS628128 17 WS