JN5169
IEEE802.15.4 Wireless Microcontroller
Rev. 1 — 5 August 2015
Product data sheet
1. General description
The JN5169 is an ultra low power, high performance wireless microcontroller suitable for
ZigBee applications. It features 512 kB embedded Flash, 32 kB RAM and 4 kB EEPROM
memory, allowing OTA upgrade capability without external memory. The 32-bit RISC
processor offers high coding efficiency through variable width instructions, a multi-stage
instruction pipeline and low-power operation with programmable clock speeds. It also
includes a 2.4 GHz IEEE802.15.4 compliant transceiver and a comprehensive mix of
analog and digital peripherals. The best in class RX operating current (down to 13 mA and
with a 0.7 A sleep timer mode) gives excellent battery life allowing operation direct from
a coin cell.
The peripherals support a wide range of applications. They include a 2-wire compatible
I2C-bus and SPI-bus which can operate as either master or slave, a 6-channel ADC with a
battery monitor and a temperature sensor. It can support a large switch matrix of up to 100
elements, or alternatively a 40-key capacitive touch pad.
2. Features and benefits
2.1 Benefits
Single chip device to run stack and application
Very low current solution for long battery life; over 10 years
Very low RX current for low standby power of mains powered nodes
Integrated power amplifier for long range and robust communication
High tolerance to interference from other 2.4 GHz radio sources
Supports multiple network stacks
Highly featured 32-bit RISC CPU for high performance and low power
Large embedded Flash memory to enable over-the-air firmware updates without
external Flash memory
System BOM is low in component count and cost
Flexible sensor interfacing options
Very thin quad flat 6 6 mm, 40 terminal package; lead-free and RoHS compliant
Temperature range: 40 C to +125 C
2.2 Features: radio
2.4 GHz IEEE802.15.4 compliant
RX current 14.7 mA, in low power receive mode 13 mA
Receiver sensitivity 96 dBm
Configurable transmit power, for example:
JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
10 dBm, 23.3 mA
8.5 dBm, 19.6 mA
3 dBm, 14 mA
Radio link budget 106 dB
Maximum input level of +10 dBm
Compensation for temperature drift of crystal oscillator frequency
128-bit AES security processor
MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers
Integrated ultra low-power RC sleep oscillator (0.7 A)
2.0 V to 3.6 V battery operation
Deep sleep current 50 nA (wake-up from IO)
< 0.15 $ external component cost
Antenna diversity (Auto RX)
2.3 Features: microcontroller
32-bit RISC CPU; 1 MHz to 32 MHz clock speed
Variable instruction width for high coding efficiency
Multi-stage instruction pipeline
512 kB Flash
32 kB RAM
4 kB EEPROM
Data EEPROM with guaranteed 100 k write operations
ZigBee PRO stack with Home Automation, Light Link and Smart Energy profiles
2-wire I2C-bus compatible serial interface; can operate as either master or slave
5 PWM (4 timers, 1 timer/counter)
2 low-power sleep counters
2 UARTs
SPI-bus master and slave port, 3 selects
Supply voltage monitor with 8 programmable thresholds
6-input 10-bit ADC, comparator
Battery and temperature sensors
Watchdog and Supply Voltage Monitor (SVM)
Up to 20 Digital IO (DIO) pins
3. Applications
JN5169
Product data sheet
Robust and secure low-power wireless applications
ZigBee Smart Energy networks
ZigBee Light Link networks
ZigBee Home Automation networks
Toys and gaming peripherals
Energy harvesting - for example, self-powered light switch
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 92
JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
4. Overview
The JN5169 wireless microcontroller that provides a fully integrated solution for
applications that use the IEEE802.15.4 standard in the 2.4 GHz to 2.5 GHz ISM frequency
band, including ZigBee PRO applications based on the Smart Energy, Light Link and
Home Automation profiles.
The JN5169 features 512 kB embedded Flash, 32 kB RAM and 4 kB EEPROM memory
and radio outputs up to 10 dBm.
Applications that transfer data wirelessly tend to be more complex than applications for
wired solutions. Wireless protocols make stringent demands on frequencies, data formats,
timing of data transfers, security and other issues. Application development must consider
the requirements of the wireless network in addition to the product functionality and user
interfaces. To minimize this complexity, NXP provides a series of software libraries and
interfaces that control the transceiver and peripherals of the JN5169. These libraries and
interfaces remove the need for the developer to understand wireless protocols and greatly
simplifies the programming complexities of power modes, interrupts and hardware
functionality.
In view of the above, we do not provide the JN5169 register details in this data sheet.
The device includes a wireless transceiver, RISC CPU, on-chip memory and an extensive
range of peripherals.
4.1 Wireless transceiver
The wireless transceiver comprises a 2.45 GHz radio, a modem, a baseband controller
and a security coprocessor. In addition, the radio also provides an output to control
transmit-receive switching of external devices such as power amplifiers allowing
applications that require increased transmit power to be realized very easily. Section 15.1
describes a complete reference design including Printed-Circuit Board (PCB) design and
Bill Of Materials (BOM).
The security coprocessor provides hardware-based 128-bit AES-CCM modes as
specified by the IEEE802.15.4 2006 standard. Specifically this includes encryption and
authentication covered by the MIC-32/-64/-128, ENC and ENC-MIC-32/-64/-128 modes of
operation.
The transceiver elements (radio, modem and baseband) work together to provide
IEEE802.15.4 (2006) MAC and PHY functionality under the control of a protocol stack.
Applications incorporating IEEE802.15.4 functionality can be developed rapidly by
combining user-developed application software with a protocol stack library.
4.2 RISC CPU and memory
A 32-bit RISC CPU allows software to be run on-chip, its processing power being shared
between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user
application. The JN5169 has a unified memory architecture. Code memory, data memory,
peripheral devices and I/O ports are organized within the same linear address space. The
device contains up to 512 kB of Flash, 32 kB of RAM and 4 kB EEPROM.
JN5169
Product data sheet
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Rev. 1 — 5 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 92
JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
4.3 Peripherals
The following peripherals are available on chip:
• Master SPI-bus port with 3 select outputs
• Slave SPI-bus port
• 2 UARTs: one capable of hardware flow control (4-wire, includes RTS/CTS); the other
just 2-wire (RX/TX)
• 1 programmable timer/counter which supports Pulse Width Modulation (PWM) and
capture/compare, plus 4 PWM timers which support PWM and Timer modes only
• 2 programmable sleep timers and 1 tick timer
• 2-wire serial interface (compatible with SMbus and I2C-bus) supporting master and
slave operation
•
•
•
•
•
•
•
•
•
•
20 digital I/O lines (multiplexed with peripherals such as timers, SPI-bus and UARTs)
2 digital outputs (multiplexed with SPI-bus port)
10-bit, Analog-to-Digital Converter (ADC) with up to 6 input channels
Programmable analog comparator
Internal temperature sensor and battery monitor
2 low-power pulse counters
Random number generator
Watchdog timer and Supply Voltage Monitor
JTAG hardware debug port
Transmit and receive antenna diversity with automatic receive switching based on
received energy detection
User applications access the peripherals using the JN516x Integrated Peripherals API
(Application Programming Interface). This allows applications to use a tested and easily
understood view of the peripherals facilitating rapid system development.
5. Ordering information
Table 1.
Ordering information
Type number
JN5169
JN5169
Product data sheet
Package
Name
Description
Version
HVQFN40
Plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 6 0.85 mm
SOT618-8
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Rev. 1 — 5 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 92
JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
6. Block diagram
WATCHDOG
TIMER
2.4 GHz
RADIO
INCLUDING
DIVERSITY
VOLTAGE
BROWNOUT
FLASH
512 kB
RAM
32 kB
2-WIRE SERIAL
(MASTER/SLAVE)
32-BIT
RISC CPU
O-QPSK
MODEM
4 X PWM
PLUS TIMER
2 X UART
4 kB
EEPROM
XTAL
SPI-BUS
MASTER AND SLAVE
IEEE802.15.4
MAC
ACCELERATOR
20 DIO
PLUS 2 DO
SLEEP COUNTER
6 CHAN
10 BIT ADC
POWER
MANAGEMENT
128-BIT AES
ENCRYPTION
ACCELERATOR
BATTERY AND
TEMP SENSORS
aaa-013126
Fig 1.
Block diagram
JN5169
Product data sheet
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Rev. 1 — 5 August 2015
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JN5169
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IEEE802.15.4 Wireless Microcontroller
7. Functional diagram
SPI-BUS
SLAVE
TICK TIMER
PROGRAMMABLE
INTERRUPT
CONTROLLER
32-BIT RISC CPU
FLASH
512 kB
EEPROM
4 kB
UART0
UART1
1.8 V
TIMER0
XTAL_IN
XTAL_OUT
32 MHz XTAL
CLOCK
GENERATOR
CLOCK
SOURCE
AND
RATE
SELECT
HIGHSPEED
RC
OSC
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
DIO8
TXD1
RXD1
VB_XX(1)
VOLTAGE
REGULATORS
DIO1
TXD0
RXD0
RTS0
CTS0
CPU and 16 MHz
system clock
VDD
DIO0
SPICLK
SPIMOSI
SPIMISO
SPISEL0
SPISEL1
SPISEL2
SPI-BUS
MASTER
from peripherals
RAM
32 kB
SPISCLK
SPISMOSI
SPISMISO
SPISSEL
DIO9
TIM0CK_GT
TIM0OUT MUX
TIM0CAP
PWM1
PWM2
PWM3
PWM4
PWMs
DIO10
DIO11
DIO12
DIO13
DIO14
RESET_N
RESET
WATCHDOG
TIMER
WAKEUP
TIMER0
VOLTAGE
REGULATORS
WAKEUP
TIMER1
32 kHz
RC
OSC
32 kHz
XTAL
OSC
DIO15
DIO16
PC0
PC1
PULSE
COUNTERS
DIO17
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
32KIN
ANTENNA
DIVERSITY
DIO18
DIO19
DO0
ADO
ADE
DO1
32KXTALIN
32KXTALOUT
WIRELESS
TRANSCEIVER
SECURITY
PROCESSOR
SUPPLY
MONITOR
ADC1
VREF/ADC2
ADC3
ADC4
ADC5
ADC6
2-WIRE
INTERFACE
JTAG
DEBUG
32 kHz CLOCK
SELECT
SIF_D
SIF_CLK
DIGITAL
BASEBAND
MUX
ADC
RF_IO
RADIO
IBIAS
TEMPERATURE
SENSOR
COMP1M
COMP1P
COMPARATOR1
aaa-013127
(1) With XX = SYNTH or VCO or RF2 or RF1 or DIG.
Fig 2.
Functional block diagram
JN5169
Product data sheet
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Rev. 1 — 5 August 2015
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6 of 92
JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
8. Pinning information
31 DIO8/TIM0CK_GT/PC1/PWM4
32 DIO9/TIM0CAP/32KXTALIN/RXD1/32KIN
33 DIO10/TIM0OUT/32KXTALOUT
34 DIO11/PWM1/TXD1
35 VB_DIG
36 DIO12(1)
37 DIO13(2)
38 DIO14(3)
terminal 1
index area
39 VSS
40 DIO15(4)
8.1 Pinning
DIO16/SPISMOSI/SIF_CLK/COMP1P 1
30 VDDD
DIO17/SPISMISO/SIF_D/COMP1M/PWM4 2
29 DIO7/RXD0/JTAG_TDI/PWM3
RESET_N 3
28 DIO6/TXD0/JTAG_TDO/PWM2
XTAL_OUT 4
27 DIO5/RTS0/JTAG_TMS/PWM1/PC1
XTAL_IN 5
26 DIO4/CTS0/JTAG_TCK/TIM0OUT/PC0
JN5169
VB_SYNTH 6
25 i.c.
i.c. 7
24 DIO19/SPISEL0
VB_VCO 8
23 DIO18/SPIMOSI
DO0/SPICLK/PWM2 20
DIO3/RFTX/TIM0CAP/ADC6 19
DIO2/RFRX/TIM0CK_GT/ADC5 18
DIO0/ADO/SPISEL1/ADC3 16
DIO1/ADE/SPISEL2/ADC4/PC0 17
ADC1 15
VB_RF1 14
21 VSS
RF_IO 13
IBIAS 10
VB_RF2 12
22 DO1/SPIMISO/PWM3
VREF/ADC2 11
VDDA 9
aaa-013128
Transparent top view
Refer to Section 15 for important applications information regarding the connection of the paddle to the PCB.
(1) Multi-function: DIO12/PWM2/CTS0/JTAG_TCK/ADO/SPISMOSI.
(2) Multi-function: DIO13/PWM3/RTS0/JTAG_TMS/ADE/SPISMISO.
(3) Multi-function: DIO14/SIF_CLK/TXD0/TXD1/JTAG_TDO/SPISEL1/SPISSEL.
(4) Multi-function: DIO15/SIF_D/RXD0/RXD1/JTAG_TDI/SPISEL2/SPISCLK.
Fig 3.
Pin configuration
JN5169
Product data sheet
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Rev. 1 — 5 August 2015
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JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
8.2 Pin description
Table 2.
Pin description
Symbol
Pin Type[1]
Description
DIO16/SPISMOSI/SIF_CLK/COMP1P
1
DIO16 — DIO16
I/O
COMP1P — comparator plus input
SIF_CLK — Serial Interface clock
SPISMOSI — SPI-bus slave Master Out Slave In input
DIO17/SPISMISO/SIF_D/COMP1M/PWM4
2
I/O
DIO17 — DIO17
COMP1M — comparator minus input
SIF_D — Serial Interface Data
SPISMISO — SPI-bus slave Master In Slave Out output
PWM4 — PWM 4 output
RESET_N
3
I
RESET_N — reset input
XTAL_OUT
4
O
XTAL_OUT — system crystal oscillator
XTAL_IN
5
I
XTAL_IN — system crystal oscillator
VB_SYNTH
6
P
VB_SYNTH — regulated supply voltage
i.c.
7
-
internally connected; leave open
VB_VCO
8
P
VB_VCO — regulated supply voltage
VDDA
9
P
VDDA — analog supply voltage
IBIAS
10
I
IBIAS — bias current control
VREF/ADC2
11
P
VREF — analog peripheral reference voltage
I
ADC2 — ADC input 2
VB_RF2
12
P
VB_RF2 — regulated supply voltage
RF_IO
13
I/O
RF_IO — RF antenna
VB_RF1
14
P
VB_RF1 — regulated supply voltage
ADC1
15
I
ADC1 — ADC input
DIO0/ADO/SPISEL1/ADC3
16
I/O
DIO0 — DIO0
ADO — antenna diversity odd output
SPISEL1 — SPI-bus master select output 1
ADC3 — ADC input: ADC3
DIO1/ADE/SPISEL2/ADC4/PC0
17
I/O
DIO1 — DIO1
ADE — antenna diversity even output
SPISEL2 — SPI-bus master select output 2
ADC4 — ADC input: ADC4
PC0 — pulse counter 0 input
DIO2/RFRX/TIM0CK_GT/ADC5
18
I/O
DIO2 — DIO2
RFRX — radio receiver control output
TIM0CK_GT — timer0 clock/gate input
ADC5 — ADC input: ADC5
JN5169
Product data sheet
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Rev. 1 — 5 August 2015
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JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
Table 2.
Pin description …continued
Symbol
Pin Type[1]
Description
DIO3/RFTX/TIM0CAP/ADC6
19
DIO3 — DIO3
I/O
RFTX — radio transmitter control output
TIM0CAP — timer0 capture input
ADC6 — ADC input: ADC6
DO0/SPICLK/PWM2[2]
20
O
DO0 — DO0
SPICLK — SPI-bus master clock output
PWM2 — PWM2 output
VSS
21
GND
VSS — ground
DO1/SPIMISO/PWM3[3]
22
I/O
DO1 — DO1
SPIMISO — SPI-bus Master In, Slave Out input
PWM3 — PWM3 output
DIO18/SPIMOSI
23
I/O
DIO18 — DIO18
SPIMOSI — SPI-bus Master Out Slave In output
DIO19/SPISEL0
24
I/O
DIO19 — DIO19
SPISEL0 — SPI-bus master Select Output 0
i.c.
25
-
internally connected; leave open
DIO4/CTS0/JTAG_TCK/TIM0OUT/PC0
26
I/O
DIO4 — DIO4
CTS0 — UART 0 clear to send input
JTAG_TCK — JTAG CLK input
TIM0OUT — timer0 PWM output
PC0 — pulse counter 0 input
DIO5/RTS0/JTAG_TMS/PWM1/PC1
27
I/O
DIO5 — DIO5
RTS0 — UART 0 request to send output
JTAG_TMS — JTAG mode select input
PWM1 — PWM1 output
PC1 — pulse counter 1 input
DIO6/TXD0/JTAG_TDO/PWM2
28
I/O
DIO6 — DIO6
TXD0 — UART 0 transmit data output
JTAG_TDO — JTAG data output
PWM2 — PWM2 data output
DIO7/RXD0/JTAG_TDI/PWM3
29
I/O
DIO7 — DIO7
RXD0 — UART 0 receive data input
JTAG_TDI — JTAG data input
PWM3 — PWM 3 data output
VDDD
30
P
VDDD — digital supply voltage
DIO8/TIM0CK_GT/PC1/PWM4
31
I/O
DIO8 — DIO8
TIM0CK_GT — timer0 clock/gate input
PC1 — pulse counter1 input
PWM4 — PWM 4 output
JN5169
Product data sheet
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Rev. 1 — 5 August 2015
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JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
Table 2.
Pin description …continued
Symbol
Pin Type[1]
Description
DIO9/TIM0CAP/32KXTALIN/RXD1/32KIN
32
DIO9 — DIO9
I/O
TIM0CAP — Timer0 Capture input
32KXTALIN — 32 kHz External Crystal input
RXD1 — UART1 Receive Data input
32KIN — 32 kHz External clock input
DIO10/TIM0OUT/32KXTALOUT
33
I/O
DIO10 — DIO10
TIM0OUT — Timer0 PWM Output
32KXTALOUT — 32 kHz External Crystal output
DIO11/PWM1/TXD1
34
I/O
DIO11 — DIO11
PWM1 — PWM1 output
TXD1 — UART1 Transmit Data output
VB_DIG
35
P
VB_DIG — regulated supply voltage
DIO12[4]
36
I/O
DIO12 — DIO12
PWM2 — PWM2 output
CTS0 — UART0 clear to send input
JTAG_TCK — JTAG CLK input
ADO — antenna diversity odd output
SPISMOSI — SPI-bus slave Master Out, Slave In input
DIO13[5]
37
I/O
DIO13 — DIO13
PWM3 — PWM3 output
RTS0 — UART0 request to send output
JTAG_TMS — JTAG mode select input
ADE — antenna diversity even output
SPISMISO — SPI-bus slave master in slave out output
DIO14[6]
38
I/O
DIO14 — DIO14
SIF_CLK — serial interface clock
TXD0 — UART 0 transmit data output
TXD1 — UART 1 transmit data output
JTAG_TDO — JTAG data output
SPISEL1 — SPI-bus master select output 1
SPISSEL — SPI-bus slave select input
VSS
39
GND
VSS — ground
DIO15[7]
40
I/O
DIO15 — DIO15
SIF_D — serial interface data
RXD0 — UART 0 receive data input
RXD1 — UART 1 receive data input
JTAG_TDI — JTAG data input
SPISEL2 — SPI-bus master select output 2
SPISCLK — SPI-bus slave clock input
VSSA
[1]
-
GND
VSSA — Exposed die paddle
P = power supply; G = ground; I = input, O = output; I/O = input/output.
JN5169
Product data sheet
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JN5169
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IEEE802.15.4 Wireless Microcontroller
[2]
JTAG programming mode: must be left floating high during reset to avoid entering JTAG programming mode.
[3]
UART programming mode: leave pin floating high during reset to avoid entering UART programming mode or hold it low to program.
[4]
Multi-function: DIO12/PWM2/CTS0/JTAG_TCK/ADO/SPISMOSI.
[5]
Multi-function: DIO13/PWM3/RTS0/JTAG_TMS/ADE/SPISMISO.
[6]
Multi-function: DIO14/SIF_CLK/TXD0/TXD1/JTAG_TDO/SPISEL1/SPISSEL.
[7]
Multi-function: DIO15/SIF_D/RXD0/RXD1/JTAG_TDI/SPISEL2/SPISCLK.
The PCB schematic and layout rules detailed in Section 15.1 must be followed. Failure to
do so will likely result in the JN5169 failing to meet the performance specification detailed
in this data sheet and the worst case may result in the device not functioning in the end
application.
8.2.1 Power supplies
The device is powered from the VDDA and VDDD pins, each being decoupled with a 100 nF
ceramic capacitor. VDDA is the power supply to the analog circuitry; it should be decoupled
to ground. VDDD is the power supply for the digital circuitry; it should also be decoupled to
ground. In addition, a common 10 F tantalum capacitor is required for low frequencies.
Decoupling pins for the internal 1.8 V regulators are provided with each pin requiring a
100 nF capacitor located as close to the device as practical. VB_SYNTH and VB_DIG
require only a 100 nF capacitor. VB_RF1 and VB_RF2 should be connected together as
close to the device as practical, and require one 100 nF capacitor and one 47 pF
capacitor. The pin VB_VCO requires a 10 nF capacitor. See Figure 48 for a schematic
diagram.
VSSA and VSS are the ground pins.
Users are strongly discouraged from connecting their own circuits to the 1.8 V regulated
supply pins, as the regulators have been optimized to supply only enough current for the
internal circuits.
8.2.2 Reset
RESET_N is an active-low reset input pin that is connected to a 500 k internal pull-up
resistor. It may be pulled low by an external circuit. See Section 9.4.2 for more details.
8.2.3 32 MHz oscillator
A crystal is connected between XTAL_IN and XTAL_OUT to form the reference oscillator,
which drives the system clock. A capacitor to analog ground is required on each of these
pins. See Section 9.3.1 for more details. The 32 MHz reference frequency is divided down
to 16 MHz and this is used as the system clock throughout the device.
8.2.4 Radio
The radio is a single-ended design, requiring two capacitors and just two inductors to
match the 50 microstrip line to the RF_IO pin.
An external resistor (43 k) is required between IBIAS and analog ground (paddle) to set
various bias currents and references within the radio.
JN5169
Product data sheet
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Rev. 1 — 5 August 2015
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JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
8.2.5 Analog peripherals
The ADC requires a reference voltage to use as part of its operation. It can use either an
internal reference voltage or an external reference connected to VREF. This voltage is
referenced to analog ground and the performance of the analog peripherals is dependent
on the quality of this reference.
There are 6 ADC inputs and a pair of comparator inputs. ADC1 has a designated input pin
but ADC2 uses the same pin as VREF, invalidating its use as an ADC pin when an
external reference voltage is required. The remaining 4 ADC channels are shared with the
digital I/Os DIO0, DIO1, DIO2 and DIO3. When these 4 ADC channels are selected, the
corresponding DIOs must be configured as inputs with their pull-ups disabled. Similarly,
the comparator shares pins 1 and 2 with DIO16 and DIO17, so when the comparator is
selected these pins must be configured as inputs with their pull-ups disabled. The analog
I/O pins on the JN5169 can have signals applied up to 0.3 V higher than VDDA. A
schematic view of the analog I/O cell is shown in Figure 4. Figure 5 demonstrates a
special case, where a digital I/O pin doubles as an input to analog devices. This applies to
ADC3, ADC4, ADC5, ADC6, COMP1P and COMP1M.
In reset, sleep and deep sleep, the analog peripherals are all OFF. In sleep, the
comparator may optionally be used as a wake-up source.
Unused ADC and comparator inputs should not be left unconnected - for example,
connected to analog ground.
VDDA
ANALOG
PERIPHERAL
analog
I/O pin
VSSA
Fig 4.
aaa-017249
Analog I/O cell
8.2.6 Digital Input/Output
For the DC properties of these pins, see Section 14.2. When used in their primary
function, all Digital Input/Output pins are bidirectional and are connected to weak internal
pull-up resistors (50 k nominal) that can be disabled. When used in their secondary
function (selected when the appropriate peripheral block is enabled through software
library calls), their direction is fixed by the function. The pull-up resistor is enabled or
disabled independently of the function and direction; the default state from reset is
enabled.
A schematic view of the Digital I/O cell shown in Figure 5. The dotted lines through
resistor RESD represent a path that exists only on DIO0, DIO1, DIO2, DIO3, DIO16 and
DIO17 which are also inputs to the ADC (ADC3, ADC4, ADC5 and ADC6) and
Comparator (COMP1P and COMP1M) respectively. To use these DIO pins for their
analog functions, the DIO must be set as an input with its pull-up resistor, RPU, disabled.
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COMP1 input
Pu
IE
RPU
RESD
RPROT
DIOx(1) Pin
I
RDN
Pd
VSS
VSS
O
OE
aaa-015437
(1) With x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 or 19.
Fig 5.
DIO equivalent schematic
In reset, the digital peripherals are all off and the DIO pins are set as high-impedance
inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and
the output level that was set at the start of sleep. If the DIO pins were enabled as inputs
and the interrupts were enabled, then these pins may be used to wake up the JN5169
from sleep.
9. Functional description
9.1 CPU
The CPU of the JN5169 is a 32-bit load and store RISC processor. It has been architected
for 3 key requirements:
• Low power consumption for battery powered applications
• High performance to implement a wireless protocol at the same time as complex
applications
• Efficient coding of high-level languages such as C provided with the Software
Developer’s Kit
It features a linear 32-bit logical address space with unified memory architecture,
accessing both code and data in the same address space. Registers for peripheral units,
such as the timers, UART and the baseband processor, are also mapped into this space.
The CPU has access to a block of 15 32-bit General-Purpose (GP) registers together
with a small number of special purpose registers which are used to store processor state
and control interrupt handling. The contents of any GP register can be loaded from or
stored to memory. Arithmetic and logical operations, shift and rotate operations, and
signed and unsigned comparisons can be performed either between two registers and
stored in a third, or between registers and a constant carried in the instruction. Operations
between general or special-purpose registers execute in one cycle while those that
access memory requires a further cycle to allow the memory to respond.
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The instruction set manipulates 8-bit, 16-bit and 32-bit data; this means that programs can
use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly
useful for protocols and high-end applications allowing algorithms to be implemented in
fewer instructions than on smaller word-size processors, and allowing execution in fewer
clock cycles. In addition, the CPU supports hardware Multiply that can be used to
efficiently implement algorithms needed by Digital Signal Processing applications.
The instruction set is designed for the efficient implementation of high-level languages
such as C. Access to fields in complex data structures is very efficient due to the provision
of several addressing modes, together with the ability to use any of the GP registers to
contain the address of objects. Subroutine parameter passing is also made more efficient
by using GP registers rather than pushing objects onto the stack. The recommended
programming method for the JN5169 is to use C, which is supported by a software
developer kit comprising a C compiler, linker and debugger.
The CPU architecture also contains features that make the processor suitable for
embedded, real-time applications. In some applications, it may be necessary to use a
real-time operating system to allow multiple tasks to run on the processor. To provide
protection for device-wide resources being altered by one task and affecting another, the
processor can run in either supervisor or user mode, the former allowing access to all
processor registers, while the latter only allows the GP registers to be manipulated.
Supervisor mode is entered on reset or interrupt; tasks starting up would normally run in
user mode in an RTOS environment.
Embedded applications require efficient handling of external hardware events. Exception
processing (including reset and interrupt handling) is enhanced by the inclusion of a
number of shadow registers into which the PC and status register contents are copied as
part of the operation of the exception hardware. This means that the essential registers for
exception handling are stored in one cycle, rather than the slower method of pushing them
onto the processor stack. The PC is also loaded with the vector address for the exception
that occurred, allowing the handler to start executing in the next cycle.
To improve power consumption, a number of power-saving modes are implemented in the
JN5169, described more fully in Section 10. One of these modes is the CPU doze mode;
under software control, the processor can be shut down and on an interrupt it will wake up
to service the request. Additionally, it is possible under software control to set the speed of
the CPU to 1 MHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz or 32 MHz. This feature can be used
to trade off processing power against current consumption.
9.2 Memory organization
This section describes the different memories found within the JN5169. The device
contains Flash, RAM and EEPROM memory, the wireless transceiver and peripherals all
within the same linear address space.
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Unpopulated
0xFFFFFFFF
0xF0008000
RAM
0xF0000000
0x04008000
Shadow RAM
0x04000000
Peripherals
0x02000000
Flash and
EEPROM Registers
0x01000000
0x00100000
Flash
Applications
Code
(512 kB)
0x00080000
Flash Boot Code 8 kB
0x00000000
Fig 6.
aaa-017150
JN5169 memory map
9.2.1 Flash
The embedded Flash consists of 2 parts: an 8 kB region used for holding boot code and a
512 kB region used for application code. The maximum number of write cycles or
endurance is 10 k guaranteed, and typically 50 k, while the data retention is guaranteed
for at least 10 years. The boot code region is pre-programmed by NXP on supplied parts
and contains code to handle reset, interrupts and other events (see Section 6). It also
contains a Flash Programming interface to allow interaction with the PC-based Flash
programming utility which allows user code compiled using the supplied toolchain to be
programmed into the Application space. For further information, see the Application Note
on the NXP Wireless Connectivity TechZone Ref. 1.
9.2.2 RAM
The JN5169 devices contain 32 kB of high-speed RAM, which can be accessed by the
CPU in a single clock cycle. It is primarily used to hold the CPU Stack together with
program variables and data. If necessary, the CPU can execute code contained within the
RAM (although it would normally just execute code directly from the embedded Flash).
Software can control the power supply to the RAM allowing the contents to be maintained
during a sleep period when other parts of the device are unpowered, allowing a quicker
resumption of processing once woken.
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9.2.3 OTP configuration memory
The JN5169 devices contain a quantity of One Time Programmable (OTP) memory as
part of the embedded Flash (Index Sector). This can be used to securely hold such things
as a user 64-bit MAC address and a 128-bit AES security key. A limited number of further
bits are available for customer use for storage of configuration or other information. By
default, the 64-bit MAC address is pre-programmed by NXP on supplied parts; however,
customers can use their own MAC address and override the default one. The user MAC
address and other data can be written to the OTP memory using the Flash programmer.
Details on how to obtain and install MAC addresses can be found in the dedicated
Application Note.
For further information on how to program and use this facility, see BeyondStudio for NXP
User Guide (JN-UG-3098) on the NXP Wireless Connectivity TechZone Ref. 1.
9.2.4 EEPROM
The JN5169 devices contain 4 kB of EEPROM. The maximum number of write cycles or
endurance is 100 k guaranteed, and 500 k typically, while the data retention is guaranteed
for at least 10 years. This non-volatile memory is primarily used to hold persistent data
generated from such things as the network stack software component (for example
network topology, routing tables). As the EEPROM holds its contents through sleep and
reset events, more stable operation and faster recovery is possible after outages. Access
to the EEPROM is via registers mapped into the Flash and EEPROM registers region of
the address map.
The customer may use part of the EEPROM to store their own data by interfacing with the
Persistent Data Manager (PDM). Optionally, the PDM can also store data in an external
memory. For further information, see the NXP Wireless Connectivity TechZone Ref. 1.
9.2.5 External memory
An optional external serial non-volatile memory (for instance Flash or EEPROM) with a
SPI-bus interface may be used to provide additional storage for program code, such as a
new code image or further data for the device when external power is removed. The
memory can be connected to the SPI-bus master interface using select line SPISEL0 (see
Figure 7 for details).
serial
memory
JN5169
SPISEL0
SS
SPIMISO
SDO
SPIMOSI
SDI
SPICLK
CLK
aaa-013129
Fig 7.
Connecting external serial memory
The contents of the external serial memory may be encrypted. The AES security
processor combined with a user programmable 128-bit encryption key is used to encrypt
the contents of the external memory. The encryption key is stored in the Flash memory
index sector. When bootloading program code from external serial memory, the JN5169
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automatically accesses the encryption key to execute the decryption process. The user
program code does not need to handle any of the decryption processes; it is transparent.
For more details, including the how the program code encrypts data for the external
memory, see the Application Note JN51xx Boot Loader Operation (JN-AN-1003) on the
NXP Wireless Connectivity TechZone Ref. 1.
9.2.6 Peripherals
All peripherals have their registers mapped into the memory space. Access to these
registers requires three peripheral clock cycles. Applications have access to the
peripherals through the software libraries that present a high-level view of the peripheral's
functions through a series of dedicated software routines. These routines provide both a
tested method for using the peripherals and allow bug-free application code to be
developed more rapidly. For details, see JN516x Integrated Peripherals API User Guide
(JN-UG-3087) on the NXP Wireless Connectivity TechZone Ref. 1.
9.2.7 Unused memory address
Any attempt to access an unpopulated memory area will result in a bus error exception
(interrupt) being generated.
9.3 System clocks
Two system clocks are used to drive the on-chip subsystems of the JN5169. The wake-up
timers are driven from a low frequency clock (notionally 32 kHz). All other subsystems
(transceiver, processor, memory and digital and analog peripherals) are driven by a
high-speed clock (notionally 32 MHz), or a divided-down version of it.
The high-speed clock is either generated by the accurate crystal-controlled oscillator
(32 MHz) or the less accurate high-speed RC oscillator (27 MHz to 32 MHz calibrated).
The low-speed clock is either generated by the accurate crystal-controlled oscillator
(32 kHz to 768 kHz), the less accurate RC oscillator (centered on 32 kHz) or can be
supplied externally.
9.3.1 High-speed (32 MHz) system clock
The selected high-speed system clock is used directly by the radio subsystem, whereas a
divided-by-two version is used by the remainder of the transceiver and the digital and
analog peripherals. The direct or divided-down version of the clock is used to drive the
processor and memories (32 MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz or 1 MHz).
0+]&5<67$/
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',9%<
25
3(5,3+(5$/6<67(0&/2&.
&38&/2&.
DDD
Fig 8.
JN5169
Product data sheet
System and CPU clocks
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Crystal oscillators are generally slow to start. Hence to provide a fast start-up following a
sleep cycle or reset, the fast RC oscillator is always used as the initial source for the
high-speed system clock. The oscillator starts very quickly and will run at 25 MHz to
32 MHz (uncalibrated) or 32 MHz 5 % (calibrated). Although this means that the system
clock will be running at an undefined frequency (slightly slower or faster than nominal),
this does not prevent the CPU and Memory subsystems operating normally, so the
program code can execute. However, it is not possible to use the radio or UARTs, as even
after calibration (initiated by the user software calling an API function) there is still a 5 %
tolerance in the clock rate over voltage and temperature. Other digital peripherals can be
used (e.g. SPI-bus master/slave), but care must be taken if using timers due to the clock
frequency inaccuracy.
Further details of the high-speed RC oscillator can be found in Section 9.3.1.2
On wake-up from sleep, the JN5169 uses the fast RC oscillator. It can then either:
• Automatically switch over to use the 32 MHz clock source when it has started up
• Continue to use the fast RC oscillator until software triggers the switch-over to the
32 MHz clock source - for example, when the radio is required
• Continue to use the RC oscillator until the device goes back into one of the sleep
modes
The use of the fast RC oscillator at wake-up means that there is no need to wait for the
32 MHz crystal oscillator to stabilize. Consequently, the application code will start
executing quickly using the clock from the high-speed RC oscillator.
9.3.1.1
32 MHz crystal oscillator
The JN5169 contains the necessary on-chip components to build a 32 MHz reference
oscillator with the addition of an external crystal resonator and two tuning capacitors. The
schematic of these components is shown in Figure 8. The two capacitors, C1 and C2,
should typically be 12 pF and use a C0G dielectric. Due to the small size of these
capacitors, it is important to keep the traces to the external components as short as
possible. The on-chip transconductance amplifier is compensated for temperature
variation and is self-biasing by means of the internal resistor R1. This oscillator provides
the frequency reference for the radio and therefore it is essential that the reference PCB
layout and BOM are carefully followed. The oscillator includes a function which flags when
the amplitude of oscillation has reached a satisfactory level for full operation, and this is
checked before the source of the high-speed system clock is changed to the 32 MHz
crystal oscillator.
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JN5169
R1
XTAL_IN
XTAL_OUT
C1
C2
aaa-013130
Fig 9.
9.3.1.2
32 MHz crystal oscillator connections
High-speed RC oscillator
An on-chip high-speed RC oscillator is provided in addition to the 32 MHz crystal oscillator
for two purposes; to allow a fast start-up from reset or sleep and to provide a lower current
alternative to the crystal oscillator for non-timing critical applications. By default the
oscillator will run at 27 MHz, typically, with a wide tolerance. It can be calibrated, using a
software API function, which will result in a nominal frequency of 32 MHz with a 1.6%
tolerance at 3 V and 25 C. However, it should be noted that over the full operating range
of voltage and temperature this will increase to 5%. The calibration information is
retained through speed cycles and when the oscillator is disabled, so typically the
calibration function only needs to be called once. No external components are required for
this oscillator. The electrical specification of the oscillator can be found in Section 14.3.9.
9.3.2 Low-speed (32 kHz) system clock
The 32 kHz system clock is used for timing the length of a sleep period (see Section 10).
The clock can be selected from one of three sources through the application software:
• 32 kHz RC oscillator
• 32 kHz crystal oscillator
• 32 kHz external clock
Upon a chip reset or power-up, the JN5169 defaults to using the internal 32 kHz RC
oscillator. If another clock source is selected, then it will remain in use for all 32 kHz timing
until a chip reset is performed.
9.3.2.1
32 kHz RC oscillator
The internal 32 kHz RC oscillator requires no external components. The internal timing
components of the oscillator have a wide tolerance due to manufacturing process
variation and so the oscillator runs nominally at 32 kHz 10 % +40 %. To make this useful
as a timing source for accurate wake-up from sleep, a frequency calibration factor derived
from the more accurate 16 MHz clock may be applied. The calibration factor is derived
through software; details can be found in Section 9.9.9. Software must check that the
32 kHz RC oscillator is running before using it. The oscillator has a default current
consumption of around 0.5 A. Optionally, this can be reduced to 0.375 A. However, the
calibrated accuracy and temperature coefficient will be worse as a consequence.
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9.3.2.2
32 kHz crystal oscillator
In order to obtain more accurate sleep periods, the JN5169 contains the necessary
on-chip components to build a 32 kHz oscillator with the addition of an external
32.768 kHz crystal and two tuning capacitors. The crystal should be connected between
32KXTALIN and 32KXTALOUT (DIO9 and DIO10), with two equal capacitors to ground,
one on each pin. Due to the small size of the capacitors, it is important to keep the traces
to the external components as short as possible.
The electrical specification of the oscillator can be found in Section 14.3.9. The oscillator
cell is flexible and can operate with a range of commonly available 32.768 kHz crystals
with load capacitances from 6 pF to 12.5 pF. However, the maximum ESR of the crystal
and the supply current are both functions of the actual crystal used.
JN5169
32KXTALIN
32KXTALOUT
aaa-013131
Fig 10. 32 kHz crystal oscillator connections
9.3.2.3
32 kHz external clock
An externally supplied 32 kHz reference clock on the 32KIN input (DIO9) may be provided
to the JN5169. This would allow the 32 kHz system clock to be sourced from a very stable
external oscillator module, allowing more accurate sleep cycle timings compared to the
internal RC oscillator.
9.4 Reset
A system reset initializes the device to a pre-defined state and forces the CPU to start
program execution from the reset vector. The reset process that the JN5169 goes through
is as follows.
When power is first applied or when the external reset is released, the high-speed RC
oscillator and 32 MHz crystal oscillator are activated. After a short wait period
(approximately 13 s) while the high-speed RC starts up, and as long as the supply
voltage satisfies the default Supply Voltage Monitor (SVM) threshold (2.0 V + 0.045 V
hysteresis), the internal 1.8 V regulators are turned on to power the processor and
peripheral logic. The regulators are allowed to stabilize (about 15 s) followed by a further
wait (approximately 150 s) to allow the Flash and EEPROM bandgaps to stabilize and
allow their initialization, including reading the user SVM threshold from the Flash. This is
applied to the SVM, and after a brief pause (approximately 2.5 s) the SVM is checked
again. If the supply is above the new SVM threshold, the CPU and peripheral logic are
released from reset and the CPU starts to run code beginning at the reset vector. This
runs the bootloader code contained within the Flash, which looks for a valid application to
run, first from the internal Flash and then from any connected external serial memory over
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the SPI-bus master interface. Once found, required variables are initialized in RAM before
the application is called at its AppColdStart entry point. For more details on the bootloader,
see the Application Note on the NXP Wireless Connectivity TechZone Ref. 1.
The JN5169 has 5 sources of reset:
•
•
•
•
•
Internal Power-On Reset/Brown-Out Reset (BOR)
External reset
Software reset
Watchdog timer
Supply voltage detect
Remark: When the device exits a reset condition, device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure operation. If these conditions are not
met, then the device must be held in reset until the operating conditions are met
(see Section 14.3.1)
9.4.1 Internal Power-On Reset/Brown-Out Reset (BOR)
For the majority of applications, the Internal Power-On Reset is capable of generating the
required reset signal. When power is applied to the device, the Power-On Reset circuit
monitors the rise of the VDD supply. When the VDD reaches the specified threshold, the
reset signal is generated. This signal is held internally until the power supply and oscillator
stabilization time has elapsed, when the internal reset signal is then removed and the
CPU is allowed to run.
The BOR circuit has the ability to reject spikes on the VDD rail to avoid false triggering of
the reset module. Typically for a negative going square pulse of duration 1 s, the voltage
must fall to 1.2 V before a reset is generated. Similarly for a triangular wave pulse of 10 s
width, the voltage must fall to 1.3 V before causing a reset. The exact characteristics are
complex and these are only examples.
VDD
internal RESET
aaa-017251
Fig 11. Internal Power-On Reset
When the supply drops below the POR ‘falling’ threshold, it will retrigger the reset. If
necessary, use of the external reset circuit shown in Figure 12 is suggested.
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VDD
R1
18 kΩ
RESET_N
JN5169
C1
470 nF
aaa-013132
Fig 12. External reset generation
The external resistor and capacitor provide a simple reset operation when connected to
the RESET_N pin but are not necessary.
9.4.2 External reset
An external reset is generated by a low level on the RESET_N pin. Reset pulses longer
than the minimum pulse width will generate a reset during active or sleep modes. Shorter
pulses are not guaranteed to generate a reset. The JN5169 is held in reset while the
RESET_N pin is low. When the applied signal reaches the reset threshold voltage (Vrst) on
its positive edge, the internal reset process starts.
The JN5169 has an internal 500 k pull-up resistor connect to the RESET_N pin. The pin
is an input for an external reset only. By holding the RESET_N pin low, the JN5169 is held
in reset, resulting in a typical current of 6 A.
RESET_N pin
reset
internal reset
aaa-017252
Fig 13. External reset
9.4.3 Software reset
A system reset can be triggered at any time through software control, causing a full chip
reset and invalidating the RAM contents. For example, this can be executed within a
user’s application upon detection of a system failure.
9.4.4 Supply Voltage Monitor (SVM)
An internal SVM is used to monitor the supply voltage to the JN5169; this can be used
while the device is awake or is in CPU doze mode. Dips in the supply voltage below a
variable threshold can be detected and can be used to cause the JN5169 to perform a
chip reset. Equally, dips in the supply voltage can be detected and used to cause an
interrupt to the processor, when the voltage either drops below the threshold or rises
above it.
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The SVM is enabled by default from power-up and can extend the reset during power-up.
This will keep the CPU in reset until the voltage exceeds the SVM threshold voltage. The
threshold voltage is configurable to 1.95 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.7 V or 3.0 V
and is controllable by software. From power-up, the threshold is set according to the value
stored in Flash and the default chip configuration is for the 2.0 V threshold. It is expected
that the threshold is set to the minimum needed by the system.
9.4.5 Watchdog timer
A watchdog timer is provided to guard against software lock-ups. It operates by counting
cycles of the high-speed RC system clock. A pre-scaler is provided to allow the expiry
period to be set between typically 8 ms and 16.4 s (dependent on high-speed RC
accuracy: +30 %, 15 %). Failure to restart the watchdog timer within the pre-configured
timer period will cause a chip reset to be performed. A status bit is set if the watchdog was
triggered so that the software can differentiate watchdog initiated resets from other resets,
and can perform any required recovery once it restarts. Optionally, the watchdog can
cause an exception rather than a reset; this preserves the state of the memory and is
useful for debugging.
After power-up, reset, start from deep sleep or start from sleep, the watchdog is always
enabled with the largest time-out period and will commence counting as if it had just been
restarted. Under software control, the watchdog can be disabled. If it is enabled, the user
must regularly restart the watchdog timer to stop it from expiring and causing a reset. The
watchdog runs continuously, even during doze. However the watchdog does not operate
during sleep or deep sleep, or when the hardware debugger has taken control of the CPU.
If enabled, it will restart automatically once the debugger has unstalled the CPU.
9.5 Interrupt system
A hardware-vectored interrupt system is provided on the JN5169. The JN5169 provides
several interrupt sources, some associated with CPU operations (CPU exceptions) and
others which are used by hardware in the device. When an interrupt occurs, the CPU
stops executing the current program and loads its program counter with a fixed hardware
address specific to that interrupt. The interrupt handler or interrupt service routine is
stored at this location and is run on the next CPU cycle. Execution of interrupt service
routines is always performed in supervisor mode. Interrupt sources and their vector
locations are shown in Table 3.
Table 3.
JN5169
Product data sheet
Interrupt vectors
Interrupt source
Vector location
Interrupt definition
Bus error
0x08
typically caused by an attempt to access an invalid
address or a disabled peripheral
Tick timer
0x0E
tick timer interrupt asserted
Alignment error
0x14
load/store address to non-naturally aligned location
Illegal instruction
0x1A
attempt to execute an unrecognized instruction
Hardware interrupt
0x20
interrupt asserted
System call
0x26
system call initiated by b.sys instruction
Trap
0x2C
caused by the b.trap instruction or the debug unit
Reset
0x38
caused by software or hardware reset
Stack overflow
0x3E
stack overflow
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9.5.1 System calls
The b.trap and b.sys instructions allow processor exceptions to be generated by software.
A system call exception will be generated when the b.sys instruction is executed. This
exception can, for example, be used to enable a task to switch the processor into
supervisor mode when a real-time operating system is in use (see Section 9.5.3 for further
details).
The b.trap instruction is commonly used for trapping errors and for debugging.
9.5.2 Processor exceptions
9.5.2.1
Bus error
A bus error exception is generated when software attempts to access a memory address
that does not exist, or is not populated with memory or peripheral registers.
9.5.2.2
Alignment
Alignment exceptions are generated when software attempts to access objects that are
not aligned to natural word boundaries. 16-bit objects must be stored on even byte
boundaries, while 32-bit objects must be stored on quad byte boundaries. For instance,
attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception
as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit
object addresses are 0xFFF0, 0xFFF4, 0xFFF8 etc.
9.5.2.3
Illegal instruction
If the CPU reads an unrecognized instruction from memory as part of its instruction fetch,
it will cause an illegal instruction exception.
9.5.2.4
Stack overflow
When enabled, a stack overflow exception occurs if the stack pointer reaches a
programmable location.
9.5.3 Hardware interrupts
Hardware interrupts generated from the transceiver, analog or digital peripherals and DIO
pins are individually masked using the Programmable Interrupt Controller (PIC).
Management of interrupts is provided in the JN516x Integrated Peripherals API User
Guide (JN-UG-3087) on the NXP Wireless Connectivity TechZone Ref. 1. For details of
the interrupts generated from each peripheral, see the respective section in this data
sheet.
Interrupts can be used to wake the JN5169 from sleep. The peripherals, baseband
controller, security coprocessor and PIC are powered down during sleep but the DIO
interrupts and optionally the pulse counters, wake-up timers and analog comparator
interrupts remain powered to bring the JN5169 out of sleep.
Prioritized external interrupt handling (i.e., interrupts from hardware peripherals) is
provided to enable an application to control an events priority to provide for deterministic
program execution.
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IEEE802.15.4 Wireless Microcontroller
The priority Interrupt controller provides 15 levels of prioritized interrupts. The priority level
of all interrupts can be set, with value 0 being used to indicate that the source can never
produce an external interrupt, 1 for the lowest priority source(s) and 15 for the highest
priority source(s). Note that multiple interrupt sources can be assigned the same priority
level if desired.
If while processing an interrupt, a new event occurs at the same or lower priority level, a
new external interrupt will not be triggered. However, if a new higher priority event occurs,
the external interrupt will again be asserted, interrupting the current interrupt service
routine.
Once the interrupt service routine is complete, lower priority events can be serviced.
9.6 Wireless transceiver
The wireless transceiver comprises a 2.4 GHz radio, modem, a baseband processor, a
security coprocessor and PHY controller. These blocks, with protocol software provided
as a library, implement an IEEE802.15.4 standards-based wireless transceiver that
transmits and receives data over the air in the unlicensed 2.4 GHz band.
9.6.1 Radio
Figure 14 shows the single ended radio architecture.
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Fig 14. Radio architecture
The radio comprises a low-IF receive path and a direct modulation transmit path, which
converge at the TX/RX switch. The switch connects to the external single-ended matching
network, which consists of two inductors and a capacitor. This arrangement creates a
50 port and removes the need for a balun. A 50 single-ended antenna can be
connected directly to this port.
The 32 MHz crystal oscillator feeds a divider, which provides the frequency synthesizer
with a reference frequency. The synthesizer contains programmable feedback dividers,
phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO
has no external components, and includes calibration circuitry to compensate for
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IEEE802.15.4 Wireless Microcontroller
differences in internal component values due to process and temperature variations. The
VCO is controlled by a Phase-Locked Loop (PLL) that has an internal loop filter. A
programmable charge pump is also used to tune the loop characteristic.
The receiver chain starts with the low noise amplifier/mixer combination whose outputs
are passed to a low pass filter, which provides the channel definition. The signal is then
passed to a series of amplifier blocks forming a limiting strip. The signal is converted to a
digital signal before being passed to the Modem. The gain control for the RX path is
derived in the Automatic Gain Control (AGC) block within the Modem, which samples the
signal level at various points down the RX chain. To improve the performance and reduce
current consumption, automatic calibration is applied to various blocks in the RX path.
In the transmit direction, the digital stream from the Modem is passed to a digital
sigma-delta modulator which controls the feedback dividers in the synthesizer (dual point
modulation). The VCO frequency now tracks the applied modulation. The 2.4 GHz signal
from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be
selected from one of six settings. The output of the PA drives the antenna via the RX/TX
switch
When enabled, the JN5169 radio is automatically calibrated for optimum performance. In
operating environments with a significant variation in temperature (e.g. greater than
20 C) due to diurnal or ambient temperature variation, it is recommended to recalibrate
the radio to maintain performance. Recalibration is only required on Routers and End
Devices that never sleep. End Devices that sleep when idle are automatically recalibrated
when they wake. An Application Note JN516x Temperature-Dependent Operating
Guidelines (JN-AN-1186) (on the NXP Wireless Connectivity TechZone Ref. 1) describes
this in detail and includes a software API function which can be used to test the
temperature using the on-chip temperature sensor and trigger a recalibration if there has
been a significant temperature change since the previous calibration.
9.6.1.1
Radio external components
In order to realize the full performance of the radio, it is essential that the reference PCB
layout and BOM are carefully followed (see Section 15).
The radio is powered from a number of internal 1.8 V and 2.8 V regulators fed from the
analog supply VDDA, in order to provide good noise isolation between the digital logic of
the JN5169 and the analog blocks. These regulators are also controlled by the baseband
controller and protocol software to minimize power consumption. Decoupling for internal
regulators is required as described in Section 8.2.1.
For single-ended antennas or connectors, a balun is not required. However a matching
network is needed.
The RF matching network requires three external components and the IBIAS pin requires
one external component as shown in Figure 15. These components are critical and should
be placed close to the JN5169 pins and analog ground as defined in Table 37. Specifically,
the output of the network comprising L2, C1, L1 and C4 is designed to present an
accurate match to a 50 resistive network as well as provide a DC path to the final output
stage or antenna. Users wishing to match to other active devices such as amplifiers
should design their networks to match to 50 at the output of L1.
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IEEE802.15.4 Wireless Microcontroller
IBIAS
R1
43 kΩ
VB_RF2 RF_IO
VB_RF1
VB_RF
L2
to coaxial socket
or integrated antenna
L1
4.3 nH
C4
1 pF
3 nH
C1
VB_RF
C12
47 pF
C3
100 nF
1.8 pF
aaa-017149
Fig 15. External radio components
9.6.1.2
Antenna diversity
Support is provided for antenna diversity, which is a technique that maximizes the
performance of an antenna system. It allows the radio to switch between two antennas
that have very low correlation between their received signals. Typically, this is achieved by
spacing two antennae around 0.25 wavelengths apart or by using 2 orthogonal
polarizations. So, if a packet is transmitted and no acknowledgement is received, the
radio system can switch to the other antenna for the retry, with a different probability of
success.
Additionally antenna diversity can be enabled while in receive mode waiting for a packet.
The JN5169 measures the received energy in the relevant radio channel every 40 s and
the measured energy level is compared with a pre-set energy threshold, which can be set
by the application program. The JN5169 device will automatically switch the antenna if the
measurement is below this threshold, except if waiting for an acknowledgement from a
previous transmission or if in the process of receiving a packet, when it will wait until this
has finished. Also, it will not switch if a preamble symbol having a signal quality above a
minimum specified threshold has not been detected in the last 40 s.
Both modes can be used at once and use the same ADO (SELA) and ADE (SELB)
outputs to control the external switch.
The JN5169 can provide an output (ADO) on DIO12 or DIO0 that is asserted on
odd-numbered retries. Further, the complement of this output (ADE) can be made
available on DIO13 or DIO1. Either or both of these signals can be used to control an
antenna switch to support antenna diversity (see Figure 16 and Figure 17).
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IEEE802.15.4 Wireless Microcontroller
antenna A
antenna B
A
ADO (DIO12 or DIO0)
ADE (DIO13 or DIO1)
B
SELA
RF switch: single-pole, double-throw (SPDT)
SELB
COM
device RF port
aaa-017081
Fig 16. Simple antenna diversity implementation using external RF switch
ADE (DIO13 or DIO1)
ADO (DIO12 or DIO0)
TX active
RX active
1st TX-RX cycle
2nd TX-RX cycle (1st retry)
aaa-017082
Fig 17. Antenna diversity ADO signal for TX with acknowledgement
If only one DIO pin can be used, then either ADE or ADO can be connected to the first
switch control pin and the same signal inverted on the second pin with an inverter on the
PCB.
9.6.2 Modem
The modem performs all the necessary modulation and spreading functions required for
digital transmission and reception of data at 250 kbits/s in the 2.4 GHz radio frequency
band in compliance with the IEEE802.15.4 standard.
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IEEE802.15.4 Wireless Microcontroller
5;
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9&2
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Fig 18. Modem architecture
Features provided to support network channel selection algorithms include Energy
Detection (ED), Link Quality Indication (LQI) and fully programmable Clear Channel
Assessment (CCA).
The modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates
the implementation of the IEEE802.15.4 ED function and LQI function.
The ED and LQI are both related to receiver power in the same way, as shown in
Figure 19. LQI is associated with a received packet, whereas ED is an indication of signal
power-on air at a particular moment.
The CCA capability of the modem supports all modes of operation defined in the
IEEE802.15.4 standard, namely Energy above ED threshold, Carrier Sense and Carrier
Sense and/or energy above ED threshold.
aaa-018590
260
Decimal
code
220
200
180
160
140
120
100
80
60
40
20
0
-105
-85
-65
-45
-25
-5
15
Input power (dBm)
Fig 19. Energy detect value versus receive power level
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IEEE802.15.4 Wireless Microcontroller
9.6.3 Baseband processor
The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC
layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer
hardware/software partitioning enables software to implement the sequencing of events
required by the protocol and to schedule timed events with millisecond resolution, and the
hardware to implement specific events with microsecond timing resolution. The protocol
software layer performs the higher-layer aspects of the protocol, sending management
and data messages between End Device and Co-ordinator nodes, using the services
provided by the baseband processor.
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Fig 20. Baseband processor
9.6.3.1
Transmit
A transmission is performed by software writing the data to be transferred into the TX
frame buffer in RAM, together with parameters such as the destination address and the
number of retries allowed, as well as programming one of the protocol timers to indicate
the time at which the frame is to be sent. This time will be determined by the software
tracking the higher-layer aspects of the protocol such as superframe timing and slot
boundaries. Once the packet is prepared and protocol timer set, the supervisor block
controls the transmission. When the scheduled time arrives, the supervisor controls the
sequencing of the radio and modem to perform the type of transmission required, fetching
the packet data directly from RAM. It can perform all the algorithms required by
IEEE802.15.4 such as CSMA/CA without processor intervention including retries and
random back-offs.
When the transmission begins, the header of the frame is constructed from the
parameters programmed by the software and sent with the frame data through the
serializer to the modem. At the same time, the radio is prepared for transmission. During
the passage of the bitstream to the modem, it passes through a CRC checksum generator
that calculates the checksum on-the-fly, and appends it to the end of the frame.
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9.6.3.2
Reception
During reception, the radio is set to receive on a particular channel. On receipt of data
from the modem, the frame is directed into the RX frame buffer in RAM where both header
and frame data can be read by the protocol software. An interrupt may be provided on
receipt of the frame. An additional interrupt may be provided after the transmission of an
acknowledgement frame in response to the received frame, if an acknowledgement frame
has been requested and the auto acknowledge mechanism is enabled, see
Section 9.6.3.3. As the frame data is being received from the modem, it is passed through
a checksum generator; at the end of the reception the checksum result is compared with
the checksum at the end of the message to ensure that the data has been received
correctly. During reception, the modem determines the Link Quality, which is made
available at the end of the reception as part of the requirements of IEEE802.15.4.
9.6.3.3
Auto acknowledge
Part of the protocol allows for transmitted frames to be acknowledged by the destination
sending an acknowledge packet within a very short window after the transmitted frame
has been received. The JN5169 baseband processor can automatically construct and
send the acknowledgement packet without processor intervention and hence avoid the
protocol software being involved in time-critical processing within the acknowledge
sequence. The JN5169 baseband processor can also request an acknowledge for
packets being transmitted and handle the reception of acknowledged packets without
processor intervention.
9.6.3.4
Security
The transmission and reception of secured frames using the Advanced Encryption
Standard (AES) algorithm is handled by the security coprocessor and the stack software.
The application software must provide the appropriate encrypt/decrypt keys for the
transmission or reception. On transmission, the key can be programmed at the same time
as the rest of the frame data and set-up information.
9.6.4 Security coprocessor
The security coprocessor is available to the application software to perform
encryption/decryption operations. A hardware implementation of the encryption engine
significantly speeds up the processing of the encrypted packets over a pure software
implementation. The AES library for the JN5169 provides operations that utilize the
encryption engine in the device and allow the contents of memory buffers to be
transformed. Information such as the type of security operation to be performed and the
encrypt/decrypt key to be used must also be provided.
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Fig 21. Security coprocessor architecture
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IEEE802.15.4 Wireless Microcontroller
9.7 Digital Input/Output
There are 20 Digital I/O (DIO) pins which, when used as general-purpose pins, can be
configured as either an input or an output, with each having a selectable internal pull-up
resistor. In addition, there are 2 Digital Output (DO) pins.
Most DIO pins are shared with the digital and analog peripherals of the device. When a
peripheral is enabled, it takes control over the device pins allocated to it. However, note
that most peripherals have two alternative pin allocations to alleviate clashes between
uses, and many peripherals can disable the use of specific pins if not required. See
Section 8.2 and the individual peripheral descriptions for full details of the available pinout
arrangements.
Following a reset (and while the RESET_N input is held low), all peripherals are forced off
and the DIO pins are configured as inputs with the internal pull-ups turned on. When a
peripheral is not enabled, the DIO pins associated with it can be used as digital inputs or
outputs. Each pin can be controlled individually by setting the direction and then reading
or writing to the pin.
The individual pull-up resistors, RPU, can also be enabled or disabled as needed and the
setting is held through sleep cycles. The pull-ups are generally configured once after reset
depending on the external components and functionality. For instance, outputs should
generally have the pull-ups disabled. An input that is always driven should also have the
pull-up disabled.
When configured as an input, each pin can be used to generate an interrupt upon a
change of state (selectable transition either from low to high or high to low); the interrupt
can be enabled or disabled. When the device is sleeping, these interrupts become events
that can be used to wake up the device. Equally the status of the interrupt may be read.
See Section 10 for further details on sleep and wake-up.
The state of all DIO pins can be read, irrespective of whether the DIO is configured as an
input or an output.
Throughout a sleep cycle, the direction of the DIOs and the state of the outputs are held.
This is based on the resultant of the GPIO Data/Direction registers and the effect of any
enabled peripherals at the point of entering sleep. Following a wake-up these directions
and output values are maintained under control of the GPIO data/direction registers. Any
peripherals enabled before the sleep cycle are not automatically re-enabled; this must be
done through software after the wake-up.
For example, if DIO0 is configured to be SPISEL1 then it becomes an output. The output
value is controlled by the SPI-bus functional block. If the device then enters a sleep cycle,
the DIO will remain an output and hold the value being output when entering sleep. After
wake-up, the DIO will still be an output with the same value but controlled from the GPIO
Data/Direction registers. It can be altered with the software functions that adjust the DIO,
or the application may reconfigure it to be SPISEL1.
Unused DIO pins are recommended to be set as inputs with the pull-up enabled.
Two DIO pins can optionally be used to provide control signals for RF circuitry (e.g.
switches and PA) in high-power range extenders.
DIO3/RFTX is asserted when the radio is in the transmit state and similarly, DIO2/RFRX is
asserted when the radio is in the receiver state.
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IEEE802.15.4 Wireless Microcontroller
SPI
SLAVE
SPISCLK
SPISMOSI
SPISMISO
SPISSEL
DIO0/ADO/SPISEL1/ADC3
DIO1/ADE/SPISEL2/ADC4/PC0
SPI
MASTER
UART0
UART1
SPICLK
SPIMOSI
SPIMISO
SPISEL0
SPISEL1
SPISEL2
TXD0
RXD0
RTS0
CTS0
TXD1
RXD1
DIO2/RFRX/TIM0CK_GT/ADC5
DIO3/RFTX/TIM0CAP/ADC6
DIO4/CTS0/JTAG_TCK/TIM0OUT/PC0
DIO5/RTS0/JTAG_TMS/PWM1/PC1
DIO6/TXD0/JTAG_TDO/PWM2
DIO7/RXD0/JTAG_TDI/PWM3
DIO8/TIM0CK_GT/PC1/PWM4
DIO9/TIM0CAP/32KXTALIN/RXD1/32KIN
TIMER0
PWMs
TIM0CK_GT
MUX
TIM0OUT
TIM0CAP
PWM1
PWM2
PWM3
PWM4
DIO10/TIM0OUT/32KXTALOUT
DIO11/PWM1/TXD1
DIO12/PWM2/CTS0/JTAG_TCK/ADO/SPISMOSI
DIO13/PWM3/RTS0/JTAG_TMS/ADE/SPISMISO
DIO14/SIF_CLK/TXD0/TXD1/JTAG_TDO/SPISEL1/SPISSEL
2-WIRE
INTERFACE
SIF_D
SIF_CLK
DIO15/SIF_D/RXD0/RXD1/JTAG_TDI/SPISEL2/SPISCLK
DIO16/COMP1P/SIF_CLK/SPISMOSI
PULSE
COUNTERS
JTAG
DEBUG
PC0
PC1
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
DIO17/COMP1M/SIF_D/SPISMISO/PWM4
DIO18/SPIMOSI
DIO19/SPISEL0
DO0/SPICLK/PWM2
ANTENNA
DIVERSITY
ADO
ADE
DO1/SPIMISO/PWM3
aaa-017083
Fig 22. DIO block diagram
9.8 Serial Peripheral Interface-bus
9.8.1 SPI-bus master
The SPI-bus allows high-speed synchronous data transfer between the JN5169 and
peripheral devices. The JN5169 operates as a master on the SPI-bus and all other
devices connected to the SPI-bus are expected to be slave devices under the control of
the JN5169 CPU. The SPI-bus includes the following features:
• Full-duplex, 3-wire synchronous data transfer
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IEEE802.15.4 Wireless Microcontroller
•
•
•
•
•
•
•
Programmable bit rates (up to 16 Mbit/s)
Programmable transaction size up to 32 bits
Standard SPI-bus modes 0, 1, 2 and 3
Manual or automatic slave select generation (up to 3 slaves)
Maskable transaction complete interrupt
LSB first or MSB first data transfer
Supports delayed read edges
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Fig 23. SPI-bus block diagram
The SPI-bus employs a simple shift register data transfer scheme. Data is clocked out of
and into the active devices in a first-in, first-out fashion allowing SPI-bus devices to
transmit and receive data simultaneously. Master-Out-Slave-In or Master-In-Slave-Out
data transfer is relative to the clock signal SPICLK generated by the JN5169.
The JN5169 provides 3-slave selects, SPISEL0 to SPISEL2 to allow three SPI-bus
peripherals on the bus. SPISEL0 is accessed on DI019. SPISEL1 is accessed, depending
upon the configuration, on DIO0 or DIO14. SPISEL2 is accessed on DIO1 or DIO15. This
is enabled under software control. The following table details which DIOs are used for the
SPISEL signals depending upon the configuration.
Table 4.
Signal
SPI-bus master I/O
DIO assignment
Standard pins
Alternative pins
SPISEL1
DIO0
DIO14
SPISEL2
DIO1
DIO15
SPICLK
DO0
SPIMISO
DO1
SPIMOSI
DIO18
SPISEL0
DIO19
The interface can transfer from 1-bit to 32-bit without software intervention and can keep
the slave select lines asserted between transfers when required, to enable longer
transfers to be performed.
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IEEE802.15.4 Wireless Microcontroller
When the device reset is active, all the SPI-bus master pins are configured as inputs with
their pull-up resistors active. The pins stay in this state until the SPI-bus master block is
enabled, or the pins are configured for some other use.
SLAVE 0
SLAVE 1
FLASH/
EEPROM
MEMORY
SI
C
SS
SO
SPISEL0
USER
DEFINED
SI
SPISEL1
C
SLAVE 2
SS
SO
USER
DEFINED
SI
C
SS
SO
SPISEL2
SPIMOSI
JN5169
SPICLK
SPIMISO
aaa-013133
Fig 24. Typical JN5169 SPI-bus peripheral connection
The data transfer rate on the SPI-bus is determined by the SPICLK signal. The JN5169
supports transfers at selectable data rates from 16 MHz to 125 kHz selected by a clock
divider. Both SPICLK clock phase and polarity are configurable. The clock phase
determines which edge of SPICLK is used by the JN5169 to present new data on the
SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. The
interface should be configured appropriately for the SPI-bus slave being accessed.
Table 5.
SPI-bus configurations
SPICLK
Mode
Description
0
0
SPICLK is low when idle - the first edge is positive. Valid data is
output on SPIMOSI before the first clock and changes every
negative edge. SPIMISO is sampled every positive edge.
0
1
1
SPICLK is low when idle – the first edge is positive. Valid data is
output on SPIMOSI every positive edge. SPIMISO is sampled
every negative edge.
1
0
2
SPICLK is high when idle – the first edge is negative. Valid data
is output on SPIMOSI before the first clock edge and is changed
every positive edge. SPIMISO is sampled every negative edge.
1
1
3
SPICLK is high when idle – the first edge is negative. Valid data
is output on SPIMOSI every negative edge. SPIMISO is
sampled every positive edge.
Polarity
Phase
0
If more than one SPISEL line is to be used in a system, they must be used in numerical
order starting from SPISEL0. A SPISEL line can be automatically de-asserted between
transactions if required, or it may stay asserted over a number of transactions. For
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JN5169
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IEEE802.15.4 Wireless Microcontroller
devices such as memories where a large amount of data can be received by the master
by continually providing SPICLK transitions, the ability for the select line to stay asserted
is an advantage since it keeps the slave enabled over the whole of the transfer.
A transaction commences with the SPI-bus being set to the correct configuration, and
then the slave device is selected. Upon commencement of transmission (1-bit to 32-bit)
data is placed in the FIFO data buffer and clocked out, at the same time generating the
corresponding SPICLK transitions. Since the transfer is full-duplex, the same number of
data bits is being received from the slave as it transmits. The data that is received during
this transmission can be read (1-bit to 32-bit). If the master simply needs to provide a
number of SPICLK transitions to allow data to be sent from a slave, it should perform
transmit using dummy data. An interrupt can be generated when the transaction has
completed or alternatively the interface can be polled.
If a slave device wishes to signal the JN5169 indicating that it has data to provide, it may
be connected to one of the DIO pins that can be enabled as an interrupt.
Figure 25 shows a complex SPI-bus transfer, reading data from a Flash device that can
be achieved using the SPI-bus master interface. The slave select line must stay low for
many separate SPI-bus accesses, and therefore manual slave select mode must be used.
The required slave select can then be asserted (active low) at the start of the transfer. A
sequence of 8-bit and 32-bit transfers can be used to issue the command and address to
the Flash device and then to read data back. Finally, the slave select can be deselected to
end the transaction.
instruction transaction
SPISELx[1]
0
1
2
3
4
6
5
7
9
8
10
28
29
30
31
SPICLK
Instruction (0x03)
24-bit address
23
MSB
SPIMOSI
22
21
3
2
1
0
SPIMISO
read data bytes transaction(s) 1-N
SPISELx[1]
0
1
2
3
4
6
5
7
8
9
10
8N-1
SPICLK
value unused by peripherals
SPIMOSI
SPIMISO
7
MSB
6
5
4
3
byte 1
2
1
0
6
7
MSB
5
3
2
1
0
LSB
byte 2
byte N
aaa-018154
(1) With x = 0, 1 or 2.
Fig 25. Example SPI-bus waveforms: reading from Flash device using mode 0
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9.8.2 SPI-bus slave
The SPI-bus slave interface allows high-speed synchronous data transfer between the
JN5169 and a peripheral device. The JN5169 operates as a slave on the SPI-bus and an
external device, connected to the SPI-bus operates as the master. The pins are different
from the SPI-bus master interface and are shown in the Table 6.
Table 6.
SPI-bus slave I/O
Signal
DIO assignment
Standard pins
Alternative pins
SPISCLK
DIO15
-
SPISMISO
DIO13
DIO17
SPISMOSI
DIO12
DIO16
SPISSEL
DIO14
-
The SPI-bus employs a simple shift register data transfer scheme, with SPISSEL acting
as the active-low select control. Data is clocked out of and into the active devices in a
first-in, first-out fashion allowing SPI-bus devices to transmit and receive data
simultaneously. Master-Out-Slave-In or Master-In-Slave-Out data transfer is relative to the
clock signal SPISCLK generated by the external master.
The SPI-bus slave includes the following features:
• Full-duplex synchronous data transfer
• Slaves to external clock up to 8 MHz
• Supports 8-bit transfers (MSB or LSB first configurable), with SPISSEL deasserted
between each transfer
• Internal FIFO up to 255 bytes for transmit and receive
• Standard SPI-bus mode 0; data is sampled on positive clock edge
• Maskable interrupts for receive FIFO not empty, transmit FIFO empty, receive FIFO fill
level above threshold, transmit FIFO below threshold, transmit FIFO overflow, receive
FIFO underflow, transmit FIFO underflow, receive time-out
• Programmable receive time-out period allows an interrupt to be generated to prompt
the receive FIFO to be read if no further data arrives within the time-out period
9.9 Timers
9.9.1 Peripheral timer/counters
A general-purpose timer/counter unit, Timer0, is available that can be configured to
operate in one of four possible modes:
1. Timer: can generate interrupts OFF rise and fall counts. Can be gated by external
signal
2. Counter: counts number of transitions on external event signal. Can use low-high,
high-low or both transitions PWM/Single pulse: outputs repeating Pulse Width
Modulation signal or a single pulse. Can set period and mark-space ratio
3. Capture: measures times between transitions of an applied signal
4. Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes
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The Timer functionality is as follows:
• Clocked from internal system clock (16 MHz)
• 5-bit prescaler, divides system clock by 2prescale as the clock to the timer (prescaler
range is 0 to 16)
• 16-bit counter, 16-bit Rise and Fall (period) registers
• Timer: can generate interrupts off Rise and Fall counts. Can be gated by external
signal
• Counter: counts number of transitions on external event signal. Can use low-high,
high-low or both transitions
• PWM/Single pulse: outputs repeating Pulse Width Modulation signal or a single pulse.
Can set period and mark-space ratio
• Capture: measures times between transitions of an applied signal
• Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes
• Timer usage of external IO can be controlled on a pin by pin basis
Four further timers are also available that support the same functionality but have no
counter or capture mode. These are referred to as PWM timers. Additionally, it is not
possible to gate these four timers with an external signal.
sw
reset
system
reset
interrupt
enable
single
shot
RESET
GENERATOR
interrupt
FALL
INTERRUPT
GENERATOR
-1
<
TIMxCAP(1)
CAPTURE
GENERATOR
RISE
=
TIMxCK_GT(1)
>=
EN
edge
select
D
COUNTER
PWM/∆Σ
Q
TIMxOUT(1)
PWM/∆Σ
EN
SYSCLK
PRESCALER
DELTA SIGMA
PWM/∆Σ
aaa-018994
(1) With x = 0.
Fig 26. Timer unit block diagram
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The clock source for the Timer0 unit is fed from the 16 MHz system clock. This clock
passes to a 5-bit prescaler where a value of 0 leaves the clock unmodified and other
values divide it by 2prescale. For example, a prescale value of 2 applied to the 16 MHz
system clock source results in a timer clock of 4 MHz.
The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the
gate function is selected, then the counter is frozen when the clock/gate input is high.
An interrupt can be generated whenever the counter is equal to the value in either of the
High or Low registers.
Table 7 details which DIOs are used for Timer0 and the PWM timers depending upon the
configuration.
Table 7.
Timer and PWM I/O
Signal
DIO assignment
Standard pins
Alternative pins
TIM0CK_GT
DIO8
DIO2
TIM0CAP
DIO9
DIO3
TIM0OUT
DIO10
DIO4
PWM1
DIO11
DIO5
PWM2
DIO12
DIO6
PWM3
DIO13
DIO7
PWM4
DIO17
DIO8
The alternative pin locations can be configured separately for each counter/timer under
software control, without affecting the operation or location of the others. If operating in
timer mode, it is not necessary to use any of the DIO pins, allowing the standard DIO
functionality to be available to the application.
9.9.2 Pulse Width Modulation mode
Pulse Width Modulation (PWM) mode, as used by PWM timers 1, 2, 3 and 4 and
optionally by Timer0, allows the user to specify an overall cycle time and pulse length
within the cycle. The pulse can be generated either as a single shot or as a train of pulses
with a repetition rate determined by the cycle time.
In this mode, the cycle time and low periods of the PWM output signal can be set by the
values of two independent 16-bit registers (fall and rise). The counter increments and its
output is compared to the 16-bit Rise and Fall registers. When the counter is equal to the
Rise register, the PWM output is set to high; when the counter reaches the Fall value, the
output returns to low. In continuous mode, when the counter reaches the Fall value, it will
reset and the cycle repeats. If either the cycle time or low periods are changed while in
continuous mode, the new values are not used until a full cycle has completed. The PWM
waveform is available on PWM1, 2, 3, 4 or TIM0OUT when the output driver is enabled.
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ULVH
IDOO
DDD
Fig 27. PWM output timings
9.9.3 Capture mode
The capture mode can be used to measure the time between transitions of a signal
applied to the capture input (TIM0CAP). When the capture is started, on the next
low-to-high transition of the captured signal, the count value is stored in the rise register,
and on the following high-to-low transition, the counter value is stored in the fall register.
The pulse width is the difference in counts in the two registers multiplied by the period of
the prescaled clock. Upon reading the capture registers, the counter is stopped. The
values in the high and low registers will be updated whenever there is a corresponding
transition on the capture input, and the value stored will be relative to when the mode was
started. Therefore, if multiple pulses are seen on TIM0CAP before the counter is stopped,
only the last pulse width will be stored.
9
5
3
4
CLK
TIMxCAP(1)
tr
tr
tf
tf
capture mode enabled
rise
x
9
x
fall
3
14
7
aaa-018997
(1) With x = 0.
Fig 28. Capture mode
9.9.4 Counter/timer mode
The counter/timer can be used to generate interrupts, based on the timers or event
counting, for software to use. As a timer, the clock source is from the system clock,
prescaled if required. The timer period is programmed into the Fall register and the Fall
register match interrupt enabled. The timer is started as either a single-shot or a repeating
timer, and generates an interrupt when the counter reaches the Fall register value.
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When used to count external events on TIM0CK_GT, the clock source is selected from the
input pin and the number of events programmed into the Fall register. The Fall register
match interrupt is enabled and the counter started, usually in single-shot mode. An
interrupt is generated when the programmed number of transitions is seen on the input
pin. The transitions counted can configure to be rising edges, falling edges or both rising
and falling edges.
Edges on the event signal must be at least 100 ns apart; that is pulses must be wider than
100 ns.
9.9.5 Delta-sigma mode
A separate delta-sigma mode is available, allowing a low-speed delta-sigma DAC to be
implemented with up to 16-bit resolution. This requires that a resistor-capacitor network is
placed between the output DIO pin and digital ground. A stream of pulses with digital
voltage levels is generated which is integrated by the RC network to give an analog
voltage. A conversion time is defined in terms of a number of clock cycles. The width of
the pulses generated is the period of a clock cycle. The number of pulses output in the
cycle, together with the integrator RC values, will determine the resulting analog voltage.
For example, generating approximately half the number of pulses that make up a
complete conversion period will produce a voltage on the RC output of VDD, provided the
RC time constant is chosen correctly. During a conversion, the pulses will be
pseudo-randomly dispersed throughout the cycle in order to produce a steady voltage on
the output of the RC network.
The output signal is asserted for the number of clock periods defined in the high register,
with the total period being 216 cycles. For the same value in the high register, the pattern
of pulses on subsequent cycles is different, due to the pseudo-random distribution.
The delta-sigma converter output can operate in a Return-To-Zero (RTZ) or
Non-Return-to-Zero (NRZ) mode. The NRZ mode will allow several pulses to be output
next to each other. The RTZ mode ensures that each pulse is separated from the next by
at least one period. This improves linearity if the rise and fall times of the output are
different to one another. Essentially, the output signal is low on every other output clock
period, and the conversion cycle time is twice the NRZ cycle time; that is 217 clocks. The
integrated output will only reach half VDDD in RTZ mode, since even at full scale only half
the cycle contains pulses. Figure 29 and Figure 30 illustrate the difference between RTZ
and NRZ for the same programmed number of pulses.
1
1
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Fig 29. Return-To-Zero mode in operation
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1
1
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Fig 30. Non-Return-To-Zero mode in operation
9.9.6 Example timer/counter application
Figure 31 shows an application of the JN5169 timers to provide closed-loop speed
control. Timer PWM1 is configured in PWM mode to provide a variable mark-space ratio
switching waveform to the gate of the NFET. This in turn controls the power in the DC
motor.
Timer 0 is configured to count the rising edge events on the CLK/GATE pin over a
constant period. This converts the tacho pulse stream output into a count proportional to
the motor speed. This value is then used by the application software executing the control
algorithm.
If required for other functionality, the unused IO associated with the timers could be used
as general-purpose DIO.
+12 V
1N4007
JN5169 PWM1
TIMER0
TACHO
M
IRF521
CLK/GATE
CAPTURE
PWM
1 pulse/rev
aaa-013134
Fig 31. Closed-loop PWM speed control using JN5169 timers
9.9.7 Tick timer
The JN5169 contains a hardware timer that can be used for generating timing interrupts to
software. It may be used to implement regular events such as ticks for software timers or
an operating system, as a high-precision timing reference or can be used to implement
system monitor time-outs as used in a watchdog timer. Features include:
• 32-bit counter
• 28-bit match value
• Maskable timer interrupt
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• Single-shot, restartable and continuous modes of operation
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Fig 32. Tick timer
The tick timer is clocked from a continuous 16 MHz clock, which is fed to a 32-bit wide
resettable up-counter, gated by a signal from the mode control block. A match register
allows comparison between the counter and a programmed value. The match value,
measured in 16 MHz clock cycles is programmed through software, in the range 0 to
0x0FFFFFFF. The output of the comparison can be used to generate an interrupt (if the
interrupt is enabled) and used in controlling the counter in the different modes. Upon
configuring the timer mode, the counter is also reset.
If the mode is programmed as single-shot, the counter begins to count from zero until the
match value is reached. The match signal will be generated which will cause an interrupt
(if enabled) and the counter will stop counting. The counter is restarted by reprogramming
the mode.
If the mode is programmed as restartable mode, the operation of the counter is the same
as for the single-shot mode, except that when the match value is reached the counter is
reset and begins counting from zero. An interrupt will be generated when the match value
is reached (if it is enabled).
Continuous mode operation is similar to restartable mode, except that when the match
value is reached the counter is not reset but continues to count. An interrupt will be
generated when the match value is reached (if enabled).
9.9.8 Wake-up timers
Two 41-bit wake-up timers are available on the JN5169, driven from the 32 kHz internal
clock. They may run during sleep periods when the majority of the rest of the device is
powered down, to time sleep periods or other long period timings that may be required by
the application. The wake-up timers do not run during deep sleep and may optionally be
disabled in sleep mode through software control. When a wake-up timer expires, it
typically generates an interrupt; if the device is asleep then the interrupt may be used as
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an event to end the sleep period. See Section 10 for further details on how the wake-up
timers are used during sleep periods. Features include:
• 41-bit down counter
• Optionally runs during sleep periods
• Clocked by 32 kHz system clock; either 32 kHz RC oscillator, 32 kHz XTAL oscillator
or 32 kHz clock input
A wake-up timer consists of a 41-bit down counter clocked from the selected 32 kHz
clock. An interrupt or wake-up event can be generated when the counter reaches zero. On
reaching zero, the counter will continue to count down until stopped, which allows the
latency in responding to the interrupt to be measured. If an interrupt or wake-up event is
required, the timer interrupt should be enabled before loading the count value for the
period. Once the counter value has been loaded and the counter started, the count-down
begins. The counter can be stopped at any time through software control - the counter will
remain at the value that it contained when it was stopped and no interrupt will be
generated. The status of the timers can be read to indicate if the timers are running and/or
have expired; this is useful when the timer interrupts are masked. This operation will reset
any expired status flags.
9.9.9 32 kHz RC oscillator calibration
The 32 kHz RC oscillator that can be used to time sleep periods is designed to require
very little power to operate and be self-contained, requiring no external timing
components and hence is lower cost. As a consequence of using on-chip resistors and
capacitors, the inherent absolute accuracy and temperature coefficient is lower than that
of a crystal oscillator, but once calibrated the accuracy approaches that of a crystal
oscillator. Sleep time periods should be as close to the desired time as possible in order to
allow the device to wake up in time for important events - for example, beacon
transmissions in the IEEE802.15.4 protocol. If the sleep time is accurate, the device can
be programmed to wake up very close to the calculated time of the event and so keep
current consumption to a minimum. If the sleep time is less accurate, it will be necessary
to wake up earlier in order to be certain that the event will be captured. If the device wakes
earlier, it will be awake for longer and so reduce battery life.
In order to allow sleep time periods to be as close to the desired length as possible, the
true frequency of the RC oscillator needs to be determined to better than the initial 30 %
accuracy. The calibration factor can then be used to calculate the true number of nominal
32 kHz periods needed to make up a particular sleep time. A calibration reference
counter, clocked from the 16 MHz system clock, is provided to allow comparisons to be
made between the 32 kHz RC clock and the 16 MHz system clock when the JN5169 is
awake and running from the 32 MHz crystal.
Wake-up Timer0 counts for a set number of 32 kHz clock periods during which the
reference counter runs. When the wake-up timer reaches zero the reference counter is
stopped, allowing software to read the number of 16 MHz clock ticks generated during the
time represented by the number of 32 kHz ticks programmed in the wake-up timer. The
true period of the 32 kHz clock can thus be determined and used when programming a
wake-up timer to achieve a better accuracy and hence more accurate sleep periods
For an RC oscillator running at exactly 32000 Hz, the value returned by the calibration
procedure should be 10000, for a calibration period of twenty 32000 Hz clock periods. If
the oscillator is running faster than 32000 Hz, then the count will be less than 10000; if
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running slower then the value will be higher. For a calibration count of 9000, indicating
that the RC oscillator period is running at approximately 35 kHz, in order to time for a
period of 2 seconds the timer should be loaded with 71,111 ((10000/9000) (32000 2))
rather than 64000.
9.10 Pulse counters
Two 16-pulse counters are provided that can increment during all modes of operation
(including sleep). The first pulse counter, PC0, increments from pulses received on DIO1
or DIO4. The other pulse counter, PC1, operates from DIO5 or DIO8 depending upon the
configuration. This is enabled under software control. The pulses can be de-bounced
using the 32 kHz clock to guard against false counting on slow or noisy edges. Increments
occur from a configurable rising or falling edge on the respective DIO input.
Each counter has an associated 16-bit reference that is loaded by the user. An interrupt
(and wake-up event, if asleep) may be generated when a counter reaches its
pre-configured reference value. The two counters may optionally be cascaded together to
provide a single 32-bit counter, linked to any of the four DIOs. The counters do not
saturate at 65535, but naturally roll-over to 0. Additionally, the pulse counting continues
when the reference value is reached without software interaction so that pulses are not
missed even if there is a long delay before an interrupt is serviced or during the wake-up
process.
The system can work with signals of up to 100 kHz with no debounce, or from 5.3 kHz to
1.7 kHz with debounce. When using debounce the 32 kHz clock must be active, so for
minimum sleep currents the debounce mode should not be used.
9.11 Serial communications
The JN5169 has two Universal Asynchronous Receiver/Transmitter (UART) serial
communication interfaces. These provide similar operating features to the industry
standard 16550A device operating in FIFO mode. The interfaces perform serial-to-parallel
conversion on incoming serial data and parallel-to-serial conversion on outgoing data from
the CPU to external devices. In both directions, a configurable FIFO buffer (with a default
depth of 16-byte) allows the CPU to read and write multiple characters on each
transaction. This means that the CPU is freed from handling data on a
character-by-character basis, with the associated high processor overhead. The UARTs
have the following features:
• Emulates behavior of industry standard NS16450 and NS16550A UARTs
• Configurable transmit and receive FIFO buffers (with default depths of 16 bytes for
each), with direct access to fill levels of each. Adds/deletes standard start, stop and
parity bits to/from the serial data
•
•
•
•
Independently controlled transmit, receive, status and data sent interrupts
Optional modem flow control signals CTS and RTS on UART0
Fully programmable data formats: baud rate, start, stop and parity settings
False start-bit detection, parity, framing and FIFO overrun error detect and break
indication
• Internal diagnostic capabilities: loopback controls for communications link fault
isolation
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• Flow control by software or automatically by hardware
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Fig 33. UART block diagram
The serial interfaces contain programmable fields that can be used to set number of data
bits (5, 6, 7 or 8), even, odd, set-at-1, set-at-0 or no-parity detection and generation of
single or multiple stop bit (for 5-bit data, multiple is 1.5 stop bits; for 6 data bits or 7 data
bits or 8 data bits, multiple is 2 bits).
The baud rate is programmable up to 1 Mbits/s, e.g. 4.8 kbits/s, 9.6 kbits/s, 19.2 kbits/s,
38.4 kbits/s.
For applications requiring hardware flow control, UART0 provides two control signals:
Clear-To-Send (CTS) and Request-To-Send (RTS). CTS is an indication sent by an
external device to the UART that it is ready to receive data. RTS is an indication sent by
the UART to the external device that it is ready to receive data. RTS is controlled from
software activities, while the value of CTS can be read. Monitoring and control of CTS and
RTS are software activity, normally performed as part of interrupt processing. The signals
do not control parts of the UART hardware, but simply indicate to software the state of the
UART external interfaces. Alternatively, the automatic flow control mode can be used, in
which the hardware controls the value of the generated RTS (negated if the receive FIFO
fill level is greater than a programmable threshold of 8 bytes, 11 bytes, 13 bytes or 15
bytes), and only transmits data when the incoming CTS is asserted.
Software can read characters, one byte at a time, from the receive FIFO and can also
write to the transmit FIFO, one byte at a time. The transmit and receive FIFOs can be
cleared and reset independently of each other. The status of the transmit FIFO can be
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checked to see if it is empty and if there is a character being transmitted. The status of the
receive FIFO can also be checked, indicating if a condition such as parity error, framing
error or break indication has occurred. It also shows if an overrun error has occurred
(receive buffer full and another character arrives) and if there is data held in the receive
FIFO.
UART0 and UART1 can both be configured to use standard or alternative DIO lines, as
shown in Table 8. Additionally, UART0 can be configured to be used in 2-wire mode
(where CTS0 and RTS0 are not configured), and UART1 can be configured in 1-wire
mode (where RXD1 is not configured). These freed up DIO pins can then be used for
other purposes.
Table 8.
UART I/O
Signal
DIO assignment
CTS0
Standard pins
Alternative pins
DIO4
DIO12
RTS0
DIO5
DIO13
TXD0
DIO6
DIO14
RXD0
DIO7
DIO15
TXD1
DIO14
DIO11
RXD1
DIO15
DIO9
Remark: With the automatic flow control threshold set to 15, the hardware flow control
within the UART’s block negates RTS when the Receive FIFO is about to become full. In
some instances, it has been observed that remote devices that are transmitting data do
not respond quickly enough to the de-asserted CTS and continue to transmit data. In
these instances, the data will be lost in a receive FIFO overflow
9.11.1 Interrupts
Interrupt generation can be controlled for the UART’s block and is divided into four
categories:
• Received Data Available: set when data in the RX FIFO queue reaches a particular
level (the trigger level can be configured as 1, 4, 8 or 14) or if no character has been
received for 4-character times.
• Transmit FIFO Empty: set when the last character from the TX FIFO is read and starts
to be transmitted
• Receiver Line Status: set when one of the following occurs
a. Parity Error - the character at the head of the receive FIFO has been received with
a parity error
b. Overrun Error - the RX FIFO is full and another character has been received at the
receiver shift register
c. Framing Error - the character at the head of the receive FIFO does not have a valid
stop bit
d. Break Interrupt – occurs when the RXD line has been held low for an entire
character
• Modem Status: generated when the CTS (Clear To Send) input control line changes.
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9.11.2 UART application
The following example shows the UART0 connected to a 9-pin connector compatible with
a PC. As the JN5169 device pins do not provide the RS232 line voltage, a level shifter is
used.
PC COM
port
1
6
JN5169
pin
signal
1
2
3
4
5
6
7
8
9
CD
RD
TD
DTR
SG
DSR
RTS
CTS
RI
5
9
TXD
CTS
RS232
RXD
LEVEL
SHIFTER
UART0
RTS
aaa-013135
Fig 34. JN5169 serial communication link
9.12 JTAG test interface
The JN5169 includes a JTAG interface for the purposes of software debugging when used
in conjunction with the BeyondStudio for NXP development environment.
For further details, see the NXP Wireless Connectivity TechZone Ref. 1.
The JTAG interface does not support boundary scan testing. It is recommended that the
JN5169 is not connected as part of the board scan chain.
9.13 2-wire serial interface (I2C-bus)
The JN5169 includes an industry-standard I2C-bus 2-wire synchronous serial interface
that can operate as a master (MSIF) or slave (SSIF), providing a simple and efficient
method of data exchange between devices. The system uses a serial data line (SIF_D)
and a serial clock line (SIF_CLK) to perform bidirectional data transfers and includes the
following features.
Common to both master and slave:
• Compatible with both I2C-bus and SMbus peripherals
• Support for 7-bit and 10-bit addressing modes
• Optional pulse suppression on signal inputs (60 ns guaranteed, 125 ns typical)
Master only:
•
•
•
•
JN5169
Product data sheet
Multi-master operation
Software-programmable clock frequency
Clock stretching and wait state generation
Software-programmable acknowledge bit
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• Interrupt or bit-polling driven byte-by-byte data-transfers
• Bus busy detection
Slave only:
•
•
•
•
•
2 programmable slave addresses
General call in 7-bit addressing
Simple byte-level transfer protocol
Write data flow control with optional clock stretching or acknowledge mechanism
Read data preloaded or provided as required.
The serial interface is accessed, depending upon the configuration, DIO14 and DIO15 or
DIO16 and DIO17. This is enabled under software control. The following table details
which DIOs are used for the serial interface depending upon the configuration.
Table 9.
2-wire serial interface I/O
Signal
DIO assignment
Standard pins
Alternative pins
SIF_CLK
DIO14
DIO16
SIF_D
DIO15
DIO17
9.13.1 Connecting devices
The clock and data lines, SIF_D and SIF_CLK, are alternative functions of DIO15 and
DIO14 respectively. The serial interface function of these pins is selected when the
interface is enabled. They are both bidirectional lines, connected internally to the positive
supply voltage via weak (50 k) programmable pull-up resistors. However, it is
recommended that external 4.7 k pull-ups be used for reliable operation at high bus
speeds, as shown in Figure 35. When the bus is free, both lines are HIGH. The output
stages of devices connected to the bus must have an open-drain or open-collector in
order to perform the wired-AND function. The number of devices connected to the bus is
solely dependent on the bus capacitance limit of 400 pF.
As this is an optional interface with two alternative positions, the DIO cells have not been
customized for I2C-bus operation. In particular, note that there are ESD diodes to the
nominal 3 volt supply (VDDD) from the SIF_CLK and SIF_D pins. Therefore, if the VDDD
supply is removed from the JN5169 and this then discharges to ground, a path would exist
that could pull down the bus lines (see Section 8.2.6).
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VDD
JN5169
RP
DIO14
SIF
DIO15
RP
pull-up
resistors
SIF_CLK
SIF_D
D1_IN
CLK1_IN
D2_IN
CLK2_IN
D1_OUT
CLK1_OUT
D2_OUT
CLK2_OUT
DEVICE 2
DEVICE 1
aaa-013136
Fig 35. Connection details
9.13.2 Clock stretching
Slave devices can use clock stretching to slow down the read transfer bit-rate. After the
master has driven SIF_CLK low, the slave can drive SIF_CLK low for the required period
and then release it. If the slave’s SIF_CLK low period is greater than the master’s low
period, then the resulting SIF_CLK bus signal low period is stretched, thus inserting wait
states.
FORFNKHOGORZ
E\VODYH
6,)B&/.
PDVWHU6,)B&/.
6,)B&/.
VODYH6,)B&/.
6,)B&/.
ZLUHGDQG6,)B&/.
DDD
Fig 36. Clock stretching
9.13.3 Master 2-wire serial interface
When operating as a master device, the 2-wire serial interface provides the clock signal
and a prescale register determines the clock rate, allowing operation up to 400 kbit/s.
Data transfer is controlled from the processor bus interface at a byte level, with the
processor responsible for indicating when start, stop, read, write and acknowledge control
should be generated. Data written into a transmit buffer will be transferred out across the
2-wire interface when prompted. Data received on the interface is made available in a
receive buffer from where it can be read. The completion of a particular transfer may be
indicated by means of an interrupt or detected by polling a status bit.
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The first byte of data transferred by the device after a start bit is the slave address. The
JN5169 supports both 7-bit and 10-bit slave addresses by generating either one or two
address transfers. Only the slave with a matching address will respond by returning an
acknowledge bit.
The master interface provides a true multi-master bus including collision detection and
arbitration that prevents data corruption. If two or more masters simultaneously try to
control the bus, a clock synchronization procedure determines the bus clock. Because of
the wired-AND connection of the interface, a high-to-low transition on the bus affects all
connected devices. This means a high-to-low transition on the SIF_CLK line causes all
concerned devices to count off their low period. Once the clock input of a device has gone
low, it will hold the SIF_CLK line in that state until the clock high state is reached when it
releases the SIF_CLK line. Due to the wired-AND connection, the SIF_CLK line will
therefore be held low by the device with the longest low period, and held high by the
device with the shortest high period.
VWDUWFRXQWLQJ
ORZSHULRG
VWDUWFRXQWLQJ
KLJKSHULRG
ZDLWHVWDWH
6,)B&/.
PDVWHU6,)B&/.
6,)B&/.
PDVWHU6,)B&/.
ZLUHGDQG6,)B&/.
6,)B&/.
DDD
Fig 37. Multi-master clock synchronization
After each transfer has completed, the status of the device must be checked to ensure
that the data has been acknowledged correctly, and that there has been no loss of
arbitration.
Remark: Loss of arbitration may occur at any point during the transfer, including data
cycles. An interrupt will be generated when arbitration has been lost.
9.13.4 Slave 2-wire serial interface
When operating as a slave device, the 2-wire serial interface does not provide a clock
signal, although it may drive the clock signal low if it is required to apply clock stretching.
The interface allows both 7-bit and 10-bit addresses to be used. Only transfers which
have an address that matches a value programmed into the interface’s Address register
are accepted. This address match could be due to a general call access to either of the
configurable 7-bit slave addresses or to the configurable 10-bit slave address. Addresses
defined as “reserved” will not be responded to and should not be programmed into the
Address register. A list of reserved addresses is shown in Table 10.
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Table 10.
List of 2-wire serial interface reserved addresses
Address
Name
Behavior
0000 000
general call/start byte
responded if 7-bit addressing is set
0000 001
CBUS address
ignored
0000 010
reserved
ignored
0000 011
reserved
ignored
0000 1XX
HS-mode master code
ignored
1111 1XX
reserved
ignored
1111 0XX
10-bit address
only responded on first slave address
if 10-bit address set in address register
Data transfer is controlled from the processor bus interface at a byte level, with the
processor responsible for taking write data from a receive buffer and providing read data
to a transmit buffer when prompted. A series of interrupt status bits are provided to control
the flow of data.
For writes into the slave interface, it is important that data is taken from the receive buffer
by the processor before the next byte of data arrives. To enable this, the interface returns
a Not Acknowledge (NACK) to the master if more data is received before the previous
data has been taken. This will lead to the termination of the current data transfer.
For reads from the slave interface, the data may be preloaded into the transmit buffer
when it is empty (i.e. at the start of day, or when the last data has been read), or fetched
each time a read transfer is requested. When using data preload, read data in the buffer
must be replenished following a data write, as the transmit and receive data is contained
in a shared buffer. The interface will hold the bus using clock stretching when the transmit
buffer is empty.
Interrupts may be triggered when:
• Data Buffer read data is required – a byte of data to be read should be provided to
avoid the interface from clock stretching
• Data Buffer read data has been taken – this indicates when the next data may be
preloaded into the data buffer
• Data Buffer write data is available – a byte of data should be taken from the data
buffer to avoid data backoff as defined above
• The last data in a transfer has completed – i.e. the end of a burst of data, when a Stop
or Restart is seen
• A protocol error has been spotted on the interface
9.14 Random number generator
A random number generator is provided which creates a 16-bit random number each time
it is invoked. Consecutive calls can be made to build up any length of random number.
Each call takes approximately 0.25 ms to complete. Alternatively, continuous generation
mode can be used where a new number is generated approximately every 0.25 ms. In
either mode of operation, an interrupt can be generated to indicate when the number is
available, or a status bit can be polled.
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The random bits are generated by sampling the state of the 32 MHz clock every 32 kHz
system clock edge. As these clocks are asynchronous to each other, each sampled bit is
unpredictable and hence random.
9.15 Analog peripherals
The JN5169 contains a number of analog peripherals allowing the direct connection of a
wide range of external sensors and switches.
chip boundary
supply voltage
(VDD)
Vref
internal reference
Vref select
ADC1
VREF/ADC2
ADC
ADC3 (DIO0)
ADC4 (DIO1)
ADC5 (DIO2)
ADC6 (DIO3)
temp
sensor
COMP1P (DIO16)
comparator 1
COMP1M (DIO17)
aaa-017086
Fig 38. Analog peripherals
In order to provide good isolation from digital noise, the analog peripherals and radio are
powered by the radio regulator, which is supplied from the analog supply VDDA and
referenced to analog ground VSSA.
A reference signal Vref for the ADC can be selected to be an internal band gap reference
or an external voltage reference supplied to the VREF pin. ADC input 2 cannot be used if
an external reference is required, as this uses the same pin as VREF. Note also that
ADC3, ADC4, ADC5 and ADC6 use the same pins as DIO0, DIO1, DIO2 and DIO3
respectively. These pins can only be used for the ADC if they are not required for any of
their alternative functions. Similarly, the comparator inputs are shared with DIO16 and
DIO17. If used for their analog functions, these DIOs must be put into a passive state by
configuring them as inputs with their pull-ups disabled.
The ADC is clocked from a common clock source derived from the 16 MHz clock.
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9.15.1 Analog to Digital Converter (ADC)
The 10-bit ADC uses a successive approximation design to perform high accuracy
conversions as typically required in wireless sensor network applications. It has 8
multiplexed single-ended input channels: 6 available externally, 1 connected to an internal
temperature sensor, and 1 connected to an internal supply monitoring circuit.
9.15.1.1
Operation
The input range of the ADC can be set to be from 0 V to either the reference voltage or
twice the reference voltage. The reference can be either taken from the internal voltage
reference or from the external voltage applied to the VREF pin. For example, an external
reference of 1.2 V supplied to VREF may be used to set the ADC range between 0 V and
2.4 V.
Table 11.
ADC maximum input range
VREF
Gain setting
Maximum input range Supply voltage range (VDDD)
1.2 V
0
1.2 V
2.2 V to 3.6 V
1.6 V
0
1.6 V
2.2 V to 3.6 V
1.2 V
1
2.4 V
2.6 V to 3.6 V
1.6 V
1
3.2 V
3.4 V to 3.6 V
The input clock to the ADC is 16 MHz and can be divided down to 2 MHz, 1 MHz, 500 kHz
or 250 kHz. During an ADC conversion, the selected input channel is sampled for a fixed
period and then held. This sampling period is defined as a number of ADC clock periods
and can be programmed to 2, 4, 6 or 8. The conversion period is ((3 sample period)
+ 13) clock periods. For example, for a 500 kHz conversion with a sample period of 2, the
conversion period is ((3 2) + 13) = 19 clock periods, which is equal to 38 s and
equivalent to a conversion rate of 26.32 kHz. The ADC can be operated in either a single
conversion mode or alternatively a new conversion can be started as soon as the previous
one has completed, to give continuous conversions.
If the source resistance of the input voltage is 1 kW or less, then the default sampling time
of 2 clocks should be used. The input to the ADC can be modeled as a resistor of
5 k (typ.) and 10 k (max.) to represent the on-resistance of the switches and the
sampling capacitor 8 pF. The sampling time required can then be calculated by adding the
sensor source resistance to the switch resistance, multiplying by the capacitance to give a
time constant. Assuming normal exponential RC charging, the number of time constants
required to give an acceptable error can be calculated; 7-time constants gives an error of
0.091 %, so for 10-bit accuracy 7 time constants should be the target. For a source with
zero resistance, 7-time constant is 640 ns, hence the smallest sampling window of 2 clock
periods can be used.
ADCx(1)
pins
5 kΩ
sample
switch
ADC
FRONT
END
8 pF
aaa-017253
(1) With x = 0, 1, 2, 3, 4, 5 or 6.
Fig 39. ADC input equivalent circuit
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The ADC sampling period, input range and mode (single-shot or continuous) are
controlled through software.
When the ADC conversion is complete, an interrupt is generated. Alternatively the
conversion status can be polled. When operating in continuous mode, it is recommended
that the interrupt is used to signal the end of a conversion, since conversion times may
range from 9.5 s to 148 s. Polling over this period would be wasteful of processor
bandwidth.
To facilitate the averaging of the ADC values, which is common practice in
microcontrollers, a dedicated accumulator has been added. The user can configure the
accumulation to occur over 2, 4, 8 or 16 samples. The end of conversion interrupt can be
modified to occur at the end of the chosen accumulation period. Alternatively polling can
still be used. Software can then be used to apply the appropriate rounding and shifting to
generate the average value, as well as setting up the accumulation function.
For detailed electrical specifications, see Section 14.3.7.
9.15.1.2
Supply monitor
The internal supply monitor allows the voltage on the analog supply pin VDDA to be
measured. This is achieved with a potential divider that scales the voltage by a factor of
0.666, allowing it to fall inside the input range of the ADC when set with an input range up
to twice the internal voltage reference. The resistor chain that performs the voltage
reduction is disabled until the measurement is made to avoid a continuous drain on the
supply.
9.15.1.3
Temperature sensor
The on-chip temperature sensor can be used either to provide an absolute measure of the
device temperature or to detect changes in the ambient temperature. In common with
most on-chip temperature sensors, it is not trimmed and so the absolute accuracy
variation is large; the user may wish to calibrate the sensor prior to use. The sensor forces
a constant current through a forward biased diode to provide a voltage output proportional
to the chip die temperature which can then be measured using the ADC.
Because this sensor is on-chip, any measurements taken must account for the thermal
time constants. For example, if the device has just come out of sleep mode, the user
application should wait until the temperature has stabilized before taking a measurement.
9.15.1.4
ADC sample buffer mode
In this mode, the ADC operates in conjunction with a Direct Memory Access (DMA)
engine as follows:
• ADC sampling is triggered at a configurable rate using one of the on-chip timers
(TimerX, where X = 1, 2, 3 or 4)
• ADC samples are automatically stored in a buffer located in RAM using a DMA
mechanism
• ADC inputs may be multiplexed between different analog sources
The 10-bit ADC data samples are transferred into the buffer in RAM as 16-bit words. The
maximum number of 16-bit words that may be allocated in RAM for ADC sample storage
is 2047.
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The buffer may be configured to automatically wrap around to the start when full.
Interrupts may be configured to indicate when the buffer is half-full, full or has overflowed.
The CPU may perform other tasks while the data transfer and storage is being managed
independently by the DMA engine - the CPU only needs to configure the ADC sample
buffer mode and deal with the stored samples in the buffer when an interrupt occurs.
ADC sample buffer mode allows up to eight analog inputs to be multiplexed in
combination. These inputs comprise six external inputs (ADC1 to 6, corresponding to IO
pins), an on-chip temperature sensor and an internal voltage monitor. Samples from all
the selected inputs will be produced on each timer trigger and stored in consecutive RAM
locations.
9.15.2 Comparator
The JN5169 contains one analog comparator, COMP1, that is designed to have true
rail-to-rail inputs and operate over the full voltage range of the analog supply VDDA. The
hysteresis level can be set to a nominal value of 0 mV, 10 mV, 20 mV or 40 mV. The
source of the negative input signal for the comparator can be set to the internal voltage
reference, the negative external pin (COMP1M, which uses the same pin as DIO17) or the
positive external pin (COMP1P, on the same pin as DIO16). The source of the positive
input signal can be COMP1P or COMP1M. DIO16 and DIO17 cannot be used if the
external comparator inputs are needed. The comparator output is routed to an internal
register and can be polled, or can be used to generate interrupts. The comparator can be
disabled to reduce power consumption. DIO16 and DIO17 should be configured as inputs
with pull-ups disabled when using the comparator.
The comparator also has a low-power mode in which the response time of the comparator
is slower in the normal mode, but the current required is greatly reduced. These figures
are specified in Section 14.3.8. It is the only mode that may be used during sleep, where a
transition of the comparator output will wake the device. The wake-up action and the
configuration of which edge of the comparator output will be active are controlled through
software. In sleep mode, the negative input signal source must be configured to be driven
from the external pins.
10. Power management and sleep modes
10.1 Operating modes
Three operating modes are provided in the JN5169 that enable the system power
consumption to be controlled carefully to maximize battery life.
• Active processing mode
• Sleep mode
• Deep sleep mode
The variation in power consumption of the three modes is a result of having a series of
power domains within the chip that may be controllably powered ON or OFF.
10.1.1 Power domains
The JN5169 has the following power domains:
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• VDD supply domain: supplies the wake-up timers and controller, DIO blocks,
comparator, SVM and BOR plus Fast RC, 32 kHz RC and crystal oscillators. This
domain is driven from the external supply (battery) and is always powered. The
wake-up timers and controller, and the 32 kHz RC and crystal oscillators may be
powered ON or OFF in sleep mode through software control.
• Digital logic domain: supplies the digital peripherals, CPU, Flash memory, RAM (when
in active processing mode), baseband controller, modem and encryption processor. It
is powered off during sleep mode.
• RAM domain: supplies the RAM when in active processing mode. Also supplies the
RAM during sleep mode to retain the memory contents. It may be powered ON or
OFF for sleep mode through software control.
• Radio domain: supplies the radio interface, ADCs and temperature sensor. It is
powered during transmission and reception and when the analog peripherals are
enabled. It is controlled by the baseband processor and is powered OFF during sleep
mode.
The current consumption figures for the different modes of operation of the device are
given in Section 14.1.
10.2 Active processing mode
Active processing mode in the JN5169 is where all of the application processing takes
place. By default, the CPU will execute application firmware at the selected clock speed.
All of the peripherals are available to the application, as are options to actively enable or
disable them to control power consumption; see specific peripheral sections for details.
While in active processing mode there is the option to doze the CPU but keep the rest of
the chip active; this is particularly useful for radio transmit and receive operations, where
the CPU operation is not required, therefore saving power.
10.2.1 CPU doze
While in doze mode, CPU operation is stopped but the chip remains powered and the
digital peripherals continue to run. Doze mode is entered through software and is
terminated by any interrupt request. Once the interrupt service routine has been executed,
normal program execution resumes. Doze mode uses more power than sleep and deep
sleep modes but requires less time to restart and can therefore be used as a low-power
alternative to an idle loop.
While in CPU doze, the CPU is not drawing current and therefore the basic device current
is reduced.
10.3 Sleep mode
The JN5169 enters sleep mode through software control. In this mode, most of the
internal chip functions are shut down to save power. However the states of the DIO pins
are retained, including the output values and pull-up enables, and this therefore preserves
any interface to the outside world.
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When entering into sleep mode, there is an option to retain the RAM contents throughout
the sleep period. If the wake-up timers are not to be used for a wake-up event and the
application does not require them to run continually, power can be saved by switching off
the 32 kHz oscillator if selected as the 32 kHz system clock through software control. The
oscillator will be restarted when a wake-up event occurs.
While in sleep mode, one of four possible events can cause a wake-up to occur:
transitions on DIO inputs, expiry of wake-up timers, pulse counters maturing or
comparator events. If any of these events occur and the relevant interrupt is enabled, an
interrupt is generated that will cause a wake-up from sleep. It is possible for multiple
wake-up sources to trigger an event at the same instant but only one of them will be
accountable for the wake-up period. It is therefore necessary in software to remove all
other pending wake-up events prior to requesting entry back into sleep mode; otherwise,
the device will reawaken immediately.
When wake-up occurs, a similar sequence of events to the reset process described in
Section 9.4 happens, including the checking of the supply voltage by the Supply Voltage
Monitor (Section 9.4.4). The high-speed RC oscillator is started up and, once stable, the
power to CPU system is enabled and the reset is removed. Software determines that this
is a reset from sleep and so commences with the wake-up process. If RAM contents were
held through sleep, wake-up is quicker as the software does not have to initialize RAM
contents meaning the application can recommence more quickly. See Section 14.3.5 for
wake-up timings.
10.3.1 Wake-up timer event
The JN5169 contains two 41-bit wake-up timers that are counters clocked from the
32 kHz oscillator, and can be programmed to generate a wake-up event. Following a
wake-up event, the timers continue to run. These timers are described in Section 9.9.8.
Timer events can be generated from both timers; one is intended for use by the
IEEE802.15.4 protocol, the other being available for use by the application running on the
CPU. These timers are available to run at any time, even during sleep mode.
10.3.2 DIO event
Any DIO pin when used as an input has the capability, by detecting a transition, to
generate a wake-up event. Once this feature has been enabled, the type of transition can
be specified (rising or falling edge). Even when groups of DIO lines are configured for
alternative functions, such as the UARTs or timers, any input line in the group can still be
used to provide a wake-up event. This means that an external device communicating over
the UART can wake up a sleeping device by asserting its RTS signal pin (which is the
CTS input of the JN5169).
10.3.3 Comparator event
The comparator can generate a wake-up interrupt when a change in the relative levels of
the positive and negative inputs occurs. The ability to wake up when continuously
monitoring analog signals is useful in ultra-low power applications. For example, the
JN5169 can remain in sleep mode until the voltage drops below a threshold and then be
woken up to deal with the alarm condition; the comparator has a low current mode to
facilitate this.
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10.3.4 Pulse counter
The JN5169 contains two 16-bit pulse counters that can be programmed to generate a
wake-up event. Following the wake-up event the counters will continue to operate and
therefore no pulse will be missed during the wake-up process. These counters are
described in Section 9.10.To minimize sleep current it is possible to disable the 32 kHz
RC oscillator and still use the pulse counters to cause a wake-up event, provided
debounce mode is not required.
10.4 Deep sleep mode
Deep sleep mode gives the lowest power consumption. All switchable power domains are
off and most functions in the VDD supply power domain are stopped, including the 32 kHz
RC oscillator. However, the Brown-Out Reset remains active as well as all the DIO cells.
This mode can be exited by a hardware reset on the RESET_N pin, or an enabled DIO or
comparator wake-up event. In all cases, the wake-up sequence is equivalent to a
power-up sequence, with no knowledge retained from the previous time the device was
awake.
11. Limiting values
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDDA
analog supply voltage
VDDD
digital supply voltage
VDD(regd)
Conditions
regulated supply voltage
on pins VB_xx
Min
Max
Unit
0.3
+3.6
V
0.3
+3.6
V
[1]
0.3
+1.98
V
VXTAL_OUT
voltage on pin XTAL_OUT
[1]
0.3
VB_xx + 0.3
V
VXTAL_IN
voltage on pin XTAL_IN
[1]
0.3
VB_xx + 0.3
V
VRF_IO
voltage on pin RF_IO
[1]
0.3
VB_xx + 0.3
V
VVREF
voltage on pin VREF
0.3
VDDA + 0.3
V
VADC1
voltage on pin ADC1
0.3
VDDA + 0.3
V
VIBIAS
voltage on pin IBIAS
0.3
VDDA + 0.3
V
VIO(dig)
digital input/output voltage
0.3
VDDD + 0.3
V
Tstg
storage temperature
VESD
[1]
electrostatic discharge voltage
40
+150
C
HBM
[2]
-
2000
V
CDM
[3]
-
1000
V
With xxx = SYNTH or VCO or RF2 or RF1 or DIG.
[2]
Testing for HBM discharge is performed as specified in JEDEC Standard JS-001.
[3]
Testing for CDM discharge is performed as specified in JEDEC Standard JESD22-C101.
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12. Recommended operating conditions
Table 13.
Operating conditions
Symbol
Parameter
Conditions
VDDA
analog supply voltage
VDDD
digital supply voltage
Tamb
ambient temperature
[1]
[1]
standard range
Min
Max
Unit
2
3.6
V
2
3.6
V
40
+125
C
To reach the maximum TX power, 2.8 V is the minimum.
13. Thermal characteristics
Table 14.
Thermal characteristics
Symbol
Parameter
Rth(j-a)
Tj(max)
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to ambient
-
29.9
-
K/W
maximum junction temperature
-
-
125
C
Min
Typ
Max
Unit
32 MHz
-
7.8
-
mA
16 MHz
-
5.1
-
mA
8 MHz
-
3.8
-
mA
4 MHz
-
3
-
mA
2 MHz
-
2.6
-
mA
1 MHz
-
2.5
-
mA
radio in receive mode; maximum input level
at 10 dBm
-
15
-
mA
radio in receive mode; maximum input level
at 10 dBm; VDD = 3 V; Tamb = 25 °C
-
14.7
-
mA
radio in receive mode; maximum input level
at 0 dBm
-
13
-
mA
14. Characteristics
14.1 DC current
Table 15. Active processing
VDD = 2 V to 3.6 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
IDD
Parameter
supply current
Conditions
CPU processing at:
[1]
CPU in software doze -
radio in transmit mode 10 dBm
[2]
-
23.3
-
mA
radio in transmit mode 8.5 dBm
[2]
-
19.6
-
mA
-
14
-
mA
-
400
-
A
radio in transmit mode 3 dBm
II(ADC)
[3]
ADC input current
[4]
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Table 15. Active processing …continued
VDD = 2 V to 3.6 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
IDD(comp)
Parameter
comparator supply
current
Conditions
operating mode
IDD(tmr)
IDD(sintf)
UART supply current
timer supply current
Typ
Max
Unit
-
73
-
A
-
0.8
-
A
per UART
[4]
-
60
-
A
per timer
[4]
-
60
-
A
[4]
-
50
-
A
Min
Typ
Max
Unit
-
0.10
-
A
in sleep mode; with I/O and RC oscillator
timer wake-up; Tamb = 25 C
-
0.73
-
A
for 32 kHz crystal oscillator
-
0.6
-
A
low-power mode
IDD(UART)
Min
[4]
serial interface supply
current
[1]
Digital consumption only. When in CPU doze, the current related to CPU speed is not consumed.
[2]
To reach the maximum TX power, 2.8 V is the minimum.
[3]
Temperature sensor and battery measurements require ADC.
[4]
These numbers should be added to IDD if the feature is being used.
Table 16. Sleep mode
VDD = 2 V to 3.6 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
IDDD(IO)
Parameter
input/output digital
supply current
Conditions
in sleep mode; with I/O wake-up;
Tamb = 25 °C
[1]
IDD(xtal)
crystal oscillator
supply current
Iret(RAM)
RAM retention current Tamb = 25 C
[2]
-
0.7
-
A
comparator supply
current
[2]
-
0.8
-
A
Min
Typ
Max
Unit
-
50
-
nA
IDD(comp)
low-power mode
[3]
[1]
Waiting on I/O event.
[2]
RAM and comparator supply currents should be added to IDDD(IO)(sleep) if the feature is being used.
[3]
Reduced response time.
Table 17. Deep sleep mode
VDD = 2 V to 3.6 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
IDDD
[1]
Parameter
Conditions
digital supply current
deep sleep mode; measured at 25 C
[1]
Waiting on chip RESET or I/O event.
14.2 I/O characteristics
Table 18. I/O characteristics
VDD = 2 V to 3.6 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
Rpu(int)(DIO)
Parameter
Conditions
internal pull-up resistance on pins
JN5169
Product data sheet
DIOx[1]
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Rev. 1 — 5 August 2015
Min
Typ
Max
Unit
40
50
60
k
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Table 18. I/O characteristics …continued
VDD = 2 V to 3.6 V; Tamb = 40 C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rpu(int)(RESET_N) internal pull-up resistance on pin RESET_N VDD = 3.6 V
300
425
550
k
VDD = 3.0 V
400
500
700
k
VDD = 2.2 V
650
830
1100
k
VDD = 2.0 V
750
950
1350
k
VDD
V
0.27V
V
Digital voltages
I/O
HIGH-level input voltage
VIH
0.7VD D
0.3
LOW-level input voltage
VIL
-
DD
Vhys(i)
input hysteresis voltage
200
310
400
mV
Output on pins DIOx[1]
VOH
HIGH-level output voltage
6.8 mA load
VDD 0.4
VDD
V
VOL
LOW-level output voltage
6.8 mA load
0
-
0.4
V
ILIL
LOW-level input leakage current
VDD = 3.6 V; Tamb = 25 C
-
2
-
nA
ILIH
HIGH-level input leakage current
VDD = 3.6 V; Tamb = 25 C
-
2
-
nA
Currents
[1]
With x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 or 19.
14.3 AC characteristics
14.3.1 Reset and Supply Voltage Monitor
Vth(POR)
VDD
internal RESET
tstab
aaa-017254
Fig 40. Internal Power-On Reset without showing Brown-Out
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RESET_N
trst
Vrst
internal RESET
tstab
aaa-017255
Fig 41. Externally applied reset
Table 19.
Externally applied reset
Symbol
Parameter
Conditions
trst
reset time
external reset pulse width to
initiate reset sequence
Vrst
reset voltage
external threshold voltage
Vth(POR)
power-on reset threshold voltage
rise time > 10 ms
spike
spike rejection
Min
Typ
Max
Unit
[1]
1
-
-
s
[2]
0.7VDD
-
-
V
rising
-
1.44
-
V
falling
-
1.41
-
V
-
1.2
-
V
-
1.3
-
V
-
180
-
s
depth of pulse to trigger reset
1 s square wave
10 s triangular wave
tstab
stabilization time
reset
IDD
supply current
chip current when held in reset
Irst(bo)
brownout reset current
Vth
threshold voltage
Vhys
hysteresis voltage
JN5169
Product data sheet
[3]
supply threshold voltage
monitor; configurable in eight
levels
supply voltage monitor;
corresponding to the eight
threshold levels
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Rev. 1 — 5 August 2015
-
6
-
A
-
80
-
nA
1.86
1.94
2.00
V
1.92
2.00
2.06
V
2.02
2.10
2.16
V
2.11
2.20
2.27
V
2.21
2.30
2.37
V
2.30
2.40
2.47
V
2.59
2.70
2.78
V
2.88
3.00
3.09
V
-
37
-
mV
-
38
-
mV
-
45
-
mV
-
52
-
mV
-
58
-
mV
-
65
-
mV
-
82
-
mV
-
100
-
mV
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[1]
Assumes internal pull-up resistor value of 100 k worst case and 5 pF external capacitance.
[2]
Minimum voltage to avoid being reset.
[3]
Time from release of reset to start of executing of bootloader code from internal Flash. An extra 15 s is incurred if the BOR circuit has
been activated (e.g. if the supply voltage has been ramped up from 0 V).
Vth + Vhys
Vth(POR)
Vth(POR)
Vth
VDDD
internal SVM
internal BOReset
aaa-017274
Fig 42. Brown-Out Reset followed by Supply Voltage Monitor trigger
14.3.2 SPI-bus master timing
SPISELx(1)
tsu(S)
th(S)
SPICLK
(mode = 0, 1)
Tclk
SPICLK
(mode = 2, 3)
th(D)
SPIMISO
(mode = 0, 2)
tsu(D)
th(D)
SPIMISO
(mode = 1, 3)
td(Q)
tsu(D)
SPIMOSI
(mode = 1, 3)
td(Q)
SPIMOSI
(mode = 0, 2)
aaa-017275
(1) With x = 0, 1 or 2.
Fig 43. SPI-bus master timing
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Table 20.
SPI-bus master timing
Symbol
Parameter
Tclk
clock period
tsu(D)
data input set-up time
Conditions
th(D)
data input hold time
td(Q)
data output delay time
tsu(S)
chip select set-up time
th(S)
chip select hold time
Min
Typ
Max
Unit
62.5
-
-
ns
3.3 V
12.5
-
-
ns
2.7 V
13
-
-
ns
2.0 V
14
-
-
ns
0
-
-
ns
-
-
15
ns
60
-
-
ns
SPICLK = 16 MHz
30
-
-
ns
SPICLK < 16 MHz; mode = 0 or 2
0
-
-
ns
SPICLK < 16 MHz; mode = 1 or 3
60
-
-
ns
on SPIMOSI
14.3.3 SPI-bus slave timing
SPISSEL
Tclk
tidle
tsu(S)
th(S)
SPISCLK
th(D)
tsu(D)
SPISMOSI
td(S-Q)
td(C-Q)
SPISMISO
aaa-017276
Fig 44. SPI-bus slave timing
Table 21.
SPI-bus slave timing
Symbol
Parameter
Tclk
Min
Typ
Max
Unit
clock period
125
-
-
ns
tidle
idle time
125
-
-
ns
tsu(D)
data input set-up time
10
-
-
ns
th(D)
data input hold time
10
-
-
ns
td(C-Q)
clock to data output
delay time
-
-
30
ns
JN5169
Product data sheet
Conditions
SPISCLK falling edge to SPISMISO output
delay time
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Table 21.
SPI-bus slave timing
Symbol
Parameter
Min
Typ
Max
Unit
td(S-Q)
chip select to data output SPISSEL falling edge to SPISMISO output
delay time
delay time
-
-
30
ns
tsu(S)
chip select set-up time
SPISSEL falling edge to SPISCLK rising edge
delay time
30
-
-
ns
th(S)
chip select hold time
SPISCLK falling edge to SPISSEL rising edge
delay time
30
-
-
ns
Conditions
14.3.4 2-wire serial interface
SIF_D
tSU;DAT
tr
tf
tHD;STA
tr
tw(spike)
tBUF
t(SIF_CLK)L
SIF_CLK
tHD;STA tHD;DAT
tf
t(SIF_CLK)H
S
tSU;STA
tSU;STO
Sr
P
S
aaa-017277
Fig 45. 2-wire serial interface timing
Table 22.
2-wire serial interface
Symbol
Parameter
Conditions
Standard mode
Min
fclk
clock frequency
tHD;STA
hold time (repeated)
START condition
t(SIF_CLK)L
LOW period of the
SIF_CLK clock
SIF_CLK; DIO14; pin 38
set-up time for a
repeated START
condition
tSU;DAT
data set-up time
Max
Min
Unit
Max
0
100
0
400
kHz
4
-
0.6
-
s
4.7
-
1.3
-
s
4
-
0.6
-
s
4.7
-
0.6
-
s
data setup time SIF_D
0.25
-
0.1
-
s
-
0[2]
-
s
[1]
t(SIF_CLK)H HIGH period of the
SIF_CLK clock
tSU;STA
Fast mode
tHD;DAT
data hold time
data hold time SIF_D
0[2]
tr
rise time
rise time SIF_D and SIF_CLK
-
1000
20 + 0.1Cb 300
ns
tf
fall time
fall time SIF_D and SIF_CLK
-
300
20 + 0.1Cb 300
ns
tSU;STO
set-up time for STOP
condition
4
-
0.6
-
s
tBUF
bus free time
between a STOP
and START
condition
4.7
-
1.3
-
s
tw(spike)
spike pulse width
-
60
-
60
ns
JN5169
Product data sheet
pulse width of spikes that will be
suppressed by input filters
[1]
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Table 22.
2-wire serial interface
Symbol
Parameter
Conditions
Standard mode
Min
Cb
capacitive load for
each bus line
-
VnL
noise margin at the
LOW level
noise margin at the LOW level for
each connected device (including
hysteresis)
VnH
noise margin at the
HIGH level
noise margin at the HIGH level for
each connected device (including
hysteresis)
Fast mode
Max
400
Min
Unit
Max
-
400
pF
0.1VDD -
0.1VDD
-
V
0.2VDD -
0.2VDD
-
V
[1]
After this period, the first clock pulse is generated.
[2]
A device must internally provide a hold time of at least 300 ns for the SIF_D signal (with respect to the VIH(min) of the SIF_CLK signal) to
bridge the undefined region of the falling edge of SIF_CLK.
14.3.5 Wake-up timings
Table 23.
Wake-up timings
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tstartup
start-up time
CPU start-up time; time for crystal to stabilize
ready to run CPU; reached oscillator amplitude
threshold. Default bias current
-
0.74
-
ms
radio start-up time; time for crystal to stabilize
ready for radio activity
-
1
-
ms
from reset RESET_N pin, BOR or SVM
-
180
-
s
twake
wake-up time
from deep sleep mode or from sleep mode
-
170
-
s
twake
wake-up time
from CPU Doze mode
-
0.2
-
s
14.3.6 Band gap reference
Table 24. Band gap reference
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
VDDA(bg)
band gap analog
supply voltage
Conditions
Min
Typ
Max
Unit
1.198
1.235
1.260
V
14.3.7 Analog to Digital Converters
Table 25. Analog to Digital Converters
VDD = 3 V; Vref = 1.2 V; Tamb = -40 C to +125 C; unless otherwise specified.
Symbol
Vi
Vref
Parameter
input voltage
reference voltage
Conditions
Min
Typ
Max
Unit
switchable
[1]
0.04
-
2Vref
V
internal
[2]
-
-
-
V
-
1.2
-
V
-
400
-
A
-
1.6
-
LSB
external; allowable range into VREF pin
IADCx
current on pins ADCx[3]
INL
integral non-linearity
Tamb = 40 C to +85 C
DNL
differential non-linearity
guaranteed monotonic
Tamb = 40 C to +125 C
JN5169
Product data sheet
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[4]
-
1.8
-
LSB
0.5
-
+0.5
LSB
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Table 25. Analog to Digital Converters …continued
VDD = 3 V; Vref = 1.2 V; Tamb = -40 C to +125 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
EO
offset error
0 to Vref range
-
10
-
mV
0 to 2 Vref range
-
20
-
mV
0 to Vref range
-
10
-
mV
0 to 2 Vref range
-
20
-
mV
16
-
1
-
MHz
32
-
0.5
-
MHz
64
-
0.25
-
MHz
9.5
-
148
s
-
8
-
pF
gain error
EG
fclk(int)
internal clock frequency
16 MHz input clock
tconv
conversion time
Ci(a)
analog input capacitance in series with 5 k resistor
[5]
programmable
[1]
See Section 9.15.1.1.
[2]
See Section 14.3.6.
[3]
With x = 1, 2, 3, 4, 5 or 6.
[4]
Guaranteed monotonic.
[5]
Number of internal clock periods to sample input (programmable at 2, 4, 6 or 8).
14.3.8 Comparator
Table 26. Comparator
VDD = 2 V to 3.6 V; Tamb = 40 °C to +125 C; unless otherwise specified.
Symbol
Parameter
response time
tresp
Conditions
Min
Typ
Max
Unit
operating mode
[1]
-
90
-
ns
low-power mode
[2]
-
2.2
-
ns
[3]
-
130
-
ns
-
10
-
mV
-
20
-
mV
tres(tot)
total response time
operating mode; including delay to interrupt
controller
Vhys
hysteresis voltage
programmable in 3 steps
Vref
reference voltage
VI(cm)
common-mode input
voltage
II
input current
-
40
-
mV
-
-
-
V
0
-
VDD
V
operating mode
-
73
-
A
low-power mode
-
0.8
-
A
[4]
[1]
250 mV overdrive; 10 pF load.
[2]
250 mV overdrive; no digital delay.
[3]
Digital delay can be up to a maximum of two 16 MHz clock periods.
[4]
See Section 14.3.6.
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14.3.9 32 kHz RC oscillator
Table 27. 32 kHz RC oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
fxtal
[1]
Parameter
Conditions
crystal frequency
accuracy
Min
32 kHz clock uncalibrated accuracy; without
temperature and voltage variation
[1]
Typ
32 21% 32
Max
Unit
32 +
53%
kHz
calibration done in operating mode; calibrated
32 kHz accuracy; for a 1 s sleep period
calibrating over 20 x 32 kHz clocks periods
-
300
-
ppm
calibration done in low-power mode; calibrated
32 kHz accuracy; for a 1 s sleep period
calibrating over 20 x 32 kHz clocks periods
-
600
-
ppm
Measured at 3 V and 25 °C.
14.3.10 32 kHz crystal oscillator
Table 28. 32 kHz crystal oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Parameter
Conditions
IDD(xtal)
crystal oscillator
supply current
tstartup
start-up time
of cell and counter-logic
Min
Typ
Max
Unit
[1]
-
0.6
-
A
[2]
-
0.6
-
s
[1]
This is sensitive to the ESR of the crystal, VDD and total capacitance at each pin.
[2]
Assuming crystal with ESR of less than 40 k, CL = 9 pF and external capacitances = 15 pF (VDD / 2 mV(p-p).
When external 32 kHz oscillator is used, external capacitances of 15 pF are implemented.
Total external capacitance needs to be 2 CL, allowing for stray capacitance from chip,
package and PCB (CL = 9 pF).
14.3.11 32 MHz crystal oscillator
Table 29. 32 MHz crystal oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Parameter
Conditions
IDD(xtal)
crystal oscillator supply
current
tstartup
start-up time
of cell and counter-logic
Min
Typ
Max
Unit
[1]
-
275
-
A
[2]
-
0.74
-
ms
[1]
Excluding band gap ref.
[2]
Assuming crystal with ESR of less than 40 k, CL = 9 pF and external capacitances = 15 pF (VDD / 2 mV(p-p).
When external 32 MHz oscillator is used, external capacitances of 15 pF are
implemented. Total external capacitance needs to be 2 CL, allowing for stray
capacitance from chip, package and PCB (CL = 9 pF).
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14.3.12 High-speed RC oscillator
Table 30. High-speed RC oscillator
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Parameter
IDD(xtal)
fosc
tstartup
Conditions
Min
Typ
Max
Unit
crystal oscillator supply current of cell
-
145
-
A
oscillator frequency
uncalibrated
26.1 16% 26.1
26.1 18%
MHz
calibrated
32.1 4%
32.1
32.1 + 5%
MHz
-
2.4
-
s
start-up time
14.3.13 Temperature sensor
Table 31. Temperature sensor
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Parameter
Tsen
Min
Typ
Max
Unit
sensor temperature
40
-
+125
°C
Gsen
sensor gain
-
1.66
-
mV/°C
Tsen
sensor temperature
accuracy
-
7
-
°C
Vo
output voltage
540
-
840
mV
Vsen
sensor voltage
-
720
-
mV
[1]
Conditions
[1]
at VDD = 3.0 V and Tamb = 25 °C
Includes absolute variation due to manufacturing and temperature.
14.3.14 Non-volatile memory
Table 32. Non-volatile memory
VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Nendu
Parameter
Conditions
endurance
Min
Typ
Max
Unit
Flash; program/erase
[1]
10
50
-
kCycle
EEPROM; program/erase
[2]
100
500
-
kCycle
ter
erase time
Flash; one sector
-
100
-
ms
tprog
programming time
Flash; per page of 256 bytes
-
1.0
-
ms
ter
erase time
EEPROM; one 64-byte page
-
1.8
-
ms
tprog
programming time
EEPROM; between 1 byte and 64 bytes
-
1.1
-
ms
tret
retention time
powered; Flash and EEPROM
10
-
-
year
[1]
See Section 9.2.1.
[2]
See Section 9.2.4.
14.3.15 Radio transceiver
This JN5169 meets all the requirements of the IEEE802.15.4 standard over 2.0 V to 3.6 V
and offers the improved RF characteristics shown in Table 33. All RF characteristics are
measured single ended.
This part also meets the following regulatory body approvals, when used with NXP’s
Module Reference Designs. Compliant with FCC part 15 rules, IC Canada and ETSI ETS
300-328.
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The PCB schematic and layout rules detailed in Section 15.1.1 must be followed. Failure
to do so will likely result in the JN5169 failing to meet the performance specification
detailed herein and worst case may result in device not functioning in the end application.
Table 33. RF port characteristics
Single-ended; Impedance = 50 [1]; VDD = 2 V to 3.6 V; Tamb = 40C to +125C; unless otherwise specified.
Symbol
Parameter
frange
frequency range
VESD
electrostatic discharge
voltage
[1]
Conditions
Min
Typ
2.4
Max
Unit
2.485
GHz
pin 17
HBM
-
2
-
kV
CDM
-
1000
-
V
With external matching inductors and assuming PCB layout as in Section 15.1.1.
Table 34. Radio transceiver characteristics: +25 C
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SRX
receiver sensitivity
nominal for 1 % PER, as per 802.15.4
-
96
93.5
dBm
Pi(RX)(max)
maximum receiver input
power
1 % PER, measured as sensitivity; supply
current at 14.7 mA
-
10
-
dBm
1 % PER, measured as sensitivity; supply
current at 13 mA
-
0
-
dBm
Receiver
ch
channel rejection
1 % PER, with wanted signal 3 dB, above sensitivity as per 802.15.4
modulated interferer[1][2]
1 channel
-
19
-
dBc
+1 channel
-
34
-
dBc
2 channel
-
40
-
dBc
+2 channel
-
44
-
dBc
co-channel
-
7
-
dBc
1 channel
-
25
-
dBc
+1 channel
-
50
-
dBc
CW interferer[1][2]
2 channel
-
57
-
dBc
+2 channel
-
60
-
dBc
-
48
-
dBc
all frequencies except wanted/2 which is
8 dB lower
-
45
-
dBc
3G frequency at 2.1 GHz
-
5
-
dBm
LTE frequency at 2.5 GHz
-
18
-
dBm
ib
in-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; 2.4 GHz to 2.4835 GHz;
modulated interferers at 3 channel
separation
[1]
oob
out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity
[1]
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Table 34. Radio transceiver characteristics: +25 C …continued
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Psp(RX)
receiver spurious power
measured conducted into 50
30 MHz to 1 GHz
1 GHz to 12 GHz
PL(lo)
local oscillator leakage
power
IMP
intermodulation
protection
1 % PER at with wanted signal 3 dB above
sensitivity; modulated interferers at 3 and 6
channel separation
RSSI
RSSI variation
95 dBm to 10 dBm; available through
JN5169 Integrated Peripherals API
[1]
Min
Typ
Max
Unit
-
-
70
dBm
-
-
70
dBm
-
-
58
dBm
-
46
-
dB
4
-
+4
dB
-
dBm
Transmitter
output power
[3]
Po(cr)
control range output
power
in 6 major steps and then 4 fine steps
[4]
Psp(TX)
transmitter spurious
power
measured conducted into 50
Po
- 10
-
42
-
dB
30 MHz to 1 GHz
-
-
65
dBm
1 GHz to 12.5 GHz (harmonic 2)
-
-
36
dBm
exceptions
1.8 GHz to 1.9 GHz
-
-
65
dBm
5.15 GHz to 5.3 GHz
-
-
65
dBm
-
3
4.5
%
-
38
20
dBc
EVMoffset
error vector magnitude
offset
at maximum output power
PSD
power spectral density
at greater than 3.5 MHz offset
[5]
[1]
Blocker rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, as per IEE802.15.4.
[2]
Channels 11, 17, 24 low/high values reversed.
[3]
To reach the maximum TX power, 2.8 V is the minimum on VDDA.
[4]
Up to an extra 2.5 dB of attenuation is available if required.
[5]
See IEEE802.15.4.
Table 35. Radio transceiver characteristics: 40 C
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SRX
receiver sensitivity
nominal for 1 % PER, as per 802.15.4
-
96.5
-
dBm
Pi(RX)(max)
maximum receiver input
power
1 % PER, measured as sensitivity; supply
current at 14.7 mA
-
10
-
dBm
1 % PER, measured as sensitivity; supply
current at 13 mA
-
0
-
dBm
Receiver
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Table 35. Radio transceiver characteristics: 40 C …continued
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
ch
channel rejection
1 % PER, with wanted signal 3 dB, above sensitivity as per 802.15.4
Max
Unit
modulated interferer[1][2]
1 channel
-
19
-
dBc
+1 channel
-
34
-
dBc
2 channel
-
40
-
dBc
+2 channel
-
44
-
dBc
-
7
-
dBc
ib
in-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; 2.4 GHz to 2.4835 GHz;
modulated interferers at 3 channel
separation
[1]
-
48
-
dBc
oob
out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; all frequencies except wanted/2
which is 8 dB lower
[1]
-
45
-
dBc
Psp(RX)
receiver spurious power
measured conducted into 50
30 MHz to 1 GHz
-
-
70
dBm
1 GHz to 12 GHz
-
-
70
dBm
-
-
58
dBm
-
45
-
dB
-
4
-
dB
- 10
-
dBm
co-channel
PL(lo)
local oscillator leakage
power
IMP
intermodulation
protection
1 % PER at with wanted signal 3 dB above
sensitivity; modulated interferers at 3 and 6
channel separation
RSSI
RSSI variation
95 dBm to 10 dBm; available through
JN5169 Integrated Peripherals API
[1]
Transmitter
output power
[3]
Po(cr)
control range output
power
in 6 major steps and then 4 fine steps
[4]
Psp(TX)
transmitter spurious
power
measured conducted into 50
Po
-
42
-
dB
30 MHz to 1 GHz
-
-
65
dBm
1 GHz to 12.5 GHz (harmonic 2)
-
-
36
dBm
1.8 GHz to 1.9 GHz
-
-
65
dBm
5.15 GHz to 5.3 GHz
-
-
65
dBm
-
3
-
%
-
38
-
dBc
exceptions
EVMoffset
error vector magnitude
offset
at maximum output power
PSD
power spectral density
at greater than 3.5 MHz offset
[5]
[1]
Blocker rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, as per IEE802.15.4.
[2]
Channels 11, 17, 24 low/high values reversed.
[3]
To reach the maximum TX power, 2.8 V is the minimum on VDDA.
[4]
Up to an extra 2.5 dB of attenuation is available if required.
[5]
See IEEE802.15.4.
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Table 36. Radio transceiver characteristics: +125 C
VDD = 2 V to 3.6 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SRX
receiver sensitivity
nominal for 1 % PER, as per 802.15.4
-
94
-
dBm
Pi(RX)(max)
maximum receiver input
power
1 % PER, measured as sensitivity; supply
current at 14.7 mA
-
5
-
dBm
1 % PER, measured as sensitivity; supply
current at 13 mA
-
0
-
dBm
Receiver
ch
channel rejection
1 % PER, with wanted signal 3 dB, above sensitivity as per 802.15.4
modulated interferer[1][2]
1 channel
-
18
-
dBc
+1 channel
-
31
-
dBc
2 channel
-
38
-
dBc
+2 channel
-
42
-
dBc
-
7
-
dBc
ib
in-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; 2.4 GHz to 2.4835 GHz;
modulated interferers at 3 channel
separation
[1]
-
46
-
dBc
oob
out-of-band rejection
1 % PER with wanted signal 3 dB above
sensitivity; all frequencies except wanted/2
which is 8 dB lower
[1]
-
42
-
dBc
Psp(RX)
receiver spurious power
measured conducted into 50
30 MHz to 1 GHz
-
-
70
dBm
1 GHz to 12 GHz
-
-
70
dBm
-
-
58
dBm
-
45
-
dB
-
4
-
dB
co-channel
PL(lo)
local oscillator leakage
power
IMP
intermodulation
protection
1 % PER at with wanted signal 3 dB above
sensitivity; modulated interferers at 3 and 6
channel separation
RSSI
RSSI variation
95 dBm to 10 dBm; available through
JN5169 Integrated Peripherals API
[1]
Transmitter
output power
[3]
-
10
-
dBm
Po(cr)
control range output
power
in 6 major steps and then 4 fine steps
[4]
-
42
-
dB
Psp(TX)
transmitter spurious
power
measured conducted into 50
30 MHz to 1 GHz
-
-
65
dBm
1 GHz to 12.5 GHz (harmonic 2)
-
-
36
dBm
1.8 GHz to 1.9 GHz
-
-
65
dBm
5.15 GHz to 5.3 GHz
-
-
65
dBm
-
3
-
%
-
38
-
dBc
Po
exceptions
EVMoffset
error vector magnitude
offset
at maximum output power
PSD
power spectral density
at greater than 3.5 MHz offset
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[1]
Blocker rejection is defined as the value, when 1 % PER is seen with the wanted signal 3 dB above sensitivity, as per IEE802.15.4.
[2]
Channels 11, 17, 24 low/high values reversed.
[3]
To reach the maximum TX power, 2.8 V is the minimum on VDDA.
[4]
Up to an extra 2.5 dB of attenuation is available if required.
[5]
See IEEE802.15.4.
15
Major steps
10
(PA = 5)
5
(PA = 4)
0
-5
(PA = 3)
-10
-15
(PA = 2)
-20
-25
(PA = 1)
-30
(PA = 0)
Att 2.5 dB ON
fine step 3
fine step 2
fine step 1
fine step 0
fine step 3
fine step 2
fine step 1
fine step 0
-35
Att 2.5 dB OFF
aaa-018591
At VDD = 3 V and Tamb = 25 °C.
Fig 46. Control range output power
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aaa-018592
-94
Sensitivity
-95
-96
-97
-40
-20
0
20
40
60
80
100
120
140
Temp (°C)
Fig 47. Receiver sensitivity versus temperature
15. Application information
15.1 JN5169 module reference designs
For customers wishing to integrate the JN5169 device directly into their system, NXP
provides a range of module reference designs, covering standard, medium and
high-power modules fitted with different antennas.
To ensure the correct performance, it is strongly recommended that where possible the
design details provided by the reference designs are used in their exact form for all end
designs; this includes component values, pad dimensions, track layouts etc. In order to
minimize all risks, it is recommended that the entire layout of the appropriate reference
module, if possible, be replicated in the end design.
For full details, see the NXP Wireless Connectivity TechZone Ref. 1; Contact technical
support.
15.1.1 Schematic diagram
A schematic diagram of the JN5169 reference module is shown in Figure 48. Details of
component values and PCB layout constraints can be found in Table 37.
The paddle should be connected directly to ground. Any pads that require connection to
ground should do so by connecting directly to the paddle.
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IEEE802.15.4 Wireless Microcontroller
2-wire
Serial Port
Timer0
TIM0CK_GT
31
TIM0CAP
32
TIM0OUT
33
DIO11
34
VB_DIG
35
DIO12
36
DIO13
37
38
VSS
23
9
22
10
21
RXD0
TXD0
UART0/JTAG
RTS0
CTS0
i.c.
DIO19
DIO18
DO1(1)
VSS
DO0(2)
DIO3
R1
43 kΩ
ADC1
11
ADC2
C14
100 nF
VDDD
20
8
19
24
18
7
17
25
14
IBIAS
26
VSSA
6
VDD
C13
10 μF
SIF_CLK
27
13
VDDA
C2
10 nF
4
VB_RF1
i.c.
VB_VCO
C15
100 nF
28
5
VB_SYNTH
C11
12 pF
3
DIO2
XTAL_IN
29
12
Y1
30
SPISEL2
XTAL_OUT
VDD
2
16
RESET_N
C16
100 nF
1
15
COMP1M
RF_IO
Analog IO
VB_RF2
C10
12 pF
SPISEL1
COMP1P
39
40
SIF_D
C7
100 nF
SPI select
Analog IO
VB_RF
L2
3 nH
To coaxial socket
or integrated antenna
L1
4.3 nH
C1
1.8 pF
Analog IO
VB_RF
C12
47 pF
C3
100 nF
aaa-013331
C4
1 pF
(1) The JN5169 will enter UART programming mode if SPIMISO (DO1) pin 22 is low after RESET.
(2) The JN5169 will enter JTAG programming mode if SPICLK (DO0) pin 20 is low after RESET.
Fig 48. JN5169 PCB antenna module reference design
Table 37.
Components
Component
Function
Value
Remarks
[1]
C1
AC coupling
1.8 pF
C2
VB VCO decoupling
10 nF
locate less than 5 mm from U1 pin 8
C3
VB RF decoupling
100 nF
locate less than 5 mm from U1 pin 12 and UI pin 14
C4
RF matching capacitor
1 pF
C7
VB Dig decoupling
100 nF
locate less than 5 mm from U1 pin 35
C10
crystal load capacitance
12 pF 5 % C0G
adjacent to pin 4 and Y1 pin 1
C11
crystal load capacitance
12 pF 5 % C0G
adjacent to pin 5 and Y1 pin 3
C12
VB RF decoupling
47 pF
locate less than 5 mm from U1 pin 12 and UI pin 14
C13
power source
decoupling
10 F
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Table 37.
Components
Component
Function
Value
Remarks
C14
analog power
decoupling
100 nF
locate less than 5 mm from U1 pin 9
C15
VB synth decoupling
100 nF
locate less than 5 mm from U1 pin 6
C16
digital power decoupling 100 nF
L1
RF matching inductor
4.3 nH
[1]
MuRata LQP15MN4N3B02 can be used up to 85 °C;
MuRata LQG15MN4N3B02 can be used up to 125 °C
L2
load inductor
3 nH
[1]
MuRata LQP15MN3N0B02 can be used up to 85 °C;
MuRata LQG15MN3N0B02 can be used up to 125 °C
Y1
crystal
32 MHz; CL = 9 pF
[1]
adjacent to pin 5 and Y1 pin 30
AEL X32M000000S039 or
NDK NX3225SA EXS00A-CS08207 or
MuRata XR16GD32M000KYQ01R0 (2016) or
Epson Toyocom X1E000021016700
Must be copied directly from the reference design.
15.1.2 PCB design and reflow profile
PCB and land pattern designs are key to the reliability of any electronic circuit design.
The Institute for Interconnecting and Packaging Electronic Circuits (IPC) defines a
number of standards for electronic devices. One of these is the "Surface Mount Design
and Land Pattern Standard" IPC-SM-782 commonly referred to as “IPC782". This
specification defines the physical packaging characteristics and land patterns for a range
of surface-mounted devices. IPC782 is also a useful reference document for general
surface mount design techniques, containing sections on design requirements, reliability
and testability. NXP strongly recommends that this be referred to when designing the
PCB.
NXP also provides an Application Note AN10366, “HVQFN application information”, (see
the NXP Wireless Connectivity TechZone Ref. 1), which describes the reflow soldering
process. The suggested reflow profile from this Application Note is shown in Figure 49.
The specific paste manufacturers guidelines on peak flow temperature, soak times, time
above liquids and ramp rates should also be referenced.
WHPSHUDWXUH
& DDF
3EIUHHSURILOH
WLPHPLQVHF
Fig 49. Recommended reflow profile for lead-free solder paste (SNAgCu) or PPF lead
frame
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15.1.3 Moisture sensitivity level (MSL)
If there is moisture trapped inside a package and the package is exposed to a reflow
temperature profile, the moisture may turn into steam, which expands rapidly. This may
cause damage to the inside of the package (delamination) and may result in a cracked
semiconductor package body (the popcorn effect). A package’s MSL depends on the
package characteristics and on the temperature to which it is exposed to during reflow
soldering. This is explained in more detail in NXP Wireless Connectivity TechZone
(Ref. 1).
Depending on the damage after this test, an MSL of 1 (not sensitive to moisture) to 6 (very
sensitive to moisture) is attached to the semiconductor package.
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16. Footprint information for reflow soldering
Footprint information for reflow soldering of HVQFN40 package
SOT618-8
Hx
Gx
D
0.105
0.125
C
nSPx
SPx
nSPy
Hy
SPy tot
SPy
Gy
SLy By
Ay
SPx tot
X
SLx
Bx
Ax
0.29
0.24
0.85 0.9
solder land
solder land plus solder paste
solder paste deposit
occupied area
Dimensions in mm
detail X
nSPx
nSPy
3
3
Recommended stencil thickness: 0.1 mm
P
Ax
Ay
Bx
By
C
D
Gx
Gy
Hx
Hy
SLx
SLy
SPx
SPy
SPx tot
SPy tot
0.5
7.0
7.0
5.2
5.2
0.9
0.29
6.3
6.3
7.25
7.25
4.7
4.7
0.7
0.7
2.7
2.7
Issue date
15-04-29
15-04-30
sot618-8_fr
Fig 50. Reflow soldering information for the HVQFN40 package
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17. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A
B
D
SOT618-8
terminal 1
index area
E
A
A1
c
detail X
e1
C
1/2 e
e
v
w
b
11
20
C A B
C
y1 C
y
L
21
10
e
e2
Eh
1/2 e
1
30
terminal 1
index area
40
31
X
Dh
0
2.5
Dimensions
Unit
mm
5 mm
scale
A(1)
A1
b
max 1.00 0.05 0.30
nom 0.85 0.02 0.21
min 0.80 0.00 0.18
c
D(1)
Dh
E(1)
Eh
e
e1
e2
L
v
0.2
6.1
6.0
5.9
4.85
4.70
4.55
6.1
6.0
5.9
4.85
4.70
4.55
0.5
4.5
4.5
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
SOT618-8
References
IEC
JEDEC
JEITA
MO-220
---
sot618-8_po
European
projection
Issue date
13-11-19
14-01-16
Fig 51. Package outline SOT618-8 HVQFN40
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18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 52) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 38 and 39
Table 38.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 39.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 52.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 52. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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19. Abbreviations
Table 40.
JN5169
Product data sheet
Abbreviations
Acronym
Description
API
Application Program Interface
ADC
Analog to Digital Converter
BOR
Brown-Out Reset
CCA
Clear Channel Assessment
CDM
Charged Device Model
CTS
Clear-To-Send
CW
Continuous Wave
ED
Energy Detection
ESR
Equivalent Series Resistance
FIFO
First In First Out
GP
General Purpose
HBM
Human Body Model
HS
High Speed
IO
Input Output
IPC
Interconnecting and Packaging Electronic Circuits
LQI
Link Quality Indication
MSIF
Master Serial InterFace
MSL
Moisture sensitivity level
NACK
Not ACKnowledge
NRZ
Non-Return-to-Zero
OOK
On-Off Key
OTA
Over-The-Air
PA
Power Amplifier
PIC
Programmable Interrupt Controller
PDM
Persistent Data Manager
POR
Power-On Reset
PPF
Palladium Pre Plated
RISC
Reduce Instruction Set Computing
RTS
Request-To-Send
RTOS
Real-Time Operating System
RTZ
Return-To-Zero
SDK
Software Developer’s Kit
SMbus
System Management bus
SSIF
Slave Serial InterFace
SVM
Supply Voltage Monitor
SYNTH
SYNTHesizer
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20. References
[1]
JN5169
Product data sheet
Wireless Connectivity TechZone —
http://www.nxp.com/techzones/wireless-connectivity
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21. Revision history
Table 41.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
JN5169 v1
20150805
Product data sheet
-
-
Modifications:
JN5169
Product data sheet
•
Initial version.
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22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
22.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
JN5169
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
23. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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IEEE802.15.4 Wireless Microcontroller
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8
Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . .23
SPI-bus master I/O . . . . . . . . . . . . . . . . . . . . . .34
SPI-bus configurations . . . . . . . . . . . . . . . . . .35
SPI-bus slave I/O . . . . . . . . . . . . . . . . . . . . . . .37
Timer and PWM I/O . . . . . . . . . . . . . . . . . . . . .39
UART I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2-wire serial interface I/O . . . . . . . . . . . . . . . . .49
List of 2-wire serial interface reserved
addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
ADC maximum input range. . . . . . . . . . . . . . . .54
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .59
Operating conditions . . . . . . . . . . . . . . . . . . . .60
Thermal characteristics . . . . . . . . . . . . . . . . . .60
Active processing . . . . . . . . . . . . . . . . . . . . . .60
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Deep sleep mode . . . . . . . . . . . . . . . . . . . . . .61
I/O characteristics . . . . . . . . . . . . . . . . . . . . . .61
Externally applied reset . . . . . . . . . . . . . . . . . .63
SPI-bus master timing . . . . . . . . . . . . . . . . . . .65
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
SPI-bus slave timing . . . . . . . . . . . . . . . . . . . . 65
2-wire serial interface. . . . . . . . . . . . . . . . . . . . 66
Wake-up timings . . . . . . . . . . . . . . . . . . . . . . . 67
Band gap reference . . . . . . . . . . . . . . . . . . . . 67
Analog to Digital Converters . . . . . . . . . . . . . . 67
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
32 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . 69
32 kHz crystal oscillator . . . . . . . . . . . . . . . . . 69
32 MHz crystal oscillator . . . . . . . . . . . . . . . . . 69
High-speed RC oscillator . . . . . . . . . . . . . . . . 70
Temperature sensor . . . . . . . . . . . . . . . . . . . . 70
Non-volatile memory . . . . . . . . . . . . . . . . . . . . 70
RF port characteristics . . . . . . . . . . . . . . . . . . 71
Radio transceiver characteristics: +25 °C . . . . 71
Radio transceiver characteristics: -40 °C . . . . 72
Radio transceiver characteristics: +125 °C . . . 74
Components. . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SnPb eutectic process (from J-STD-020C) . . . 83
Lead-free process (from J-STD-020C) . . . . . . 83
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 85
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 87
25. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional block diagram . . . . . . . . . . . . . . . . . . . .6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7
Analog I/O cell . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DIO equivalent schematic . . . . . . . . . . . . . . . . . .13
JN5169 memory map . . . . . . . . . . . . . . . . . . . . .15
Connecting external serial memory . . . . . . . . . . .16
System and CPU clocks . . . . . . . . . . . . . . . . . . .17
32 MHz crystal oscillator connections . . . . . . . . .19
32 kHz crystal oscillator connections . . . . . . . . . .20
Internal Power-On Reset . . . . . . . . . . . . . . . . . . .21
External reset generation. . . . . . . . . . . . . . . . . . .22
External reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Radio architecture . . . . . . . . . . . . . . . . . . . . . . . .25
External radio components . . . . . . . . . . . . . . . . .27
Simple antenna diversity implementation using
external RF switch . . . . . . . . . . . . . . . . . . . . . . . .28
Antenna diversity ADO signal for TX with
acknowledgement . . . . . . . . . . . . . . . . . . . . . . . .28
Modem architecture . . . . . . . . . . . . . . . . . . . . . . .29
Energy detect value versus receive power level .29
Baseband processor . . . . . . . . . . . . . . . . . . . . . .30
Security coprocessor architecture . . . . . . . . . . . .31
DIO block diagram . . . . . . . . . . . . . . . . . . . . . . . .33
SPI-bus block diagram. . . . . . . . . . . . . . . . . . . . .34
Typical JN5169 SPI-bus peripheral connection . .35
Example SPI-bus waveforms: reading from Flash
device using mode 0 . . . . . . . . . . . . . . . . . . . . . .36
Timer unit block diagram . . . . . . . . . . . . . . . . . . .38
PWM output timings. . . . . . . . . . . . . . . . . . . . . . .40
Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . .40
JN5169
Product data sheet
Fig 29. Return-To-Zero mode in operation . . . . . . . . . . . 41
Fig 30. Non-Return-To-Zero mode in operation . . . . . . . 42
Fig 31. Closed-loop PWM speed control using JN5169
timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Fig 32. Tick timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Fig 33. UART block diagram . . . . . . . . . . . . . . . . . . . . . . 46
Fig 34. JN5169 serial communication link. . . . . . . . . . . . 48
Fig 35. Connection details. . . . . . . . . . . . . . . . . . . . . . . . 50
Fig 36. Clock stretching. . . . . . . . . . . . . . . . . . . . . . . . . . 50
Fig 37. Multi-master clock synchronization . . . . . . . . . . . 51
Fig 38. Analog peripherals . . . . . . . . . . . . . . . . . . . . . . . 53
Fig 39. ADC input equivalent circuit . . . . . . . . . . . . . . . . 54
Fig 40. Internal Power-On Reset without showing
Brown-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Fig 41. Externally applied reset. . . . . . . . . . . . . . . . . . . . 63
Fig 42. Brown-Out Reset followed by Supply Voltage
Monitor trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Fig 43. SPI-bus master timing. . . . . . . . . . . . . . . . . . . . . 64
Fig 44. SPI-bus slave timing . . . . . . . . . . . . . . . . . . . . . . 65
Fig 45. 2-wire serial interface timing . . . . . . . . . . . . . . . . 66
Fig 46. Control range output power. . . . . . . . . . . . . . . . . 75
Fig 47. Receiver sensitivity versus temperature . . . . . . . 76
Fig 48. JN5169 PCB antenna module reference design. 77
Fig 49. Recommended reflow profile for lead-free solder
paste (SNAgCu) or PPF lead frame . . . . . . . . . . 78
Fig 50. Reflow soldering information for the HVQFN40
package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Fig 51. Package outline SOT618-8 HVQFN40 . . . . . . . . 81
Fig 52. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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26. Contents
1
2
2.1
2.2
2.3
3
4
4.1
4.2
4.3
5
6
7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.3
9.3.1
9.3.1.1
9.3.1.2
9.3.2
9.3.2.1
9.3.2.2
9.3.2.3
9.4
9.4.1
9.4.2
9.4.3
9.4.4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features: radio . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features: microcontroller . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Wireless transceiver . . . . . . . . . . . . . . . . . . . . . 3
RISC CPU and memory . . . . . . . . . . . . . . . . . . 3
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
32 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . 11
Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Analog peripherals . . . . . . . . . . . . . . . . . . . . . 12
Digital Input/Output . . . . . . . . . . . . . . . . . . . . . 12
Functional description . . . . . . . . . . . . . . . . . . 13
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory organization . . . . . . . . . . . . . . . . . . . 14
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OTP configuration memory. . . . . . . . . . . . . . . 16
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External memory . . . . . . . . . . . . . . . . . . . . . . 16
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Unused memory address . . . . . . . . . . . . . . . . 17
System clocks. . . . . . . . . . . . . . . . . . . . . . . . . 17
High-speed (32 MHz) system clock . . . . . . . . 17
32 MHz crystal oscillator. . . . . . . . . . . . . . . . . 18
High-speed RC oscillator . . . . . . . . . . . . . . . . 19
Low-speed (32 kHz) system clock . . . . . . . . . 19
32 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . 19
32 kHz crystal oscillator . . . . . . . . . . . . . . . . . 20
32 kHz external clock . . . . . . . . . . . . . . . . . . . 20
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Internal Power-On Reset/Brown-Out Reset
(BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
External reset . . . . . . . . . . . . . . . . . . . . . . . . . 22
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 22
Supply Voltage Monitor (SVM) . . . . . . . . . . . . 22
9.4.5
9.5
9.5.1
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
9.5.2.4
9.5.3
9.6
9.6.1
9.6.1.1
9.6.1.2
9.6.2
9.6.3
9.6.3.1
9.6.3.2
9.6.3.3
9.6.3.4
9.6.4
9.7
9.8
9.8.1
9.8.2
9.9
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
9.9.8
9.9.9
9.10
9.11
9.11.1
9.11.2
9.12
9.13
9.13.1
9.13.2
9.13.3
9.13.4
9.14
9.15
9.15.1
9.15.1.1
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . .
Interrupt system . . . . . . . . . . . . . . . . . . . . . . .
System calls. . . . . . . . . . . . . . . . . . . . . . . . . .
Processor exceptions. . . . . . . . . . . . . . . . . . .
Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Illegal instruction . . . . . . . . . . . . . . . . . . . . . .
Stack overflow . . . . . . . . . . . . . . . . . . . . . . . .
Hardware interrupts . . . . . . . . . . . . . . . . . . . .
Wireless transceiver. . . . . . . . . . . . . . . . . . . .
Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Radio external components . . . . . . . . . . . . . .
Antenna diversity . . . . . . . . . . . . . . . . . . . . . .
Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baseband processor . . . . . . . . . . . . . . . . . . .
Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto acknowledge . . . . . . . . . . . . . . . . . . . . .
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Security coprocessor . . . . . . . . . . . . . . . . . . .
Digital Input/Output . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface-bus . . . . . . . . . . .
SPI-bus master . . . . . . . . . . . . . . . . . . . . . . .
SPI-bus slave. . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral timer/counters. . . . . . . . . . . . . . . .
Pulse Width Modulation mode . . . . . . . . . . . .
Capture mode . . . . . . . . . . . . . . . . . . . . . . . .
Counter/timer mode . . . . . . . . . . . . . . . . . . . .
Delta-sigma mode . . . . . . . . . . . . . . . . . . . . .
Example timer/counter application. . . . . . . . .
Tick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-up timers . . . . . . . . . . . . . . . . . . . . . . .
32 kHz RC oscillator calibration . . . . . . . . . . .
Pulse counters . . . . . . . . . . . . . . . . . . . . . . . .
Serial communications. . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART application . . . . . . . . . . . . . . . . . . . . . .
JTAG test interface . . . . . . . . . . . . . . . . . . . .
2-wire serial interface (I2C-bus) . . . . . . . . . . .
Connecting devices . . . . . . . . . . . . . . . . . . . .
Clock stretching . . . . . . . . . . . . . . . . . . . . . . .
Master 2-wire serial interface. . . . . . . . . . . . .
Slave 2-wire serial interface. . . . . . . . . . . . . .
Random number generator . . . . . . . . . . . . . .
Analog peripherals . . . . . . . . . . . . . . . . . . . . .
Analog to Digital Converter (ADC) . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
24
24
24
24
24
24
25
25
26
27
28
30
30
31
31
31
31
32
33
33
37
37
37
39
40
40
41
42
42
43
44
45
45
47
48
48
48
49
50
50
51
52
53
54
54
continued >>
JN5169
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 5 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
91 of 92
JN5169
NXP Semiconductors
IEEE802.15.4 Wireless Microcontroller
9.15.1.2 Supply monitor . . . . . . . . . . . . . . . . . . . . . . . .
9.15.1.3 Temperature sensor . . . . . . . . . . . . . . . . . . . .
9.15.1.4 ADC sample buffer mode . . . . . . . . . . . . . . . .
9.15.2
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Power management and sleep modes. . . . . .
10.1
Operating modes . . . . . . . . . . . . . . . . . . . . . .
10.1.1
Power domains . . . . . . . . . . . . . . . . . . . . . . . .
10.2
Active processing mode . . . . . . . . . . . . . . . . .
10.2.1
CPU doze . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.1
Wake-up timer event. . . . . . . . . . . . . . . . . . . .
10.3.2
DIO event . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.3.3
Comparator event . . . . . . . . . . . . . . . . . . . . . .
10.3.4
Pulse counter . . . . . . . . . . . . . . . . . . . . . . . . .
10.4
Deep sleep mode . . . . . . . . . . . . . . . . . . . . . .
11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .
12
Recommended operating conditions. . . . . . .
13
Thermal characteristics . . . . . . . . . . . . . . . . .
14
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
14.1
DC current . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2
I/O characteristics . . . . . . . . . . . . . . . . . . . . . .
14.3
AC characteristics. . . . . . . . . . . . . . . . . . . . . .
14.3.1
Reset and Supply Voltage Monitor . . . . . . . . .
14.3.2
SPI-bus master timing . . . . . . . . . . . . . . . . . .
14.3.3
SPI-bus slave timing . . . . . . . . . . . . . . . . . . . .
14.3.4
2-wire serial interface . . . . . . . . . . . . . . . . . . .
14.3.5
Wake-up timings . . . . . . . . . . . . . . . . . . . . . . .
14.3.6
Band gap reference . . . . . . . . . . . . . . . . . . . .
14.3.7
Analog to Digital Converters . . . . . . . . . . . . . .
14.3.8
Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3.9
32 kHz RC oscillator . . . . . . . . . . . . . . . . . . . .
14.3.10 32 kHz crystal oscillator . . . . . . . . . . . . . . . . .
14.3.11 32 MHz crystal oscillator. . . . . . . . . . . . . . . . .
14.3.12 High-speed RC oscillator . . . . . . . . . . . . . . . .
14.3.13 Temperature sensor . . . . . . . . . . . . . . . . . . . .
14.3.14 Non-volatile memory. . . . . . . . . . . . . . . . . . . .
14.3.15 Radio transceiver . . . . . . . . . . . . . . . . . . . . . .
15
Application information. . . . . . . . . . . . . . . . . .
15.1
JN5169 module reference designs . . . . . . . . .
15.1.1
Schematic diagram . . . . . . . . . . . . . . . . . . . . .
15.1.2
PCB design and reflow profile . . . . . . . . . . . .
15.1.3
Moisture sensitivity level (MSL) . . . . . . . . . . .
16
Footprint information for reflow soldering . .
17
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
18
Soldering of SMD packages . . . . . . . . . . . . . .
18.1
Introduction to soldering . . . . . . . . . . . . . . . . .
18.2
Wave and reflow soldering . . . . . . . . . . . . . . .
18.3
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . .
18.4
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .
55
55
55
56
56
56
56
57
57
57
58
58
58
59
59
59
60
60
60
60
61
62
62
64
65
66
67
67
67
68
69
69
69
70
70
70
70
76
76
76
78
79
80
81
82
82
82
82
83
19
20
21
22
22.1
22.2
22.3
22.4
23
24
25
26
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
86
87
88
88
88
88
89
89
90
90
91
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 August 2015
Document identifier: JN5169