SSL4120T
Resonant power supply control IC with PFC
Rev. 1 — 21 June 2012
Objective data sheet
1. General description
The SSL4120T integrates a Power Factor Corrector (PFC) controller and a controller for a
Half-Bridge resonant Converter (HBC) in a multi-chip IC. It provides the drive function for
the discrete MOSFET in an up-converter and for the two discrete power MOSFETs in a
resonant half-bridge configuration.
The efficient operation of the PFC is achieved by implementing functions such as
quasi-resonant operation at high power levels and quasi-resonant operation with valley
skipping at lower power levels. OverCurrent Protection (OCP), OverVoltage Protection
(OVP), and demagnetization sensing ensure safe operation under all conditions.
The HBC module is a is a high-voltage controller for a zero-voltage switching LLC
resonant converter. It contains a high-voltage level shift circuit and several protection
circuits including OCP, open-loop protection, capacitive mode protection and a general
purpose latched protection input.
The high-voltage chip is fabricated using a proprietary high-voltage Bipolar-CMOS-DMOS
power logic process that enables efficient direct start-up from the rectified universal mains
voltage. The low-voltage Silicon On Insulator (SOI) chip is used for accurate, high-speed
protection functions and control.
The topology of a PFC circuit and a resonant converter controlled by the SSL4120T is
very flexible, enabling it to be used in a broad range of applications with a wide mains
voltage range. Combining PFC and HBC controllers in a single IC makes the SSL4120T
ideal for controlling power supplies in LCD and plasma televisions.
Highly efficient and reliable power supplies providing over 100 W can be designed easily
using the SSL4120T, with a minimum of external components.
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
2. Features and benefits
2.1 General features
Integrated PFC and HBC controllers
Universal mains supply operation (70 V to 276 V (AC))
High level of integration resulting in a low external component count and a cost
effective design
Enable input (enable only PFC or both PFC and HBC controllers)
On-chip high-voltage start-up source
Stand-alone operation or IC supplied from external DC source
2.2 PFC controller features
Boundary mode operation with on-time control
Valley/zero voltage switching for minimum switching losses
Frequency limiting to reduce switching losses
Accurate boost voltage regulation
Burst mode switching with soft-start and soft-stop
2.3 HBC controller features
Integrated high-voltage level shifter
Adjustable minimum and maximum frequency
Maximum 500 kHz half-bridge switching frequency
Adaptive non-overlap time
Burst mode switching
2.4 Protection features
Safe restart mode for system fault conditions
General latched protection input for output overvoltage protection or external
temperature protection
Protection timer for time-out and restart
Overtemperature protection
Soft (re)start for both controllers
Undervoltage protection for mains (brownout), boost, IC supply and output voltage
Overcurrent regulation and protection for both controllers
Accurate overvoltage protection for boost voltage
Capacitive mode protection for HBC controller
3. Applications
The device can be used in all LED lighting applications that require very efficient, low Total
Harmonic Distortion (THD), high power-factor, true universal input voltage and
cost-effective power supply solution between 10 W and 300 W."
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
2 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
4. Ordering information
Table 1.
Ordering information
Type number
Package
SSL4120T
Name
Description
Version
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
5. Block diagram
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Fig 1. Block diagram of SSL4120T
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
3 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
6. Pinning information
6.1 Pinning
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Fig 2. Pin configuration
6.2 Pin description
Table 2.
Pin description
Symbol
SSL4120T
Objective data sheet
Pin
Description
COMPPFC
1
frequency compensation for PFC controller; externally connected to filter
SNSMAINS
2
sense input for mains voltage; externally connected to resistive divided
mains voltage
SNSAUXPFC
3
sense input for PFC demagnetization timing; externally connected to
auxiliary winding of PFC
SNSCURPFC 4
sense input for momentary current and soft start of the PFC controller;
externally connected to current sense resistor and soft start filter
SNSOUT
5
sense input for monitoring the output voltage of the HBC; externally
connected to the auxiliary winding; sense input for burst mode of HBC
controller or PFC and HBC controllers
SUPIC
6
low-voltage supply for SUPIC input; output of internal HV start-up source;
externally connected to auxiliary winding of HBC or to external DC supply
GATEPFC
7
gate driver output for PFC MOSFET
PGND
8
power ground; reference (ground) for HBC low-side and PFC driver
SUPREG
9
regulated SUPREG IC supply; output from internal regulator; input for
drivers; externally connected to SUPREG buffer capacitor
GATELS
10
gate driver output for low-side MOSFET of HBC
n.c.
11
not connected; high-voltage spacer.
SUPHV
12
high-voltage supply input for internal HV start-up source; externally
connected to boost voltage
GATEHS
13
gate driver output for high-side MOSFET of HBC
SUPHS
14
high-side driver supply input; externally connected to bootstrap capacitor
(CSUPHS)
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© NXP B.V. 2012. All rights reserved.
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SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Table 2.
Pin description …continued
Symbol
Pin
Description
HB
15
reference for high-side driver; input for half-bridge slope detection;
externally connected to half-bridge node HB between HBC MOSFETs (see
Figure 19)
n.c.
16
not connected; high-voltage spacer
SNSCURHBC 17
sense input for momentary HBC current; externally connected to resonant
current sense resistor
SGND
18
signal ground; reference (ground) for IC.
CFMIN
19
minimum frequency setting for HBC; externally connected to capacitor
RFMAX
20
maximum frequency setting for HBC; externally connected to resistor
SNSFB
21
sense input for output voltage regulation feedback; externally connected to
opto-coupler
SSHBC/EN
22
combined soft start timing of HBC and IC enable input; enabling of PFC or
PFC and HBC controllers; externally connected to soft start capacitor and
enable pull-down signal
RCPROT
23
protection timer setting for time-out and restart; externally connected to
resistor and capacitor
SNSBOOST
24
sense input for boost voltage; externally connected to resistive divided
boost voltage
7. Functional description
7.1 Overview of IC modules
The functionality of the SSL4120T can be grouped as follows:
• Supply module:
Supply management for the IC; includes the restart and (latched) shut-down states
• Protection and restart timer:
Externally adjustable timer used for delayed protection and restart timing
• Enable input:
Control input for enabling and disabling the controllers; very low current consumption
when disabled
• PFC controller:
Controls and protects the power factor converter; generates a 400 V (DC) boost
voltage from the rectified AC mains input with a high power factor
• HBC controller:
Controls and protects the resonant converter; generates a regulated (mains isolated)
output voltage from the 400 V (DC) boost voltage
Figure 1 shows the block diagram of the SSL4120T. A typical application is illustrated in
Figure 19.
SSL4120T
Objective data sheet
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Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
5 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
7.2 Power supply
The SSL4120T contains several supply related pins.
7.2.1 Low-voltage supply input (pin SUPIC)
The SUPIC pin is the main low-voltage supply input to the IC. All internal circuits (other
than the high voltage circuit) are directly or indirectly (via SUPREG) supplied from this pin.
SUPIC is connected externally to a buffer capacitor CSUPIC. This buffer capacitor can be
charged in several ways:
•
•
•
•
from the internal high voltage start-up source
from the auxiliary winding of the HBC transformer
from the capacitive supply of the switching half-bridge node
from an external DC supply, e.g. a standby supply
The IC starts operating when voltage on SUPIC reaches the start level, provided that the
voltage on SUPREG has also reached the start level. The start level depends on the
condition of the SUPHV pin:
• High voltage present on SUPHV, VSUPHV > Vdet(SUPHV).
This is the case with a stand-alone application where CSUPIC is initially charged from
the HV start-up source. The start level is Vstart(hvd)(SUPIC) (typ. 22 V). The wide
difference between the start and stop (Vuvp(SUPIC)) levels allows energy to be stored in
the SUPIC buffer capacitor which is used to supply the IC until the output voltage has
stabilized.
• Not connected or no voltage present at SUPHV, VSUPHV < Vdet(SUPHV).
This is the case when the SSL4120T is supplied from an external DC source. The
start level is Vstart(nohvd)(SUPIC) (typ. 17 V). The IC is supplied from the DC supply
during start-up. To minimize power dissipation, the DC supply to pin SUPIC should be
above, but close to, Vuvp(SUPIC) (typ. 15 V).
The IC will stop operating when VSUPIC drops below Vuvp(SUPIC). This is the SUPIC
UnderVoltage Protection (UVP) voltage (UVP-SUPIC; see Section 7.9). The PFC
controller will stop switching immediately, but the HBC controller will continue operating
until the low-side MOSFET becomes active.
The current consumption depends on the state of the IC. The SSL4120T operating states
are described in Section 7.3.
• Disabled IC state
When the IC is disabled via the SSHBC/EN pin, the current consumption is very low
(Idism(SUPIC)).
• SUPIC charge, SUPREG charge, Thermal hold, Restart and Protection shut-down
states
Only a small section of the IC is active while CSUPIC and CSUPREG are charging during
a restart sequence prior to start-up or during shut-down after a protection function has
been activated. The PFC and HBC controllers are disabled. Current consumption is
limited to Iprotm(SUPIC).
SSL4120T
Objective data sheet
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Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
6 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
• Boost charge state
The PFC controller is switching; the HBC controller is off. The current from the high
voltage start-up source is large enough to supply SUPIC (current consumption <
Ich(nom)(SUPIC)).
• Operational supply state
Both the PFC and HBC controllers are switching. Current consumption is Ioper(SUPIC).
When the HBC controller is enabled, the switching frequency will be high initially and
the current consumption of the HBC MOSFET drivers will be dominant. The stored
energy in CSUPIC will supply the initial SUPIC current before the SUPIC supply source
takes over.
Pin SUPIC has a low short-circuit detection voltage (Vscp(SUPIC); typ. 0.65 V). The current
dissipated in the HV start-up source is limited while VSUPIC < Vscp(SUPIC) (see
Section 7.2.4).
7.2.2 Regulated supply (pin SUPREG)
The voltage range on pin SUPIC exceeds that of the gate voltages of the external
MOSFETs. For this reason, the SSL4120T contains an integrated series stabilizer. The
series stabilizer creates an accurate regulated voltage (Vreg(SUPREG); typ. 10.9 V) at the
buffer capacitor CSUPREG. This stabilized voltage is used to:
•
•
•
•
supply the internal PFC driver
supply the internal low-side HBC driver
supply the internal high-side driver via external components
as a reference voltage for optional external circuits
The SUPREG series stabilizer is enabled after CSUPIC has been fully charged. This
ensures that any optional external circuitry connected to SUPREG will not dissipate any of
the start-up current.
To ensure that the external MOSFETs receive sufficient gate drive current, the voltage on
SUPREG must reach Vstart(SUPREG) (and the voltage on SUPIC must reach the start level)
before the IC starts operating.
SUPREG is provided with undervoltage protection (UVP-SUPREG; see Section 7.9).
When VSUPREG falls below Vuvp(SUPREG) (typ. 10.3 V), two events will be triggered:
• The IC will stop operating to prevent unreliable switching because the gate driver
voltage is too low. The PFC controller will stop switching immediately, but the HBC
controller will continue until the low-side stroke is active.
• The maximum current from the internal SUPREG series stabilizer is reduced to
Ich(red)(SUPREG) (typ. 5.4 mA). This will reduce the dissipation in the series stabilizer in
the event of an overload at SUPREG while SUPIC is supplied from an external DC
source.
7.2.3 High-side driver floating supply (pin SUPHS)
The high-side driver is supplied by an external bootstrap buffer capacitor, CSUPHS. The
bootstrap capacitor is connected between the high-side reference pin HB and the
high-side driver supply input pin SUPHS. CSUPHS is charged from pin SUPREG via an
SSL4120T
Objective data sheet
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7 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
external diode DSUPHS. The voltage drop between SUPREG and SUPHS can be
minimized by carefully selecting the appropriate diode, especially when using large
MOSFETs and high switching frequencies.
7.2.4 High voltage supply input (pin SUPHV)
In a stand-alone power supply application, this pin is connected to the boost voltage.
CSUPIC and CSUPREG will be charged by the HV start-up source (which delivers a constant
current from SUPHV to SUPIC) via this pin.
Short-circuit protection on pin SUPIC (SCP-SUPIC; see Section 7.9) limits the dissipation
in the HV start-up source when SUPIC is shorted to ground and limits the current on
SUPHV (to Ired(SUPHV)) as long as the voltage on SUPIC is below Vscp(SUPIC).
Under normal operating conditions, the voltage on pin SUPIC will exceed Vscp(SUPIC) very
quickly after start-up and the HV start-up source will switch to the nominal current
Inom(SUPHV).
During start-up and restart, the HV start-up source will charge CSUPIC and regulate the
voltage on SUPIC by hysteretic control. So the start level has a small degree of hysteresis
Vstart(hys)(SUPIC). The HV start-up source switches-off when VSUPIC exceeds the start level
Vstart(hvd)(SUPIC). Current consumption through pin SUPHV will be low (Itko(SUPHV)).
Once start-up is complete and the HBC controller is operating, SUPIC can be supplied
from the auxiliary winding of the HBC transformer. In this operational state, the HV
start-up source is disabled.
7.3 Flow diagram
The operation of the SSL4120T can be divided into a number of states - see Figure 3. The
abbreviations used in Figure 3 are explained In Table 8.
SSL4120T
Objective data sheet
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8 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
START
UVP supplies = yes
NO SUPPLY
-All off
enable PFC = no
UVP supplies = no
DISABLED lC
-Only "Enable lC" detection active
Explanation flow diagram symbols
Enable PFC = yes
THERMAL HOLD
STATE NAME
-Minimum functionality active
-action 1
-action 2
-...
Disabled items are not mentioned
exit condition 1
reached
OTP = no
exit condition 2
reached
SUPIC CHARGE
-HV start-up source on
UVP SUPIC = no
OTP = yes
exit condition
next state can be entered
from any state when exit
condition is true
SUPREG CHARGE
-HV start-up source on
-Series stabilizer on
UVP SUPREG = no
UVP SUPIC= yes
OTP = yes
BOOST CHARGE
-HV start-up source on
-Series stabilizer on
-PFC on
*1Protection timer is activated by:
-UVP output
-OLP HBC
-OCR HBC
-HFP
UVP boost = no &
Enable lC = yes
SCP boost = yes
UVP SUPREG = yes
UVP SUPIC = yes
OTP = yes
UVP SUPREG = yes
UVP SUPIC = yes
OPERATIONAL SUPPLY
-Series stabilizer on
-PFC on
-HBC on
SCP boost = yes
Protection timer
passed *1
RESTART
OVP output =yes
UVP boost = yes
or Enable IC = no
OTP = yes
PROTECTION SHUTDOWN
-HV start-up source on
-Restart timer on
Mains reset = yes
Restart time passed
014aaa851
Fig 3.
Flow diagram of the SSL4120T
Table 3.
Operating states
State
Description
No supply
Supply voltages on SUPIC and SUPHV are too low to provide any functionality. Undervoltage
protection (UVP-supplies; see Section 7.9) is active when VSUPHV < Vrst(SUPHV) and
VSUPIC < Vrst(SUPIC). The IC is reset.
Disabled IC
IC is completely disabled because pin SSHBC/EN is LOW.
Thermal hold
Activated as long as OTP is active. IC is not operating. PFC and HBC controllers are disabled
and CSUPIC and CSUPREG are not charged.
SUPIC charge
IC supply capacitor (CSUPIC) is charged by HV start-up source. CSUPREG is not charged.
SUPREG charge
Stabilized supply capacitor (CSUPREG) is charged by series regulator.
SSL4120T
Objective data sheet
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SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Table 3.
Operating states …continued
State
Description
Boost charge
Boost voltage is built up by operational PFC.
Operational supply
Output voltage is generated. Both PFC and HBC controllers are fully operational.
Restart
Activated when a protection function is triggered. Restart timer is activated. During this time,
PFC and HBC controllers are disabled and CSUPREG is not charged. CSUPIC is charged.
Protection shut-down
Activated when a protection function is triggered. IC is not operational. PFC and HBC controllers
are disabled and CSUPIC and CSUPREG are not charged.
7.4 Enable input (pin SSHBC/EN)
The power supply application can be completely disabled by pulling pin SSHBC/EN LOW.
Figure 4 illustrates the internal functionality. When a voltage is present on pin SUPHV or
on pin SUPIC, a current Ipu(EN) (typ. 42 μA) flows out of SSHBC/EN. If the pin is not
pulled-down, this current will lift the voltage up to Vpu(EN) (typ. 3 V). Since this voltage is
above both Ven(PFC)(EN) (typ. 1.2 V) and Ven(IC)(EN) (typ. 2.2 V), the IC will be completely
enabled.
The IC can be completely disabled by pulling the voltage on SSHBC/EN down below both
Ven(PFC)(EN) and Ven(IC)(EN) via an opto-coupler driven from the secondary side of the HBC
transformer (see Figure 4). The PFC controller will stop switching immediately, but the
HBC controller will continue switching until the low-side stroke is active. It is also possible
to control the voltage on SSHBC/EN from another circuit on the secondary side via a
diode. The external pull-down current must be larger than the internal soft start charge
current Iss(hf)(SSHBC).
If the voltage on SSHBC/EN is pulled down below Ven(IC)(EN), but not below Ven(PFC)(EN),
only the HBC will be disabled. This feature can be useful when another power converter is
connected to the boost voltage of the PFC.
The low-side power switch of the HBC will be on when the HBC is disabled via the
SSHBC/EN pin.
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
10 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
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7.5 IC protection
7.5.1 IC restart and shut-down
In addition to the protection functions that influence the operation of the PFC and HBC
controllers, a number of protection functions are provided that disable both controllers.
See the protection overview in Section 7.9 for details on which protections trigger a restart
or a protection shut-down.
• Restart
When the SSL4120T enters the Restart state, the PFC and HBC controllers are
switched off. After a period defined by the Restart timer, the IC automatically restarts
following the normal start-up cycle.
• Protection shut-down
When the SSL4120T enters the Protection shut-down state, the PFC and HBC
controllers are switched off. The Protection shut-down state is latched, so the IC will
not start up again automatically. It can be restarted by resetting the Protection
shut-down state in one of the following ways:
– by lowering VSUPIC and VSUPHV below their respective reset levels, Vrst(SUPIC) and
Vrst(SUPHV)
– via a fast shut-down reset (see Section 7.5.3).
– via the enable pin (see Section 7.4)
• Thermal hold
In the Thermal hold state, the PFC and HBC controllers are switched off. The Thermal
hold state remains active until the IC junction temperature drops to about 10 °C below
Totp (see Section 7.5.6).
SSL4120T
Objective data sheet
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Rev. 1 — 21 June 2012
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11 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
7.5.2 Protection and restart timer
The SSL4120T contains a programmable timer which can be used for timing several
protection functions. The timer can be used in two ways - as a protection timer and as a
restart timer. The timing of the timers can be set independently via an external resistor
Rprot and capacitor Cprot connected to pin RCPROT.
7.5.2.1
Protection timer
Certain error conditions can be allowed to persist for a period of time before protective
action needs to be taken. The protection timer defines the protection period - how long the
error is allowed to persist before the protection function is triggered. The protection
functions that use the protection timer can be found in the protection overview in
Section 7.9.
present
short
error
long
error
repetative
error
Error
none
Ich(slow)(RCPROT)
IRCPROT
0
Vu(RCPROT)
VRCPROT
0
passed
Protection time
t
014aaa853
Fig 5.
Operation of the protection timer
Figure 5 shows the operation of the protection timer. When an error condition occurs, a
fixed current Ich(slow)(RCPROT) (typ. 100 μA) flows out of the RCPROT pin and charges
Cprot. Rprot will cause the voltage to rise exponentially. The protection time has elapsed
when the voltage on RCPROT reaches the upper switching level Vu(RCPROT) (typ. 4 V). At
this instant, the appropriate protective action is taken and Cprot is discharged.
If the error condition is removed before the voltage on RCPROT reaches Vu(RCPROT), Cprot
is discharged via Rprot and no action is taken.
The voltage on RCPROT may be raised above Vu(RCPROT) by an external circuit to force a
restart.
7.5.2.2
Restart timer
Certain error conditions require the IC to be disabled for a period of time, particularly when
the error condition can cause components to overheat. In such cases, the IC should be
disabled to allow the power supply to cool down, before restarting automatically. The
restart time is determined by the restart timer. The restart timer is active in the Restart
state. The protection functions that trigger a restart can be found in the protection
overview in Section 7.9.
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Resonant power supply control IC with PFC
yes
Restart request
no
Vu(RCPROT)
VRCPROT
Vl(RCPROT)
0
passed
Restart time
t
014aaa854
Fig 6.
Operation of the restart timer
Figure 6 shows the operation of the restart timer. Normally Cprot is discharged to 0 V.
When a restart is requested, Cprot is quickly charged to the upper switching level
Vu(RCPROT). Then the RCPROT pin becomes high ohmic and Cprot discharges through
Rprot. The restart time has elapsed when VRCPROT reaches the lower switching level
Vl(RCPROT) (typ. 0.5 V). The IC then restarts and Cprot is discharged.
7.5.3 Fast shut-down reset (pin SNSMAINS)
The latched Protection shut-down state will be reset when VSUPIC and VSUPHV drop below
their respective reset levels, Vrst(SUPIC) and Vrst(SUPHV). Typically, the PFC boost capacitor,
Cboost, will need to discharge before VSUPIC and VSUPHV drop below their reset levels,
which can take a long time.
Fast shut-down reset facilitates a faster reset. When the mains supply is interrupted, the
voltage on pin SNSMAINS will fall. As soon as VSNSMAINS falls below Vrst(SNSMAINS) and
subsequently rises again by a hysteresis value, the IC will leave the Protection shut-down
state. The boost capacitor Cboost does not need to be discharged to initiate a new start-up.
The Protection shut-down state can also be ended by pulling down the enable input (pin
SSHBC/EN).
7.5.4 Output overvoltage protection (pin SNSOUT)
The SSL4120T outputs are provided with overvoltage protection (OVP-output; see
Section 7.9). The output voltage can be measured via the auxiliary winding of the
resonant transformer. This voltage can be sensed at the SNSOUT pin via an external
rectifier and resistive divider. An overvoltage is detected when the SNSOUT voltage
exceeds Vovp(SNSOUT) (typ. 3.5 V). Once an overvoltage has been detected, the
SSL4120T will go to the Protection shut-down state.
Additional external protection circuits, such as an external overtemperature protection
circuit, can be connected to this pin. They should be connected to pin SNSOUT via a
diode so that the error condition will trigger an OVP event.
7.5.5 Output undervoltage protection (pin SNSOUT)
In applications where the SSL4120T is supplied from the auxiliary winding of the HBC
transformer, a SUPIC undervoltage protection event (UVP-SUPIC) will be triggered
automatically when an error condition results in a drop in the output voltage.
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Resonant power supply control IC with PFC
In applications where the SSL4120T is supplied from a separate DC source (e.g. a
standby supply), the SSL4120T will not automatically stop switching if an error condition
causes the output voltage to fall. For this reason, the SSL4120T outputs are provided with
undervoltage protection (UVP output; see Section 7.9). A UVP output event will restart the
IC if VSNSOUT drops below Vuvp(SNSOUT) (typ. 2.3 V).
During start-up, the output voltage will be below Vuvp(SNSOUT) for a time. This should not
be considered an error condition provided it doesn’t last longer than expected. For this
reason, the protection timer is started as soon as VSNSOUT drops below Vuvp(SNSOUT). The
Restart state is activated if the UVP output event is still active once the protection time has
expired.
7.5.6 OverTemperature Protection (OTP)
Accurate internal overtemperature protection is provided in the SSL4120T. When the
junction temperature exceeds the overtemperature protection activation temperature, Totp
(typ. 150 °C), the IC will go to the Thermal hold state. The SSL4120T will exit the Thermal
hold state when the temperature falls again, to around 10 °C below Totp.
7.6 Burst mode operation (pin SNSOUT)
The HBC and PFC controllers can be operated in Burst mode. In Burst mode the
controllers will be on for a period, then off for a period. Burst mode operation increases
efficiency under low-load conditions.
A low-load condition can be detected using a simple external circuit that makes use of the
information from the feedback loop or from the average primary current. The detection
circuit can pull down pin SNSOUT to pause operation of the SSL4120T for a burst-off
time. Both controllers, or only the HBC controller, can be paused during the burst-off time:
• Burst-off level for HBC, Vburst(HBC) (typ. 1 V).
When VSNSOUT drops below Vburst(HBC), operation of the HBC controller will be
suspended. Both the high-side and the low-side power switches will be off. The PFC
continues to operate normally. When VSNSOUT rises above Vburst(HBC) again, the HBC
controller will resume normal operation, without executing a soft start sequence.
• Burst-off level for PFC, Vburst(PFC) (typ. 0.4 V).
When VSNSOUT drops below Vburst(PFC), operation of the PFC controller will also be
suspended (the HBC will have been paused already). When VSNSOUT rises above
Vburst(PFC) again, the PFC controller will resume normal operation via a PFC soft start
(see Section 7.7.6).
To ensure Burst mode is not activated before the output voltage becomes valid, a current
from the SNSOUT pin (typ. 100 μA) will hold VSNSOUT at Vpu(SNSOUT), which is above both
burst levels. The resistance between the SNSOUT pin and ground should therefore be
greater than 20 kΩ.
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Resonant power supply control IC with PFC
7.7 PFC controller
The PFC controller converts the rectified universal mains voltage into an accurately
regulated boost voltage of 400 V (DC). It operates in quasi-resonant or discontinuous
conduction mode and is controlled via an on-time control system. The resulting mains
harmonic current emissions of a typical application will easily meet the class-D MHR
requirements.
The PFC controller uses valley switching to minimize losses. A primary stroke is only
started once the previous secondary stroke has ended and the voltage across the PFC
MOSFET has reached a minimum value.
7.7.1 PFC gate driver (pin GATEPFC)
The circuit driving the gate of the power MOSFET has a high current sourcing capability
Isource(GATEPFC) (typ. 500 mA) and a high current sink capability Isink(GATEPFC) (typ. 1.2 A).
This permits fast turn-on and turn-off of the power MOSFET to ensure efficient operation.
The driver is supplied from the regulated SUPREG supply.
7.7.2 PFC on-time control
The PFC operates under on-time control. The on-time of the PFC MOSFET is determined
by:
• The error amplifier and the loop compensation via the voltage on pin COMPPFC
At Vton(COMPPFC)zero (typ. 3.5 V), the on-time is reduced to zero. At Vton(COMPPFC)max
the on-time is at a maximum
• Mains compensation via the voltage on pin SNSMAINS
7.7.2.1
PFC error amplifier (pins COMPPFC and SNSBOOST)
The boost voltage is divided via a high-ohmic resistive divider. It is fed to the SNSBOOST
pin. The transconductance error amplifier, which compares the SNSBOOST voltage with
an accurate trimmed reference voltage Vreg(SNSBOOST), is connected to this pin. The
output current is filtered by the external loop compensation network at the COMPPFC pin.
In a typical application, the bandwidth of the regulation loop is set by a resistor and two
capacitors.
The COMPPFC voltage is clamped at a maximum of Vclamp(COMPPFC). This avoids a long
recovery time in the event that the boost voltage rises above the regulation level for a
period of time.
7.7.2.2
PFC mains compensation (pin SNSMAINS)
The mathematical equation for the transfer function of a power factor corrector contains
the square of the mains input voltage. In a typical application, this will result in a low
bandwidth for low mains input voltages, while at high mains input voltages the MHR
requirements may be hard to meet.
The SSL4120T contains a correction circuit to compensate for this effect. The average
mains voltage is measured via the SNSMAINS pin and this information is fed to an
internal compensation circuit. Figure 7 illustrates the relationship between the SNSMAINS
voltage, the COMPPFC voltage, and the on-time. This compensation makes it is possible
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Resonant power supply control IC with PFC
to keep the regulation loop bandwidth constant over the full mains input range, yielding a
fast transient response on load steps, while still complying with class-D MHR
requirements.
ton(max)(lowmains)
VSNSMAINS = 0.9 V
on-time
VSNSMAINS = 3.3 V
ton(max)(highmains)
0
Vton(COMPPFC)max
Vton(COMPPFC)zero VCOMPPFC
014aaa855
Fig 7.
Relationship between on-time, SNSMAINS voltage and COMPPFC voltage
7.7.3 PFC demagnetization sensing (pin SNSAUXPFC)
The voltage on the SNSAUXPFC pin is used to detect transformer demagnetization.
During the secondary stroke, the transformer is magnetized and current flows in the boost
output. During this time, VSNSAUXPFC < Vdemag(SNSAUXPFC) (typ. −100 mV) and the PFC
MOSFET is kept off.
After some time, the transformer becomes demagnetized and current stops flowing in the
boost output. From that moment, VSNSAUXPFC > Vdemag(SNSAUXPFC) and valley detection is
started. The MOSFET remains off.
To ensure switching continues under all circumstances, the MOSFET is forced to
switch on if the magnetizing of the transformer (VSNSAUXPFC < Vdemag(SNSAUXPFC)) is not
detected within tto(mag) (typ. 50 μs) after GATEPFC goes LOW.
It is recommended that a 5 kΩ series resistor be connected to this pin to protect the
internal circuitry, against lightning for example. The resistor should be placed close to the
IC on the printed circuit board to prevent incorrect switching due to external disturbances.
7.7.4 PFC valley sensing (pin SNSAUXPFC)
The PFC MOSFET is switched on for the next stroke to reduce switching losses and EMI
if the voltage at the drain of the MOSFET is at its minimum (valley switching),
see Figure 8.
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Resonant power supply control IC with PFC
on
GATEPFC
off
VBoost
VRect
Dr(PFC)
0
VRect/N
Aux(PFC)
0
Vdemag(SNSAUXPFC)
(VBoost − VRect)/N
lTr(PFC)
0
demagnetized
Demagnetization
magnetized
Valley
(= top for detection)
t
014aaa856
Fig 8.
Demagnetization and valley detection
Valleys are detected by the valley sensing block connected to the SNSAUXPFC pin. This
block measures the voltage at the auxiliary winding of the PFC transformer, which is a
reduced and inverted copy of the MOSFET drain voltage. When a valley of the drain
voltage (= top at SNSAUXPFC voltage) is detected, the MOSFET is switched on.
If no top is detected on the SNSAUXPFC pin (= valley at the drain) within tto(vrec)
(typ. 4 μs) after demagnetization was detected, the MOSFET is forced to switch on.
7.7.5 PFC frequency and off-time limiting
For transformer optimization and to minimize switching losses, the switching frequency is
limited to fmax(PFC). If the frequency for quasi-resonant operation is above fmax(PFC), the
system will switch to Discontinuous conduction mode. The PFC MOSFET is switched on
when the drain-source voltage is at a minimum (valley switching).
The minimum off-time is limited to toff(PFC)min to ensure proper control of the PFC MOSFET
under all circumstances.
7.7.6 PFC soft start and soft stop (pin SNSCURPFC)
The PFC controller features a soft start function which slowly increases the primary peak
current at start-up and a soft stop function which slowly decreases the transformer peak
current, before operations are halted. This is to prevent transformer rattle at start-up or
during Burst mode operation.
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Resonant power supply control IC with PFC
This is achieved by connecting a resistor Rss(PFC) and a capacitor Css(PFC) between
pin SNSCURPFC and the current sense resistor Rcur(PFC). At start-up, an internal current
source Ich(ss)(PFC) charges the capacitor to VSNSCURPFC = Ich(ss)(PFC) × Rss(PFC). The
voltage is limited to the maximum PFC soft start clamp voltage, Vclamp(ss)PFC. The
additional voltage across the charged capacitor results in a reduced peak current. After
start-up, the internal current source is switched-off, capacitor Css(PFC) discharges across
Rss(PFC) and the peak current increases.
The start level and the time constant of the rising primary current can be adjusted
externally by changing the values of Rss(PFC) and Css(PFC).
V ocr ( PFC ) – ( I ch ( ss ) ( PFC ) × R ss ( PFC ) )
I Cur ( PFC ) ( pk ) = --------------------------------------------------------------------------------------------R cur ( PFC )
τ = R ss ( PFC ) × C ss ( PFC )
Soft stop is achieved by switching on the internal current source Ich(ss)(PFC).This current
charges Css(PFC) and the increasing capacitor voltage reduces the peak current. The
charge current will flow as long as the voltage on pin SNSCURPFC is below the maximum
PFC soft start voltage (typ. 0.5 V). If VSNSCURPFC exceeds the maximum PFC soft start
voltage, the soft start current source will start limiting the charge current. To accurately
determine if the capacitor is charged, the voltage is only measured during the off-time of
the PFC power switch. The operation of the PFC is stopped when VSNSCURPFC >
Vstop(ss)(PFC).
7.7.7 PFC overcurrent regulation, OCR-PFC (pin SNSCURPFC)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an
external sense resistor (Rcur(PFC)) connected to the source of the external MOSFET. The
voltage is measured via the SNSCURPFC pin and is limited to Vocr(PFC).
A voltage peak will appear on VSNSCURPFC when the PFC MOSFET is switched on due to
the discharging of the drain capacitance. The leading edge blanking time, tleb(PFC),
ensures that the overcurrent sensing block will not react to this transitory peak.
7.7.8 PFC mains undervoltage protection/brownout protection, UVP-mains
(pin SNSMAINS)
The voltage on the SNSMAINS pin is sensed continuously to prevent the PFC trying to
operate at very low mains input voltages. PFC switching stops as soon as VSNSMAINS
drops below Vuvp(SNSMAINS). Mains undervoltage protection is also called brownout
protection.
VSNSMAINS is clamped to a minimum value of Vpu(SNSMAINS) for fast restart as soon as the
mains input voltage recovers after a mains-dropout. The PFC (re)starts once VSNSMAINS
exceeds the start level Vstart(SNSMAINS).
7.7.9 PFC boost overvoltage protection, OVP-boost (pin SNSBOOST)
An overvoltage protection circuit has been built in to prevent boost overvoltages during
load steps and mains transients.
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Resonant power supply control IC with PFC
Switching of the power factor correction circuit is inhibited as soon as the voltage on the
SNSBOOST pin rises above Vovp(SNSBOOST). PFC switching resumes as soon as
VSNSBOOST drops below Vovp(SNSBOOST) again.
Overvoltage protection will also be triggered in the event of an open circuit at the resistor
connected between SNSBOOST and ground.
7.7.10 PFC short circuit/open-loop protection, SCP/OLP-PFC (pin SNSBOOST)
The power factor correction circuit will not start switching until the voltage on the
SNSBOOST pin rises above Vscp(SNSBOOST). This acts as short circuit protection for the
boost voltage (SCP-boost).
The SNSBOOST pin draws a small input current Iprot(SNSBOOST). If this pin gets
disconnected, the residual current will pull down VSNSBOOST, triggering short circuit
protection (SCP-boost). This combination creates an open-loop protection (OLP-PFC).
7.8 HBC controller
The HBC controller converts the 400 V boost voltage from the PFC into one or more
regulated DC output voltages and drives two external MOSFETS in a half-bridge
configuration connected to a transformer. The transformer, which has a leakage
inductance and a magnetizing inductance, forms the resonant circuit in combination with
the resonant capacitor and the load at the output. The regulation is realized via frequency
control.
7.8.1 HBC high-side and low-side driver (pin GATEHS and GATELS)
Both drivers have identical driving capability. The output of each driver is connected to the
equivalent gate of an external high-voltage power MOSFET.
The low-side driver is referenced to pin PGND and is supplied from SUPREG.
The high-side driver is floating. The reference for the high-side driver is pin HB, connected
to the midpoint of the external half-bridge. The high-side driver is supplied from SUPHS
which is connected to the external bootstrap capacitor CSUPHS. The bootstrap capacitor is
charged from SUPREG via external diode DSUPHS when the low-side MOSFET is on.
7.8.2 HBC boost undervoltage protection, UVP-boost (pin SNSBOOST)
The voltage on the SNSBOOST pin is sensed continuously to prevent the HBC controller
trying to operate at very low boost input voltages. Once VSNSBOOST drops below
Vuvp(SNSBOOST), HBC switching stops the next time GATELS goes HIGH. HBC switching
resumes as soon as VSNSBOOST rises above Vstart(SNSBOOST).
7.8.3 HBC switch control
HBC switch control determines when the MOSFETs switch on and off. It uses the output
from several other blocks.
• A divider is used to realize alternate switching of the high- and low-side MOSFETs for
each oscillator cycle. The oscillator frequency is twice the half-bridge frequency.
• The controlled oscillator determines the switch-off point.
• Adaptive non-overlap time sensing determines the switch-on point. This is the
adaptive non-overlap time function.
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Resonant power supply control IC with PFC
• Several protection circuits and the state of the SSHBC/EN input determine whether
the resonant converter is allowed to start switching.
Figure 9 provides an overview of typical switching behavior.
GATEHS
GATELS
VBoost
HB
0
ITr(HBC) 0
CFMIN
t
014aaa857
Fig 9.
Switching behavior of the HBC
7.8.4 HBC Adaptive Non-Overlap (ANO) time function (pin HB)
7.8.4.1
Inductive mode (normal operation)
The high efficiency characteristic of a resonant converter is the result of Zero-Voltage
Switching (ZVS) of the power MOSFETs, also called soft switching. To facilitate soft
switching, a small non-overlap time is required between the on-times of the high- and
low-side MOSFETs. During this non-overlap time, the primary resonant current
(dis-)charges the capacitance of the half-bridge between ground and the boost voltage.
After this (dis-)charge, the body diode of the MOSFET starts conducting and because the
voltage across the MOSFET is zero, there are no switching losses when the MOSFET is
switched on. This mode of operation is called inductive mode because the switching
frequency is above the resonance frequency and the resonant tank has an inductive
impedance.
The time required for the HB transition depends on the amplitude of the resonant current
at the instant of switching. There is a complex relationship between this amplitude, the
frequency, the boost voltage and the output voltage. Ideally the IC should switch the
MOSFET on as soon as the HB transition has been completed. If it waits any longer, the
HP voltage may swing back, especially at high output loads. The advanced adaptive
non-overlap time function takes care of this timing, so that it’s not necessary to chose a
fixed dead time (which is always a compromise). This saves on external components.
Adaptive non-overlap time sensing measures the HB slope after one MOSFET has been
switched off. Normally, the HB slope starts immediately (the voltage starts rising or falling).
Once the transition at the HB node is complete, the slope ends (the voltage stops
rising/falling). This is detected by the ANO time sensor and the other MOSFET is switched
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Resonant power supply control IC with PFC
on. In this way the non-overlap time is optimized automatically, minimizing switching
losses, even if the HB transition cannot be fully completed. Figure 10 illustrates the
operation of the adaptive non-overlap time function in Inductive mode.
GATEHS
GATELS
VBoost
HB
0
fast HB slope
slow HB slope
t
incomplete HB slope
014aaa858
Fig 10. Adaptive non-overlap time function (normal inductive operation)
The non-overlap time depends on the HB slope, but has upper and lower limits.
An integrated minimum non-overlap time, tno(min), prevents cross conduction occurring
under any circumstances.
The maximum non-overlap time is limited to the oscillator charge time. If the HB slope
lasts longer than the oscillator charge time (= 1⁄4 of HB switching period) the MOSFET is
forced to switch on. In this case the MOSFET is not soft switching. This limitation ensures
that, at very high switching frequencies, the MOSFET on-time is at least 1⁄4 of the HB
switching period.
7.8.4.2
Capacitive mode
The description above holds for normal operation with a switching frequency above the
resonance frequency. When an error condition occurs (e.g. output short, load pulse too
high) the switching frequency can be lower than the resonance frequency. The resonant
tank then has a capacitive impedance. In Capacitive mode, the HB slope does not start
after the MOSFET has switched off. Switching on the other MOSFET is not recommended
in this situation. The absence of soft switching increases dissipation in the MOSFETs. In
Capacitive mode, the body diode in the switched-off MOSFET may start conducting.
Switching on the other MOSFET at this instant can result in the immediate destruction of
the MOSFETs.
The advanced adaptive non-overlap time of the SSL4120T will always wait until the slope
at the half-bridge node starts. It guarantees safe switching of the MOSFETs in all
circumstances. Figure 11 illustrates the operation of the adaptive non-overlap time
function in Capacitive mode.
In Capacitive mode, half the resonance period may elapse before the resonant current
changes back to the correct polarity and starts charging the half-bridge node. The
oscillator is slowed down until the half-bridge slope starts to allow this relatively long
waiting time. See Section 7.8.5 for more details on the oscillator.
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Resonant power supply control IC with PFC
GATEHS
0
GATELS
0
VBoost
no HB slope
HB
0
wrong polarity
ITr(HBC) 0
CFMIN
t
0
delayed
oscillator
014aaa939
delayed switch-on
during capacitive mode
Fig 11. Adaptive non-overlap time function (capacitive operation)
The MOSFET will be forced to switch on if the half-bridge slope fails to start and the
oscillator voltage reaches Vu(CFMIN).
The switching frequency is increased to eliminate the problems associated with
Capacitive mode operation. This is explained in Section 7.8.11.
7.8.5 HBC slope controlled oscillator (pins CFMIN and RFMAX)
The slope-controlled oscillator determines the switching frequency of the half-bridge. The
oscillator generates a triangular waveform between Vu(CFMIN) and Vl(CFMIN) at the external
capacitor Cfmin.
Figure 12 shows how the frequency is determined.
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Resonant power supply control IC with PFC
VOLTAGE PIN SSHBC
FEEDBACK CURRENT
PIN SNSFB
POLARITY INVERSION
(max 2.5 V)
CONVERSION TO
VOLTAGE (max 1.5 V)
VOLTAGE PIN RFMAX
FIXED fmin CURRENT
CONVERSION TO CURRENT
via Rfmax
(DIS-)CHARGE CURRENT
PIN CFMIN
CONVERSION TO
FRQUENCY via Cfmin
014aaa860
Fig 12. Determination of frequency
Two external components determine the frequency range:
• Capacitor Cfmin connected between pin CFMIN and ground sets the minimum
frequency in combination with an internally trimmed current source Iosc(min).
• Resistor Rfmax connected between pin RFMAX and ground sets the frequency range
and thus the maximum frequency.
The oscillator frequency depends on the charge and discharge currents of Cfmin. The
(dis-)charge current contains a fixed component, Iosc(min), that determines the minimum
frequency, and a variable component that is 4.9 times greater than the current in pin
RFMAX. IRFMAX is determined by the value of Rfmax and the voltage on pin RFMAX:
• The voltage on pin RFMAX is Vfmin(RFMAX) (typ. 0 V) at the minimum frequency.
• The voltage on pin RFMAX is Vfmax(fb)(RFMAX) (typ. 1.5 V) at the maximum feedback
frequency.
• The voltage on pin RFMAX is Vfmax(ss)(RFMAX) (typ. 2.5 V) at the maximum soft start
frequency.
The maximum frequency of the oscillator is limited internally. The HB frequency is limited
to flimit(HB) (min. 500 kHz). Figure 13 illustrates the relationship between VRFMAX, Rfmax,
Cfmin and fHB.
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Resonant power supply control IC with PFC
flimit(HB)
fmax(B)
C
B
fmax(A)
A
fHB
fmin(B and C)
fmin(A)
0
VRFMAX
Vfmax(fb)(RFMAX) Vfmax(ss)(RFMAX)
014aaa861
A: Cfmin = high, Rfmax = high
B: Cfmin = low, Rfmax = low
C: Cfmin = low, Rfmax = too low
Fig 13. Function of Rfmax and Cfmin
The oscillator is controlled by the slope of the half-bridge. The oscillator charge current is
initially set to a low value Iosc(red) (typ. 30 μA). When the start of the half-bridge slope is
detected, the charge current is increased to its normal value. This feature is used in
combination with the adaptive non-overlap time function as described in Section 7.8.4.2
and Figure 11. Since the half-bridge slope normally starts directly after the MOSFET is
switched off, the length of time the oscillator current is low will be negligible under normal
operating conditions.
7.8.6 HBC feedback input (pin SNSFB)
In a typical power supply application, the output voltage is compared and amplified on the
secondary side. The output of the error amplifier is transferred to the primary side via an
opto-coupler. This opto-coupler can be connected directly to the SNSFB pin.
The SNSFB pin supplies the opto-coupler from an internal voltage source Vpu(SNSFB)
(typ. 8.4 V) with a series resistance RO(SNSFB). The series resistance allows spike filtering
via an external capacitor. To ensure sufficient bias current for the opto-coupler, the
feedback input has a threshold current Ifmin(SNSFB) (typ. 0.66 mA) at which the frequency is
at a minimum. The maximum frequency is reached at Ifmax(SNSFB) (typ 2.2 mA). The
maximum frequency that can be reached via the SNSFB pin is lower (typ. 60 %) than the
maximum frequency that can be reached via the SSHBC/EN pin. Figure 14 shows the
relationship between ISNSFB, VSNSFB and VRFMAX.
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Resonant power supply control IC with PFC
Vpu(SNSFB)
Vfmax(ss)(RFMAX)
VSNSFB
Volp(SNSFB)
VSSHBC = 8.4 V
Vfmin(SNSFB)
VSNSFB
Vfmax(fb)(RFMAX)
VRFMAX
Vfmax(SNSFB)
Vclamp(SNSFB)
VRFMAX
0
0 Iolp(SNSFB) Ifmin(SNSFB)
Ifmax(SNSFB)
ISNSFB
0
Iclamp(SNSFB)
014aaa862
Fig 14. Transfer function of feedback input
Below the level for minimum frequency, VSNSFB is clamped at Vclamp(SNSFB) (typ. 3.2 V).
This clamp enables a fast recovery of the output voltage regulation loop after an
overshoot of the output voltage. The maximum current the clamp can deliver is
Iclamp(SNSFB) (typ. 7.3 mA).
7.8.7 HBC open-loop protection, OLP-HBC (pin SNSFB)
Under normal operating conditions, the opto-coupler current will be between Ifmin(SNSFB)
and Ifmax(SNSFB) and will pull down the voltage at pin SNSFB. Due to an error in the
feedback loop, the current could be less than Ifmin(SNSFB) with the HBC controller
delivering maximum output power.
The HBC controller features open-loop protection (OLP-HBC), which monitors the voltage
on pin SNSFB. When VSNSFB exceeds Volp(SNSFB), the protection timer is started. The
Restart state is activated if the OLP condition is still present after the protection time has
elapsed.
7.8.8 HBC soft start (pin SSHBC/EN)
The relationship between switching frequency and output current is not constant. It
depends strongly on the output voltage and the boost voltage. This relationship can be
complex. The SSL4120T contains a soft start function to ensure that the resonant
converter starts or restarts with safe currents. This soft start function forces a start at such
a high frequency that currents will be acceptable under all conditions. Soft start then
slowly decreases the frequency. Normally, output voltage regulation will have taken over
frequency control before soft start has reached its minimum frequency. Limiting the output
current during start-up also limits the rate at which the output voltage rises and prevents
an overshoot.
Soft start utilizes the voltage on pin SSHBC/EN. The timing of the soft start is set by
external capacitor Css(HBC). Pin SSHBC/EN is also used as an enable input. Soft start
voltage levels are above the enable voltage thresholds.
7.8.8.1
Soft start voltage levels
The relationship between the soft start voltage at pin SSHBC/EN and the voltage at pin
RFMAX, which is directly related to the frequency, is illustrated in Figure 15.
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Resonant power supply control IC with PFC
VRFMAX
fmax
fHB
Vfmax,ss(RFMAX)
fHB
Vfmax,fb(RFMAX)
VRFMAX
fmin
0
Vfmax(SSHBC)
0
Vpu(EN)
Vclamp(SSHBC)
Vfmin(SSHBC)
VSSHBC
ISNSFB < Ifmin(SNSFB)
Ifmin(SNSFB) < ISNSFB < Ifmax(SNSFB)
014aaa863
Fig 15. Relation between SSHBC/EN voltage and frequency
VRFMAX and VSSHBC/EN are of opposite polarity. At initial start-up, VSSHBC/EN is below
Vfmax(SSHBC) (typ. 3.2 V), which corresponds to the maximum frequency. During start-up,
Css(HBC) is charged, VSSHBC/EN rises and the frequency decreases. The contribution of the
soft start function is zero when VSSHBC/EN is above Vfmin(SSHBC) (typ. 7.9 V).
VSSHBC/EN is clamped at a maximum of Vclamp(SSHBC) (typ. 8.4 V) (frequency is at a
minimum) and at a minimum (≈ 3 V). Below Vfmax(SSHBC) (maximum frequency), the
discharge current is reduced to a maximum-frequency soft start current of typically 5 μA
The voltage is clamped at a minimum of Vpu(EN) (typ. 3 V). Both clamp levels are just
outside the operating area of Vfmax(SSHBC) to Vfmin(SSHBC). The margins avoid frequency
disturbance during normal output voltage regulation, but ensure that overcurrent
regulation can respond quickly.
7.8.8.2
Soft start charge and discharge
At initial start-up, the soft start capacitor Css(HBC) is charged to obtain a decreasing
frequency sweep from maximum to operating frequency. As well as being used to softly
start up the resonant converter, the soft start functionality is also used for regulation
purposes (such as overcurrent regulation). Css(HBC) can therefore be charged or
discharged. In the case of overcurrent regulation, a continuous alternation between
charging and discharging takes place. In this way VSSHBC/EN can be regulated, thereby
overruling the signal from the feedback input.
The (dis-)charge current can have a high value, Iss(hf)(SSHBC) (typ. 160 μA), resulting in a
fast (dis-)charge, or it can have a low value Iss(lf)(SSHBC) (typ. 40 μA), resulting in a slow
(dis-)charge. This two-speed soft start sweep allows for a combination of a short start-up
time for the resonant converter and stable regulation loops (such as overcurrent
regulation).
The fast (dis-)charge speed is used for the upper frequency range where VSSHBC/EN is
below Vss(hf-lf)(SSHBC) (typ. 5.6 V). In the upper frequency range, the currents in the
converter do not react strongly to frequency variations.
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SSL4120T
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Resonant power supply control IC with PFC
The slow (dis-)charge speed is used for the lower frequency range where VSSHBC/EN is
above Vss(hf-lf)(SSHBC) (typ. 5.6 V). In the lower frequency range, the currents in the
converter react strongly to frequency variations.
Section 7.8.10.2 describes how the two-speed soft start function is used for overcurrent
regulation.
The soft start capacitor is neither charged nor discharged during non-operation time in
Burst mode. The soft start voltage will not change during this time.
7.8.8.3
Soft start reset
Some protection functions, such as overcurrent protection, require fast correction of the
operating frequency set point, but do not require switching to stop. See the protection
overview in Section 7.9 for details on which protection functions use this step to the
maximum frequency. The SSL4120T has a special fast soft start reset feature for the HBC
controller that forces Vfmax(ss)(RFMAX) on pin RFMAX. Soft start reset is also used when the
HBC controller is enabled via the SSHBC/EN pin or after a restart to ensure a safe start at
maximum frequency. Soft start reset is not used when the operation was stopped in Burst
mode.
When a protection function is activated, the oscillator control input is disconnected from
the soft start capacitor, Css(HBC), connected between pin SSHBC/EN and ground and the
switching frequency is immediately set to a maximum. Setting the switching frequency to
a maximum will restore safe switching operation in most cases. At the same time, the
capacitor is discharged to the maximum frequency level, Vfmax(SSHBC). Once VSSHBC/EN
has reached this level, the oscillator control input is connected to the pin again and the
normal soft start sweep follows. Figure 16 shows the soft start reset and the two-speed
frequency sweep downwards.
Protection
on
off
Vfmin(SSHBC)
VSSHBC/EN
Vss(hf-lf)(SSHBC)
Vfmax(SSHBC)
0
fmax
fHB
fmin
0
regulation
fmax
forced
t
fast
sweep
slow sweep
regulation
014aaa864
Fig 16. Soft start reset and two-speed soft start
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Resonant power supply control IC with PFC
7.8.9 HBC high-frequency protection, HFP-HBC (pin RFMAX)
Normally the converter will not operate continuously at maximum frequency because it will
sweep down to much lower values. Certain error conditions, such as a disconnected
transformer, could cause the converter to operate continuously at maximum frequency. If
zero-voltage switching conditions are no longer present, the MOSFETs can overheat. The
SSL4120T features High-Frequency Protection (HFP) for the HBC controller to protect it
from being damaged in such circumstances.
HFP senses the voltage at pin RFMAX. This voltage indicates the current frequency.
When the frequency is higher than 75 % of the soft start frequency range, the protection
timer is started. The 75 % level corresponds to an RFMAX voltage of Vhfp(RFMAX)
(typ. 1.83 V).
7.8.10 HBC overcurrent regulation and protection, OCR and OCP
(pin SNSCURHBC)
The HBC controller is protected against overcurrent in two ways:
• Overcurrent regulation (OCR-HBC) which increases the frequency slowly; the
protection timer is also started.
• Overcurrent protection (OCP-HBC) which steps to maximum frequency.
A boost voltage compensation function is included to reduce the variation in the output
current protection level.
7.8.10.1
Boost voltage compensation
The primary current, also known as the resonant current, is sensed via pin SNSCURHBC.
It senses the momentary voltage across an external current sense resistor Rcur(HBC). The
use of the momentary current signal allows for fast overcurrent protection and simplifies
the stabilizing of overcurrent regulation. The OCR and OCP comparators compare
VSNSCURHBC with the maximum positive and negative values.
For the same output power, the primary current is higher when the boost voltage is low. A
boost compensation is included to reduce the dependency of the protected output current
level on the boost voltage. The boost compensation sources and sinks a current from the
SNSCURHBC pin. This current creates a voltage drop across the series resistor Rcurcmp.
The amplitude of the current depends linearly on the boost voltage. At nominal boost
voltage the current is zero and the voltage VCur(HBC) across the current sense resistor is
also present at the SNSCURHBC pin. At the UVP-boost start level Vuvp(SNSBOOST), the
current is at a maximum. The direction of the current, sink or source, depends on the
active gate signal. The voltage drop created across Rcurcmp reduces the amplitude at the
pin, resulting in a higher effective current protection level. The amount of compensation is
set by the value of Rcurcmp. Figure 17 shows how the boost compensation works for an
artificial current signal. The sinking compensation current only flows when VSNSCURHBC is
positive because of the circuit implementation.
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Resonant power supply control IC with PFC
Vreg
VBoost
Vuvp
t
GATEHS
t
GATELS
t
sink
ISNSCURHBC
sink current only with positive VSNSCURHBC
0
t
source
VCur(HBC) = Rcur(HBC) × ICur(HBC)
Iocp(high)
Iocr(high)
Iocp(nom)
Iocr(nom)
ICur(HBC)
0
−Iocr(nom)
−Iocp(nom)
−Iocr(high)
−Iocp(high)
t
VSNSCURHBC
Vocp(HBC)
Vocr(HBC)
VSNSCURHBC
0
−Vocr(HBC)
−Vocp(HBC)
t
nominal VBoost
no compensation
nominal OCR
nominal VBoost
no compensation
nominal OCP
low VBoost
strong compensation
high OCR
low VBoost
strong compensation
high OCP
014aaa865
Fig 17. Boost voltage compensation
7.8.10.2
Overcurrent regulation, OCR-HBC
The lowest comparator levels at the SNSCURHBC pin, Vocr(HBC) (typ. −0.5 V and +0.5 V),
relate to the overcurrent regulation voltage. There are comparators for both the positive
and negative polarities. The positive comparator is active during the high-side on-time and
the following high-side to low-side non-overlap time. The negative comparator is active
during the remaining time. If either level is exceeded, the frequency will be slowly
increased. This is accomplished by discharging the soft start capacitor. Each time the
OCR level is exceeded, the event is latched until the next stroke and the soft start
discharge current is enabled. When both the positive and negative OCR levels are
exceeded, the soft start discharge current will flow continuously.
Overcurrent regulation is very effective at limiting the output current during start-up. A
smaller soft start capacitor can be used to achieve a faster start-up. Using a smaller
capacitor may result in an output current that is too high at times, but the OCR function will
slow down the frequency sweep when needed to keep the output current within the
specified limits. Figure 18 shows the operation of the OCR during output voltage start-up.
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Resonant power supply control IC with PFC
Iocr
ICur(HBC)
0
t
−Iocr
Iss(hf)(SSHBC)
ISSHBC/EN Iss(If)(SSHBC)
−Iss(If)(SSHBC)
t
−Iss(hf)(SSHBC)
Vfmin(SSHBC)
VSSHBC/EN
Vss(hf-lf)(SSHBC)
Vfmax(SSHBC)
t
0
Vreg
VOutput
t
0
Fast soft-start sweep (charge and discharge)
Slow soft-start sweep (charge and discharge)
014aaa866
Fig 18. Overcurrent regulation during start-up
The protection timer is also started. The Restart state is activated when the OCR-HBC
condition is still present after the protection time has elapsed.
7.8.10.3
Overcurrent protection, OCP-HBC
Under normal operating conditions, OCR is able to ensure the current remains below the
specified maximum values. In the event of certain error conditions, however, it might not
be fast enough to limit the current. OCP is implemented to protect against those error
conditions. The OCP level, Vocp(HBC) (typ. −1 V and +1 V), is higher than the OCR level
Vocr(HBC).
When the OCP level is reached, the frequency immediately jumps to the maximum value
via the soft start reset, followed by a normal sweep down.
7.8.11 HBC capacitive mode regulation, CMR (pin HB)
The MOSFETs in the half-bridge drive the resonant circuit. Depending on the output load,
the output voltage, and the switching frequency this resonant circuit can have an inductive
impedance or a capacitive impedance. Inductive impedance is preferred because it
facilitates efficient zero-voltage switching.
Harmful switching in Capacitive mode is prevented by the adaptive non-overlap time
function (see Section 7.8.4.2). An extra action is performed which results in Capacitive
Mode Regulation (CMR). CMR causes the half-bridge circuit to return to Inductive mode
from Capacitive mode.
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Resonant power supply control IC with PFC
Capacitive mode is detected when the HB slope does not start within tto(cmr) after the
MOSFETs have switched off. Detection of Capacitive mode will increase the switching
frequency. This is realized by discharging the soft start capacitor with a relatively high
current Icmr(hf)(SSHBC) from the instant tto(cmr) has expired until the half-bridge slope has
started. The frequency increase regulates the HBC to the border between capacitive and
inductive mode.
7.9 Protection overview
Table 4.
Overview protections
Protected Symbol
Part
Protection
Affected
Action
Description
IC
UVP-SUPIC
Undervoltage protection SUPIC
IC
disable
Section 7.2.1
IC
UVP-SUPREG
Undervoltage protection SUPREG IC
disable
Section 7.2.2
IC
UVP-supplies
Undervoltage protection supplies
IC
disable and reset
Section 7.3
IC
SCP-SUPIC
Short circuit protection SUPIC
IC
low HV start-up current
Section 7.2.4
IC
OVP-output
Overvoltage protection output
IC
shut-down
Section 7.5.4
IC
UVP-output
Undervoltage protection output
IC
restart after protection time Section 7.5.5
IC
OTP
Overtemperature protection
IC
disable
Section 7.5.6
PFC
OCR-PFC
Overcurrent regulation PFC
PFC
switch off cycle-by-cycle
Section 7.7.7
PFC
UVP-mains
Undervoltage protection mains
PFC
suspend switching
Section 7.7.8
PFC
OVP-boost
Overvoltage protection boost
PFC
suspend switching
Section 7.7.9
PFC
SCP-boost
Short circuit protection boost
IC
restart
Section 7.7.10
PFC
OLP-PFC
Open-loop protection PFC
IC
restart
Section 7.7.10
HBC
UVP-boost
Undervoltage protection boost
HBC
disable
Section 7.8.2
HBC
OLP-HBC
Open-loop protection HBC
IC
restart after protection time Section 7.8.7
HBC
HFP-HBC
High-frequency protection HBC
IC
restart after protection time Section 7.8.9
HBC
OCR-HBC
Overcurrent regulation HBC
HBC
IC
increase frequency
Section 7.8.10.2
restart after protection time
HBC
OCP-HBC
Overcurrent protection HBC
HBC
step to maximum
frequency
Section 7.8.10.3
HBC
CMR
Capacitive mode regulation
HBC
increase frequency
Section 7.8.11
HBC
ANO
Adaptive non-overlap
HBC
prevent hazardous
switching
Section 7.8.4
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8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to pin SGND;
Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current
ratings are valid provided the maximum power rating is not violated.
Symbol
Parameter
Conditions
Min
Max
Unit
VSUPHV
voltage on pin SUPHV
continuous
−0.4
+630
V
VSUPHS
voltage on pin SUPHS
DC
−0.4
+570
V
t < 0.5 s
−0.4
+630
V
referenced to pin HB
−0.4
+14
V
Voltages
VSUPIC
voltage on pin SUPIC
−0.4
+38
V
VSNSAUXPFC
voltage on pin SNSAUXPFC
−25
+25
V
VSUPREG
voltage on pin SUPREG
−0.4
+12
V
VSNSOUT
voltage on pin SNSOUT
−0.4
+12
V
VRCPROT
voltage on pin RCPROT
−0.4
+12
V
VSNSFB
voltage on pin SNSFB
−0.4
+12
V
VSSHBC/EN
voltage on pin SSHBC/EN
−0.4
+12
V
VGATEHS
voltage on pin GATEHS
t < 10 µs for I > 10 mA
−0.4
VSUPHS + 0.4
V
VGATELS
voltage on pin GATELS
t < 10 µs for I > 10 mA
−0.4
VSUPREG + 0.4
V
VGATEPFC
voltage on pin GATEPFC
t < 10 µs for I > 10 mA
−0.4
VSUPREG + 0.4
V
VSNSCURHBC
voltage on pin SNSCURHBC
−5
+5
V
VSNSBOOST
voltage on pin SNSBOOST
−0.4
+5
V
VSNSMAINS
voltage on pin SNSMAINS
−0.4
+5
V
VSNSCURPFC
voltage on pin SNSCURPFC
−0.4
+5
V
VCOMPPFC
voltage on pin COMPPFC
−0.4
+5
V
VCFMIN
voltage on pin CFMIN
−0.4
+5
V
VPGND
voltage on pin PGND
−1
+1
V
−0.8
+2
A
−1
+10
mA
-
0.8
W
current limited
Currents
IGATEPFC
current into pin GATEPFC
ISNSCURPFC
current into pin SNSCURPFC
duty cycle < 10 %
General
Tamb < 75 °C
Ptot
total power dissipation
Tstg
storage temperature
−55
+150
°C
Tj
junction temperature
−40
+150
°C
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Resonant power supply control IC with PFC
Table 5.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).; All voltages are measured with respect to pin SGND;
Currents are positive when flowing into the IC; The voltage ratings are valid provided other ratings are not violated; Current
ratings are valid provided the maximum power rating is not violated.
Symbol
Parameter
Conditions
Electrostatic discharge voltage
Human body model
Min
Max
Unit
ESD
VESD
Pin 12 (SUPHV)
[1]
-
1.5
kV
Pin 13,14,15 (HS driver)
[1]
-
1
kV
other pins
[1]
-
2
kV
[2]
-
200
V
-
500
V
Machine model
All pins
Charged device model
All pins
[1]
Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
[2]
Equivalent to discharging a 200 pF capacitor through a 0.75 μH coil and a 10 Ω resistor.
9. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
In free air; JEDEC single
layer test board
90
K/W
10. Characteristics
Table 7.
Characteristics
Tamb = 25 °C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
High-voltage start-up source (pin SUPHV)
Idism(SUPHV)
disable mode current on pin
SUPHV
Disabled IC state
-
150
-
μA
Ired(SUPHV)
reduced current on pin SUPHV
VSUPIC < Vscp(SUPIC)
-
1.1
-
mA
Inom(SUPHV)
nominal current on pin SUPHV
VSUPIC < Vstart(hvd)(SUPIC)
-
5.1
-
mA
Itko(SUPHV)
takeover current on pin SUPHV
VSUPIC > Vstart(hvd)(SUPIC)
Vdet(SUPHV)
detection voltage on pin SUPHV
Vrst(SUPHV)
reset voltage on pin SUPHV
-
7
-
μA
-
-
25
V
VSUPIC < Vrst(SUPIC)
-
7
-
V
Low-voltage IC supply (pin SUPIC)
Vstart(hvd)(SUPIC)
start voltage with high voltage
detected
VSUPHV > Vdet(SUPHV)
21
22
23
V
Vstart(nohvd)(SUPIC)
start voltage with no high voltage
detected
VSUPHV < Vdet(SUPHV) or open
16.1
17
17.9
V
Vstart(hys)(SUPIC)
hysteresis of start voltage on pin
SUPIC
-
0.3
-
V
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Resonant power supply control IC with PFC
Table 7.
Characteristics …continued
Tamb = 25 °C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vuvp(SUPIC)
undervoltage protection voltage on
pin SUPIC
14.2
15
15.8
V
Vrst(SUPIC)
reset voltage on pin SUPIC
-
7
-
V
Vscp(SUPIC)
short-circuit protection voltage on
pin SUPIC
0.55
0.65
0.75
V
Ich(red)(SUPIC)
reduced charge current on pin
SUPIC
-
−0.95
-
mA
Ich(nom)(SUPIC)
nominal charge current on pin
SUPIC
-
−4.8
-
mA
Idism(SUPIC)
current on pin SUPIC in disabled
mode
Disabled IC state
-
0.25
-
mA
Iprotm(SUPIC)
current on pin SUPIC in protection
mode
SUPIC charge, SUPREG
charge; Restart or
Shut-down state
-
0.4
-
mA
Ioper(SUPIC)
current on pin SUPIC in operating
mode
Operational supply state;
Driver pins open.
-
3
-
mA
VSUPHV < Vrst(SUPHV)
VSUPIC < Vscp(SUPIC)
Regulated supply (pin SUPREG)
ISUPREG = −40 mA
[1]
10.6
10.9
11.2
V
start voltage on pin SUPREG
[1]
-
10.7
-
V
Vuvp(SUPREG)
undervoltage protection voltage on
pin SUPREG
[1]
-
10.3
-
V
Ich(SUPREG)max
maximum charge current on pin
SUPREG
VSUPREG > Vuvp(SUPREG)
−40
−100
-
mA
Ich(red)(SUPREG)
reduced charge current on pin
SUPREG
VSUPREG < Vuvp(SUPREG);
T = 25 °C.
-
−5.5
-
mA
T = 140 °C
−2.5
-
-
mA
Vreg(SUPREG)
regulation voltage on pin SUPREG
Vstart(SUPREG)
Enable input (pin SSHBC/EN)
Ven(PFC)(EN)
PFC enable voltage on pin EN
PFC only
[2]
0.8
1.2
1.4
V
[2]
1.8
2.2
2.4
V
-
−42
-
μA
-
3
-
V
-
0.8
-
V
Ven(IC)(EN)
IC enable voltage on pin EN
PFC + HBC
Ipu(EN)
pull-up current on pin EN
VSSHBC/EN = 2.5 V
Vpu(EN)
pull-up voltage on pin EN
Fast shut-down reset (pin SNSMAINS)
Vrst(SNSMAINS)
reset level on pin SNSMAINS
[2]
Protection and restart timer (pin RCPROT)
Vu(RCPROT)
upper voltage on pin RCPROT
3.8
4
4.2
V
Vl(RCPROT)
lower voltage on pin RCPROT
0.4
0.5
0.6
V
Ich(fast)(RCPROT)
fast-charge current on pin RCPROT
-
−2.2
-
mA
Ich(slow)(RCPROT)
slow-charge current on pin
RCPROT
−120
−100
−80
μA
SSL4120T
Objective data sheet
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Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
34 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Table 7.
Characteristics …continued
Tamb = 25 °C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Output voltage protection sensing, UVP/OVP output (pin SNSOUT)
Vovp(SNSOUT)
overvoltage protection voltage on
pin SNSOUT
[2]
3.4
3.5
3.6
V
Vuvp(SNSOUT)
under-voltage protection voltage on
pin SNSOUT
[2]
2.2
2.35
2.5
V
[2]
130
150
160
°C
Overtemperature protection
Totp
overtemperature protection trip
temperature
Burst mode activation (pin SNSOUT)
Vburst(HBC)
HFC burst mode voltage
[2]
0.9
1.1
1.2
V
Vburst(PFC)
PFC burst mode voltage
[2]
0.3
0.4
0.5
V
Ipu(SNSOUT)
pull-up current on pin SNSOUT
-
−100
−80
μA
Vpu(SNSOUT)
pull-up voltage on pin SNSOUT
RSNSOUT = 25 kΩ to SGND
-
1.5
-
V
PFC driver (pin GATEPFC)
Isource(GATEPFC)
source current on pin GATEPFC
VGATEPFC = 2 V
-
−0.5
Isink(GATEPFC)
sink current on pin GATEPFC
VGATEPFC = 2 V
-
0.7
-
A
VGATEPFC = 10 V
-
1.2
-
A
A
PFC on-timer (pin COMPPFC)
Vton(COMPPFC)zero
zero on-time voltage on pin
COMPPFC
-
3.5
-
V
Vton(COMPPFC)max
maximum on-time voltage on pin
COMPPFC
-
1.25
-
V
fmax(PFC)
PFC maximum frequency
300
380
460
kHz
toff(PFC)min
minimum PFC off-time
-
0.8
-
μs
PFC error amplifier (pin SNSBOOST and COMPPFC)
Vreg(SNSBOOST)
regulation voltage on pin
SNSBOOST pin
ICOMPPFC = 0 A
2.475 2.5
2.525 V
gm
transconductance
VSNSBOOST to ICOMPPFC
-
80
-
μA/V
Isink(COMPPFC)
sink current on pin COMPPFC
VSNSBOOST = 2 V
-
39
-
μA
Isource(COMPPFC)
source current on pin COMPPFC
VSNSBOOST = 3.3 V
Vclamp(COMPPFC)
clamp voltage on pin COMPPFC
-
−39
-
μA
-
3.9
-
V
high mains;
VSNSMAINS = 3.3 V
3.5
4.7
5.9
μs
low mains;
VSNSMAINS = 0.97 V
29
44
59
μs
4
-
-
V
[3]
PFC mains compensation (pin SNSMAINS)
ton(max)
Vmvc(SNSMAINS)max
SSL4120T
Objective data sheet
maximum on-time
maximum mains voltage
compensation voltage on pin
SNSMAINS
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Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
35 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Table 7.
Characteristics …continued
Tamb = 25 °C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PFC demagnetization sensing (pin SNSAUXPFC)
Vdemag(SNSAUXPFC)
demagnetization voltage on pin
SNSAUXPFC
−150
−100
−50
mV
tto(mag)
magnetization time-out time
40
50
60
μs
Iprot(SNSAUXPFC)
protection current on pin
SNSAUXPFC
−75
−33
-
nA
-
-
1.7
V/μs
VSNSAUXPFC = 50 mV
PFC valley sensing (pin SNSAUXPFC)
(dV/dt)vrec(min)
minimum valley recognition rate of
voltage change
tslope(vrec)min
minimum valley recognition slope
time
VSNSAUXPFC = 1 Vpp
[4]
-
-
300
ns
demagnetization to ΔV/Δt = 0
[5]
-
-
50
ns
td(val-dem)max
maximum valley-to-demag delay
time
-
200
-
ns
tto(vrec)
valley recognition time-out time
3
4
6
μs
-
−60
-
μA
0.46
0.5
0.54
V
PFC soft start (pin SNSCURPFC)
Ich(ss)(PFC)
PFC soft-start charge current
PFC soft-start clamp voltage
[1]
Vstop(ss)(PFC)
PFC soft-start stop voltage
[1]
Rss(PFC)
PFC soft-start resistor
Vclamp(ss)(PFC)
-
0.45
-
V
12
-
-
kΩ
0.49
0.52
0.55
V
PFC overcurrent sensing (pin SNSCURPFC)
Vocr(PFC)
PFC overcurrent regulation voltage
dV/dt = 50 mV/μs
0.51
0.54
0.57
V
tleb(PFC)
leading edge blanking time
250
310
370
ns
Iprot(SNSCURPFC)
protection current on pin
SNSCURPFC
−50
−33
-
nA
dV/dt = 200 mV/μs
PFC mains voltage sensing and clamp (pin SNSMAINS)
start voltage on pin SNSMAINS
[1]
1.11
1.15
1.19
V
Vuvp(SNSMAINS)
undervoltage protection voltage on
pin SNSMAINS
[1]
0.84
0.89
0.94
V
Vpu(SNSMAINS)
pull-up voltage on pin SNSMAINS
UVP-mains active
-
1.05
-
V
Ipu(SNSMAINS)
maximum clamp current
UVP-mains active
-
−42
−35
μA
Iprot(SNSMAINS)
Protection current on pin
SNSMAINS
VSNSMAINS > Vuvp(SNSMAINS)
-
33
100
nA
Vstart(SNSMAINS)
[1]
PFC boost voltage protection sensing, SCP/UVP/OVP boost (pin SNSBOOST)
Vscp(SNSBOOST)
short-circuit protection voltage on
pin SNSBOOST
0.35
0.4
0.45
V
Vstart(SNSBOOST)
start voltage on pin SNSBOOST
-
2.3
2.4
V
Vuvp(SNSBOOST)
undervoltage protection voltage on
pin SNSBOOST
1.5
1.6
-
V
Vovp(SNSBOOST)
overvoltage protection voltage on
pin SNSBOOST
2.59
2.63
2.67
V
SSL4120T
Objective data sheet
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Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
36 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Table 7.
Characteristics …continued
Tamb = 25 °C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Iprot(SNSBOOST)
protection current on pin
SNSBOOST
VSNSBOOST = 2.5 V
-
45
100
nA
HBC high-side and low-side driver (pin GATEHS and GATELS)
Isource(GATEHS)
source current on pin GATEHS
VGATEHS − VHB = 4 V
-
−310
-
mA
Isource(GATELS)
source current on pin GATELS
VGATELS − VPGND = 4 V
-
−310
-
mA
Isink(GATEHS)
sink current on pin GATEHS
Isink(GATELS)
sink current on pin GATELS
Vrst(SUPHS)
reset voltage on pin SUPHS
Iq(SUPHS)
quiescent current on pin SUPHS
VGATEHS − VHB = 2 V;
-
560
-
mA
VGATEHS − VHB = 11 V
-
1.9
-
A
VGATELS − VPGND = 2 V
-
560
-
mA
VGATELS − VPGND = 11 V
-
1.9
-
A
-
4.5
-
V
VSUPHS − VHB = 11 V
-
37
-
μA
HBC adaptive non-overlap time (pin HB)
(dV/dt)ano(min)
minimum adaptive non-overlap time
rate of voltage change
-
-
120
V/μs
tno(min)
minimum non-overlap time
-
-
160
ns
HBC current controlled oscillator (pin CFMIN and RFMAX)
fmin(HB)
minimum frequency on pin HB
Cfmin = 390 pF;
VSSHBC/EN > Vfmin(SSHBC)
VSNSFB > Vfmin(SNSFB)
40
44
48
kHz
Iosc(min)
minimum oscillator current
VRFMAX = 0 V; charge and
discharge
-
150
-
μA
Iosc(max)
maximum oscillator current
Rfmax = 15 kΩ;
VRFMAX=2.5 V;
VSSHBC/EN < Vfmax(SSHBC)
-
970
-
μA
Iosc(red)
reduced oscillator current
slowed-down oscillator
-
−30
-
μA
ICFMIN/IRFMAX
current on pin CFMIN to current on
pin RFMAX ratio
-
4.9
-
flimit(HB)
limit frequency on pin HB
500
670
-
kHz
Vu(CFMIN)
upper voltage on pin CFMIN
2.85
3
3.15
V
Cfmin = 20 pF
Vl(CFMIN)
lower voltage on pin CFMIN
0.9
1
1.1
V
Vfmin(RFMAX)
minimum frequency voltage on pin
RFMAX
-
0
-
V
Vfmax(ss)(RFMAX)
maximum soft start frequency
voltage on pin RFMAX
VSSHBC/EN < Vfmax(SSHBC)
2.4
2.5
2.6
V
Vfmax(fb)(RFMAX)
maximum feedback frequency
voltage on pin RFMAX
VSNSFB < Vfmax(SNSFB)
1.45
1.55
1.65
V
HBC feedback input (pin SNSFB)
Vpu(SNSFB)
pull-up voltage on pin SNSFB
-
8.4
-
V
RO(SNSFB)
output resistance on pin SNSFB
-
1.5
-
kΩ
Volp(SNSFB)
open-loop protection voltage on pin
SNSFB
[2]
7
7.7
7.9
V
Iolp(SNSFB)
open-loop protection current on pin
SNSFB
[2]
−0.35 −0.26
−0.1
mA
SSL4120T
Objective data sheet
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Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
37 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Table 7.
Characteristics …continued
Tamb = 25 °C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vfmin(SNSFB)
minimum frequency voltage on pin
SNSFB
6.1
6.4
6.9
V
Ifmin(SNSFB)
minimum frequency current on pin
SNSFB
VSSHBC/EN > Vfmin(SSHBC)
−0.86 −0.66
−0.46 mA
Vfmax(SNSFB)
maximum frequency voltage on pin
SNSFB
VSSHBC/EN > Vfmin(SSHBC)
3.9
4.1
4.3
V
Ifmax(SNSFB)
maximum frequency current on pin
SNSFB
VSSHBC/EN > Vfmin(SSHBC)
-
−2.2
-
mA
Vclamp(SNSFB)
clamp voltage on pin SNSFB
maximum frequency;
ISNSFB = −4 mA
-
3.2
-
V
Iclamp(SNSFB)
clamp current on pin SNSFB
maximum frequency;
VSNSFB = 0 V
-
−7.3
-
mA
-
3.2
-
V
7.5
7.9
8.3
V
-
8.4
-
V
-
5.6
-
V
HBC soft-start (pin SSHBC/EN)
Vfmax(SSHBC)
maximum frequency voltage on pin
SSHBC
Vfmin(SSHBC)
minimum frequency voltage on pin
SSHBC
Vclamp(SSHBC)
clamp voltage on pin SSHBC
Vss(hf-lf)(SSHBC)
high-low frequency soft-start
voltage on pin SSHBC
Iss(hf)(SSHBC)
high frequency soft-start current on
pin SSHBC
VSNSFB > Vfmin(SNSFB)
[2]
VSSHBC < Vss(lf-hf)(SSHBC)
charge current
-
−160
-
μA
discharge current
-
160
-
μA
charge current
-
−40
-
μA
discharge current
low frequency soft-start current on
pin SSHBC
VSSHBC > Vss(lf-hf)(SSHBC)
-
40
-
μA
Icmr(hf)(SSHBC)
high frequency CMR current on pin
SSHBC
VSSHBC < Vss(lf-hf)(SSHBC)
discharge only
-
1800
-
μA
Icmr(lf)(SSHBC)
low frequency CMR current on pin
SSHBC
VSSHBC > Vss(lf-hf)(SSHBC)
discharge only
-
440
-
μA
1.7
1.83
2
V
positive level;
HS on + HS-LS non-overlap
time
0.45
0.5
0.55
V
negative level;
LS on + LS-HS non-overlap
time
−0.55 −0.5
Iss(lf)(SSHBC)
HBC high frequency sensing, HFP - HBC (pin RFMAX)
Vhfp(RFMAX)
[2]
High-frequency protection voltage
on pin RFMAX
HBC overcurrent sensing, OCR/OCP - HBC (pin SNSCURHBC)
Vocr(HBC)
SSL4120T
Objective data sheet
HBC overcurrent regulation voltage
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
−0.45 V
© NXP B.V. 2012. All rights reserved.
38 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Table 7.
Characteristics …continued
Tamb = 25 °C; VSUPIC = 20 V; VSUPHV > 40 V; all voltages are measured with respect to SGND; currents are positive when
flowing into the IC; unless otherwise specified.
Symbol
Parameter
Vocp(HBC)
HBC overcurrent protection voltage
Ibstc(SNSCURHBC)max
maximum boost compensation
current on pin SNSCURHBC
Conditions
Min
Typ
Max
Unit
positive level;
HS on + HS-LS non-overlap
time
0.9
1
1.1
V
negative level;
LS on + LS-HS non-overlap
time
−1.1
−1
−0.9
V
source current;
VSNSCURHBC = −0.5 V
-
−170
-
μA
sink current;
VSNSCURHBC = 0.5 V
-
170
-
μA
-
690
-
ns
VSNSBOOST = 1.8 V
HBC Capacitive Mode Protection (CMP) (pin HB)
tto(cmr)
[1]
time-out capacitive mode regulation
The marked levels on this pin are correlated. The voltage difference between the levels has much less spread than the absolute value of
the levels themselves.
[2]
Switching level has some hysteresis. The hysteresis falls within the limits.
[3]
For a typical application with a compensation network on pin COMPPFC, like the example in Figure 19.
[4]
Minimum required voltage change time for valley recognition on pin SNSAUXPFC.
[5]
Minimum time required between demagnetization detection and ΔV/Δt = 0 on pin SNSAUXPFC.
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
39 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
11. Application information
5HFW
%RRVW
7U3)&
&683,&
$X[3)&
0DLQV
'683+6
&ERRVW
&UHFW
&6835(*
683+9 683,&
&683+6
6835(*
6160$,16
616&853)&
&XU3)&
5FXU3)&
&+%
&XU+%&
616&85+%&
*$7(3)&
3RZHU)DFWRU
&RQWUROOHU
5HVRQDQW
+DOI%ULGJH 616287
&RQWUROOHU
7U+%&
&5HV
*$7(/6
616$8;3)&
5VV3)&
+%
+%
616%2267
'U3)&
683+6
*$7(+6
5FXUFPS
2XWSXW
5FXU+%&
&VV3)&
616)%
&2033)&
5)0$;
5SURW
&)0,1
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66/
66+%&(1
5IPD[
&IPLQ
&VV+%&
&SURW
3*1'
6*1'
'LVDEOH
DDD
Fig 19. Application diagram of SSL4120T
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
40 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
12. Package outline
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
15.6
15.2
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.61
0.60
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT137-1
075E05
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 20. Package outline SOT137 (SO24)
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
41 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
13. Abbreviations
Table 8.
SSL4120T
Objective data sheet
Abbreviations
Acronym
Description
ANO
Adaptive Non-Overlap
CMOS
Complementary Metal-Oxide-Semiconductor'
CMR
Capacitive Mode Regulation
DMOS
Double-diffused Metal-Oxide-Semiconductor
EMI
ElectroMagnetic Interference
HBC
Half-Bridge Converter or Controller. Resonant converter which generates the
regulated output voltage.
HFP
High-Frequency Protection
HV
High-voltage
OCP
OverCurrent Protection
OCR
OverCurrent Regulation
OLP
Open-Loop Protection
OTP
OverTemperature Protection
OVP
OverVoltage Protection
PFC
Power Factor Converter or Controller. Converter which performs the power factor
correction.
UVP
UnderVoltage Protection
SCP
Short-Circuit Protection
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
42 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
14. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SSL4120T v.1
20120621
Objective data sheet
-
-
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
43 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
SSL4120T
Objective data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
44 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
45 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
17. Contents
1
2
2.1
2.2
2.3
2.4
3
4
5
6
6.1
6.2
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
7.5
7.5.1
7.5.2
7.5.2.1
7.5.2.2
7.5.3
7.5.4
7.5.5
7.5.6
7.6
7.7
7.7.1
7.7.2
7.7.2.1
7.7.2.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
General features . . . . . . . . . . . . . . . . . . . . . . . . 2
PFC controller features. . . . . . . . . . . . . . . . . . . 2
HBC controller features . . . . . . . . . . . . . . . . . . 2
Protection features . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Overview of IC modules . . . . . . . . . . . . . . . . . . 5
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Low-voltage supply input
(pin SUPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Regulated supply
(pin SUPREG) . . . . . . . . . . . . . . . . . . . . . . . . . 7
High-side driver floating supply
(pin SUPHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
High voltage supply input
(pin SUPHV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Enable input (pin SSHBC/EN) . . . . . . . . . . . . 10
IC protection . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IC restart and shut-down . . . . . . . . . . . . . . . . 11
Protection and restart timer . . . . . . . . . . . . . . 12
Protection timer . . . . . . . . . . . . . . . . . . . . . . . 12
Restart timer . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fast shut-down reset
(pin SNSMAINS). . . . . . . . . . . . . . . . . . . . . . . 13
Output overvoltage protection
(pin SNSOUT) . . . . . . . . . . . . . . . . . . . . . . . . 13
Output undervoltage protection
(pin SNSOUT) . . . . . . . . . . . . . . . . . . . . . . . . 13
OverTemperature Protection (OTP) . . . . . . . . 14
Burst mode operation
(pin SNSOUT) . . . . . . . . . . . . . . . . . . . . . . . . 14
PFC controller. . . . . . . . . . . . . . . . . . . . . . . . . 15
PFC gate driver
(pin GATEPFC). . . . . . . . . . . . . . . . . . . . . . . . 15
PFC on-time control . . . . . . . . . . . . . . . . . . . . 15
PFC error amplifier
(pins COMPPFC and SNSBOOST) . . . . . . . . 15
PFC mains compensation
(pin SNSMAINS). . . . . . . . . . . . . . . . . . . . . . . 15
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.8.4.1
7.8.4.2
7.8.5
7.8.6
7.8.7
7.8.8
7.8.8.1
7.8.8.2
7.8.8.3
7.8.9
7.8.10
7.8.10.1
7.8.10.2
7.8.10.3
7.8.11
7.9
PFC demagnetization sensing
(pin SNSAUXPFC). . . . . . . . . . . . . . . . . . . . .
PFC valley sensing
(pin SNSAUXPFC). . . . . . . . . . . . . . . . . . . . .
PFC frequency and off-time limiting . . . . . . . .
PFC soft start and soft stop
(pin SNSCURPFC) . . . . . . . . . . . . . . . . . . . .
PFC overcurrent regulation, OCR-PFC
(pin SNSCURPFC) . . . . . . . . . . . . . . . . . . . .
PFC mains undervoltage protection/brownout
protection, UVP-mains
(pin SNSMAINS) . . . . . . . . . . . . . . . . . . . . . .
PFC boost overvoltage protection,
OVP-boost (pin SNSBOOST) . . . . . . . . . . . .
PFC short circuit/open-loop protection,
SCP/OLP-PFC
(pin SNSBOOST). . . . . . . . . . . . . . . . . . . . . .
HBC controller . . . . . . . . . . . . . . . . . . . . . . . .
HBC high-side and low-side driver
(pin GATEHS and GATELS) . . . . . . . . . . . . .
HBC boost undervoltage protection,
UVP-boost (pin SNSBOOST) . . . . . . . . . . . .
HBC switch control. . . . . . . . . . . . . . . . . . . . .
HBC Adaptive Non-Overlap
(ANO) time function (pin HB) . . . . . . . . . . . . .
Inductive mode (normal operation) . . . . . . . .
Capacitive mode . . . . . . . . . . . . . . . . . . . . . .
HBC slope controlled oscillator
(pins CFMIN and RFMAX) . . . . . . . . . . . . . . .
HBC feedback input
(pin SNSFB). . . . . . . . . . . . . . . . . . . . . . . . . .
HBC open-loop protection, OLP-HBC
(pin SNSFB). . . . . . . . . . . . . . . . . . . . . . . . . .
HBC soft start
(pin SSHBC/EN) . . . . . . . . . . . . . . . . . . . . . .
Soft start voltage levels . . . . . . . . . . . . . . . . .
Soft start charge and discharge . . . . . . . . . . .
Soft start reset . . . . . . . . . . . . . . . . . . . . . . . .
HBC high-frequency protection, HFP-HBC
(pin RFMAX) . . . . . . . . . . . . . . . . . . . . . . . . .
HBC overcurrent regulation and protection,
OCR and OCP (pin SNSCURHBC) . . . . . . . .
Boost voltage compensation . . . . . . . . . . . . .
Overcurrent regulation, OCR-HBC . . . . . . . .
Overcurrent protection, OCP-HBC. . . . . . . . .
HBC capacitive mode regulation, CMR
(pin HB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection overview . . . . . . . . . . . . . . . . . . . .
16
16
17
17
18
18
18
19
19
19
19
19
20
20
21
22
24
25
25
25
26
27
28
28
28
29
30
30
31
continued >>
SSL4120T
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 June 2012
© NXP B.V. 2012. All rights reserved.
46 of 47
SSL4120T
NXP Semiconductors
Resonant power supply control IC with PFC
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
Application information. . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
33
33
40
41
42
43
44
44
44
44
45
45
46
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 21 June 2012
Document identifier: SSL4120T