UM3699 Rev. A RELIABILITY REPORT FOR UM3699 PLASTIC ENCAPSULATED DEVICES June 25, 2008 UNION INTEGRATED PRODUCTS Written by Reviewed by Sindy Bi Quality Assurance Engineer Tina Liu Quality Assurance Executive Director Conclusion The UM3699 successfully meets the quality and reliability standards required of all Union products. In addition, Union’s continuous reliability monitoring program ensures that all outgoing products will continue to meet Union’s quality and reliability standards. Table of Contents I. .........Device Description II. ........Manufacturing Information III. .......Packaging Information IV.........Die Information I. V. ........Quality Assurance Information VI. .......Reliability Evaluation ......Attachments Device Description A. General The UM3699 dual independent ultra low RON DPDT analog switch operates from a single +1.65V to +5.5V supply. It features a 0.6Ω (max) RON for its NO and NC switch at a +3.0V supply. The UM3699 features break-before-make switching action (15ns) with tON=50ns and tOFF=30ns at +4.5V. The device has a 3.8KΩ internal shut resistors that automatically discharge the capacitance at the normally open (NO) and normally closed (NC) terminals when they are not connected. This reduces click-and-pop noises that occur when switching audio signals between precharged points. B. Absolute Maximum Ratings Item VCC, VIN_ NO_, NC_, COM_ (Note 1) Continuous Current from COM_ to NO_/NC_ Peak Current from COM_ to NO_/NC_ (10% duty cycle) Storage Temperature Lead Temp. (Soldering, 30S) Rating -0.5V to +5.5V -0.5V to VCC ±300mA ±500mA -65°C to +150°C +260°C Note 1: Signals on NO_, NC_, and COM_ exceeding VCC or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. II. III. Manufacturing Information A. Description/ Function: Ultra-Low R ON , Dual DPDT Analog Switch B. Process: Standard 0.35 micron silicon gate CMOS C. Number of Device Transistors: 5176 D. Fabrication Location: Suzhou, Jang Su province, China E. Assembly Location: KH (Diodes Shanghai) F. Date of Initial Production: Dec, 2007 Packaging Information A. Package Type: QFN16 B. Lead Frame: Cu (C7025HH) C. Lead Finish: Ni/Pd/Au D. Die Attach: Epoxy(QM1519) E. Bondwire: Gold (1.0 mil diameter) F. Mold Material: EME-G770H-HCD G. Assembly Diagram: Attachment: AD-KH-UM3699 H. Flammability Rating: Class UL94-V0 I. IV. Classification of Moisture Sensitivity per JEDEC standard JESD22-A112: Level 1 Die Information A. Dimensions: 60 x 60 mils B. Passivation: Si3N4/SiO2 C. Interconnect: Aluminum/Si (Si=1%) D. Backside Metallization: None E. Minimum Metal Width: 0.5 microns F. Minimum Metal Spacing: 0.5 microns G. Bondpad Dimensions: 3.5 mil. Sq. H. Isolation Dielectric: SiO2 I. Die Separation Method: Wafer Saw (Silicon nitride/ Silicon dioxide) V. VI. Quality Assurance Information A. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% for all Visual Defects. B. Observed Outgoing Defect Rate: C. Sampling Plan: < 50 ppm Mil-Std-105D Reliability Evaluation A. Accelerated Life Test The results of the 125℃ biased (static) life test are shown in Table 1. Using these results, the Failure Rate (λ) is calculated as follows: λ= 1 MTTF = 1.83 2 × 77 × 168 × 2502 1 ⎞ ⎛ E A ⎞⎛ 1 − ⎟ ⎟⎜ At=exp ⎜ ⎝ k ⎠⎝ T 2 T 1 ⎠ (Chi square value for MTTF upper limit) At: thermal acceleration factor assuming a 0.8eV activation energy EA=Average thermal activation energy for expected failure mechanisms=0.8eV k= Boltzmann’s constant= 8.62×10-5 eV/K T1= Life test operating temperature=125℃ T2= System use operating temperature=25℃ λ = 28.27x 10-9 F.I.T.=28.27 (60% confidence level @ 25°C) This low failure rate represents data collected from Union’s reliability monitor program. In addition to routine production Burn-In, Union pulls a sample from every fabrication process three times per week and subjects it to an extended Burn-In prior to shipment to ensure its reliability. The reliability control level for each lot to be shipped as standard product is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Union performs failure analysis on any lot that exceeds this reliability control level. Attached Burn-In Schematic (Attachment 4#: BI-KH-UM3699) shows the static Burn-In circuit. B. Moisture Resistance Tests Union pulls pressure pot samples from every assembly process three times per week. Each lot sample must meet an LTPD = 20 or less before shipment as standard product. Additionally, the industry standard 85°C /85%RH testing is done per generic device/package family once a quarter. C. E.S.D. and Latch-Up Testing The UW002 die type has been found to have all pins able to withstand a transient pulse of ± 2000V, per Mil- Std-883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of ±200mA and/or 9V. Attachment #1 TABLE Ⅰ Reliability Evaluation Test Results UM3699 TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES DC Parameters & functionality 77 0 Static Life Test (Note 1) Ta = 125°C Biased Time = 168 hrs. Moisture Testing (Note 2) Pressure Pot T = 121°C P = 15 PSIG RH= 100% Time = 96hrs. DC Parameters & functionality 77 0 85/85 (Note 3) T = 85°C RH = 85% Vr =100V Time = 1000hrs. DC Parameters & functionality 77 0 DC Parameters 77 Mechanical Stress (Note 2) Temperature Cycle Note 1: Note 2: Note 3: -65°C/150°C 1000 Cycles JESD22 A-104 Life Test Data may represent plastic D.I.P. qualification lots. Generic Package/Process data Board Level 0 Attachment #2 TABLE II. Pin combination to be tested. 1/ 2/ Terminal A (Each pin individually connected to terminal A with the other floating) Terminal B (The common combination of all like-named pins connected to terminal B) 1. All pins except VPS1 3/ All VPS1 pins 2. All input and output pins All other input-output pins 1/ 2/ 3/ Table II is restated in narrative form in 3.4 below. No connects are not to be tested. Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 Pin combination to be tested. a. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. b. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., VSS1 , or VSS2 or VSS3 or VCC1 , or VCC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. c. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open. TERMINAL C R1 R2 S1 TERMINAL A REGULATED HIGH VOLTAGE SUPPLY S2 DUT SHORT SOCKET C1 TERMINAL B Mil Std 883D Method 3015.7 TERMINAL D R = 1.5kΩ C = 100pF CURRENT PROBE Attachment #3 Attachment #4