上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 BL3085A 上海市宜山路 810 号 Fax: 86-021-64855865 High ESD-Protected, Fail-Safe, Slew-Rate-Limited RS-485 Transceivers BL3085A GENERAL DESCRIPTION The BL3085A is a +/-15kV electrostatic discharge (ESD) protected, high-speed transceiver for RS-485 communication that contain one driver and one receiver. The device feature fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted. This means that the receiver output will be logic high even if all transmitters on a terminated bus are disabled. The BL3085A feature reduced slew-rate driver that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. All transmitter outputs and receiver inputs are protected to +/-15kV using the Human Body Air Gap Model. The transceiver typically draws 500uA of supply current when unloaded, or when fully loaded with the driver disabled. All device have a 1/8-unit-load receiver input impedance that allows up to 256 transceivers on the bus. The BL3085A is intended for half-duplex communications. BL3085A is available in industry-standard 8-pin SO or DIP packages. APPLICATIONS RS-485 Communications Level Translators Transceivers for EMI-Sensitive Applications Industrial Control Local Area Networks Energy Meter Networks Power Inverters Building Automation Networks Telecommunications Equipment PIN Configuration o RO VDD RE B DE A DI GND D 1 上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 BL3085A 上海市宜山路 810 号 Fax: 86-021-64855865 ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC) ..........................................................+ 7V Control Input Voltage (RE, DE)...................-0.3V to (VCC + 0.3V Driver Input Voltage (DI).............................-0.3V to (VCC + 0.3V) Driver Output Voltage (A, B)...............................……-8V to +13V Receiver Input Voltage (A, B) ....................................-8V to +13V Receiver Output Voltage (RO)....................-0.3V to (VCC + 0.3V) Operating Temperature Ranges...........................-40°C to +85°C DC ELECTRICAL CHARACTERISTICS (VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5 V DRIVER Differential Driver Output (no load) VOD1 Figure 1 Differential Driver Output VOD2 Figure 1, R = 27Ω Change in Magnitude of Differential Output Voltage (Note 2) ∆VOD Figure 1, R = 27Ω 0.2 V Driver Common-Mode Output Voltage VOC Figure 1, R = 27Ω 3 V Change In Magnitude of Common-Mode Voltage (Note 2) ∆VOC Figure 1, R = 27Ω 0.2 V Input High Voltage VIH1 DE, DI, RE Input Low Voltage VIL1 DE, DI, RE DI Input Hysteresis VHYS Input Current (A and B) IIN1 1.5 2 VOD1 V 0.8 100 DE = GND, VIN = 12V VCC = GND or 5.25V VIN = -7V -7V ≤ VOUT ≤ VCC Driver Short-Circuit Output Current (Note 3) V V mV 125 µA -75 -250 0V ≤ VOUT ≤ 12V 0V ≤ VOUT ≤ VCC ±25 -7V ≤ VCM ≤ 12V -200 250 mA -50 mV RECEIVER Receiver Differential Threshold Voltage VTH -125 Receiver Input Hysteresis ∆VTH 25 Receiver Voltage Output High VOH IO = -4mA, VID = -50mV Receiver Voltage Output Low VOL IO = 4mA, VID = -200mV 0.4 V Three-State Output Current at Receiver IOZR 0.4V ≤ VO ≤ 2.4V ±1 µA Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V 96 Receiver Output Short-Circuit Current IOSR 0V ≤ VRO ≤ VCC ±7 2 mV VCC -1.5 V kΩ ±95 mA 上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 BL3085A PARAMETER SYMBOL CONDITIONS 上海市宜山路 810 号 Fax: 86-021-64855865 MIN TYP MAX No load, RE = DE = VCC DI = GND or DE = GND VCC 475 1000 420 800 DE = GND, VRE = VCC 12 60 UNITS SUPPLY CURRENT Supply Current Supply Current Shutdown Mode in ISHDN µA µA SWITCHING CHARACTERISTICS (VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) PARAMETER Driver Input to Output SYMBOL CONDITIONS MIN TYP MAX tDPLH Fig 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF 250 720 2000 250 720 1000 -3 ±100 ns 530 750 ns tDPHL Driver Output | tDPLH - tDPHL | Skew Driver Rise or Fall Time Maximum Data Rate Driver High Enable to tDSKEW Fig 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF tDR, tDF Fig 3 and 5, RDIFF = 54Ω, CL1 = CL2 = 100pF fMAX Output 200 250 UNITS ns kbps tDZH Figures 4 and 6, CL = 100pF, S2 closed 2500 ns Driver Enable to Output Low tDZL Figures 4 and 6, CL = 100pF, S1 closed 2500 ns Driver Disable Time from Low tDLZ Figures 4 and 6, CL = 15pF, S1 closed 100 ns Driver Disable Time from High tDHZ Figures 4 and 6, CL = 15pF, S2 closed 100 ns Figures 7 and 9; | VID | ≥ 2.0V; rise and fall time of VID ≤ 15ns 127 200 ns tRSKD Figures 7 and 9; | VID | ≥ 2.0V; rise and fall time of VID ≤ 15ns 3 ±30 ns Receiver Enable to Output Low tRZL Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Enable to Output High tRZH Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns Receiver Disable Time from Low tRLZ Figures 2 and 8, CL = 100pF, S1 closed 20 50 ns Receiver Disable Time from High tRHZ Figures 2 and 8, CL = 100pF, S2 closed 20 50 ns 200 600 ns Receiver Input to Output | tRPLH - tRPHL | Differential Receiver Skew Time to Shutdown tRPLH, tRPHL tSHDN (Note 4) 50 Driver Enable from tDZH(SHDN) Shutdown to Output High Figures 4 and 6, CL = 15pF, S2 closed 4500 ns Driver Enable from tDZL(SHDN) Shutdown to Output Low Figures 4 and 6, CL = 15pF, S1 closed 4500 ns Receiver Enable from tRZH(SHDN) Shutdown to Output High Figures 2 and 8, CL = 100pF, S2 closed 3500 ns Receiver Enable from tRZL(SHDN) Shutdown to Output Low Figures 2 and 8, CL = 100pF, S1 closed 3500 ns 3 上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 BL3085A 上海市宜山路 810 号 Fax: 86-021-64855865 Note 1: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device ground unless otherwise noted. Note 2: ∆VOD and ∆VOC are the changes in VOD and VOC, respectively, when the DI input changes state. Note 3: Maximum current level applies to peak current just prior to foldback-current limiting; minimum current level applies during current limiting. Note 4: The device is put into shutdown by bringing RE high and DE low. If the enable inputs are in this state for less than 50ns, the device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least 600ns, the device is guaranteed to have entered shutdown. TEST CIRCUITS AND TIMING DIAGRAMS A VOD R 1k TEST POINT RECEIVER OUTPUT CRL 15pF R VCC S1 1k VOC S2 B Figure 1. Driver DC Test Load 3V DE Figure 2. Receiver Enable/Disable Timing Test Load CL1 A DI RDIFF VCC S1 500Ω OUTPUT UNDER TEST VID B CL CL2 S2 Figure 3. Driver Timing Test Circuit Figure 4. Driver Enable/Disable Timing Test Load 3V DI 1.5V 3V DE 1.5V 1.5V 1.5V 0V 0V tZH, tZH(SHDN) tPLH tPHL tHZ OUTPUT HIGH OUT (B) OUT (A, B) VO 1/2 VO VOH - 0.5V 2.3V 0V OUT (A) tZL, tZL(SHDN) VDIFF (A-B) 90% 90% 10% 10% tR VOH tLZ VCC +VOD OUT (A, B) -VOD 2.3V OUTPUT LOW tF SKEW = |tPLH - tPHL| Figure 6. Driver Enable and Disable Times Figure 5. Driver Propagation Delays 4 VOL + 0.5V V OL 上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 BL3085A 上海市宜山路 810 号 Fax: 86-021-64855865 3V A RE +1V 0V INPUT 1.5V 0V 0V B tZH, tZH(SHDN) -1V tPLH tPHL RO VCC 1.5V RO 1.5V tHZ OUTPUT HIGH 1.5V VOH - 0.5V VOH 0V 1.5V 0V tZL, tZL(SHDN) tLZ VCC RO 1.5V OUTPUT LOW Figure 7. Receiver Propagation Delays VOL + 0.5V V OL Figure 8. Receiver Enable and Disable Times B VID ATE RR RECEIVER OUTPUT A Figure 9. Receiver Propagation Delay Test Circuit PIN DESCRIPTION NAME FUNCTION 1 RO 2 RE 3 DE 4 DI 5 6 7 8 GND A B VCC Receiver Output. When RE is low and if A - B ≥ -50mV, RO will be high; if A - B ≤ -200mV, RO will be low. Receiver Output Enable. Drive RE low to enable RO; RO is high impedance when RE is high. Drive RE high and DE low to enter low-power shutdown mode. Driver Output Enable. Drive DE high to enable driver outputs. These outputs are high impedance when DE is low. Drive RE high and DE low to enter low-power shutdown mode. Driver Input. With DE high, a low on DI forces noninverting output low and inverting output high. Similarly, a high on DI forces non-inverting output high and inverting output low. Ground Noninverting Receiver Input and Noninverting Driver Output Inverting Receiver Input and Inverting Driver Output Positive Supply 4.75V ≤ VCC ≤ 5.25V PIN 5 BL3085A 上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 上海市宜山路 810 号 Fax: 86-021-64855865 FUNCTION TABLES TRANSMITTING INPUTS RE X X 0 1 DE 1 1 0 0 RECEIVING INPUTS RE 0 0 0 1 1 DI 1 0 X X B 0 1 High-Z DE X X X 1 0 A-B ≥ -0.05V ≤ -0.2V Open/shorted X X OUTPUTS A 1 0 High-Z Shutdown OUTPUT RO 1 0 1 High-Z Shutdown X = Don’t care Shutdown mode, driver and receiver outputs high impedance DETAILED DESCRIPTION The BL3085A high-speed transceiver for RS-485 communication contains one driver and one receiver. These devices feature fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted, or when they are connected to a terminated transmission line with all drivers disabled (see the Fail-Safe section). The BL3085A feature reduced slew-rate driver that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 250kbps (see the Reduced EMI and Reflections section). The BL3085A is a half-duplex transceiver. The part operates from a single +5V supply. Drivers are output short-circuit current limited. Thermal shutdown circuitry protects drivers against excessive power dissipation. When activated, the thermal shutdown circuitry places the driver outputs into a high impedance state. RECEIVER INPUT FILTERING The receiver of the BL3085A, when operating in 250kbps, incorporate input filtering in addition to input hysteresis. This filtering enhances noise immunity with differential signals that have very slow rise and fall times. Receiver propagation delay increases by 20% due to this filtering. FAIL-SAFE The BL3085A guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between -50mV and -200mV. If the input voltage of differential receiver (A-B) is greater than or equal to -50mV, RO is logic high. If A-B is less than or equal to -200mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver differential input voltage is pulled to 0V by the termination. With the receiver thresholds of the BL3085A, this results in a logic high with a 50mV minimum noise margin. Unlike previous fail-safe devices, the -50mV to -200mV threshold complies with the +/-200mV EIA/TIA-485 standard. 6 BL3085A 上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 上海市宜山路 810 号 Fax: 86-021-64855865 ESD PROTECTION As with BL3085A, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the BL3085A have extra protection against static electricity. The ESD-protected pins are tested with reference to the ground pin in a powered-down condition. They are tested to +/-15kV using the Human Body Model. POWER USAGE IN AN RS-485 TRANSCEIVER Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the receiving nodes, plus the termination resistors at each end of the bus. The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard defines a unit load as allowing up to 1mA. With up to 32 unit loads allowed on the bus, the total current supplied to all receivers can be as high as 32mA. The BL3085A is rated as a 1/8 unit load device. The bus input current is less than 1/8mA, allowing up to 256 nodes on a single bus. Any combination of these devices and/or other RS-485 transceivers with a total of 32 unit loads or less can be connected to the line. The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120ohm resistor at each end, this sums to 25mA differential output current whenever the bus is active. Typically the BL3085A can drive more than 25mA to a 60ohm load, resulting in a differential output voltage higher than the minimum required by the standard. Overall, the total load current can be 60mA to a loaded RS-485 bus. This is in addition to the current required by the transceiver itself; the BL3085A circuitry requires only about 0.4mA with both driver and receiver enabled, and only 0.3mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode, neither the driver nor receiver is active. And the supply current is very low. Supply current increases with signaling rate primarily due to the totem pole outputs of the driver. When these outputs change state, there is a moment when both the high-side and low-side output transistors are conducting and this creates a short spike in the supply current. As the frequency of state changes increases, more power is used. LOW-POWER SHUTDOWN MODE When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode, most internal circuitry is powered down except over temperature protection circuit, and the supply current is typically 15uA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. 7 BL3085A 上海贝岭股份有限公司 zip: 200233 Tel: 86-021-64850700 上海市宜山路 810 号 Fax: 86-021-64855865 If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the DI input after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the DI input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature. If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. DRIVER OUTPUT PROTECTION Two mechanisms prevent excessive output current and power dissipation caused by faults or by bus contention. The first, a fold back current limit on the output stage, provides immediate protection against short circuits over the whole common-mode voltage range. The second, a thermal shutdown circuit, force the driver outputs into a high-impedance state if the die temperature becomes excessive. LAYOUT CONSIDERATION A ground plane is recommended when using a high frequency device like the BL3085A. A 0.1uF ceramic bypass capacitor less than 1/4 inch away from the VDD pin is recommended. Good bypassing is especially needed when operating at maximum frequency or when package to package matching is very important. The PC board traces connected to the A and B outputs must be kept as symmetrical and short as possible to obtain the same parasitic board capacitance. This maintains the good matching characteristics of the low-to-high and high to low transitions of the BL3085A. Note that output A to output B capacitance should also be minimized. If routed adjacent to each other on the same layer, they should be separated by an amount at least as wide as the trace widths. If output A and output B are routed on different signal planes, they should not be routed directly on top of each other. A trace width lateral separation is also recommended. As mentioned before, care should also be taken when routing the DI input. To achieve consistent board-to board propagation delay, the ringing on this signal should be kept below a few hundred millivolts. 8