74LCX574 Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Features General Description ■ 5V tolerant inputs and outputs The LCX574 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-toHIGH Clock (CP) transition. ■ 2.3V–3.6V VCC specifications provided ■ 7.5ns tPD max. (VCC = 3.3V), 10µA ICC max. ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal(1) ■ ±24mA output drive (VCC = 3.0V) ■ Implements proprietary noise/EMI reduction circuitry ■ Latch-up performance exceeds JEDEC 78 conditions ■ ESD performance – Human body model > 2000V – Machine model > 200V Note: 1. To ensure the high impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. The LCX574 is functionally identical to the LCX374 except for the pinouts. The LCX574 is designed for low voltage applications with capability of interfacing to a 5V signal environment. The LCX574 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Information Order Number Package Number Package Description 74LCX574WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX574SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX574BQX(2) MLP20B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm 74LCX574MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX574MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs December 2013 Pin Assignments for SOIC, SOP, SSOP, TSSOP OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 20 2 19 3 18 4 17 5 16 6 7 15 14 8 13 9 12 10 11 D0 D1 D2 D3 D4 D5 D6 D7 CP VCC O0 O1 O2 O3 O4 O5 O6 O7 CP OE O0 O1 O2 O3 O4 O5 O6 O7 Truth Table Inputs OE CP D Pad Assignments for DQFN OE VCC 1 Internal Outputs 20 Q On Function H H L NC Z Hold H H H NC Z Hold H L H Z Load H H L Z Load L L H L Data Available D0 2 19 O0 D1 3 18 O1 H L H D2 4 17 O2 L H L NC NC No Change in Data D3 5 16 O3 L H H NC NC No Change in Data D4 6 15 O4 D5 7 14 O5 D6 8 13 O6 D7 9 12 O7 10 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change 11 GND CP Functional Description (Bottom View) (Top View) The LCX574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the loading of the flip-flops. Pin Descriptions Pin Names D0–D7 Data Available Description Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs DAP No Connect Note: DAP (Die Attach Pad) Logic Diagram D0 D1 D2 D3 D4 D5 D6 D7 CP C Q D C Q D C Q D C Q D C Q D C Q D C Q D C Q D OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 2 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Logic Symbol Connection Diagrams Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Value Units Supply Voltage –0.5 to +7.0 V VI DC Input Voltage –0.5 to +7.0 V VO DC Output Voltage –0.5 to +7.0 V VCC Parameter Conditions Output in 3-STATE Output in HIGH or LOW State(3) –0.5 to VCC + 0.5 IIK DC Input Diode Current VI < GND –50 mA IOK DC Output Diode Current VO < GND –50 mA VO > VCC +50 IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature –65 to +150 °C Recommended Operating Conditions(4) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH / IOL Output Current Conditions Min. Max. Units Operating 2.0 3.6 V Data Retention 1.5 3.6 0 5.5 V HIGH or LOW State 0 VCC V 3-STATE 0 5.5 VCC = 3.0V–3.6V ±24 VCC = 2.7V–3.0V ±12 VCC = 2.3V–2.7V TA ∆t / ∆V Free-Air Operating Temperature Input Edge Rate VIN = 0.8V–2.0V, VCC = 3.0V mA ±8 –40 85 °C 0 10 ns /V Notes: 3. IO Absolute Maximum Rating must be observed. 4. Unused inputs must be held HIGH or LOW. They may not float. ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 3 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Absolute Maximum Ratings TA = –40°C to +85°C Symbol VIH VIL VOH VOL Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage VCC (V) Conditions Min. 2.3–2.7 1.7 2.7–3.6 2.0 Max. V 2.3–2.7 0.7 2.7–3.6 0.8 2.3–3.6 IOH = –100µA V VCC – 0.2 2.3 IOH = –8mA 1.8 2.7 IOH = –12mA 2.2 3.0 IOH = –18mA 2.4 IOH = –24mA 2.2 V IOL = 100µA 0.2 2.3 IOL = 8mA 0.6 2.7 IOL = 12mA 0.4 3.0 IOL = 16mA 0.4 IOL = 24mA 0.55 2.3–3.6 Units V Input Leakage Current 2.3–3.6 0 ≤ VI ≤ 5.5V ±5.0 µA IOZ 3-STATE Output Leakage 2.3–3.6 0 ≤ VO ≤ 5.5V, VI = VIH or VIL ±5.0 µA IOFF Power-Off Leakage Current 0 VI or VO = 5.5V 10 µA ICC Quiescent Supply Current µA II ∆ICC Increase in ICC per Input 2.3–3.6 VI = VCC or GND 10 2.3–3.6 3.6V ≤ VI, VO ≤ 5.5V(5) ±10 2.3–3.6 VIH = VCC –0.6V 500 µA AC Electrical Characteristics TA = –40°C to +85°C, RL = 500Ω VCC = 3.3V ± 0.3V, CL = 50pF Symbol Parameter Min. fMAX VCC = 2.7V, CL = 50pF VCC = 2.5 ± 0.2V, CL = 30pF Max. Min. Max. Min. Max. Units Maximum Clock Frequency 150 tPHL, tPLH Propagation Delay, CP to On 1.5 8.5 1.5 9.5 1.5 10.5 ns tPZL, tPZH Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5 ns tPLZ, tPHZ Output Disable Time 1.5 6.5 1.5 7.0 1.5 7.8 tS Setup Time 2.5 2.5 4.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.3 3.3 4.0 ns tOSHL, tOSLH Output to Output Skew(6) MHz 1.0 ns ns Notes: 5. Outputs disabled or 3-STATE only. 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 4 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs DC Electrical Characteristics TA = 25°C Symbol Parameter VCC (V) VOLP Quiet Output Dynamic Peak VOL 3.3 VOLV Quiet Output Dynamic Valley VOL Conditions Typical Units CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V 0.6 3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 2.5 CL = 30pF, VIH = 2.5V, VIL = 0V –0.6 V Capacitance Symbol Parameter Conditions Typical Units Input Capacitance VCC = Open, VI = 0V or VCC 7 pF COUT Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25 pF CIN ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 5 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Dynamic Switching Characteristics VCC OPEN 500Ω TEST SIGNAL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ GND DUT VI CL 500Ω Figure 1. AC Test Circuit (CL includes probe and jig capacitance) DATA IN Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V tPZH, tPHZ GND VCC Vmi tpxx OUTPUT CONTROL GND DATA OUT DATA OUT Vmo tW DATA IN VCC Vmi tS tPLH Vmo OUTPUT CONTROL Vmi tPZL tPLZ Vmo VCC GND VCC GND trec MR OR CLEAR Vmo Vmi Setup Time, Hold Time and Recovery Time for Logic Propagation Delay, Pulse Width and trec Waveforms DATA OUT Vmi tS tPHL tH CONTROL INPUT Vmi OUTPUT Vmi GND trec CLOCK VOH VY Vmo 3-STATE Output High Enable and Disable Times for Logic Waveform for Inverting and Non-Inverting Functions CONTROL IN GND tPHZ tPZH tpxx VCC Vmi tr VCC tf GND ANY OUTPUT VX VOL 3-STATE Output Low Enable and Disable Times for Logic 90% 90% 10% 10% VOH VOL trise and tfall Figure 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) VCC Symbol 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC / 2 Vmo 1.5V 1.5V VCC / 2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH – 0.3V VOH – 0.3V VOH – 0.15V ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 6 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs AC Loading and Waveforms (Generic for LCX Family) Input Stage P2 P1 VCC Data ESD P5 D2 N+/P– X1 VDD N1 N2 GTO™ Output Input Stage D6 N+/P– P4 P3 N5 Enable N4 ESD D4 N+/P– N3 ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 7 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Schematic Diagram (Generic for LCX Family) Tape Format for DQFN Package Designator Tape Section Number Cavities Cavity Status Cover Tape Status BQX Leader (Start End) 125 (typ) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330.0) ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 B C D N W1 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) W2 0.724 (18.4) www.fairchildsemi.com 8 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Tape and Reel Specification 13.00 12.60 A 11.43 20 11 B 9.50 10.65 7.60 10.00 7.40 2.25 1 10 0.51 0.35 PIN ONE INDICATOR 0.25 M 0.65 1.27 1.27 C B A LAND PATTERN RECOMMENDATION 2.65 MAX SEE DETAIL A 0.33 0.20 C 0.75 0.25 X 45° SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) GAGE PLANE (R0.10) 0.10 C 0.30 0.10 0.25 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-013, VARIATION AC, ISSUE E B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) CONFORMS TO ASME Y14.5M-1994 1.27 0.40 SEATING PLANE E) LANDPATTERN STANDARD: SOIC127P1030X265-20L (1.40) DETAIL A F) DRAWING FILENAME: MKT-M20BREV3 SCALE: 2:1 Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 9 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Physical Dimensions 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 10 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 5. 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 11 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 6. 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 12 74LCX574 — Low Voltage Octal D-Type Flip-Flop with 5V Tolerant Inputs and Outputs Physical Dimensions (Continued) Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©2006 Fairchild Semiconductor Corporation 74LCX574 Rev. 1.6.1 www.fairchildsemi.com 13 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 © Fairchild Semiconductor Corporation www.fairchildsemi.com