TABLE 5 PRELIMINARY © 2013 Rochester Electronics, LLC. All Rights Reserved 05092013 AM186ED/EDLV Am186TMED/EDLV High Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers DISTINCTIVE CHARACTERISTICS E86TM family 80C186- and 80C188-compatible microcontroller with enhanced bus interface – Lower system cost with higher performance – 3.3-V ± 0.3-V operation (Am186EDLV microcontrollers) Programmable DRAM Controller – Supports zero-wait-state operation with 50-ns DRAM at 40 MHz, 60-ns @ 33 MHz, 70-ns @ 25 MHz – Includes programmable CAS-before-RAS refresh capability High performance – 20-, 25-, 33-, and 40-MHz operating frequencies – Zero-wait-state operation at 40 MHz with 70-ns static memory – 1-Mbyte memory address space – 64-Kbyte I/O space Enhanced features provide improved memory access and remove the requirement for a 2x clock input – Nonmultiplexed address bus – Processor operates at the clock input frequency – 8-bit or 16-bit programmable bus sizing including 8-bit boot option Enhanced integrated peripherals – 32 programmable I/O (PIO) pins – Two full-featured asynchronous serial ports allow full-duplex, 7-bit, 8-bit, or 9-bit data transfers D GENERAL DESCRIPTION R The Am186TMED/EDLV microcontrollers are part of the AMD E86TM family of embedded microcontrollers and microprocessors based on the x86 architecture. The Am186ED/EDLV microcontrollers are the ideal upgrade for 80C186/188 designs requiring 80C186/188 compatibility, increased performance, serial communications, a direct bus interface, and more than 64K of memory. The Am186ED/EDLV microcontrollers integrate a complete DRAM controller to take advantage of low DRAM costs. This reduces memory subsystem costs while maintaining SRAM performance.The Am186ED/EDLV microcontrollers also integrate the functions of a CPU, nonmultiplexed address bus, three timers, watchdog timer, chip selects, interrupt controller, two DMA controllers, two asynchronous serial ports, programmable bus – Serial port hardware handshaking with CTS, RTS, ENRX, and RTR selectable for each port – Improved serial port operation enhances 9-bit DMA support – Independent serial port baud rate generators – DMA to and from the serial ports – Watchdog timer can generate NMI or reset – A pulse-width demodulation option – A data strobe, true asynchronous bus interface option included for DEN – Reset configuration register Familiar 80C186 peripherals – Two independent DMA channels – Programmable interrupt controller with up to 8 external and 8 internal interrupts – Three programmable 16-bit timers – Programmable memory and peripheral chip-select logic – Programmable wait state generator – Power-save clock divider Software-compatible with the 80C186 and 80C188 microcontrollers with widely available native development tools, applications, and system software A compatible evolution of the Am186EM, Am186ES, and Am186ER microcontrollers Available in the following packages: – 100-pin, thin quad flat pack (TQFP) – 100-pin, plastic quad flat pack (PQFP) A T F sizing, and programmable I/O (PIO) pins on one chip. Compared to the 80C186/188 microcontrollers, the Am186ED/EDLV microcontrollers enable designers to reduce the size, power consumption, and cost of embedded systems, while increasing reliability, functionality, and performance. The Am186ED/EDLV microcontrollers have been designed to meet the most common requirements of embedded products developed for the communications, office automation, mass stor age, and general embedded markets. Specific applications include PBXs, multiplexers, modems, disk drives, hand-held and desktop terminals, fax machines, printers, photocopiers, and industrial controls. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Publication# 21336 Rev: A Amendment/0 Issue Date: May 1997 For complete Rochester ordering guide, please refer to page 2. Please contact factory for specific package and specification availability. SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 1 of 29 Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves the right to make changes without further notice to any specification herein. Specification Number AM186ED-EDLV-SCI (A) REV B Page 1 of 29 AM186ED/EDLV Rochester Ordering Guide *Most products can also be offered as RoHS compliant, designated by a –G suffix. Please contact factory for more information. Rochester Part Number AMD Part Number Package Temperature QFP-100, Plastic 0° to +100°C AM186ED-20KI/W QFP-100, Plastic -40° to +85°C AM186ED-20VC/W TQFP-100, Plastic 0° to +100°C AM186ED-25KC/W AM186ED-25KC/W QFP-100, Plastic 0° to +100°C AM186ED-25KI/W AM186ED-25KI/W QFP-100, Plastic -40° to +85°C AM186ED-25VC/W AM186ED-25VC/W TQFP-100, Plastic 0° to +100°C AM186ED-33KC/W AM186ED-33KC/W QFP-100, Plastic 0° to +100°C AM186ED-33VC/W AM186ED-33VC/W TQFP-100, Plastic 0° to +100°C AM186ED-40KC/W AM186ED-40KC/W QFP-100, Plastic 0° to +100°C AM186ED-40VC/W AM186ED-40VC/W TQFP-100, Plastic 0° to +100°C AM186EDLV-20KC/W AM186EDLV-20KC/W QFP-100, Plastic 0° to +70°C AM186EDLV-20VC/W AM186EDLV-20VC/W TQFP-100, Plastic 0° to +70°C AM186EDLV-25KC/W AM186EDLV-25KC/W QFP-100, Plastic 0° to +70°C AM186EDLV-25VC/W AM186EDLV-25VC/W TQFP-100, Plastic 0° to +70°C AM186ED-20KC/W AM186ED-20KC/W AM186ED-20KI/W AM186ED-20VC/W Specification Number AM186ED-EDLV-SCI (A) REV B Page 2 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y TQFP CONNECTION DIAGRAMS AND PINOUTS AD0 AD8 1 AD1 AD9 3 4 AD2 AD10 5 6 AD3 AD11 7 8 AD4 AD12 9 10 AD5 GND 11 12 AD13 AD6 13 14 V CC AD14 15 16 R A INT2/INTA 0/PWD INT3/INTA 1/IRQ INT1/ SELECT UCS / ONCE1 INT0 PCS 6/A2 LCS / ONCE 0/RAS0 VCC PCS 5/A1 77 76 78 80 79 82 81 84 83 PCS2 /CTS1/ENRX1 PCS3 /RTS1/RTR1 86 85 PCS1 GND 88 87 PCS0 90 89 MCS3/ RAS1 MCS2/LCAS VCC 92 91 RES GND 94 93 TMROUT1 TMRIN1 96 95 TMRIN0 TMROUT0 98 97 D 21 22 23 24 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 34 35 S0 32 33 S2/BTSEL S1 GND X1 X2 30 31 25 28 29 TXD0 19 20 WR RD ALE ARDY CTS0/ENRX0 RXD0 17 18 BHE/ADEN UZI TXD1 RXD1 T F Am186ED/EDLV Microcontrollers 26 27 S6/CLKDIV2 2 RTS0/RTR0 AD7 AD15 100 99 DRQ0/INT5 DRQ1/INT6 Am186ED/EDLV Microcontrollers Top Side View—100-Pin Thin Quad Flat Pack (TQFP) 75 74 INT4 MCS1/UCAS 73 72 MCS0 DEN/DS 71 70 DT/R NMI 69 68 SRDY HOLD 67 66 HLDA 65 64 WLB WHB GND 63 62 A0 A1 61 60 VCC A2 59 58 A3 A4 57 56 A5 A6 55 54 A7 A8 53 52 A9 A10 51 A11 Note: Pin 1 is marked for orientation. Specification Number AM186ED-EDLV-SCI (A) REV B 14 Am186ED/EDLV Microcontrollers Page 3 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y PQFP CONNECTION DIAGRAMS AND PINOUTS AD11 AD3 AD10 AD2 AD9 87 85 83 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 47 NMI DT/R 49 46 SRDY AD1 AD8 AD0 DRQ0/INT5 DRQ1/INT6 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RAS1 MCS2/LCAS VCC PCS0 PCS1 GND PCS2/CTS1/ENRX1 PCS3/RTS1/RTR1 VCC PCS5/A1 PCS6/A2 LCS/ONCE0/RAS0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PWD INT3/INTA1/IRQ INT4 MCS1/UCAS DEN/DS MCS0 45 48 44 HLDA T F HOLD 43 WHB WLB 42 41 40 39 VCC A1 A0 GND 38 82 AD12 AD4 89 84 GND AD5 90 86 AD13 92 88 VCC AD6 94 91 AD7 AD14 95 93 S6/CLKDIV2 AD15 96 97 98 CTS0/ENRX0 RXD1 TXD1 UZI 99 D 37 A9 A R A2 A19 A18 V CC A17 A16 A15 A14 A13 A12 A11 A10 A3 CLKOUTB GND Am186ED/EDLV Microcontrollers 36 V CC CLKOUTA 35 X1 X2 A4 S0 GND 34 S2/BTSEL S1 A5 ARDY 33 RD ALE A6 BHE/ADEN WR 32 RTS0/RTR0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TXD0 A8 A7 RXD0 100 Am186ED/EDLV Microcontrollers Top Side View—100-Pin Plastic Quad Flat Pack (PQFP) Note: Pin 1 is marked for orientation. Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers Page 4 of 29 17 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage temperature Am186ED........................................ –65°C to +125°C Am186EDLV.................................... –65°C to +125°C Am186ED Microcontroller Commercial (TC) .................................0°C to +100°C Industrial* (TA)...................................–40°C to +85°C Supply voltage (VCC) .................................5 V ± 10% Voltage on any pin with respect to ground Am186ED................................... –0.5 V to Vcc +0.5 V Am186EDLV............................... –0.5 V to Vcc +0.5 V Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Am186EDLV Microcontroller Commercial (TA) ................................... 0°C to +70°C VCC up to 25 MHz................................. 3.3 V ± 0.3 V Where: TC = case temperature TA = ambient temperature *Industrial versions of Am186ED microcontrollers are available in 20 and 25 MHz operating frequencies only. T F DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES Preliminary Symbol Parameter Description VIL Input Low Voltage (Except X1) VIL1 Clock Input Low Voltage (X1) VIH Input High Voltage (Except RES and X1) VIH 1 Input High Voltage (RES) VIH 2 Clock Input High Voltage (X1) Test Conditions Am186ED Am186EDLV Output High Voltage(a) VOH Am186ED D Am186EDLV ICC 0.2VCC –0.3 V 0.8 V 2.0 VCC +0.5 V 2.4 VCC +0.5 V VCC –0.8 VCC +0.5 V 0.45 V 0.45 V 2.4 VCC +0.5 V IOH = –200 µA @ VCC –0.5 VCC –0.5 VCC V IOH = –200 µA @ VCC –0.5 VCC –0.5 VCC V 5.9 mA/MHz A R IOL = 1.5 mA (S2–S0) IOL = 1.0 mA (others) IOH = –2.4 mA @ 2.4 V VCC = 5.5 V (b) ILI Input Leakage Current @ 0.5 MHz ILO Unit –0.5 IOL = 2.5 mA (S2–S0) IOL = 2.0 mA (others) Power Supply Current @ 0°C Max –0.5 Output Low Voltage VOL Min VCC = 3.6 V (b) 4.0 0.45 V≤VIN ≤ VCC ±10 µA ±10 µA 0.45 V Output Leakage Current @ 0.5 MHz 0.45 V≤VOUT ≤VCC VCLO Clock Output Low ICLO = 4.0 mA VCHO Clock Output High (c) ICHO = –500 µA VCC –0.5 V Notes: a The LCS/ONCE0/RAS0 and UCS/ONCE1 pins have weak internal pullup resistors. Loading the LCS/ONCE0/RAS0 and UCS/ONCE1 pins in excess of IOH = –200 µA during reset can cause the device to go into ONCE mode. b Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open but held High or Low. c Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode. Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers Page 5 of 29 49 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y CAPACITANCE Preliminary Symbol Max Unit CIN Input Capacitance Parameter Description @ 1 MHz Test Conditions Min 10 pF CIO Output or I/O Capacitance @ 1 MHz 20 pF Note: Capacitance limits are guaranteed by characterization. POWER SUPPLY CURRENT Table 10 shows the variables that are used to calculate t he t y p i c a l p o we r c o n s um p t i o n v a l u e f o r t h e Am186EDLV microcontroller. For the following typical system specification shown in Figure 11, ICC has been measured at 4.0 mA per MHz of system clock. For the following typical system specification shown in Figure 12, I CC has been measured at 5.9 mA per MHz of system clock. The typical system is measured while the system is executing code in a typical application with nominal voltage and maximum case temperature. Actual power supply current is dependent on system design and may be greater or less than the typical ICC figure presented here. Typical current in Figure 12 is given by: ICC = 5.9 mA ⋅ freq(MHz) R D Volts Typical Power in Watts 20 4.0 3.6 0.288 4.0 3.6 0.360 A 120 No DC loads on the output buffers Output capacitive load set to 35 pF PIOs are disabled Typical ICC 140 Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were set to the following modes: AD bus set to data only MHz ⋅ ICC ⋅ Volts / 1000 = P MHz 25 Typical current in Figure 11 is given by: ICC = 4.0 mA ⋅ freq(MHz) T F Table 10. Typical Power Consumption Calculation for the Am186EDLV Microcontroller 100 80 ICC (mA) 60 25 MHz 20 MHz 40 20 0 10 20 30 Clock Frequency (MHz) Figure 11. Typical Icc Versus Frequency for Am186EDLV Microcontroller Timer, serial port, refresh, and DMA are enabled 280 240 40 MHz 200 33 MHz 160 ICC (mA) 25 MHz 120 20 MHz 80 40 0 10 20 30 40 50 Clock Frequency (MHz) Figure 12. Typical Icc Versus Frequency for Am186ED Microcontroller Specification Number AM186ED-EDLV-SCI (A) REV B 50 Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 6 of 29 Page 6 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Read Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol 20 MHz Description Min 25 MHz Max Min Max Unit General Timing Requirements 1 tDVCL 2 tCLDX Data in Setup 10 10 ns Data in Hold(c) 3 3 ns General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 0 25 0 20 ns 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 6 tCLAX Address Hold 0 8 tCHDX Status Hold Time 0 T F 9 tCHLH ALE Active Delay 10 tLHLL ALE Width ALE Inactive Delay 0 25 20 0 20 0 20 tCLCL –10=30 25 11 tCHLL tAVLL 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High 15 tCLAZ AD Address Float Delay 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 20 tCVCTV Control Active Delay 21 tCVDEX DEN Inactive Delay 22 tCHCTV 23 tLHAV ALE High to Address Valid 99 tPLAL PCS Active to ALE Inactive AD Address Valid to ALE Low(a) tCLCH –2 tCHCL –2 0 A tCLAX = 0 0 tCLCH –2 0 R 1(b) Control Active Delay 2(b) D 0 25 tCLCL –10=40 12 Read Cycle Timing Responses 25 0 0 0 0 25 15 tAZRL AD Address Float to RD Active 25 tCLRL RD Active Delay 0 26 tRLRH RD Pulse Width 2tCLCL –15= 85 27 tCLRH RD Inactive Delay 28 tRHLH RD Inactive to ALE High(a) ns ns ns ns ns 0 ns tCLAX = 0 20 ns 0 20 ns 20 ns 25 tCLCH –2 25 0 0 ns ns 25 0 20 ns 25 0 20 ns 0 20 ns 25 15 28 ns 15 0 0 ns ns tCHCL –2 20 24 Active(a) 20 tCLCH –2 ns 24 0 25 ns 0 20 ns 20 ns 2tCLCL –15= 65 25 ns 0 ns tCLCH –3 tCLCH –3 ns tCLCL –10=40 tCLCL –10= 30 ns tCLCH –2=21 tCLCH –2=16 ns 0 0 ns tCLCL + tCHCL–3 tCLCL + tCHCL–3 ns 29 tRHAV RD Inactive to AD Address 41 tDSHLH DS Inactive to ALE Active 59 tRHDX 66 tAVRL 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 25 0 20 ns 68 tCHAV CLKOUTA High to A Address Valid 0 25 0 20 ns RD High to Data Hold on AD Bus(c) A Address Valid to RD Low(a) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Specification Number AM186ED-EDLV-SCI (A) REV B 64 Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 7 of 29 Page 7 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Read Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol 33 MHz Description Min 40 MHz Max Min Max Unit General Timing Requirements 1 tDVCL 2 tCLDX Data in Setup 8 5 ns Data in Hold(c) 3 2 ns General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 0 15 0 12 ns 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 6 tCLAX Address Hold 0 15 8 tCHDX Status Hold Time 0 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 tAVLL 13 tLLAX AD Address Hold from ALE Inactive(a) 14 tAVCH AD Address Valid to Clock High 15 tCLAZ AD Address Float Delay MCS/PCS Active Delay 12 T F 0 12 0 16 tCLCSV tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV 23 tLHAV ALE High to Address Valid 99 tPLAL PCS Active to ALE Inactive tCLCH –2 tCHCL –2 0 A 15 0 15 tCLCH –2 0 DEN Inactive to DT/R Low(a) R Control Active Delay 2(b) 0 ns ns ns 12 ns tCLCH –2 tCLAX = 0 ns 12 tCLCL –5= 20 15 17 D 0 15 tCLCL –10=20 AD Address Valid to ALE Low(a) Read Cycle Timing Responses 15 ns ns tCHCL –2 ns 0 ns tCLAX = 0 12 0 12 tCLCH –2 15 0 12 0 ns ns ns ns ns 0 15 0 12 0 15 0 12 ns 0 15 0 12 ns 18 ns 10 12 7.5 20 ns 10 tAZRL AD Address Float to RD Active 25 tCLRL RD Active Delay 26 tRLRH RD Pulse Width 27 tCLRH RD Inactive Delay 28 tRHLH RD Inactive to ALE High(a) 29 tRHAV RD Inactive to AD Address 41 tDSHLH DS Inactive to ALE Active 59 tRHDX RD High to Data Hold on AD Bus(c) 66 tAVRL A Address Valid to RD 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 15 0 10 ns 68 tCHAV CLKOUTA High to A Address Valid 0 15 0 10 ns 24 Active(a) Low(a) 0 ns 0 0 15 2tCLCL –15= 45 0 ns 0 10 2tCLCL –10= 40 15 tCLCH –3 0 12 ns tCLCH –2 ns ns tCLCL –10=20 tCLCL –5= 20 tCLCH –2=11.5 tCLCH –2=9.25 0 0 tCLCL + tCHCL–3 ns ns ns tCLCL + tCHCL–1.25 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 8 of 29 Page 8 of 29 65 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y READ CYCLE WAVEFORMS t1 t2 t3 t4 tW CLKOUTA 66 Address A19–A0 8 68 S6 S6 INVALID S6 14 1 6 AD15–AD0(a), Address AD7–AD0(b) 2 Address AD15–AD8(b) 23 9 29 11 ALE 59 15 10 RD 5 BHE(a) 67 LCS, UCS DEN, DS 16 D 19 DT/R 22 S2–S0 (c) 28 24 12 MCS1–MCS0, PCS6–PCS5, PCS3–PCS0 T F Data A 26 25 R BHE 13 99 20 4 27 41 18 17 21 22 (c) Status 3 UZI Notes: a Am186ED/EDLV microcontrollers in 16-bit mode b Am186ED/EDLV microcontrollers in 8-bit mode c Changes in t phase preceding next bus cycle if followed by read, INTA, or halt. Specification Number AM186ED-EDLV-SCI (A) REV B 66 Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 9 of 29 Page 9 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Write Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol 20 MHz Description 25 MHz Min Max Min Max Unit 0 25 0 20 ns General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 0 25 0 20 ns 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 ns 6 tCLAX Address Hold 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 15 0 15 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 tAVLL AD Address Valid to ALE Low(a) 13 tLLAX AD Address Hold from ALE 14 tAVCH AD Address Valid to Clock High 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay tCLCL –10=40 tDXDL tCVCTV Control Active Delay 1(b) 21 tCVDEX DS Inactive Delay 22 tCHCTV Control Active Delay 2 23 tLHAV ALE High to Address Valid 99 tPLAL PCS Active to ALE Inactive Write Cycle Timing Responses Inactive(a) Low(a) 19 tCLCH –2 R tCHCL–2 0 0 tCLCH –2 A 0 0 ns T F 20 tCLCL –10=30 25 20 DEN Inactive to DT/R 0 25 20 tCLCH –2 25 ns ns ns tCHCL–2 ns 0 ns 0 20 tCLCH –2 25 ns 0 20 0 ns ns ns ns 0 15 0 15 ns 0 25 0 20 ns 0 25 0 20 ns 28 15 24 ns 25 0 20 ns 20 15 15 tCLDOX Data Hold Time 31 tCVCTX Control Inactive 32 tWLWH WR Pulse Width 33 tWHLH 34 tWHDX 35 tWHDEX WR Inactive to DEN Inactive(a) 41 tDSHLH DS Inactive to ALE Active 65 tAVWL A Address Valid to WR Low 67 tCHCSV CLKOUTA High to LCS/UCS Valid 68 tCHAV CLKOUTA High to A Address Valid 0 25 0 20 ns 87 tAVBL A Address Valid to WHB, WLB Low tCHCL –3 25 tCHCL –3 20 ns 98 tDSHDIW 30 D Delay(b) WR Inactive to ALE High(a) Data Hold after WR(a) DS High to Data Invalid—Write 0 0 0 ns ns 2tCLCL –10= 90 2tCLCL –10= 70 ns tCLCH –2 tCLCH –2 ns tCLCL –10=40 tCLCL –10=30 ns tCLCH –3 tCLCH –3 ns tCLCH –2=21 tCLCH –2=16 ns tCLCL+tCHCL –3 0 tCLCL +tCHCL –3 25 35 0 30 ns 20 ns ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. Specification Number AM186ED-EDLV-SCI (A) REV B Page 10 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Write Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol 33 MHz Description 40 MHz Min Max Min Max Unit 0 15 0 12 ns General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 0 15 0 12 ns 5 tCLAV AD Address Valid Delay and BHE 0 15 0 12 ns 6 tCLAX Address Hold 0 7 tCLDV Data Valid Delay 0 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 tAVLL AD Address Valid to ALE Low(a) 13 tLLAX AD Address Hold from ALE 14 tAVCH AD Address Valid to Clock High 16 tCLCSV MCS/PCS Active Delay 17 tCXCSX MCS/PCS Hold from Command Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay tDXDL tCVCTV Control Active Delay 1(b) 21 tCVDEX DS Inactive Delay 22 tCHCTV Control Active Delay 2 23 tLHAV ALE High to Address Valid 99 tPLAL PCS Active to ALE Inactive R tCLDOX Data Hold Time 31 tCVCTX Control Inactive 32 tWLWH WR Pulse Width 33 tWHLH WR Inactive to ALE High(a) 34 tWHDX Data Hold after 35 tWHDEX WR Inactive to DEN Inactive(a) 41 tDSHLH D tCLCH –2 Inactive(a) Low(a) 19 30 12 0 Delay(b) tCHCL–2 0 0 tCLCH –2 T F tCLCL –5= 20 A 0 0 12 tCLCH –2 15 ns ns ns ns tCHCL–2 ns 0 ns 0 12 tCLCH –2 15 ns ns 12 15 20 Write Cycle Timing Responses ns 0 15 tCLCL –10=20 DEN Inactive to DT/R 0 15 0 12 0 ns ns ns ns 0 15 0 12 ns 0 15 0 12 ns 0 15 0 12 ns 18 ns 12 ns 10 12 7.5 20 10 15 0 0 0 0 ns ns 2tCLCL –10= 50 2tCLCL –10= 40 ns tCLCH –2 tCLCH –2 ns tCLCL –10=20 tCLCL –10= 15 ns tCLCH –3 tCLCH –3 ns DS Inactive to ALE Active tCLCH –2=11.5 tCLCH –2=9.25 ns tCLCL +tCHCL –3 WR(a) 65 tAVWL A Address Valid to WR Low 67 tCHCSV CLKOUTA High to LCS/UCS Valid 68 tCHAV CLKOUTA High to A Address Valid 0 15 0 10 ns 87 tAVBL A Address Valid to WHB, WLB Low tCHCL –3 15 tCHCL –1.25 12 ns 98 tDSHDIW DS High to Data Invalid—Write 0 tCLCL +tCHCL –1.25 15 20 0 15 ns 10 ns ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals. Specification Number AM186ED-EDLV-SCI (A) REV B Page 11 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y WRITE CYCLE WAVEFORMS t1 t2 t3 t4 tW CLKOUTA 65 A19–A0 Address 68 8 S6 S6 INVALID S6 14 7 AD15–AD0(a), AD7–AD0(b) 30 Address 6 AD15–AD8(b) Address 23 11 9 34 13 ALE 31 10 WR 12 20 WHB, WLB 87 BHE 67 LCS, UCS R D 16 MCS3–MCS0, PCS6–PCS5, PCS3–PCS0 DS DT/R S2–S0 22 A 33 32 41 20 5 DEN T F Data 31 BHE 99 18 17 20 35 31 98 21 20 19 (c) (c) 22 Status 3 UZI 4 Notes: a Am186ED/EDLV microcontrollers in 16-bit mode b Am186ED/EDLV microcontrollers in 8-bit mode c Changes in t phase preceding next bus cycle if followed by read, INTA, or halt Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 12 69 of 29 Page 12 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges DRAM Parameter No. Symbol Description General Timing Responses 101 tCHCAV CLKOUTA Low to Column Address Valid CLKOUTA Low to RAS Active 102 tCLRA 103 tCHRX CLKOUTA High to RAS Inactive CLKOUTA High to CAS Active 104 tCHCA 105 tCLCX CLKOUTA Low to CAS Inactive 106 tCHRA CLKOUTA High to RAS Active CLKOUTA Low to RAS Inactive 107 tCLRX 108 tRP0W RAS Inactive Pulse Width with 0 Wait States RAS Inactive Pulse Width with 1 or 109 tRP1W More Wait States RAS To Column Address Delay 110 tRD0W Time with 0 Wait States RAS to Column Address Delay 111 tRD1W Time with 1 or More Wait States 20 MHz Min Max Preliminary 25 MHz 33 MHz Min Max Min Max 40 MHz Min Max Unit 0 25 0 20 0 15 0 12 ns 3 3 3 3 3 3 60 25 25 25 25 25 25 — 3 3 3 3 3 3 50 20 20 20 20 20 20 — 3 3 3 3 3 3 40 15 15 15 15 15 15 — 3 3 3 3 3 3 30 12 12 12 12 12 12 — ns ns ns ns ns ns ns 70 — 60 — 50 — 40 — ns 25 — 20 — 15 — 15 — ns 30 — 25 — 20 — 15 — ns A T F Frequency As guaranteed by design, the following table shows the minimum time for RAS assertion to RAS assertion. These minimums correlate to DRAM spec tRC. 40 MHz 33 MHz 25 MHz 20 MHz 0 90 110 130 150 D Wait States 1 2 110 130 130 150 150 170 170 190 R 3 150 170 190 210 Specification Number AM186ED-EDLV-SCI (A) REV B 70 Am186ED/EDLV Microcontrollers Page 13 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y DRAM Read Cycle Timing with No-Wait States t3 t4 t1 t2 t3 t4 t1 CLKOUTA 5 15 AD[15:0] 1 Data Addr. 68 2 101 A[17:1] Column Row 102 110 103 RAS T F 108 104 CAS 25 RD(a) 105 27 A Note: a The RD output connects to the DRAM output enable (OE) pin for read operations. DRAM Read Cycle Timing with Wait State(s) t4 D CLKOUTA AD[15:0] A[17:1] RAS R t1 5 15 t2 t3 t4 68 Data 2 101 Row 102 t1 1 Addr. Column 110 107 104 CAS RD(a) tw 25 109 105 27 Note: a The RD output connects to the DRAM output enable (OE) pin for read operations. Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 14 of 29 Page 14 of 29 71 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y DRAM Write Cycle Timing with No-Wait States t4 t1 t2 t3 t4 t1 CLKOUTA 5 7 30 Addr. AD[15:0] Data 68 101 Row A[17:1] 102 Column 110 103 T F RAS 108 105 104 CAS 20 WR(a) 31 A Note: a Write operations use the WR output connected to the DRAM write enable (WE) pin. R DRAM Write Cycle Timing With Wait State(s) t4 D CLKOUTA AD[15:0] A[17:1] RAS t1 5 t2 7 t3 Addr. 68 t4 t1 30 Data 101 Row 102 Column 110 107 104 CAS WR(a) tw 20 109 105 31 Note: a Write operations use the WR output connected to the DRAM write enable (WE) pin. Specification Number AM186ED-EDLV-SCI (A) REV B 72 Am186ED/EDLV Microcontrollers Page 15 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y DRAM CAS-before-RAS Cycle Timing t4 t1 t2 tW tW tW t3 t4 t1 CLKOUTA 5 AD[15:0] A[17:1] 15 FFFF 68 101 X X 106 RAS CAS(a) 104 T F 105 25 RD(b) 107 109 27 A Notes: a CAS before RAS cycle timing is always 7 clocks, independent of wait state timing. b The RD output connects to the DRAM output enable (OE) pin for read operations. D R Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers Page 16 of 29 73 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Interrupt Acknowledge Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol 20 MHz Description Min 25 MHz Max Min Max Unit General Timing Requirements 1 tDVCL Data in Setup 10 10 ns 2 tCLDX Data in Hold 3 3 ns General Timing Responses 3 tCHSV Status Active Delay 0 25 0 20 ns 4 tCLSH Status Inactive Delay 0 25 0 20 ns 7 tCLDV Data Valid Delay 0 25 0 20 ns 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width ALE Inactive Delay T F 0 25 tCLCL –10=40 11 tCHLL 12 tAVLL AD Address Invalid to ALE Low(a) tCLCH –2 15 tCLAZ AD Address Float Delay tCLAX = 0 DEN Inactive to DT/R 20 tCLCL –10= 30 25 Low(a) 19 tDXDL 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 23 tLHAV 31 tCVCTX Control Inactive Delay(b) 68 tCHAV CLKOUTA High to A Address Valid 2(c) ALE High to Address Valid R 20 tCLCH –2 25 0 tCLAX = 0 20 0 ns ns ns ns ns ns ns 0 25 0 20 ns 0 25 0 20 ns 0 25 0 20 ns A 20 15 ns 0 25 0 20 ns 0 25 0 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the INTA1–INTA0 signals. c This parameter applies to the DEN and DT/R signals. D Specification Number AM186ED-EDLV-SCI (A) REV B 74 Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 17 of 29 Page 17 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Interrupt Acknowledge Cycle (33 MHz and 40 MHz) Preliminary Parameter No. Symbol 33 MHz Description Min 40 MHz Max Min Max Unit General Timing Requirements 1 tDVCL Data in Setup 8 5 ns 2 tCLDX Data in Hold 3 2 ns General Timing Responses 3 tCHSV Status Active Delay 0 15 0 12 ns 4 tCLSH Status Inactive Delay 0 15 0 12 ns 7 tCLDV Data Valid Delay 0 15 0 12 8 tCHDX Status Hold Time 0 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 12 tAVLL AD Address Invalid to ALE Low 15 tCLAZ AD Address Float Delay T F 0 15 tCLCL –10=20 12 tCLCL –5=20 15 (a) tCLCH tCLAX = 0 (a) 12 tCLCH 15 tCLAX = 0 12 ns ns ns ns ns ns ns 19 tDXDL DEN Inactive to DT/R Low 0 20 tCVCTV Control Active Delay 1(b) 0 15 0 12 ns 21 tCVDEX DEN Inactive Delay 0 15 0 12 ns 22 tCHCTV Control Active Delay 0 15 0 12 23 tLHAV 31 tCVCTX Control Inactive Delay(b) 68 tCHAV CLKOUTA High to A Address Valid 2(c) ALE High to Address Valid R A 0 10 7.5 ns ns ns 0 15 0 12 ns 0 15 0 10 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. D b This parameter applies to the INTA1–INTA0 signals. c This parameter applies to the DEN and DT/R signals. Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers Page 18 of 29 75 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y INTERRUPT ACKNOWLEDGE CYCLE WAVEFORMS t1 t2 t3 t4 tW CLKOUTA 68 Address A19–A0 7 S6 8 Invalid S6 S6 T F 1 12 AD15–AD0 23 ALE 10 11 BHE R 20 DEN 22 DT/R S2–S0 A 4 BHE INTA1–INTA0 D 19 (c) 3 (b) Ptr 15 9 2 31 21 22 4 (a) 22 (d) Status Notes: a The status bits become inactive in the state preceding t4. b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to tCLDX (min). c This parameter applies for an interrupt acknowledge cycle that follows a write cycle. d If followed by a write cycle, this change occurs in the state preceding that write cycle. Specification Number AM186ED-EDLV-SCI (A) REV B 76 Am186ED/EDLV Microcontrollers Page 19 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Software Halt Cycle (20 MHz and 25 MHz) Preliminary Parameter No. Symbol 20 MHz Description 25 MHz Min Max Min Max Unit General Timing Responses 3 tCHSV Status Active Delay 0 25 0 20 ns 4 tCLSH Status Inactive Delay 0 25 0 20 ns 5 tCLAV AD Address Invalid Delay and BHE 0 25 0 20 ns 9 tCHLH ALE Active Delay 20 ns 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 20 ns 19 tDXDL 22 tCHCTV 68 tCHAV 25 tCLCL –10=40 DEN Inactive to DT/R Low(a) Control Active Delay tCLCL –10= 30 25 0 2(b) 0 CLKOUTA High to A Address Invalid 0 ns T F 0 ns 25 0 20 ns 25 0 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN signal. A SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Software Halt Cycle (33 MHz and 40 MHz) Parameter No. Symbol R Description General Timing Responses D 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV AD Address Invalid Delay and BHE 9 tCHLH ALE Active Delay 10 tLHLL ALE Width 11 tCHLL ALE Inactive Delay 19 tDXDL 22 68 33 MHz Preliminary 40 MHz Min Max Min Max Unit 0 15 0 12 ns 0 15 0 12 ns 0 15 0 12 ns 12 ns 12 ns 15 tCLCL –10=20 tCLCL –5=20 15 ns DEN Inactive to DT/R Low(a) 0 tCHCTV Control Active Delay 2(b) 0 15 0 12 ns tCHAV CLKOUTA High to A Address Invalid 0 15 0 10 ns 0 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a Testing is performed with equal loading on referenced pins. b This parameter applies to the DEN signal. Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers Page 20 of 29 77 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SOFTWARE HALT CYCLE WAVEFORMS t1 t2 ti ti CLKOUTA 68 A19–A0 Invalid Address 5 Invalid Address S6, AD15–AD0 10 ALE 9 11 DEN 19 DT/R 22 Status S2–S0 3 D A 4 R Specification Number AM186ED-EDLV-SCI (A) REV B 78 Am186ED/EDLV Microcontrollers T F Page 21 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Clock (20 MHz and 25 MHz) Preliminary Parameter No. Symbol 20 MHz Description 25 MHz Min Max Min Max Unit X1 Period(a) 50 60 40 60 ns CLKIN Requirements 36 tCKIN 37 tCLCK X1 Low Time (1.5 V)(a) 15 38 tCHCK (a) X1 High Time (1.5 V) 15 39 tCKHL 40 tCKLH 15 15 ns X1 Fall Time (3.5 to 1.0 V)(a) 5 5 ns X1 Rise Time (1.0 to 3.5 V)(a) 5 5 ns CLKOUT Timing 42 ns tCLCL CLKOUTA Period 50 43 tCLCH CLKOUTA Low Time (CL = 50 pF) 0.5tCLCL –2= 23 44 tCHCL CLKOUTA High Time (CL = 50 pF) 0.5tCLCL –2= 23 45 tCH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V) 3 46 tCL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V) 3 61 tLOCK Maximum PLL Lock Time 1 69 tCICOA X1 to CLKOUTA Skew 15 70 tCICOB X1 to CLKOUTB Skew A T F 40 ns 0.5tCLCL –2= 18 ns 0.5tCLCL –2= 18 25 ns 3 ns 3 ns 1 ms 15 ns 25 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a R The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation. D Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers Page 22 of 29 79 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over Commercial operating ranges Clock (33 MHz and 40 MHz) Preliminary Parameter No. Symbol 33 MHz Description 40 MHz Min Max Min Max Unit X1 Period(a) 30 60 X1 Low Time (1.5 V)(a) 10 7.5 25 60 ns ns 10 7.5 ns CLKIN Requirements 36 tCKIN 37 tCLCK 38 tCHCK X1 High Time (1.5 V)(a) 39 tCKHL X1 Fall Time (3.5 to 1.0 V) 5 5 ns 40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 5 5 ns (a) CLKOUT Timing 42 tCLCL CLKOUTA Period 43 tCLCH CLKOUTA Low Time (CL = 50 pF) 0.5tCLCL –1.5 = 13.5 44 tCHCL CLKOUTA High Time (CL = 50 pF) 0.5tCLCL –1.5 = 13.5 45 tCH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V) 3 46 tCL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V) 3 30 T F 25 ns 0.5tCLCL –1.25 = 11.25 ns 0.5tCLCL –1.25 = 11.25 ns 3 ns 3 ns 61 tLOCK Maximum PLL Lock Time 1 1 ms 69 tCICOA X1 to CLKOUTA Skew 15 15 ns 70 tCICOB X1 to CLKOUTB Skew 25 25 ns A Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. R The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation. D Specification Number AM186ED-EDLV-SCI (A) REV B 80 Am186ED/EDLV Microcontrollers Page 23 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y CLOCK WAVEFORMS Clock Waveforms—Active Mode X2 37 36 38 X1 39 CLKOUTA (Active, F= 000) 40 45 69 42 CLKOUTB 70 Clock Waveforms—Power-Save Mode X2 X1 CLKOUTA (Power-Save, F= 010) D CLKOUTB (Like X1, CBF= 1) CLKOUTB (Like CLKOUTA, CBF= 0) R A Specification Number AM186ED-EDLV-SCI (A) REV B 43 46 44 T F Page 24 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Ready and Peripheral (20 MHz and 25 MHz) Preliminary Preliminary 20 MHz 25 MHz Parameter No. Symbol Description Min Max Min Max Unit Ready and Peripheral Timing Requirements tSRYCL SRDY Transition Setup Time(a) 48 tCLSRY SRDY Transition Hold 49 tARYCH ARDY Resolution Transition Setup Time(b) 47 10 Time(a) 10 ns 3 3 ns 10 10 ns ns Time(a) 50 tCLARX ARDY Active Hold 4 4 51 tARYCHL ARDY Inactive Holding Time 6 6 ns 52 tARYLCL ARDY Setup Time(a) 15 15 ns 53 tINVCH Peripheral Setup Time(b) 10 54 tINVCL DRQ Setup Time(b) 10 Peripheral Timing Responses 55 tCLTMV Timer Output Delay T F 10 ns 10 ns 25 20 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. A SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Ready and Peripheral (33 MHz and 40 MHz) R Parameter No. Symbol Description Ready and Peripheral Timing Requirements D tSRYCL SRDY Transition Setup Time(a) 48 tCLSRY SRDY Transition Hold 49 tARYCH ARDY Resolution Transition Setup Time(b) 50 tCLARX ARDY Active Hold 51 tARYCHL ARDY Inactive Holding Time 52 tARYLCL 53 tINVCH 54 tINVCL 47 33 MHz Min Preliminary 40 MHz Max Min Max Unit 8 5 ns 3 2 ns 8 5 ns 4 3 ns 6 5 ns ARDY Setup Time(a) 10 5 ns Peripheral Setup Time(b) 8 5 ns DRQ Setup Time(b) 8 5 ns Time(a) Time(a) Peripheral Timing Responses 55 tCLTMV Timer Output Delay 15 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee proper operation. b This timing must be met to guarantee recognition at the clock edge. Specification Number AM186ED-EDLV-SCI (A) REV B Page 25 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SYNCHRONOUS, ASYNCHRONOUS, and PERIPHERAL WAVEFORMS Synchronous Ready Waveforms Case 1 tW tW tW t4 Case 2 t3 tW tW t4 Case 3 t2 t3 tW t4 Case 4 t1 t2 t3 t4 CLKOUTA 47 SRDY T F 48 Asynchronous Ready Waveforms CLKOUTA ARDY (Normally NotReady System) D ARDY (Normally Ready System) Peripheral Waveforms CLKOUTA Case 1 tW tW Case 2 t3 tW Case 3 t2 Case 4 t1 A t3 t2 R 49 tW t4 tW t4 tW t4 t3 t4 50 49 51 50 52 53 INT4–INT0, NMI, TMRIN1–TMRIN0 54 DRQ1–DRQ0 55 TMROUT1– TMROUT0 Specification Number AM186ED-EDLV-SCI (A) REV B Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 2683 of 29 Page 26 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Reset and Bus Hold (20 MHz and 25 MHz) Preliminary Parameter No. Symbol 20 MHz Description 25 MHz Min Max Min Max Unit ns Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay and BHE 0 25 0 20 15 tCLAZ AD Address Float Delay 0 25 0 20 57 tRESIN RES Setup Time 10 10 ns 58 tHVCL HOLD Setup(a) 10 10 ns ns Reset and Bus Hold Timing Responses tCLHAV HLDA Valid Delay 63 tCHCZ Command Lines Float Delay 64 tCHCV Command Lines Valid Delay (after Float) 62 0 25 0 20 T F ns 25 20 ns 25 20 ns SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Reset and Bus Hold (33 MHz and 40 MHz) Preliminary Parameter No. Symbol 33 MHz Description Reset and Bus Hold Timing Requirements 5 tCLAV AD Address Valid Delay and BHE 15 tCLAZ AD Address Float Delay 57 tRESIN RES Setup Time 58 tHVCL HOLD Setup(a) R Reset and Bus Hold Timing Responses A tCLHAV HLDA Valid Delay 63 tCHCZ Command Lines Float Delay 64 tCHCV Command Lines Valid Delay (after Float) 62 D Min 0 0 8 8 0 40 MHz Max Min Max Unit 15 0 12 ns 15 0 12 15 ns 5 ns 5 ns 0 12 ns 15 12 ns 15 12 ns Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC – 0.5 V. a This timing must be met to guarantee recognition at the next clock. Specification Number AM186ED-EDLV-SCI (A) REV B 84 Am186ED/EDLV Microcontrollers SPECIFICATION NUMBER: AM186ED-EDLV-SCI (A) REV - Page 27 of 29 Page 27 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y RESET and BUS HOLD WAVEFORMS Reset Waveforms X1 57 57 RES CLKOUTA Signals Related to Reset Waveforms RES S2/BTSEL, CLKOUTA BHE/ADEN, S6/CLKDIV2, and UZI AD15–AD0 D R A T F Three-State Three-State Specification Number AM186ED-EDLV-SCI (A) REV B Page 28 of 29 AM186ED/EDLV TABLE 5 P R E L I M I N A R Y Bus Hold Waveforms—Entering Case 1 ti ti ti Case 2 t4 ti ti CLKOUTA 58 HOLD 62 HLDA T F 15 AD15–AD0, DEN 63 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0 WHB, WLB Bus Hold Waveforms—Leaving CLKOUTA HOLD HLDA D AD15–AD0, DEN Case 1 ti Case 2 ti R 58 A ti ti ti t1 t4 t1 62 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0 WHB, WLB 5 64 Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves the right to make changes without further notice to any specification herein. Specification Number AM186ED-EDLV-SCI (A) REV B 86 Am186ED/EDLV Microcontrollers Page 29 of 29