RT8100 Synchronous Buck PWM DC/DC with Dual Voltage Control Mode General Description Features The RT8100 is an advanced DC/DC synchronous buck PWM controller with several innovative functions for specific customer’ s ASIC only. The part features RichTek’ s innovative design and topology say “analogous current mode” for current sensing and full functions for various applications including adjustable soft start, free-run and adjustable operation frequency and enable; the part is with design of 12V+12V boot strapped driver which is capable to drive up to 20Amp output current; moreover the part is with implementation of accuracy DCR current sensing topology. There are several specific features implemented and reserved for the specific customer’ s special applications including dual VCORE control mode including z Analogous Current Mode Design z tracking and stand-alone mode, and output current indication. The part is proposed with a small footprint of VQFN-16L 3x3 package. z 2.5V to 12V Switching Source Power 0.8V to 3.3V Output Voltage Regulation Adjustable VIN Feed-Forward Ramp Slope Adjustable Operation Frequency Precise Core Voltage Regulation Precise DCR Current Sensing with High Quality Capacitor, X7R ±1.5% System Accuracy Input Voltage : 12V and 5V Bias Enable Function RoHS Compliant and 100% Lead (Pb)-Free Over Current Protection External Soft Start Setting Operation Frequency up to 1MHz Dual Mode Voltage Control ` Tracking Mode ` Stand-Alone Mode Output Current Indication 16-Lead VQFN Package z z z z z z z z z z z z Ordering Information RT8100 z Package Type QV : VQFN-16L 3x3 (V-Type) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Note : Richtek products are : z Applications z z z MB memory and chipset core power Middle-high graphic card GPU and memory core power General-purpose fields including server, NB, bare-bone and mini-system ` RoHS compliant and compatible with the current require- Pin Configurations ` Suitable for use in SnPb or Pb-free soldering processes. PHASE Marking Information UGATE 12VCC (TOP VIEW) BOOT ments of IPC/JEDEC J-STD-020. 16 15 14 13 5VSB 1 12 LGATE RT 2 11 PVCC 10 SS 9 PI GND I_IND 3 17 5 6 7 8 COMP FB 4 CSP RR CSN For marking information, contact our sales representative directly or through a Richtek distributor located in your area. VQFN-16L 3X3 DS8100-06 April 2011 www.richtek.com 1 RT8100 Typical Application Circuit VIN 4 12VCC 5VSB PI 15 BOOT RR 16 12VCC 1 5VSB 9 PI UGATE 14 PHASE 13 RT8100 11 PVCC 10 SS LGATE 12 VOUT 0 CSP 6 CSN 5 2 RT 3 I_IND 0 FB 8 COMP 7 NC Figure 1. 12V-5V PI Application Circuit VIN 4 12VCC 5VSB 5VSB RR 16 12VCC 1 5VSB 9 PI 15 BOOT UGATE 14 PHASE 13 VOUT RT8100 11 PVCC LGATE 12 10 SS 2 RT 3 I_IND CSP 6 CSN 5 opt. FB 8 COMP 7 Figure 2. 12V-5V Internal VREF Application Circuit www.richtek.com 2 DS8100-06 April 2011 RT8100 VIN 4 5VSB 5VSB PI RR 16 12VCC 1 5VSB 9 PI 15 BOOT UGATE 14 PHASE 13 VOUT RT8100 11 PVCC LGATE 12 PHASE 10 SS 2 RT 3 I_IND CSP 6 CSN 5 0 FB 8 COMP 7 NC Figure 3. Single 5V PI Application Circuit VIN 4 5VSB 5VSB 5VSB PHASE RR 16 12VCC 1 5VSB 9 PI 15 BOOT UGATE 14 PHASE 13 RT8100 11 PVCC LGATE 12 10 SS 2 RT 3 I_IND VOUT 0 CSP 6 CSN 5 opt. FB 8 COMP 7 Figure 4. Single 5V Internal VREF Application Circuit DS8100-06 April 2011 www.richtek.com 3 RT8100 Functional Pin Description 5VSB(Pin 1), 12VCC (Pin 16) FB (Pin 8) The 5VSB pin is the external standby 5V power. The 12VCC pin is the external 12V power. Feedback Pin. This pin is negative input pin of the error amplifier. RT (Pin 2) PI (Pin 9) Timing Resistor. Connect a resistor from RT to GND to set the clock frequency. The free running frequency is 200kHz. External reference voltage pin. This pin sets the voltage of FB pin when close loop. I_IND (Pin 3) Stand_Alone : Pull high to 5VSB Current indicating pin. This pin uses voltage level to indicate the current of inductor. Connect this pin with a resistor to ground to set the voltage. I_IND = 4 x IX Tracking : Connect to external reference voltage. The PI pin will sink 4mA for 15μs when the OCP function acts. SS (Pin 10) IX : Internal GM sensed current, please refer to the Application Information. Soft-start Pin. This pin provides soft-start function for its controller. The COMP voltage of the converter follows the ramping voltage on the SS pin. RR (Pin 4) PVCC (Pin 11) Ramp resistor. This pin is used to set the ramp voltage. Connecting a resistor from this pin to the converter input power sets the ramping slope of the control loop of the converter. Since it is connected to the converter input power, the ramp slope is input-feed-forwarded. As VIN > 1.8V, RR pin is enabled for ramp setting. Driver Power. LGATE (Pin 12) Lower Gate Drive. This pin drives the gate of the lowside MOSFET. PHASE (Pin 13) CSN (Pin 5) Current Sense Negative Input. This pin is negative input node of the current sense amplifier used for DCR current sensing. Connect this pin with a resistor to the output node. CSP (Pin 6) Current Sense Positive Input. This pin is positive input nodes of the current sense amplifier used for DCR current sensing. Connect this pin to the junction of the filter resistor and capacitor. This pin is return node of the high-side driver. Connect this pin to high-side MOSFET source together with the lowside MOSFET drain and the inductor. UGATE (Pin 14) Upper Gate Drive. This pin drives the gate of the highside MOSFET. BOOT (Pin 15) Bootstrap Power Pin. This pin powers the high-side MOSFET driver. Connect this pin to the junction of the bootstrap capacitor. COMP (Pin 7) Compensation Pin. This pin is the output node of the error amplifier. www.richtek.com 4 GND [Exposed Pad (17)] The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. DS8100-06 April 2011 RT8100 Function Block Diagram 12VCC RT CLK Oscillator free Running 200kHz POR Soft Stsrt SS 5VSB Power_sel EN & VIN Detection PVCC To RR Pin VREF VREF_SEL PI + FB CSN CSP + GM x4 I_IND CLK RR COMP S/H S/H Ramp Current Generator OCP Current to Voltage Converter + PWMCP BOOT UGATE PHASE PWM Logic PVCC LGATE GND Driver Operation RT8100 is a highly flexible, high performance and high precision synchronous buck controller specifically designed for high-end graphic core power supply as well as DDR applications, with highly reduced external components and costs. RT8100 uses RichTek proprietary Analogous Current The wide input voltage range of the converter ranges from 3.3V to 12V. The output voltage can be set from 0.8V to 3.3V with external resistor divider. The power sequence of RT8100 includes : 1 : POR function ModeTM topology which mimics the traditional peak current 2 : VIN power supply detection mode by sensing the valley current of the inductor via DCR sensing techniques and simulating the current ramp with an artificial ramp set externally. The Analogous Current Mode topology benefits all the advantages of peak current mode converter with much higher noise immunity than conventional one. Since the compensation is easier and with less constraint than that in voltage mode, using low ESR output capacitor as MLCC is possible, which therefore dramatically reduce the board size as well as the cost and has better transient response due to higher control bandwidth. RT8100 also adopts VIN feedfoward for ramp setting, which decreases the complexity for compensation by keeping the modulator gain constant along line variations. 3 : PI pin setting to enable the whole chip. DS8100-06 April 2011 The external elements selection of RT8100 includes : 1 : RT pin resister to GND to set the operation frequency of the chip. 2 : CSN pin resister to set the current gain(ratio of inductance current IL and sensed current Ix). 3 : RR pin resister to VIN to set the slope of the VIN feed forward ramp and the effective slope compensation of current mode. 4 : Use RCSN resister to set the over current level. 5 : Capacitor at SS pin to set the soft-start time. 6 : Type two compensation at COMP pin. www.richtek.com 5 RT8100 Power on reset The POR circuitry monitors the supply voltage of the chip. When the chip power supply exceeds 4.2V, the chip releases the reset state and works according to the settings. Once the supply voltage is lower than 4.0V, POR circuitry resets the chip. VIN detection The VIN detection circuitry monitors the switching power source when power up. As VIN > 1.8V, RR pin is enabled for ramp setting and the chip is in ramp setting mode. The voltage at RR pin will be about 0.5V. Otherwise, the chip will be in VIN detection mode and RR pin is disabled for ramp setting until VIN > 1.8V. In VIN detection mode, the UGATE and LGATE will be off and SS will be pulled low by a constant current of 10uA. The chip will enter the ramp setting mode and SS will re-softstart when VIN > 1.8V. provides the reference voltage of 0.8V at the non-inverting input of both error amplifiers. The output voltage is programmed by using a voltage divider at output and feeding the voltage division back to corresponding error amplifiers. As conventional current mode PWM controller, the output voltage is locked at the VREF of error amplifier and the error signal is used as the control signal of pulse width modulator. The PWM signals are generated by comparison of EA output and current ramp waves. Power stage transforms VIN to output by PWM signal on-time ratio. Enable After POR reset, the chip monitors the voltage of PI pin. When PI is higher than 0.3V, the chip is enabled. The chip is disabled when VPI is lower than 0.3V. With a precise threshold voltage, the PI pin can be used for power sequence. Soft-start A constant current of 10uA starts to charge the capacitor connected to SS pin right after the chip has been powered up and enabled. The ramp voltage on SS pin is also used to clamp the comp voltage during soft-start, which automatically constraints the output current due to the nature of current mode topology. This brings up smaller inrush current and smooth output voltage ramp. The SS pins are also used as the timer during OCP hiccup. Frequency setting The converter switching frequency is programmed by connecting a resistor from the RT pin to GND. The frequency vs. RRT plot is shown in “Typical Operating Characteristics”. Output voltage setting and control Control loops consist of an error amplifier, a pulse width modulator, current feed back components, a gate driver and power components. The internal high accuracy bias www.richtek.com 6 DS8100-06 April 2011 RT8100 Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------- 16V BOOT, VBOOT - VPHASE ------------------------------------------------------------------------------------ 16V z PHASE to GND DC ------------------------------------------------------------------------------------------------------------- −5V to 15V < 200ns ------------------------------------------------------------------------------------------------------ −10V to 30V z BOOT to PHASE ------------------------------------------------------------------------------------------ 15V z BOOT to GND DC ------------------------------------------------------------------------------------------------------------- −0.3V to VCC+15V < 200ns ------------------------------------------------------------------------------------------------------ −0.3V to 42V z UGATE ------------------------------------------------------------------------------------------------------- VPHASE - 0.3V to VBOOT + 0.3V z LGATE ------------------------------------------------------------------------------------------------------- GND - 0.3V to VCC + 0.3V z Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND-0.3V to 7V z Power Dissipation, PD @ TA = 25°C z z z z z z z VQFN-16L 3x3 --------------------------------------------------------------------------------------------- 1.47W Package Thermal Resistance (Note 2) VQFN-16L 3x3, θJA ---------------------------------------------------------------------------------------- 68°C/W Junction Temperature ------------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------ 1.5kV MM (Machine Mode) -------------------------------------------------------------------------------------- 150V Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------------- 12V ± 10% Ambient Temperature Range ---------------------------------------------------------------------------- 0°C to 70°C Junction Temperature Range ---------------------------------------------------------------------------- 0°C to 125°C Electrical Characteristics (VIN = 12V, TA = 25°C unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Input Power Supply Voltage 12VCC 5VSB 4.5 -- 12 5 15 -- V Power On Reset V5VSBRTH 3.8 4.2 4.4 V Power On Reset Hysteresis V5VSBHYS -- 0.3 -- V ON VEN -- 0.3 -- V Hysteresis VEN -- 50 -- mV -- 10 -- mA 8 10 15 μA PI Threshold Power Supply Current IVCC 5VSB = 5V, 12VCC = 12V, VIN = 0V Soft-Start Soft-Start Current ISS To be continued DS8100-06 April 2011 www.richtek.com 7 RT8100 Parameter Symbol Test Conditions Min Typ Max Unit 170 200 230 kHz −15 -- 15 % Frequency Range 50 200 1000 kHz Maximum Duty Cycle 70 75 80 % 0.3 0.5 0.7 V -- 1.5 -- % 60 70 -- dB Oscillator Free Running Frequency f OSC Frequency Variation Up-Ramp Setting Pin VRR RRR = 120kΩ VFB VFB = 0.8V Reference Voltage Feedback Voltage Error Amplifier DC Gain Gain-Bandwidth Product GBW CLOAD = 5pF 6 10 -- MHz Trans-conductance GM RLOAD = 20kΩ 600 660 -- μA/V MAX Current (Source & Sink) I OUT VOUT = 0.5 x V5VSB 300 360 -- μA Input Offset Voltage VVOSGM RSENSE = 2kΩ −5 -- 5 mV IOMAX I IOMAXGM RSENSE = 2kΩ 90 -- -- μA 0.15 0.35 -- A -- 3.5 7 Ω 0.5 0.35 -- A -- 2 4 Ω -- 80 -- μA Current Sense GM Amplifier Gate Driver BOOT − PHASE = 12V, Upper Drive Source I UGATE Upper Drive Sink RUGATE VUGATE = 1V Lower Drive Source I LGATE PVCC = 12V, PVCC – VLGATE = 1V Lower Drive Sink RLGATE VLGATE = 1V BOOT − VUGATE = 1V Protection Over Current I OC Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 8 DS8100-06 April 2011 RT8100 Typical Operating Characteristics Efficiency vs. Output Current 95 VIN = 5V 90.5 900 VIN = 12V 800 Frequency (kHz) 1 86 Efficiency (%) Frequency vs. RRT 1000 81.5 77 72.5 68 63.5 700 500 400 RRT connected to 5VSB 300 59 200 54.5 100 50 RRT connected to GND 600 0 0 5 10 15 20 25 1 10 100 1000 Output Current (A) RRT (kπ (kΩ)) Dead Time (Rising) Dead Time (Falling) UGATE UGATE PHASE PHASE UGATE − PHASE (5V/Div) LGATE 10000 UGATE − PHASE (5V/Div) LGATE Time (25ns/Div) Time (25ns/Div) Load Transient Regulation (Rising) Load Transient Regulation (Falling) UGATE (10V/Div) UGATE (10V/Div) LGATE (10V/Div) LGATE (10V/Div) VOUT (200mV/Div) ILoad (10A/Div) VOUT (200mV/Div) ILoad (10A/Div) Time (10μs/Div) DS8100-06 April 2011 Time (50μs/Div) www.richtek.com 9 RT8100 PI Power On PI Power Off UGATE (10V/Div) UGATE (10V/Div) SS (5V/Div) SS (5V/Div) PI (500mV/Div) PI (500mV/Div) VOUT (500mV/Div) VOUT (500mV/Div) Time (5ms/Div) Time (1ms/Div) Power Off UGATE (10V/Div) Power On UGATE (20V/Div) ILoad (1A/Div) 5VSB (2V/Div) VOUT (500mV/Div) SS (2V/Div) VOUT (500mV/Div) SS (2V/Div) Time (50ms/Div) Time (10ms/Div) Standalone OCP Tracking OCP SS (2V/Div) SS (2V/Div) VOUT (500mV/Div) PI (1V/Div) UGATE (10V/Div) PI (1V/Div) UGATE (10V/Div) Time (50ms/Div) www.richtek.com 10 Time (5μs/Div) DS8100-06 April 2011 RT8100 GM 350 300 I I_IND (uA) 250 200 150 100 50 0 0 2 4 6 8 10 12 14 16 18 20 Output Current (A) DS8100-06 April 2011 www.richtek.com 11 RT8100 Application Information Current Sense, Ramp Setting RT8100 senses the inductor current through inductor DCR and feeds the current signal back to the control loop. The current sensing circuitry, as in Figure 5 consists of an RC filter, a current sensing GM together with two external resistors. The current flowing the inductor as well as the DCR causes a ripple voltage proportional to inductor ripple current across the equivalent inductor DCR as in Figure 5, The ripple voltage can be obtained using an RC filter in parallel with the inductor, if the component values satisfy the following relationships. L DCR R C The external resistor RR is used to sets the internal ramp voltage proportional to current. The simulated ramp voltage is also used to implement the slope compensation set together using a single resistor RR. The relationships between RR and the internal voltage ramp is : ( V VIN − VOUT + k OUT ) DCR 15k L R CSN L = VIN − VRR ÷ 64p RR RR = (VIN − VRR ) x ÷( R CSN 64p V VIN − VOUT + k OUT ) ÷ DCR L 15k L Where + GM - CSP(Pin) CSN(Pin) IX RCSN RDC Figure 5 L =RxC DCR The current sense GM converts the voltage drop on the capacitor in the DCR sensing network together with the resistor RCSN connected from the VOUT to the CSN pin. RCSN defines the trans-conductance of the GM stage. An extra external resistor connected from RCSN to GND is recommended to offer the capability of sensing negative inductor current in applications where negative currents are possible at light load conditions. The sensed current Ix is : I × DCR VOUT , at steady state. IX = L + R CSN RDC IX = IL × DCR R CSN , provided RDC is left opened. The valley of the sensed current Ix is sampled and held and converted to a DC voltage as a baseline of the current feedback ramp. www.richtek.com 12 VRR: the voltage at RR pin to 0.5V RR : the resistance at RR pin k : the slope compensation coefficient, which is the ratio of the desired compensation slope to the down ramp slope. The ramp voltage is summed up with the sensed baseline voltage to form a complete current feedback signal. The simulated ramp signal is fed to the comparator of the PWM modulator, comparing with error amplifier output to generate PWM pulses. Gate Control a. Before SS signal reach the bottom of the ramp voltage, UGATE and LGATE will be off. b. If PI pin is pulled low UGATE and LGATE will be off. c. When OC function occurs a constant current of 10μA starts to discharge the capacitor connected to SS pin right away. When OC occurs, UGATE and LGATE will be off. When the voltage at the capacitor connected to SS pin pass about 0.4V, a constant current of 10μA starts to charge the capacitor. The PWM signal is enable to pass to UGATE and LGATE. d. When fault conditions occur or SS < 0.4V, the current sense function will be disable. DS8100-06 April 2011 RT8100 Feedback Loop Compensation First, the ramp signal applied to the PWM comparator is proportional to the input voltage provided via the RR pin. This keeps the modulator gain constant when the input voltage varies. Second, the inductance valley current proportional signal is derived from the voltage drop across the ESR of the inductance is added to the ramp signal. This effectively creates an internal current control loop. The resistor connected to the CSN pin sets the gain in the current feedback loop. The following expression estimates the required value of the current sense resistor depending on the maximum load current and the value of the inductance DCR. R CSN = IMAX x DCR 80 μA 1) Modulator Frequency Equations The first step is to calculate the complex conjugate poles contributed by the LC output filter. The output LC filter introduces a double pole, 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. The resonant frequency of the LC filter expressed as follows : 1 FP(LC) = 2π × L OUT × COUT The next step of compensation design is to calculate the ESR zero. The ESR zero is contributed by the ESR associated with the output capacitance. Note that this requires that the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero of the output capacitor expressed as follows : 1 FZ(ESR) = 2π × COUT × ESR 2) Compensation Frequency Equations RT8100 is a analogous current mode buck converter using the high gain error amplifier with transconductance (OTA, Operational Transconductance Amplifier), as Figure 6 shown. The compensation network consists of the error amplifier and the impedance networks ZC and ZF as Figure 7 shown. VOUT The Transconductance : GM = ΔIOUT ΔVM R1 VREF + GM - VCOMP C2 FB RF C1 R2 Δ VM = (EA+) - (EA-) ; Δ IOUT = E/A output current. Figure 7. Compensation Loop VOUT EA+ EA- + - GM ROUT Figure 6. OTA Topology This transfer function of OTA is dominated by a higher DC gain and the output filter (LOUT and COUT) with a double pole frequency at FLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the peak to peak oscillator voltage VRAMP. DS8100-06 April 2011 FZ1 = 1 2π × R2 × C2 FP1 = 1 2π × R1× C1 FP2 = 1 2π × R2 × ⎛⎜ C1× C2 ⎞⎟ ⎝ C1+ C2 ⎠ Figure 8 shows the DC-DC converter's gain vs. frequency. The compensation gain uses external impedance networks ZC and ZF to provide a stable, high bandwidth loop. High crossover frequency is desirable for fast transient response, but often jeopardize the system stability. In order to cancel one of the LC filter poles, place FZ1 before the LC filter resonant frequency. In the experience, place FZ1 at 10% LC filter resonant frequency. Crossover frequency should be higher than the ESR zero but less than 1/5 of the switching frequency. The FP2 should be place at half the switching frequency. www.richtek.com 13 RT8100 80 80 Type 3 will induce three poles and two zeros. Loop Gain 60 Zeros : 40 40 Compensation Gain Gain (dB) 20 0 0 Modulator Gain -20 1 2π × R2 × C2 FZ2 = 1 2π × (R1+ R3) × C3 Poles : -40-40 -60-60 10Hz 10vdb(vo) FZ1 = 100Hz vdb(comp2)100 vdb(lo) 1.0KHz 10KHz 100KHz 1k 10k Frequency (Hz) Frequency FP1 = 1 2π × R2 × ⎛⎜ C1× C2 ⎞⎟ ⎝ C1+ C2 ⎠ FP2 = 1 2π × R3 × C3 FP3 = 1 ; × R1 R3 × C1 ⎞⎟ ⎛ 2π × ⎜ ⎝ R1+ R3 ⎠ 1.0MHz 100k 1M Figure 8. Type 2 Bode Plot There is another type of compensation called Type 3 compensation that adds a pole-zero pair to the Type 2 network. It's used to compensate output capacitor whose ESR value is much lower (pure MLCC or OSCON Capacitors). which is in the origin. We recommend FZ1 placed in 0.5 x FP(LC); FZ2 placed in FP(LC); FP1 placed in FESR and FP2 placed in 0.5 x FSW. Figure 11 shows Type 3 Bode Plot. As shown in Figure 9, to insert a network between VOUT C3 Loop Gain 60 40 Compensation Gain 20 0 dB and FB in the original Type 2 compensation network can result in Type 3 compensation. Figure 10 shows the difference of their AC response. Type 3 compensation has an additional pole-zero pair that causes a gain boost at the flat gain region. But the gain boosted is limited by the ratio (R1+R4)/R4; if R3 << R4. Gain -20 R3 -40 R1 VOUT FB + GM - R4 VCOMP C2 R2 C1 Modulator Gain -60 -80 2 3 4 5 6 7 Log Frequency Figure 9. Additional Network of Type 3 Compensation (Add between VOUT and FB) Figure 11. Type 3 Bode Plot Protection OCP FP3 Add Type 3 compensation FP1 FZ1 Pole FP2 FZ2 Original Type 3 compensation Figure 10. AC Response Curves of Type 2 and 3 www.richtek.com 14 The RT8100 use cycle by cycle current comparison. The over current level is set by RCSN resistor. When OC function occurs and SS > (5VSB −1.3), a constant current of 10μA starts to discharge the capacitor connected to SS pin right away. When OC occurs UGATE and LGATE will be off. When the voltage at the capacitor connected to SS pin pass about 0.4V, a constant current of 10μA starts to charge the capacitor. DS8100-06 April 2011 RT8100 The PWM signal is enable to pass to the UGATE and LGATE. If the OC protection occurs three times, OCSD will be activated and shut down the chip and pull low PI about 15μs in tracking mode. RT8100 uses an external resistor RCSN to set a programmable over current trip point. OCP comparator compares inductor current with this reference current. RT8100 uses hiccup mode to eliminate fault detection of OCP or reduce output current when output is shorted to ground. IX = DCR × IL R CSN OCP comparator IX 80μA + - Figure 12 OTP Monitor the temperature near the driver part within the chip. Shutdown the chip when OTP. Component Selection Components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum BOM cost and maximum reliability. Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. For a synchronous buck converter, the ripple current of inductor (ΔIL) can be calculated as follows : ΔIL = (VIN − VOUT) x VOUT VIN x fOSC x L Generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. Make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. Output Capacitor Selection The output capacitors determine the output ripple voltage (ΔVOUT) and the initial voltage drop after a high slew-rate load transient. The selection of output capacitor depends on the output ripple requirement. The output ripple voltage is described as follows : DS8100-06 April 2011 ΔVOUT = ΔIL x ESR + VOUT 1 x 2 (1 − D) 8 fOSC x L x C OUT For electrolytic capacitor application, typically 90~95% of the output voltage ripple is contributed by the ESR of output capacitors. Paralleling lower ESR ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent ESR and consequently the ripple voltage. Input Capacitor Selection Use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the MOSFETs. The buck converter draws pulsewise current from the input capacitor during the on time of upper MOSFET. The RMS value of ripple current flowing through the input capacitor is described as : IIN(RMS) = IOUT x D x (1 − D) The input bulk capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. Appropriate high frequency ceramic capacitors physically near the MOSFETs effectively reduce the switching voltage spikes. MOSFET Selection The selection of MOSFETs is based upon the considerations of RDS(ON), gate driving requirements, and thermal management requirements. The power loss of upper MOSFET consists of conduction loss and switching loss and is expressed as : PUPPER = PCOND _UPPER + PSW_UPPER = IOUT x RDS(ON) x D + 1 IOUT x VIN 2 x (TRISE + TFALL ) x fOSC where TRISE and TFALL are rising and falling time of VDS of upper MOSFET respectively. RDS(ON) and QG should be simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is express as : PLOWER = PCOND _LOWER + PRR + PDIODE = IOUT x RDS(ON) x (1 − D) + QRR x VIN x fOSC + 1 x IOUT x VF x TDIODE x fOSC 2 www.richtek.com 15 RT8100 where TDIODE is the conducting time of lower body diode. Special control scheme is adopted to minimize body diode conducting time. As a result, the RDS(ON) loss dominates the power loss of lower MOSFET. Use MOSFET with adequate RDS(ON) to minimize power loss and satisfy thermal requirements. Bypass Capacitor Notes Input capacitor CIN is typically chosen based on the ripple current requirements. COUT is typically selected based on both current ripple rating and ESR requirement. PWM Layout Considerations Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor directly to the drain of high-side MOSFET. In multi-layer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guidelines can get better performance of IC : 1. A multi-layer printed circuit board is recommended. 2. Use a middle layer of the PC board as a ground plane and making all critical component ground connections through vias to this layer. 6. The small signal wiring traces from the LGATE and UGATE pins to the MOSFET gates should be kept short and wide enough to easily handle the several Amperes of drive current. 7. The critical small signal components include any bypass capacitors, feedback components, and compensation components. Position those components close to their pins with a local GND connection, or via directly to the ground plane. 8. RT resistors should be near the RT pin respectively, and GND return should be short, and kept away from the noisy MOSFET GND. 9. Place the compensation components close to the FB and COMP pins. 10. The feedback resistors should also be located as close as possible to the relevant FB pin with vias tied straight to the ground plane as required. 11. Minimize the length of the connections between the input capacitors, CIN and the power switches by placing them nearby. 12. Position both the ceramic and bulk input capacitors as close to the upper MOSFET drain as possible, and make the GND returns (From the source of lower MOSFET to VIN, CVIN, GND) short. 13. Position the output inductor and output capacitors between the upper MOSFET and lower MOSFET and the load. 14. Because RT8100 use DCR sense topology, DCR sense point is output inductor from end to end. 15. CSN and FB must be independent path. Below PCB gerber files are our test board for your reference : 3. Use another solid layer as a power plane and break this plane into smaller islands of common voltage levels. 4. Keep the metal running from the PHASE terminal to the output inductor short. 5. Use copper filled polygons on the top and bottom circuit layers for the phase node. www.richtek.com 16 DS8100-06 April 2011 RT8100 Figure 13. Component Side Figure 14. Bottom DS8100-06 April 2011 www.richtek.com 17 RT8100 Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 V-Type 16L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 18 DS8100-06 April 2011