CYPRESS W182-5

W182
Full Feature Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable output frequency range
• Single 1.25% or 3.75% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 14-pin SOIC (Small Outline Integrated
Circuit)
W182
Output
SS%
W182-5
Output
0
Fin ≥ Fout ≥ Fin
– 1.25%
Fin + 0.625% ≥ Fin≥
– 0.625%
1
Fin ≥ Fout ≥ Fin
– 3.75%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2
FS1
Frequency Range
Key Specifications
0
0
8 MHz ≤ FIN ≤ 10 MHz
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
0
1
10 MHz ≤ FIN ≤ 15 MHz
1
0
15 MHz ≤ FIN ≤ 18 MHz
1
1
18 MHz ≤ FIN ≤ 28 MHz
Frequency Range: .............................. 8 MHz ≤ Fin ≤ 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
Simplified Block Diagram
Pin Configuration
3.3V or 5.0V
SOIC
XTAL
Input
X2
W182
Spread Spectrum
Output
(EMI suppressed)
FS2
CLKIN or X1
NC or X2
GND
GND
1
2
3
4
5
SS%
FS1
6
W182/W182-5
X1
7
14
13
12
11
10
REFOUT
OE#
SSON#
Reset
VDD
9
VDD
8
CLKOUT
3.3V or 5.0V
Oscillator or
Reference Input
W182
Spread Spectrum
Output
(EMI suppressed)
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 8, 2000, rev. *A
W182
Pin Definitions
Pin No.
Pin
Type
CLKOUT
8
O
Output Modulated Frequency: Frequency modulated copy of the input clock
(SSON# asserted).
REFOUT
14
O
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
CLKIN or X1
2
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
NC or X2
3
I
Crystal Connection: Input connection for an external crystal. If using an external reference, this pin must be left unconnected.
SSON#
12
I
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
SS%
6
I
Modulation Width Selection: When Spread Spectrum feature is turned on,
this pin is used to select the amount of variation and peak EMI reduction that
is desired on the output signal. This pin has an internal pull-up resistor.
OE#
13
I
Output Enable (Active LOW): When this pin is held HIGH, the output buffers
are placed in a high-impedance mode.This pin has an internal pull-down resistor.
Reset
11
I
Modulation Profile Restart: A rising edge on this input restarts the modulation
pattern at the beginning of its defined path. This pin has an internal pull-down
resistor.
FS1:2
7, 1
I
Frequency Selection Bit(s): These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors.
VDD
9,10
P
Power Connection: Connected to 3.3V or 5V power supply.
GND
4,5
G
Ground Connection: Connect all ground pins to the common ground plane.
Pin Name
Pin Description
2
W182
times the reference frequency. (Note: For the W182 the output
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Overview
The W182 product is one of a series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum process has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Functional Description
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pin
SS% as shown in Table 1.
The W182 uses a Phase-Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
VDD
Clock Input
Reference Input
Freq.
Divider
Q
Phase
Detector
Σ
Charge
Pump
VCO
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
3
Post
Dividers
CLKOUT
(EMI suppressed)
W182
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing
Generation
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2.
As shown in Figure 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Typical Clock
Amplitude (dB)
Amplitude (dB)
SSFTG
Spread
Spectrum
Enabled
NonSpread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MIN.
Figure 3. Typical Modulation Profile
4
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX.
W182
Absolute Maximum Ratings
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
Rating
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
0.5
W
TSTG
Storage Temperature
TA
Operating Temperature
TB
Ambient Temperature under Bias
PD
Power Dissipation
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
18
32
mA
5
ms
IDD
Supply Current
tON
Power Up Time
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
IIL
Input Low Current
Note 1
IIH
Input High Current
Note 1
IOL
Output Low Current
@ 0.4V, VDD = 3.3V
15
mA
IOH
Output High Current
@ 2.4V, VDD = 3.3V
15
mA
CI
Input Capacitance
RP
Input Pull-Up Resistor
500
kΩ
ZOUT
Clock Output Impedance
25
Ω
First locked clock cycle after Power
Good
0.8
2.4
0.4
2.4
µA
50
7
5
V
V
–50
Note:
1. Inputs FS2:1 have a pull-up resistor; Input SSON# has a pull-down resistor.
V
V
µA
pF
W182
DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10%
Parameter
Description
IDD
Supply Current
tON
Power Up Time
Test Condition
Min.
Typ.
Max.
Unit
30
50
mA
5
ms
0.15VDD
V
First locked clock cycle after
Power Good
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
IIL
Input Low Current
Note 2
IIH
Input High Current
Note 2
IOL
Output Low Current
IOH
Output High Current
@ 0.4V, VDD = 5V
@ 2.4V, VDD = 5V
CI
Input Capacitance
RP
Input Pull-Up Resistor
500
kΩ
ZOUT
Clock Output Impedance
25
Ω
0.7VDD
V
0.4
2.4
V
V
µA
–50
50
µA
24
mA
24
mA
7
pF
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10%
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
fIN
Input Frequency
Input Clock
8
28
MHz
fOUT
Output Frequency
Spread Off
8
28
MHz
tR
Output Rise Time
15-pF load, 0.8V–2.4V
2
5
ns
tF
Output Fall Time
15-pF load, 2.4 –0.8V
2
5
ns
tOD
Output Duty Cycle
15-pF load
40
60
%
tID
Input Duty Cycle
40
60
%
tJCYC
Jitter, Cycle-to-Cycle
300
ps
Harmonic Reduction
250
fout = 20 MHz, third harmonic
measured, reference board,
15-pF load
Note:
2. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.
6
8
dB
W182
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
Recommended Board Layout
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
Xtal Connection or Reference Input
Xtal Connection or NC
14
2
13
3
12
4
5
6
7
W182
GND
1
Figure 5 shows a recommended a 2-layer board layout.
11
10
9
8
C3
0.1µF
Clock
Output
R1
C1
0.1 µF
3.3V or 5V System Supply
FB
C2
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
C1, C3 = High-frequency supply decoupling
capacitor (0.1-µF recommended).
C2 = Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
R1 = Match value to line impedance
FB
Xtal Connection or Reference Input
G
Xtal Connection or NC
= Ferrite Bead
= Via To GND Plane
G
C3
G
G
C1
G
Clock Output
R1
G
Power Supply Input
(3.3V or 5V)
FB
C2
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
W182
W182-5
Package
Name
G
Package Type
14-Pin Plastic SOIC (150-mil)
Document #: 38-00789-A
7
W182
Package Diagram
14-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.