DEVELOPMENT KIT (Info Click here) LPR2430ERA • 2.4 GHz Spread Spectrum Transceiver Module • Small Size, Light Weight, Built-In Antenna • Sleep Current less than 3 µA • FCC, Canadian IC and ETSI Certified for Unlicensed Operation The LPR2430ERA 2.4 GHz transceiver module is a low cost, high-power solution for peer-to-peer, point-to-point and point-to-multipoint wireless designs. LPR2430ERA modules provide the flexibility and versatility to serve applications ranging from cable replacements to sensor networks. Based on the IEEE 802.15.4 wireless standard, the LPR2430ERA module is easy to integrate, requires no external antenna, and provides robust wireless communications in applications where mesh network operation is not required. The LPR2430ERA includes CNL V2.0 Network Layer firmware which features a flexible and simple-to-use Application Programming Interface. High Power 802.15.4 Module with Chip Antenna LPR2430ERA Absolute Maximum Ratings Rating All Input/Output Pins Value -0.3 to +6.0 Non-Operating Ambient Temperature Range -40 to +85 Units V o Shown with Shield Removed C LPR2430ERA Electrical Characteristics Characteristic Sym Notes Minimum Operating Frequency Range 2405 Operating Frequency Tolerance -300 Spread Spectrum Method Modulation Type Typical Units 2475 MHz 300 kHz Direct Sequence O-QPSK Number of RF Channels 15 RF Data Transmission Rate 250 Symbol Rate Tolerance RF Channel Spacing Maximum kb/s 120 ppm 5 MHz Receiver Sensitivity, 10E-5 BER -95 dBm Upper Adjacent Channel Rejection, +5 MHz 41 dB Lower Adjacent Channel Rejection, -5 MHz 30 dB Upper Alternate Channel Rejection, +10 MHz 55 dB Lower Alternate Channel Rejection, -10 MHz 53 dB Maximum RF Transmit Power 18 Transmit Power Adjustment Optimum Antenna Impedance www.RFM.com E-mail: [email protected] ©2009 by RF Monolithics, Inc. dBm 20 50 dB W Page 1 of 5 LPR2430ERA - 06/19/09 LPR2430ERA Electrical Characteristics Characteristic Sym Notes ADC Input Range Minimum Typical 0 ADC Input Resolution Maximum Units 3.3 V 11 ADC Input Impedance 55 PWM Output Resolution* 8 bits MW 16 1.2, 2.4, 4.8, 9.6 (default), 19.2, 28.8, 38.4, 57.6, 76.8, 115.2 UART Baud Rates bits kb/s Digital I/O: Logic Low Input Level -0.3 0.5 V Logic High Input Level 2.8 3.6 V Logic Input Internal Pull-up/Pull-down Resistor 20 KW GPIO3 Logic Low Sink Current Power Supply Voltage Range 20 VCC +3.3 Power Supply Voltage Ripple mA +5.5 Vdc 10 mVP-P Receive Mode Current 33 mA Transmit Mode Current 130 mA Sleep Mode Current Operating Temperature Range 3 -40 85 µA o C *PWM0 has 8-bit resolution, PWM1 has 16-bit resolution. Built-in PWM output filters suppress ripple to 7 bits. Additional filtering can be added externally. CAUTION: Electrostatic Sensitive Device. Observe precautions when handling. www.RFM.com E-mail: [email protected] ©2009 by RF Monolithics, Inc. Page 2 of 5 LPR2430ERA - 06/19/09 L P R 2 4 3 0 E R A B lo c k D ia g r a m 3 2 .7 6 8 k H z G N D 1 A C T IV IT Y + 3 .3 V 3 2 M H z 2 L IN K S w itc h 3 G P IO 0 (A D C _ R E F ) 4 P W R R A D IO _ T X D 5 R A D IO _ R X D 6 /H O S T _ C T S (G P IO 4 ) 7 /H O S T _ R T S (G P IO 5 ) 8 P W M 0 9 G P IO 2 (P W M 1 ) 1 0 G P IO 1 1 1 G P IO 3 (R S 4 8 5 _ E N ) 1 2 P W M 1 (G P IO 2 ) 1 3 F ilte r V C C 1 4 R e g G N D 1 5 C C 8 0 2 R a d M ic r o c F ilte r 2 4 .1 io o n T X /R X C o m b in e r 3 0 5 .4 a n d tr o lle r T /R T /R F ilte r R F IO P R E 2 8 3 0 + 3 .3 V 2 4 R S D V A D C 2 2 5 2 6 2 7 N C 2 3 A D C _ V D D 2 2 N C 2 1 R S D V 2 0 R S D V 1 9 R S D V G N D /R E S E T 1 8 A D C 0 1 7 A D C 1 1 6 Figure 1 LPR2430ERA Hardware LPR2430ERA Firmware The major hardware component of the LPR2430ERA is the CC2430 IEEE 802.15.4 compatible transceiver with integrated 8051 microcontroller. The LPR2430ERA operates in the frequency band of 2405 to 2475 MHz at a nominal output power of 63 mW. The main firmware components in the LPR2430ERA include the 802.15.4 Media Access Control (MAC) layer and the CNL V2.0 Networking Layer. CNL V2.0 supports up to 63 remotes. Network topologies include point-to-point, point-to-multipoint and peer-to-peer. CNL employs one-hop relay forwarding to mitigate network transmission problems such as multipath fading. CNL includes provisions for low-power sleep mode operation with periodic wakeup and report. The CNL Application Programming Interface (API) provides an easy-to-use, flexible set of application commands and functions. The API includes support for send/receive serial data, read/write GPIO, read ADC inputs, write PWM outputs and module configuration services. In addition, CNL supports analog and digital I/O binding, which maps an ADC measurement and the states of two digital inputs on one LPR2430ERA to a PWM output and two digital outputs on another LPR2430ERA. See the LPR2430 Series Integration Guide for complete details of the CNL API. The LPR2430ERA includes a low noise preamplifier in the receiver path and a power amplifier in the transmitter path, greatly increasing the operating range of the CC2430. Two crystals are provided to operate the CC2430, a 32 MHz crystal for normal operation and a 32.768 kHz crystal for precision sleep mode operation. The LPR2430ERA provides a variety of application hardware interfaces including a UART interface, three 11-bit ADC inputs, two PWM (DAC) outputs, and six general purpose digital I/O ports. www.RFM.com E-mail: [email protected] ©2009 by RF Monolithics, Inc. Page 3 of 5 LPR2430ERA - 06/19/09 LPR2430ERA I/O Pad Descriptions Pin Name I/O 1 GND - Power supply and signal ground. Connect to the host circuit board ground. 2 ACTIVITY O RF activity indicator. Output pulses high when a packet is sent or received. 3 LINK O Link indicator. Output is high when the radio has successfully joined a network. 4 GPIO0 (ADC_REF) I/O Description Configurable digital I/O port 0. When configured as an output, the power-on state is also configurable. This pin can also be configured as a reference voltage input for the ADCs, 0 to 3.3 V, 1.25 V typical. 5 RADIO_TXD O Serial data output (UART) from the radio to the host. 6 RADIO_RXD I Serial data input (UART) from the host to the radio. 7 GPIO4 (/HOST_CTS ) I/O Configurable digital I/O port 4. When configured as an output, the power-on state is also configurable. Also configurable as UART flow control output. The LPR2430 sets this line low to indicate it is ready to accept data from the host on the RADIO_RXD input. When the LPR2430 sets this line high, the host must stop sending data. The default state is GPIO4. 8 GPIO5 (/HOST_RTS) I/O Configurable digital I/O port 5. When configured as an output, the power-on state is also configurable. Also configurable as UART flow control input. The host sets this line low to allow data to flow from the RADIO_TXD pin. When the host sets this line high, the LPR2430 will stop sending data to the host. The default state is GPIO5. 9 PWM0 O Pulse-width modulated output 0 with internal low-pass filter. Provides a DAC function, 0 to 3.3 V. I/O Configurable digital I/O port 2. When configured as an output, the power-on state is also configurable. This pin is connected to the input of the low-pass filter driving Pin 13, and is also configurable as a PWM output. I/O Configurable digital I/O port 1. When configured as an output, the power-on state is also configurable. I/O Configurable digital I/O port 3. When configured as an output, this high current port can sink up to 20 mA. The power-on output state is also configurable. Can also be configured as active low transmit enable for controlling an RS485 or other half-duplex bus driver. O GPIO2 (Pin 10) drives this pin through a low-pass filter. Provides a DAC function when GPIO2 is configured as a PWM output. 10 11 12 13 GPIO2 (PWM1) GPIO1 GPIO3 (RS485_EN) PWM1 (GPIO2) 14 VCC I Power supply input, +3.3 to +5.5 Vdc. 15 GND - Power supply and signal grounds. Connect to the host circuit board ground. 16 GND - Power supply and signal grounds. Connect to the host circuit board ground. 17 /RESET I Active low module hardware reset. Hold this input low when the power supply input is less than 3.3 Vdc. The module firmware boots up and will accept commands about 3 seconds after this input goes high. 18 ADC0 I 11-bit ADC input 0. ADC full scale reading can be referenced to the module’s +3.3 V regulated supply, the ADC’s internal +2.5 V reference, or ADC_REF (Pin 4). 19 ADC1 I ADC input 1. Same configuration options as ADC0. 20 RSVD - Reserved pin. Leave unconnected. 21 RSVD - Reserved pin. Leave unconnected. 22 RSVD - Reserved pin. Leave unconnected. 23 RSVD - Reserved pin. Leave unconnected. 24 ADC2 I ADC input 2. Same configuration options as ADC0. 25 ADC_VDD O Module’s +3.3 V regulated supply, used for ratiometric ADC readings. Current drain should be less than 5 mA. 26 NC - No connection. 27 NC - No connection. 28 GND - RF ground. Connect to the host circuit board ground plane, and to shield when using coaxial cable. 29 NC - No connection. 30 GND - RF ground. Connect to the host circuit board ground plane, and to shield when using coaxial cable. www.RFM.com E-mail: [email protected] ©2009 by RF Monolithics, Inc. Page 4 of 5 LPR2430ERA - 06/19/09 L P R 2 4 3 0 E R A O u tlin e a n d M o u n tin g D im e n s io n s 0 .3 0 1 .1 5 0 .0 4 0 .0 5 1 5 0 .0 3 1 1 6 0 .9 8 5 A n te n n a T o p V ie w 3 0 0 .1 2 0 .1 1 D im e n s io n s in in c h e s Figure 2 Reflow Profile An example solder reflow profile for mounting the radio module on its host circuit board is shown in Figure 3. Figure 3 Note: Specifications subject to change without notice. www.RFM.com E-mail: [email protected] ©2009 by RF Monolithics, Inc. Part # M-2430-0005, Rev A Page 5 of 5 LPR2430ERA - 06/19/09