AZS15 Ultra-Low Phase Noise LVPECL, LVDS Buffer & Translator w/ Gain www.azmicrotek.com FEATURES DESCRIPTION The AZS15 is a configurable LVPECL, LVDS buffer & translator IC for low amplitude signals that is optimized for ultra-low phase noise and 2.5V3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for signals up to 1GHz. For designs with larger amplitude signals, refer to the AZS10. The AZS15 is a configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. See Table 2 for details of the configurations options that provide designers with a single IC buffer/translator solution that is extremely compact, flexible and high performance. • 2.5V-3.3V Operation Ultra-Low Phase Noise Floor o LVPECL -165dBc/Hz o LVDS -163dBc/Hz • Configurable o LVPECL or LVDS output o ÷1 or ÷2 o Enable active high or low 1GHz+ bandwidth • APPLICATIONS BLOCK DIAGRAM • GND VDD • EN VDD / 2 • Crystal or SAW based oscillators with LVPECL or LVDS outputs LVDS, PECL clock reference and drivers LVDS, PECL Signal Conversion Q PECL divider (÷2) D Gain PACKAGE AVAILABILITY mux LVDS Q b0 LOGIC • • • • Available in Die SON8 (1.5mm x 1.0mm) MSOP8 (0.118in x 0.118in) Green/RoHS Compliant/Pb-Free b1 Order Number Package Marking AZS15XR Die (Tape & Reel) die ID: AZS15 AZS15XW Die (Probed Wafer) die ID: AZS15 1 SON8 S<date code> 1 MSOP8 S15G 2 <Date Code> AZS15QG AZS15TG 1 Tape & Reel - Add 'R1' at end of order number for 7in (1k parts), 'R2' (2.5k) for 13in 2 See www.azmicrotek.com for date code format www.azmicrotek.com +1-480-962-5881 Request a Sample 2 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description Pin 1 2 3 4 5 6 7 8 1 Q 2 QN 3 GND 4 S <Date Code> EN Name EN Q QN GND D B0 B1 VDD I/O/P I O O P I I I P Description Enable Output Signal Output Signal Negative Supply Input Signal Configuration Bit Configuration Bit Positive Supply EN 1 B1 Q 2 6 B0 QN 5 D GND 8 VDD 7 Properties Configurable functionality Configurable (LVPECL, LVDS) Configurable (LVPECL, LVDS) 0V Tertiary Levels Tertiary Levels 2.375V - 3.6V 8 VDD 7 B1 3 6 B0 4 5 D S15G <Date Code> Figure 1 - Pin Configurations SON8 & MSOP8, respectively www.azmicrotek.com +1-480-962-5881 Request a Sample 2 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator ENGINEERING NOTES FUNCTIONALITY The AZS15 has 8 configurations which are determined by the static voltage levels of B0 and B1. Table 2 details the configurations. Table 2 - Possible IC Configuration Configuration Bits B0 Open Open Open Low Low Low High High High www.azmicrotek.com +1-480-962-5881 Request a Sample B1 Open Low High Open Low High Open Low High Functional Configuration Output Type LVPECL LVPECL LVPECL LVPECL LVDS LVDS LVDS LVDS Not Used Enable Polarity Active High Active High Active Low Active Low Active High Active High Active Low Active Low Not Used Division ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 Not Used 3 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator INPUT TERMINATION The D input bias is VDD/2 fed through an internal 10kΩ resistor. For clock applications, an input signal of at least 750mVpp ensures the AZS15 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. Input signal D 10kΩ A/R VDD/2 Figure 2 - Input Termination LVPECL OUTPUT TERMINATION TECHNIQUES DC COUPLING The LVPECL compatible output stage of the AZS10 uses a current drive topology to maximize switching speed as illustrated below in Figure 3. Two current source PMOS transistors (M1-M2) feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA (low output state). M3 is off, and the entire 21.1mA flows through the output pin. The associated output voltage swings match LVPECL levels when external 50Ω resistors terminate the outputs. Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use. VDD Output Stage Vbp External Circuitry M2 M1 21.1mA 21.1mA Q QN M4 M3 D Vbn 21.1mA - High 5.1mA - Low M5 50Ω 50Ω VTT = VDD - 2.0V 16mA Figure 3 - Typical Output Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 4 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator AC COUPLING Clock applications or phase noise/frequency domain testing scenarios typically require AC coupling. Figure 4 below shows the AC coupling technique. The 200Ω resistors form the required DC loads, and the 50Ω resistors provide the AC termination. The parallel combination of the 200Ω and 50Ω resistors results in a net 40Ω AC load termination. In many cases this will work well. If necessary, the 50Ω resistors can be increased to about 56Ω. Alternately, bias tees combined with current setting resistors will eliminate the lowered AC load impedance. The 50Ω resistors are typically connected to ground but can be connected to the bias level needed by the succeeding stage. VDD Output Stage Vbp 21.1mA 21.1mA M4 M3 D Vbn External Circuitry M2 M1 21.1mA - High 5.1mA - Low Q 0.01µF QN 0.01µF 200Ω M5 200Ω 50Ω 50Ω GND or VT 16mA Figure 4 - AC Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 5 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator LVDS OUTPUT TERMINATION TECHNIQUE The following LVDS termination is compliant to the LVDS specification TIA/EIA-644A. VDD Output Stage External Circuitry M2 M1 - + 350mV 3.5mA QN 100Ω Q Receiver 3.5mA M4 M3 + - Figure 5 – LVDS Termination www.azmicrotek.com +1-480-962-5881 Request a Sample 6 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator PERFORMANCE DATA Table 3 – General Specifications Parameter Description VDD Supply Voltage Vabsolute Absolute Max Power Supply Top Operating Temperature Range -40 85 °C Tstorage Storage Temperature Range -65 150 °C D -0.5 VDD + 0.5 EN -0.5 VDD + 0.5 b0 -0.5 VDD + 0.5 b1 -0.5 VDD + 0.5 VI_max Maximum Input Voltages Ib0,b1 Vtb0,b1 Min 2.375 Typ Max 2.5 3.3 Continuous 3.6 t ≤ 1s 5.5 b0, b1 Input High Current b0, b1 = VDD b0, b1 Input Low Current b0, b1 = GND 11 -11 VDD - 0.5 VDD b0, b1 Input Low Voltage Threshold 0 0.5 EN Input Current -4 3 EN Input High Voltage Threshold VDD - 0.5 VDD EN Input Low Voltage Threshold 0 0.5 Human Body Model ESD www.azmicrotek.com +1-480-962-5881 Request a Sample ESD Ratings Unit V 3.6 b0, b1 Input High Voltage Threshold IEN VtEN Conditions V V uA V uA V 2000 Machine Model 200 Charged Device Model 2000 V 7 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator Table 4 – LVPECL Performance Specifications AC Specification Guaranteed by design Parameter Description fmax Max Input Frequency RL Output Loading Rbias Input Bias Resistor Vin_swing Input Voltage Swing Vout Voltage Output Levels Conditions Min ÷1 mode 1000 ÷2 mode 1600 D input to VDD/2 ref minimum recommended1 MHz 50 Ω 10k Ω Vpp <0.6 VDD-1.25 VDD-0.88 V VDD = 2.5V, LOW VDD-1.86 VDD-1.66 V VDD = 3.3V, HIGH VDD-1.15 VDD-0.88 V VDD = 3.3V, LOW VDD-1.86 VDD-1.75 V 0.54 0.93 Vpp, Q/QN 0.75 5.47 dBm, Q/QN 0.74 0.93 Vpp, Q/QN 3.49 5.47 dBm, Q/QN 80%-20% 100 205 ps VDD = 3.3V Output Rise/Fall Time Unit VDD = 2.5V, HIGH Differential Output Voltage tr / tf Max 1 VDD = 2.5V VOD Typ PN Phase Noise Floor 1MHz Offset -165 dBc/Hz Jinteg Integrated Jitter: 12kHz-20MHz 155MHz Carrier 36 fs 2 Tenable Enable Time 2 Tdisable Disable Time EN = active 15 us EN = disabled 0.5 us 2.2 ns 3 Tprop Propagation Delay IDD Power Supply Current 1 2 0.9 EN = active4 EN = disabled5 28.5 5 mA Phase noise floor performance is dependent upon input voltage swing. Voltage swing values below recommended values may result in degraded phase noise values Into and out of tri-state condition 3 Time from D crossing VDD/2 to Q=QN 4 VDD =3.3V, Fin @ 200MHz 5 D = 0V www.azmicrotek.com +1-480-962-5881 Request a Sample 8 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator Table 5 - LVDS Performance Specifications AC Specification Guaranteed by design Parameter Description fmax Max Input Frequency RL Output Loading Rbias Input Bias Resistor Vin_swing Input Voltage Swing Vout Voltage Output Levels Conditions Min ÷1 mode 1000 ÷2 mode 1600 D input to VDD/2 ref minimum Typ Max Unit MHz 100 Ω 10k Ω 1 recommended1 Vpp <0.6 VDD = 2.5V 290 454 VDD = 3.3V 290 454 mV VOD Differential Output Voltage -50 50 mV VOC Common Mode Output Voltage 1.125 1.375 V ΔVOC Delta in Common Mode Output Voltage2 -50 50 mV VOC,PP Peak-to-Peak Common Mode Output Voltage 100 mV tr / tf Output Rise/Fall Time 80%-20% 120 220 ps PN Phase Noise Floor 1MHz Offset -163 45 dBc/Hz Jinteg Integrated Jitter: 12kHz - 20MHz 155MHz Carrier Tenable Enable Time3 EN = active 4 us Tdisable Disable Time3 EN = disabled 0.5 us 1.7 ns 4 Tprop Propagation Delay 0.8 5 IDD Power Supply Current fs EN = active EN = disabled6 12.9 5 mA 1 Phase noise floor performance is dependent upon input voltage swing. Voltage swing values below recommended values may result in degraded phase noise values 2 Between logics states 3 Into and out of tri-state condition 4 Time from D crossing VDD/2 to Q=QN 5 VDD =3.3V, Fin @ 200MHz 6 D = 0V www.azmicrotek.com +1-480-962-5881 Request a Sample 9 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator PACKAGE DIAGRAM SON8 (1.5x1.0x0.4mm) Green/RoHS compliant/Pb-Free MSL =1 www.azmicrotek.com +1-480-962-5881 Request a Sample 10 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator PACKAGE DIAGRAM MSOP8 (0.118 x 0.118 x 0.034in) Green/RoHS compliant/Pb-Free MSL =1 www.azmicrotek.com +1-480-962-5881 Request a Sample 11 Apr 2014, Rev 1.0 Arizona Microtek, Inc. AZS15 Ultra-Low Phase Noise LVPECL/LVDS Buffer/Translator DIE SPECIFICATIONS Die Size 382µm x 1012µm Pad Size 52.1µ (Octagonal) Die Coordinates (Center 0,0) EN X Coordinate (µm) -111.825 Y Coordinate (µm) 394.050 Q -111.825 197.150 Pad Name QN -111.825 -132.625 GND -114.500 -395.650 D 111.825 -393.800 B0 111.825 -179.850 B1 111.825 212.975 VDD 118.650 388.950 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 12 Apr 2014, Rev 1.0