1 Quest for the Optimum Power Distribution Architecture • Which power distribution architectures can efficiently support power systems from wall plugs, AC or DC outlets, through capacitors, super-capacitors or batteries, to processor cores – in the home, in the office, in the factory and everywhere in between? – Centralized Power Architecture (CPA) – Distributed Power Architecture (DPA) – Intermediate Bus Architecture (IBA) – Factorized Power Architecture (FPA) 2 Power Architecture Evolution Centralized Power (CPA) AC in Central Power Supply AC in Central Power Supply 5V 5 VV 1.0 3 Centralized Power Architecture Centralized power remains pervasive in smaller systems due to its simplicity and low cost • But is unable to efficiently deliver high currents at low voltages 4 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Isolated DC-DC converter DC bus System boards 5 Distributed Power Architecture Distributed power addresses architectural limitations of CPA • Provides efficient power distribution at higher voltages • Puts bricks at the Point of Load (POL) • But DPA comes at a price – Board real estate – System cost 6 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Isolated intermediate bus converter Non-isolated POL converters (niPOLs) Semi-regulated DC bus System board 7 Intermediate Bus Architecture Intermediate bus deals with the proliferation of load voltages • Puts inexpensive non-isolated buck converters at the POL • But IBA is limited by – Inability to transform V and I – Having to decrease a duty cycle to reduce output voltage – Inductive inertia standing in the way of dynamic loads 8 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Factorized Power (FPA) Non-isolated pre-regulators (PRMs) Isolated POL converters (VTMs) DC bus System board 9 Factorized Power Architecture Factorized power addresses demanding POL current and voltage requirements: • Puts a fast “current multiplier” at POL nodes • Transforms V and I down to fractional POL voltages • 100% effective duty cycle 10 IBA – Inherent Duty Cycle Limitations … Duty cycle here is only 7% IBC niPOL Isolation & Transformation NP Regulation & Step Down NS L Distribution bus e.g. Semi-regulated 48 Vdc At 0.8 Vout… Isolates steps down Semi-regulated Intermediate Bus Regulated load voltage Steps down regulates e.g. 12 Vdc 11 FPA – No Duty Cycle Limitations PRM VTM Regulation Wide range DC bus e.g. 36–75 Vdc 100% effective duty cycle at any Vout Isolation & Transformation NP L NS Regulated load voltage K = NS / NP Factorized bus 12 IBA – Inherent Step-Down Limitations niPOL IBA IBA IBA 48 Vdc 48 Vdc 48 Vdc 48 Vdc IBC IBC 12 Vdc IBC 3.0 Vdc 2.0 Vdc 2% niPOL 0.8 Vdc 7% niPOL 0.8 Vdc 26% niPOL 0.8 Vdc 40% niPOL 0.8 Vdc 13 FPA – No Step-Down Limitations niPOL IBA IBA IBA FPA 48 Vdc 48 Vdc 48 Vdc 48 Vdc 48 Vdc IBC IBC 12 Vdc IBC 3.0 Vdc 48 Vf 2.0 Vdc 2% niPOL 0.8 Vdc 7% niPOL 0.8 Vdc 26% niPOL 0.8 Vdc 40% niPOL 0.8 Vdc 100% 0.8 Vdc 14 IBA – Inherent Energy Storage & Dynamic Response Limitations Upstream storage ineffective as load bypass IBC niPOL Isolation & Transformation NP L in wrong place Bulk storage required Regulation & Step Down NS L 15 FPA – No Energy Storage or Dynamic Response Limitations Upstream storage 1/K2 times more effective No intervening L No bulk storage needed PRM Regulation L VTM Isolation & Transformation NP NS X K = NS / NP 16 Energy Storage in the Wrong Place IBC 48 Vdc NP NS 10,000 µF here… niPOL L 0.8 Vdc Energy Storage in the Right Place … can be replaced by 10 µF here PRM 48 Vdc L VTM NP NS 0.8 Vdc K = NS / NP 17 The Building Blocks of Factorized Power V•I Chips (VICs) “Full VIC” ~ 1.0 in2 surface mount package PRM – Pre-Regulator Module VTM – Voltage Transformation Module 18 Basic FPA with PRM & VTM Local Loop Wide range Factorized bus Input bus Vf Vf • K Load • PRM controls the factorized bus voltage (Vf) to regulate the VTM output • VTM transforms and isolates at the POL • Combination: efficient distribution, regulation, transformation and isolation Patents and Patents Pending 19 FPA Example Adaptive Loop with PRM 1.5 Vdc Vf = 48 Vdc 36-75 Vdc Telecom bus Load 1 K = 1/32 12 Vdc Load 2 K = 1/4 Patents and Patents Pending 20 FPA Example Independently Regulated Outputs K = 1/32 Vf = 26 Vdc 36-75 Vdc Telecom bus 0.8 Vdc Load 1 POLIC Isolated Remote Loop Adaptive Loop - 5 Vdc Vf = 40 Vdc Load 2 K = 1/8 Patents and Patents Pending 21 The Engine Under the Hood – PRM 22 “Full VIC” PRM Capabilities • • • • • • ZVS buck / boost regulator Input voltage: 1.5-400 V (up to 5:1 range) Step-up/step-down range: up to 5:1 Output power: up to 300 W Conversion efficiency: up to 98% Frequency: up to 2 MHz 23 “Full VIC” PRM Capabilities • • • • • • ZVS buck / boost regulator Input voltage: 1.5-400 V (up to 5:1 range) Step-up/step-down range: up to 5:1 Output power: up to 300 W Conversion efficiency: up to 98% Frequency: up to 2 MHz 24 PRM – ZVS Buck/Boost Engine • ZVS buck-boost topology and control architecture • High frequency operation Patents and Patents Pending 25 PRM Conduction Phases • Power cycle comprises four conduction phases 1. Input phase Patents and Patents Pending 26 PRM Conduction Phases • Power cycle comprises four conduction phases 1. Input phase 2. Input-output phase Patents and Patents Pending 27 PRM Conduction Phases • Power cycle comprises four conduction phases 1. Input phase 2. Input-output phase 3. Free-wheeling phase Patents and Patents Pending 28 PRM Conduction Phases • Power cycle comprises four conduction phases 1. Input phase 2. Input-output phase 3. Free-wheeling phase 4. Clamp phase Patents and Patents Pending 29 Vin < Vout Patents and Patents Pending 30 Vin < Vout Patents and Patents Pending 31 Vin < Vout Patents and Patents Pending 32 Vin < Vout Patents and Patents Pending 33 Vin < Vout Patents and Patents Pending 34 Vin < Vout Patents and Patents Pending 35 Vin < Vout Patents and Patents Pending 36 Vin < Vout Patents and Patents Pending 37 Vin < Vout Patents and Patents Pending 38 Vin ≅ Vout Patents and Patents Pending 39 Vin ≅ Vout Patents and Patents Pending 40 Vin ≅ Vout Patents and Patents Pending 41 Vin ≅ Vout Patents and Patents Pending 42 Vin ≅ Vout Patents and Patents Pending 43 Vin ≅ Vout Patents and Patents Pending 44 Vin ≅ Vout Patents and Patents Pending 45 Vin ≅ Vout Patents and Patents Pending 46 Vin ≅ Vout Patents and Patents Pending 47 Vin > Vout Patents and Patents Pending 48 Vin > Vout Patents and Patents Pending 49 Vin > Vout Patents and Patents Pending 50 Vin > Vout Patents and Patents Pending 51 Vin > Vout Patents and Patents Pending 52 Vin > Vout Patents and Patents Pending 53 Vin > Vout Patents and Patents Pending 54 Vin > Vout Patents and Patents Pending 55 The Engine Under the Hood – VTM 56 “Full VIC” VTM Capabilities • • • • • • • ZCS / ZVS Sine Amplitude Converter (SAC) Input voltage: 0-400 V (up to 2:1 range) Output voltage: 0-400 V Transformation ratio (K): 1/200 to 200 Output current or power: up to 100 A or 300 W Conversion efficiency: up to 97% Conversion frequency: up to 4 MHz, fixed 57 VTM / BCM SAC Power Train • Primary “Engine” is a Low Q oscillator formed by CRES and the leakage inductance of T1 Patents and Patents Pending 58 VTM / BCM SAC Power Train • The Low Q oscillator is driven by an H-bridge Patents and Patents Pending 59 VTM / BCM SAC Power Train • In this particular example, secondary rectification is also performed using an H-bridge Patents and Patents Pending 60 VTM/BCM SAC Power Train • Load current drives the Low Q oscillator by pulling primary current Patents and Patents Pending 61 VTM / BCM Sine Amplitude Converter (SAC) • The amplitude of the Low Q oscillator is proportional to the load current as reflected back to the primary Patents and Patents Pending 62 VTM / BCM Level 2 Behavioral Model 48 V to 1.5 V 100 A VTM Patents and Patents Pending 63 VTM / BCM SAC Control • The controller locks to the natural frequency of the Low Q oscillator and turns all switches ON and OFF under ZCS/ZVS conditions • Conduction states result in a 100% effective duty cycle • Control circuitry recycles the gate drive energy from each pair of switches Patents and Patents Pending 64 VTM / BCM SAC Control • Control Servo locks to Sine Amplitude Converter resonant frequency and phase, compensating for power train parametric variabilities • Soft start, inrush control and Adaptive Loop Compensation of Rout Patents and Patents Pending 65 VTM Operation Phases Patents and Patents Pending 66 VTM Operation Phases Patents and Patents Pending 67 VTM Operation Phases Patents and Patents Pending 68 VTM Operation Phases Patents and Patents Pending 69 VTM Operation Phases #1 Patents and Patents Pending 70 VTM / BCM SAC Engine – Additional Features • Bi-directional power transfer • Flexibility of topology • Common-mode cancellation 71 Superior System Performance • Higher power/current density – Power conversion building blocks occupy less space • Higher efficiency – Power conversion building blocks generate less heat • Faster transient response – Overcomes processor/power technology gap • Lower input and output noise – Reduced filtering frees up board space 72 SAC: Highest Power Density • High fixed switching frequency (up to 4 MHz) – Reduces size of all reactive components • Zero-current & zero-voltage switching (ZCS/ZVS) – Reduces stresses, losses and heat • No serial energy storage – No output inductor • 100% effective transformation duty cycle – Efficient power train utilization 73 From niPOLs to VICs 16 A / 80 W niPOL • Surface mount • Efficiency: 12 Vin to 1.2 Vout = 83% • 1.30" x 0.53" x 0.37" (33,0 mm x 13,5 mm x 9,3 mm) • Area: 0.7 in2 (4,5 cm2) • Volume: 0.25 in3 (4,1 cm3) 100 A / 300 W V•I Chip • Surface mount • Efficiency: 48 Vin to 1.2 Vout = 91% • 1.26 " x 0.85" x 0.24" (32,0 mm x 21,5 mm x 6,0 mm) • Area: 1.1 in2 (6,9 cm2) • Volume: 0.26 in3 (4,1 cm3) 74 From niPOLs to VICs 16 A / 80 W niPOL 100 A / 300 W V•I Chip 320 W/in3 1,095 W/in3 64 A/in3 365 A/in3 114 W/in2 270 W/in2 23 A/in2 91 A/in2 75 SAC: Highest Efficiency • ZCS / ZVS – No switching losses • Low Q transformer – Reduced winding losses • No serial energy storage – No inductor losses • 100% effective transformation duty cycle – Efficient power train utilization 76 Efficiency 77 Efficiency 78 SAC: Fastest Dynamic Response • No serial energy storage & Low Q transformer – No current inertia & quick settling • High fixed switching frequency (up to 4 MHz) – Minimal cycle-to-cycle delay • Load independent control – No lag due to control loop • Bi-directional power processing – Load dump energy recycled to input • Capacitance multiplication – High effective POL capacitance: Cout(eff) ~ Cin•(1/K)2 + Cout 79 Dynamic Response K = 1/32 VTM @ Vout = 1 V 0 – 100 A load step with 100 µF input capacitance and NO output capacitance 100 – 0 A load step with 100 µF input capacitance and NO output capacitance 80 SAC: Lowest Noise • ZCS/ZVS – Order of magnitude reduction in dI/dt – Significant reduction in dV/dt • Symmetric power train – Cancellation of common-mode noise • High fixed switching frequency (up to 4 MHz) – Easy to filter 81 Output Noise K = 1/32 VTM @ 1.0 V & 100 A Output voltage ripple @ 100 A with NO bypass capacitance Output voltage ripple @ 100 A with 200 µF ceramic bypass capacitance and 20 nH distribution inductance 82 The Flexibility of FPA • Most contemporary power systems are a hybrid of centralized, distributed and intermediate bus • Factorized power building blocks support existing power distribution architectures 83 V•I Chip Package Flexibility Surface mount BGA package for in-board mounting Surface mount J-Lead package for on-board mounting Surface mount extended J-Lead package for on-board mounting 84 Intermediate Bus • VTMs function as intermediate bus converters (BCMs) • More power and more performance in less space 85 Distributed Power • A PRM and VTM pair can replace bricks • Superior performance at less cost 86 VICBrick – Up to 100 A in a 0.25" High Quarter-brick Package 87 Centralized Power • PRMs can be remotely located • Low current factorized buses can be easily routed throughout the system 12 PRM VF2 VF1 12 VTM -12 V 12 PRM VF3 12 VTM +5 V Central Power Supply 12 PRM 12 VTM Central Power Supply 1.8 V 88 From the Wall Plug to the Processor Core 150 – 200 Watt FPA Solution 89 Conventional Power System Architecture 12 V Intermediate Bus ~ 12 V AC Front-end 176 W VR10 Multi-phase Buck 110 W Converter 12 V P4 Processor Pdiss ≈ 29 W 86% efficiency Pdiss ≈ 14 W 87% efficiency niPOL Linear Reg. niPOL Total Power ~ 66 W (HDD, USB, I/O, DDR, other) 90 12 V Input PRM/VTM Sub-system ~ 12 V Vf P4 Processor AC Front-end 176 W Pdiss ≈ 29 W Pdiss ≈ 12 W 86% efficiency 89% efficiency niPOL Linear Reg. niPOL Total Power ~ 66 W (HDD, USB, I/O, DDR, other) 91 Advanced Processor FPA System ~ Vicor AC Front-end Vf 103 W 12 V Pdiss ≈ 17 W P4 Processor Pdiss ≈ 7 W 93% efficiency 91% efficiency niPOL Linear Reg. niPOL Total Power ~ 66 W (HDD, USB, I/O, DDR, other) 92 Comparative Benchmark Conventional Pentium 4 Power System 12 V Input PRM / VTM Sub-System Advanced Processor FPA System 86% 18 W 6.6 W/in3 86% 18 W 6.6 W/in3 91% 11 W 25 W/in3 87% 14 W 23 W/in3 89% 12 W 59 W/in3 93% 7W 120 W/in3 75% 77% 85% 32 W 3.2 W/in3 30 W 3.3 W/in3 18 W 11.5 W/in3 Front-end Efficiency Power dissipation Power density POL (processor) Efficiency (1.2V @ 80 A) Power dissipation Power density Total (without auxiliary outputs) Efficiency Power dissipation Power density 93 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Factorized Power (FPA) Which is the Future? 94 Power Architecture Evolution Centralized Power (CPA) Distributed Power (DPA) Intermediate Bus (IBA) Factorized Power (FPA) OHMS LAW & VANISHING DUTY CYCLE Limited Applicability Fast! Efficient! Dense! From the Wall Plug… to the Processor Core! 95 FPA & V•I Chips Power Paradigm of the Future Questions? 96