Si51218 T HREE O UTPUTS F ACTORY P R O GRA MM A B LE C LOCK G ENERATOR Features Generates up to 3 LVCMOS Separate voltage supply pins clock outputs from 32.768 kHz to VDD = 2.5 to 3.3 V 200 MHz VDDO= 1.8 to 3.3 V (VDDO ≤ VDD) Accepts crystal or reference Low cycle-cycle jitter clock input Programmable output rise and 3 to 166 MHz reference clock input fall times 8 to 48 MHz crystal input Ultra small 8-pin TDFN package Programmable FSEL, PD and (1.4 mm x 1.6 mm) OE input functions Operation temperature: 0–70 C Low power dissipation Applications Crystal / XO replacement Digital Media players Portable Devices DTV/IPTV Ordering Information: See page 10. Pin Assignments Description The factory programmable Si51218 is a low power, small footprint and frequency flexible programmable clock generator targeting low power, low cost and high volume consumer and embedded applications. The device operates from a single crystal or an external clock source and generates up to 3 clock outputs from 32.768 kHz to 200 MHz. They are factory programmed to provide customized output frequencies, control inputs and ac parameter tuning like output drive strength that are optimized for customer board condition and application requirements. A separate VDDO supply pin supports clock outputs at a different voltage level. VDD 1 8 VDDO XOUT 2 7 CLKOUT3 XIN/CLKIN 3 6 CLKOUT1/REFOUT1 FSEL/OE 4 5 Si51218 CLKOUT2/REFOUT2 FSEL/OE/PD# VSS Patents pending Functional Block Diagram PLL with Modulation Control XIN/CLKIN 3 Buffers, Dividers and Switch Matrix XOUT 2 VDDO 8 VDD 1 4 To Pin 6/7 Clock Drivers V-Reg Programmable Configuration Register CLKOUT1/REFOUT1 (VDD) OE/FSEL 6 CLKOUT2/REFOUT2(VDDO) OE/FSEL/PD# 7 CLKOUT3(VDDO) To Core To Pin 4 Clock Driver and Oscillator VSS 5 Rev. 1.0 3/14 Copyright © 2014 by Silicon Laboratories Si51218 Si51218 2 Rev. 1.0 Si51218 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. Input Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2. Output Frequency Range and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3. Frequency Select (FSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4. Power Down (PD) or Output Enable (OE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. Pin Descriptions—8-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. Package Outline: 8-pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. PCB Land Pattern: 8-pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Rev. 1.0 3 Si51218 1. Electrical Specifications Table 1. DC Electrical Specifications (VDD=3.3 V ± 10% or VDD=2.5 V ± 5%, TA=0 to 70 oC) Parameter Symbol Test Condition Min Typ Max Unit VDD VDD=3.3 V ±10% 2.97 3.3 3.63 V VDD=2.5 V ±5% 2.375 2.5 2.625 V VDDO VDDO ≤ VDD 1.71 — 3.6 V Output High Voltage VOH IOH= –4 mA, VDDX=VDD or VDDO VDDX-0.5 — — V Output Low Voltage VOL IOL= 4mA, — — 0.3 V Input High Voltage VIH CMOS level 0.7 VDD — — V Input Low Voltage VIL CMOS level — — 0.3 VDD V Operating Supply Current IDD FIN=20 MHz, CLKOUT1=32.768KHz, REFOUT2=20 MHz CLKOUT3=26MHz, CL=0, VDD=VDDO=3.3 V — 6 — mA Nominal Output Impedance ZO — 30 — Operating Voltage RPUP/RPD Pin 6 — 150k — Input Pin Capacitance CIN Input Pin Capacitance — 3 5 pF Load Capacitance CL Clock outputs < 166 MHz — — 15 pF Clock outputs > 166 MHz — — 10 pF Internal Pull-up/Pull-down Resistor 4 Rev. 1.0 Si51218 Table 2. AC Electrical Specifications (VDD=3.3 V ± 10% or VDD=2.5 V ± 5%, TA=0 to 70 oC) Parameter Symbol Test Condition Min Typ Max Unit Input Frequency Range FIN1 Crystal input 8 — 48 MHz Input Frequency Range FIN2 Reference clock Input 3 — 166 MHz Output Frequency Range FOUT 0.032768 — 200 MHz Frequency Accuracy FACC Configuration dependent — 0 — ppm DCOUT Measured at VDD/2 45 50 55 % Input Duty Cycle DCIN CLKIN, CLKOUT through PLL 30 50 70 % Output Rise Time tr CLKOUT1/2/3 in MHz range CL=15 pF, 20 to 80% — 1 3.0 ns Output Fall Time tf CLKOUT1/2/3 in MHz range CL=15 pF, 20 to 80% — 1 3.0 ns Period Jitter PJ1 CLKOUT1/2/3 in MHz range, VDD=VDDO=3.3 V, CL=15 pF — 150* — ps Period Jitter PJ2 CLKOUT1/3 at 32.768KHz, VDD=VDDO=3.3 V, CL=15 pF — 1500* — ps Cycle-to-Cycle Jitter CCJ CLKOUT1/2/3, in MHz range VDD=VDDO=3.3 V, CL=15 pF — 100* — ps Power-up Time tPU Time from 0.9 VDD to valid frequencies at all clock outputs — 1.2 5.0 ms Output Enable Time tOE Time from OE raising edge to active at outputs (asynchronous) — 15 — ns Output Disable Time tOD Time from OE falling edge to active at outputs (asynchronous) — 15 — ns Output Duty Cycle *Note: Jitter performance depends on configuration and programming parameters. Rev. 1.0 5 Si51218 Table 3. Absolute Maximum Conditions Parameter Main Supply Voltage Symbol Test Condition VDD_3.3V Min Typ Max Unit –0.5 — 4.2 V Input Voltage VIN Relative to VSS –0.5 — VDD+0.5 V Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional, C-Grade 0 — 70 °C Temperature, Junction TJ Functional, power is applied — — 125 °C Temperature, Soldering TSol Non-functional — — 260 °C ESD Protection (Human Body Model) ESDHBM JEDEC (JESD 22 - A114) –4000 — 4000 V ESD Protection (Charge Device Model) ESDCDM JEDEC (JESD 22 - C101) –1500 — 1500 V ESD Protection (Machine Model) ESDMM JEDEC (JESD 22 - A115) — 200 V –200 Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. Table 4. Thermal Characteristics Parameter Symbol Test Condition Value Unit Thermal Resistance Junction to Ambient JA Still air 170.8 °C/W Thermal Resistance Junction to Case JC Still air 98.8 °C/W 6 Rev. 1.0 Si51218 2. Design Considerations 2.1. Typical Application Schematic VDD 0.1µF VDDO VDD 10µF 0.1µF CL1 XOUT CLKOUT3 Si51218 XIN CL2 CLKOUT2 CLKOUT1 VSS Dotted line shows the optional termination resistors 2.2. Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 μF must be used between VDD and VSS on the pins 1 and 8. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor and the VDD pin. In addition, a 10 µF capacitor should be placed between VDD and VSS. Crystal and Crystal Load: Only use a parallel resonant fundamental AT cut crystal. DO NOT USE higher overtone crystals. To meet the crystal initial accuracy specification (in ppm) make sure that external crystal load capacitor is matched to crystal load specification. To determine the value of CL1 and CL2, use the following formula: CL1 = CL2 = 2CL – (Cpin + Cp) Where: CL is load capacitance stated by crystal manufacturer Cpin is the Si51218 pin capacitance (4pF) Cp is the parasitic capacitance of the PCB traces. Example: If a crystal with CL=12 pF specification is used and Cp=1 pF (parasitic PCB capacitance on PCB), 19 pF external capacitors from pins XIN (pin 3) and XOUT (Pin 2) to VSS are required. Users must verify Cp value. Rev. 1.0 7 Si51218 3. Functional Description 3.1. Input Frequency Range The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used, the input frequency range is from 8.0 to 166.0 MHz. 3.2. Output Frequency Range and Outputs Up to three outputs can be programmed as CLKOUT or REFOUT. CLKOUT output can be synthesized to frequency value from 32.768 kHz to 200 MHz. REFOUT is the buffered output of the oscillator and is the same frequency as the input frequency. REFOUT2 (pin6) frequency can also be programmed to input frequency divided by 2 to 32. By using only low cost, fundamental mode crystals, the Si51218 can synthesize output frequency up to 200 MHz, eliminating the need for higher order crystals (Xtals) and crystal oscillators (XOs). The 32.768 kHz output can replace the 32.768 kHz crystal which is widely used in many embedded and mobile systems. This reduces the cost while improving the system clock accuracy, performance, and reliability. 3.3. Frequency Select (FSEL) The Si51218 pin 4 and 6 can be programmed as frequency select input (FSEL). If FSEL function is used, one output pin can switch between two predefined frequencies by FSEL input. The set of frequencies in Table 5 is given as an example. Table 5. Example Frequencies FSEL (Pin 6) CLKOUT3 (Pin 7) 0 66 MHz 1 33 MHz 3.4. Power Down (PD) or Output Enable (OE) The Si51218 pin 6 can be programmed as PD input. Pin 4 and pin 6 can be programmed as OE input. PD turns off both PLL and output buffers whereas OE only disables the output buffers to Hi-Z. 8 Rev. 1.0 Si51218 4. Pin Descriptions—8-Pin TDFN VDD 1 8 VDDO XOUT 2 7 CLKOUT3 XIN/CLKIN 3 6 CLKOUT1/REFOUT1 FSEL/OE 4 5 Si51218 CLKOUT2/REFOUT2 FSEL/OE/PD# VSS Table 6. Si51218 Pin Descriptions Pin # Name Type Description 1 VDD 2 XOUT O Crystal output. Leave this pin unconnected (floating) if an external clock input is used. 3 XIN/CLKIN I External crystal and clock input. 4 CLKOUT1/REFOUT1/ FSEL/OE I/O 5 VSS GND 6 CLKOUT2/REFOUT2/ FSEL/OE/PD I/O Programmable CLKOUT2 or REFOUT2 output or MultiFunction control input. The frequency at this pin is synthesized by internal PLL if programmed as CLKOUT2. If programmed as REFOUT2, output clock is buffered output of crystal or reference clock input. If programmed as MultiFunction control input, it can be FSEL,OE and PD. It is power by VDDO (pin 8). 7 CLKOUT3 O Programmable CLKOUT3 output. The frequency at this pin is synthesized by internal PLL. It is power by VDDO (pin 8). 8 VDDO PWR 2.5 to 3.3 V power supply. Programmable CLKOUT1 or REFOUT1 output or MultiFunction control input. The frequency at this pin is synthesized by internal PLL if programmed as CLKOUT1. If programmed as REFOUT1, output clock is buffered output of crystal or reference clock input. If programmed as MultiFunction control input, it can be FSEL and OE. Ground. PWR 1.8 to 3.3 V output power supply to CLKOUT2/3 (pin6/7). Rev. 1.0 9 Si51218 5. Ordering Information Part Number Package Type Temperature Si51218-AxxxFM 8-pin TDFN Commercial, 0 to 70 C Si51218-AxxxFMR 8-pin TDFN—Tape and Reel Commercial, 0 to 70 C Si51218 Si 52112 FMR GM2R Axxx Bx F = 0 to +70°C (Operating temp range) M = TDFN, ROHS6, Pb free R = Tape & Reel; (Blank) = Canister Base part number A = Product Revision A xxx = 2nd option code A three character code will be assigned for each configuration 10 Rev. 1.0 Si51218 6. Package Outline: 8-pin TDFN Figure 1. 8-Pin TDFN Package Table 7. Package Diagram Dimensions Dimension A A1 A3 b D D2 e E E2 L aaa bbb ccc ddd eee Min 0.70 0.00 Nom 0.75 0.02 0.20 REF. 0.20 1.60 BSC 1.05 0.40 BSC 1.40 BSC 0.25 0.35 0.10 0.10 0.10 0.07 0.08 0.15 1.00 0.20 0.30 Max 0.80 0.05 0.25 1.10 0.30 0.40 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 11 Si51218 7. PCB Land Pattern: 8-pin TDFN Figure 2. 8-Pin TDFN Land Pattern Table 8. PCB Land Pattern Dimensions (mm) 12 Dimension mm C 1.40 E 0.40 X1 0.75 Y1 0.20 X2 0.25 Y2 1.10 Rev. 1.0 Si51218 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. 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