178-Ball, Single-Channel Mobile LPDDR3 SDRAM

178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
Mobile LPDDR3 SDRAM
EDF8132A1MC, EDFA232A1MA
Features
Options
• VDD1/VDD2/VDDCA/VDDQ: 1.8V/1.2V/1.2V/1.2V
• Array configuration
– 256 Meg x 32 (DDP)
– 512 Meg x 32 (QDP)
• Packaging
– 12.0mm x 11.5mm, 178-ball FBGA package
– 13.0mm x 11.5mm, 178-ball FBGA package
• Operating temperature range
– From –30°C to +85°C
• Ultra-low-voltage core and I/O power supplies
• Frequency range
– 800 MHz (data rate: 1600 Mb/s/pin)
• 8n prefetch DDR architecture
• 8 internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on each CK_t/CK_c
edge
• Bidirectional/differential data strobe per byte of
data (DQS_t/DQS_c)
• Programmable READ and WRITE latencies (RL/WL)
• Burst length: 8
• Per-bank refresh for concurrent operation
• Auto temperature-compensated self refresh
(ATCSR) by built-in temperature sensor
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock-stop capability
• On-die termination (ODT)
• Lead-free (RoHS-compliant) and halogen-free
packaging
Table 1: Configuration Addressing – Single-Channel Package
Architecture
256 Meg x 32
512 Meg x 32
8Gb
16Gb
2
4
Density per package
Die per package
Ranks (CS_n) per channel
Die per rank
Configuration per rank (CS_n)
2
2
CS0_n
1
2
CS1_n
1
2
CS0_n
16 Meg x 32 x 8 banks
32 Meg x 16 x 8 banks x 2
CS1_n
16 Meg x 32 x 8 banks
32 Meg x 16 x 8 banks x 2
16K A[13:0]
16K A[13:0]
CS0_n
1K A[9:0]
2K A[10:0]
CS1_n
1K A[9:0]
2K A[10:0]
Row addressing
Column
addressing/CS_n
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178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
Table 2: Key Timing Parameters
Speed
Grade
Clock Rate
(MHz)
Data Rate
(Mb/s/pin)
WRITE Latency
(Set A)
READ
Latency
GD
800
1600
6
12
Table 3: Part Number Description
Part
Number
Total
Density
Configuration
Ranks
Channels
Package
Size
Ball
Pitch
EDF8132A1MC-GD-F-D
EDF8132A1MC-GD-F-R
8Gb
256 Meg x 32
2
1
12.0mm x 11.5mm
(0.9mm MAX height)
0.80mm
0.65mm
EDFA232A1MA-GD-F-D
EDFA232A1MA-GD-F-R
16Gb
512 Meg x 32
2
1
13.0mm x 11.5mm
(1.1mm MAX height)
0.80mm
0.65mm
Figure 1: Marketing Part Number Chart
E
D
F
81 32
A
1
Micron Technology
(Micron Japan)
MC- GD - F - D
Packing Media
D = Dry Pack (Tray)
R = Tape and Reel
Type
D = Packaged device
Environment Code
Product Family
F = Lead-free (RoHS-compliant)
and halogen-free
F = Mobile LPDDR3 SDRAM
Speed
Density/Chip Select
GD = 1600 Mbps
81 = 8Gb/2-CS
A2 = 16Gb/2-CS
Package
MC = Stacked FBGA
MA = Stacked FBGA
Organization
32 = x32
Revision
Power Supply Interface
A = VDD1 = 1.8V, V DD2 = VDDCA = VDDQ = 1.2V,
S8 device, HSUL_12
Note:
1. The characters highlighted in gray indicate the physical part marking found on the device.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
Contents
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Block Diagrams .................................................................................................................................
Package Dimensions .......................................................................................................................................
178-Ball Package – MR0–MR3, MR5–MR8, MR11 Contents ...............................................................................
IDD Specifications – Dual Die, Single Channel ..................................................................................................
IDD Specifications – Quad Die, Single Channel .................................................................................................
Pin Capacitance .............................................................................................................................................
LPDDR3 Array Configuration ..........................................................................................................................
General Notes ............................................................................................................................................
Functional Description ...................................................................................................................................
Simplified Bus Interface State Diagram ............................................................................................................
Power-Up and Initialization ............................................................................................................................
Voltage Ramp and Device Initialization .......................................................................................................
Initialization After Reset (Without Voltage Ramp) ........................................................................................
Power-Off Sequence .......................................................................................................................................
Uncontrolled Power-Off Sequence ..............................................................................................................
Standard Mode Register Definition ..................................................................................................................
Mode Register Assignments and Definitions ................................................................................................
Commands and Timing ..................................................................................................................................
ACTIVATE Command .....................................................................................................................................
8-Bank Device Operation ............................................................................................................................
Read and Write Access Modes .........................................................................................................................
Burst READ Command ...................................................................................................................................
tDQSCK Delta Timing .................................................................................................................................
Burst WRITE Command ..................................................................................................................................
Write Data Mask .............................................................................................................................................
PRECHARGE Command .................................................................................................................................
Burst READ Operation Followed by PRECHARGE .........................................................................................
Burst WRITE Followed by PRECHARGE .......................................................................................................
Auto Precharge ...........................................................................................................................................
Burst READ with Auto Precharge .................................................................................................................
Burst WRITE with Auto Precharge ...............................................................................................................
REFRESH Command ......................................................................................................................................
REFRESH Requirements .............................................................................................................................
SELF REFRESH Operation ...............................................................................................................................
Partial-Array Self Refresh (PASR) – Bank Masking .........................................................................................
Partial-Array Self Refresh – Segment Masking ..............................................................................................
MODE REGISTER READ .................................................................................................................................
MRR Following Idle Power-Down State ........................................................................................................
Temperature Sensor ...................................................................................................................................
DQ Calibration ...........................................................................................................................................
MODE REGISTER WRITE ................................................................................................................................
MRW RESET Command ..............................................................................................................................
MRW ZQ Calibration Commands ................................................................................................................
ZQ External Resistor Value, Tolerance, and Capacitive Loading .....................................................................
MRW – CA Training Mode ...........................................................................................................................
MRW - Write Leveling Mode ........................................................................................................................
On-Die Termination (ODT) .............................................................................................................................
ODT Mode Register ....................................................................................................................................
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
Asychronous ODT ...................................................................................................................................... 87
ODT During READ Operations (READ or MRR) ............................................................................................ 88
ODT During Power-Down ........................................................................................................................... 88
ODT During Self Refresh ............................................................................................................................. 88
ODT During Deep Power-Down .................................................................................................................. 88
ODT During CA Training and Write Leveling ................................................................................................ 88
Power-Down .................................................................................................................................................. 91
Deep Power-Down ......................................................................................................................................... 97
Input Clock Frequency Changes and Stop Events ............................................................................................. 98
Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 98
Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 99
NO OPERATION Command ............................................................................................................................ 99
Truth Tables .................................................................................................................................................. 100
Absolute Maximum Ratings ........................................................................................................................... 107
Electrical Specifications – IDD Measurements and Conditions ......................................................................... 108
IDD Specifications ...................................................................................................................................... 109
AC and DC Operating Conditions ................................................................................................................... 112
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 113
VREF Tolerances ......................................................................................................................................... 114
Input Signal .............................................................................................................................................. 115
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 117
Single-Ended Requirements for Differential Signals .................................................................................... 118
Differential Input Crosspoint Voltage ......................................................................................................... 119
Input Slew Rate ......................................................................................................................................... 121
Output Characteristics and Operating Conditions ........................................................................................... 122
Single-Ended Output Slew Rate .................................................................................................................. 122
Differential Output Slew Rate ..................................................................................................................... 124
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 126
Output Driver Impedance .............................................................................................................................. 127
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 128
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 128
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 129
ODT Levels and I-V Characteristics ............................................................................................................ 133
Clock Specification ........................................................................................................................................ 134
tCK(abs), tCH(abs), and tCL(abs) ................................................................................................................ 135
Clock Period Jitter .......................................................................................................................................... 135
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 135
Cycle Time Derating for Core Timing Parameters ........................................................................................ 136
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 136
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 136
Clock Jitter Effects on Read Timing Parameters ........................................................................................... 136
Clock Jitter Effects on Write Timing Parameters .......................................................................................... 137
Refresh Requirements .................................................................................................................................... 138
AC Timing ..................................................................................................................................................... 139
CA and CS_n Setup, Hold, and Derating .......................................................................................................... 146
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 153
Revision History ............................................................................................................................................ 160
Rev. D – 9/14 ............................................................................................................................................. 160
Rev. C – 7/14 .............................................................................................................................................. 160
Rev. B – 5/14 .............................................................................................................................................. 160
Rev. A – 3/14 .............................................................................................................................................. 160
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 178-Ball Single-Channel FBGA – 2 x 4Gb Die, 12.0mm x 11.5mm ....................................................... 10
Figure 3: 178-Ball Single-Channel FBGA – 4 x 4Gb Die, 13.0mm x 11.5mm ....................................................... 11
Figure 4: Dual-Rank, Dual-Die, Single-Channel Package Block Diagram .......................................................... 13
Figure 5: Dual-Rank, Quad-Die, Single-Channel Package Block Diagram ......................................................... 14
Figure 6: 178-Ball FBGA (12.0mm x 11.5mm) – EDF8132A1MC ........................................................................ 15
Figure 7: 178-Ball FBGA (13.0mm x 11.5mm) – EDFA232A1MA ........................................................................ 16
Figure 8: Functional Block Diagram ............................................................................................................... 30
Figure 9: Simplified State Diagram ................................................................................................................. 32
Figure 10: Voltage Ramp and Initialization Sequence ...................................................................................... 35
Figure 11: Command and Input Setup and Hold ............................................................................................. 46
Figure 12: CKE Input Setup and Hold ............................................................................................................. 46
Figure 13: ACTIVATE Command .................................................................................................................... 47
Figure 14: tFAW Timing .................................................................................................................................. 48
Figure 15: READ Output Timing ..................................................................................................................... 49
Figure 16: Burst READ – RL = 12, BL = 8, tDQSCK > tCK ................................................................................... 49
Figure 17: Burst READ – RL = 12, BL = 8, tDQSCK < tCK ................................................................................... 50
Figure 18: Burst READ Followed by Burst WRITE – RL = 12, WL = 6, BL = 8 ....................................................... 50
Figure 19: Seamless Burst READ – RL = 6, BL = 8, tCCD = 4 .............................................................................. 51
Figure 20: tDQSCKDL Timing ........................................................................................................................ 52
Figure 21: tDQSCKDM Timing ....................................................................................................................... 53
Figure 22: tDQSCKDS Timing ......................................................................................................................... 54
Figure 23: Data Input (WRITE) Timing ........................................................................................................... 55
Figure 24: Burst WRITE ................................................................................................................................. 56
Figure 25: Method for Calculating tWPRE Transitions and Endpoints ............................................................... 56
Figure 26: Method for Calculating tWPST Transitions and Endpoints ............................................................... 57
Figure 27: Burst WRITE Followed by Burst READ ............................................................................................ 57
Figure 28: Seamless Burst WRITE – WL = 4, BL = 8, tCCD = 4 ............................................................................ 58
Figure 29: Data Mask Timing ......................................................................................................................... 59
Figure 30: Write Data Mask – Second Data Bit Masked .................................................................................... 59
Figure 31: Burst READ Followed by PRECHARGE – BL = 8, RU(tRTP(MIN)/tCK) = 2 ........................................... 61
Figure 32: Burst WRITE Followed by PRECHARGE – BL = 8 .............................................................................. 62
Figure 33: LPDDR3 – Burst READ with Auto Precharge .................................................................................... 63
Figure 34: Burst WRITE with Auto Precharge – BL = 8 ...................................................................................... 64
Figure 35: REFRESH Command Timing .......................................................................................................... 68
Figure 36: Postponing REFRESH Commands .................................................................................................. 68
Figure 37: Pulling In REFRESH Commands .................................................................................................... 68
Figure 38: All-Bank REFRESH Operation ........................................................................................................ 70
Figure 39: Per-Bank REFRESH Operation ....................................................................................................... 70
Figure 40: SELF REFRESH Operation .............................................................................................................. 72
Figure 41: MRR Timing .................................................................................................................................. 74
Figure 42: READ to MRR Timing .................................................................................................................... 75
Figure 43: Burst WRITE Followed by MRR ...................................................................................................... 75
Figure 44: MRR After Idle Power-Down Exit .................................................................................................... 76
Figure 45: Temperature Sensor Timing ........................................................................................................... 77
Figure 46: MR32 and MR40 DQ Calibration Timing ......................................................................................... 78
Figure 47: MODE REGISTER WRITE Timing ................................................................................................... 79
Figure 48: MODE REGISTER WRITE Timing for MRW RESET .......................................................................... 80
Figure 49: ZQ Timings ................................................................................................................................... 82
Figure 50: CA Training Timing ....................................................................................................................... 83
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178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
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Figure 91:
Write-Leveling Timing ................................................................................................................... 86
Functional Representation of On-Die Termination .......................................................................... 87
Asynchronous ODT Timing – RL = 12 ............................................................................................. 89
Automatic ODT Timing During READ Operation – RL = m ............................................................... 90
ODT Timing During Power-Down, Self Refresh, Deep Power-Down Entry/Exit ................................. 90
Power-Down Entry and Exit Timing ................................................................................................ 92
CKE Intensive Environment ........................................................................................................... 92
REFRESH to REFRESH Timing in CKE Intensive Environments ....................................................... 93
READ to Power-Down Entry ........................................................................................................... 93
READ with Auto Precharge to Power-Down Entry ............................................................................ 94
WRITE to Power-Down Entry ......................................................................................................... 94
WRITE with Auto Precharge to Power-Down Entry .......................................................................... 95
REFRESH Command to Power-Down Entry .................................................................................... 95
ACTIVATE Command to Power-Down Entry ................................................................................... 96
PRECHARGE Command to Power-Down Entry ............................................................................... 96
MRR Power-Down Entry ................................................................................................................ 97
MRW Command to Power-Down Entry .......................................................................................... 97
Deep Power-Down Entry and Exit Timing ....................................................................................... 98
V REF DC Tolerance and V REF AC Noise Limits ................................................................................. 114
LPDDR3-1600 to LPDDR3-1333 Input Signal ................................................................................. 115
LPDDR3-2133 to LPDDR3-1866 Input Signal ................................................................................. 116
Differential AC Swing Time and tDVAC .......................................................................................... 117
Single-Ended Requirements for Differential Signals ....................................................................... 118
V IX Definition ............................................................................................................................... 120
Differential Input Slew Rate Definition for CK and DQS .................................................................. 121
Single-Ended Output Slew Rate Definition ..................................................................................... 123
Differential Output Slew Rate Definition ........................................................................................ 124
Overshoot and Undershoot Definition ........................................................................................... 125
HSUL_12 Driver Output Reference Load for Timing and Slew Rate ................................................. 126
Output Driver ............................................................................................................................... 127
Output Impedance = 240Ω, I-V Curves After ZQRESET ................................................................... 131
Output Impedance = 240Ω, I-V Curves After Calibration ................................................................. 132
ODT Functional Block Diagram .................................................................................................... 133
Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock ................................................. 149
Typical Slew Rate – tIH for CA and CS_n Relative to Clock ............................................................... 150
Tangent Line – tIS for CA and CS_n Relative to Clock ...................................................................... 151
Tangent Line – tIH for CA and CS_n Relative to Clock ..................................................................... 152
Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe ............................................................. 156
Typical Slew Rate – tDH for DQ Relative to Strobe ........................................................................... 157
Tangent Line – tDS for DQ with Respect to Strobe .......................................................................... 158
Tangent Line – tDH for DQ with Respect to Strobe .......................................................................... 159
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
List of Tables
Table 1: Configuration Addressing – Single-Channel Package ............................................................................ 1
Table 2: Key Timing Parameters ....................................................................................................................... 2
Table 3: Part Number Description .................................................................................................................... 2
Table 4: Ball/Pad Descriptions ....................................................................................................................... 12
Table 5: Mode Register Contents .................................................................................................................... 17
Table 6: IDD Specifications ............................................................................................................................. 19
Table 7: IDD6 Partial-Array Self Refresh Current at 45°C .................................................................................... 22
Table 8: IDD6 Partial-Array Self Refresh Current at 85°C .................................................................................... 22
Table 9: IDD Specifications ............................................................................................................................. 23
Table 10: IDD6 Partial-Array Self Refresh Current at 45°C .................................................................................. 26
Table 11: IDD6 Partial-Array Self Refresh Current at 85°C .................................................................................. 26
Table 12: Input/Output Capacitance .............................................................................................................. 27
Table 13: AC Timing Addendum for ODT ........................................................................................................ 27
Table 14: Voltage Ramp Conditions ................................................................................................................ 33
Table 15: Initialization Timing Parameters ...................................................................................................... 35
Table 16: Power Supply Conditions ................................................................................................................ 36
Table 17: Power-Off Timing ............................................................................................................................ 36
Table 18: Mode Register Assignments ............................................................................................................. 37
Table 19: MR0 Device Feature 0 (MA[7:0] = 00h) .............................................................................................. 38
Table 20: MR0 Op-Code BIt Definitions .......................................................................................................... 38
Table 21: MR1 Device Feature 1 (MA[7:0] = 01h) .............................................................................................. 39
Table 22: MR1 Op-Code Bit Definitions .......................................................................................................... 39
Table 23: Burst Sequence ............................................................................................................................... 39
Table 24: MR2 Device Feature 2 (MA[7:0] = 02h) .............................................................................................. 39
Table 25: MR2 Op-Code Bit Definitions .......................................................................................................... 40
Table 26: LPDDR3 READ and WRITE Latency ................................................................................................. 40
Table 27: MR3 I/O Configuration 1 (MA[7:0] = 03h) ......................................................................................... 41
Table 28: MR3 Op-Code Bit Definitions .......................................................................................................... 41
Table 29: MR4 Device Temperature (MA[7:0] = 04h) ........................................................................................ 41
Table 30: MR4 Op-Code Bit Definitions .......................................................................................................... 41
Table 31: MR5 Basic Configuration 1 (MA[7:0] = 05h) ...................................................................................... 42
Table 32: MR5 Op-Code Bit Definitions .......................................................................................................... 42
Table 33: MR6 Basic Configuration 2 (MA[7:0] = 06h) ...................................................................................... 42
Table 34: MR6 Op-Code Bit Definitions .......................................................................................................... 42
Table 35: MR7 Basic Configuration 3 (MA[7:0] = 07h) ...................................................................................... 42
Table 36: MR7 Op-Code Bit Definitions .......................................................................................................... 42
Table 37: MR8 Basic Configuration 4 (MA[7:0] = 08h) ...................................................................................... 42
Table 38: MR8 Op-Code Bit Definitions .......................................................................................................... 43
Table 39: MR9 Test Mode (MA[7:0] = 09h) ....................................................................................................... 43
Table 40: MR10 Calibration (MA[7:0] = 0Ah) ................................................................................................... 43
Table 41: MR10 Op-Code Bit Definitions ........................................................................................................ 43
Table 42: MR11 ODT Control (MA[7:0] = 0Bh) ................................................................................................. 44
Table 43: MR11 Op-Code Bit Definitions ........................................................................................................ 44
Table 44: MR16 PASR Bank Mask (MA[7:0] = 010h) .......................................................................................... 44
Table 45: MR16 Op-Code Bit Definitions ........................................................................................................ 44
Table 46: MR17 PASR Segment Mask (MA[7:0] = 011h) .................................................................................... 44
Table 47: MR17 PASR Segment Mask Definitions ............................................................................................ 44
Table 48: MR17 PASR Row Address Ranges in Masked Segments ...................................................................... 45
Table 49: MR63 RESET (MA[7:0] = 3Fh) – MRW Only ....................................................................................... 45
Table 50: Reserved Mode Registers ................................................................................................................. 45
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
Table 51: Bank Selection for PRECHARGE by Address Bits ............................................................................... 60
Table 52: PRECHARGE and Auto Precharge Clarification ................................................................................. 65
Table 53: REFRESH Command Scheduling Separation Requirements .............................................................. 67
Table 54: Bank- and Segment-Masking Example ............................................................................................. 73
Table 55: Temperature Sensor Definitions and Operating Conditions .............................................................. 76
Table 56: Data Calibration Pattern Description ............................................................................................... 78
Table 57: Truth Table for MRR and MRW ........................................................................................................ 79
Table 58: CA Training Mode Enable (MR41 (29H, 0010 1001b), OP = A4H (1010 0100b)) .................................... 84
Table 59: CA Training Mode Disable (MR42 (2AH, 0010 1010b), OP = A8H(1010 1000b)) .................................... 84
Table 60: CA to DQ Mapping (CA Training Mode Enabled with MR41) ............................................................. 84
Table 61: CA Training Mode Enable (MR48 (30H, 0011 0000b), OP = C0H (1100 0000b)) .................................... 85
Table 62: CA to DQ Mapping (CA Training Mode Enabled with MR48) ............................................................. 85
Table 63: DRAM Termination Function in Write-Leveling Mode ...................................................................... 89
Table 64: ODT States Truth Table ................................................................................................................... 89
Table 65: Command Truth Table ................................................................................................................... 100
Table 66: CKE Truth Table ............................................................................................................................. 101
Table 67: Current State Bank n to Command to Bank n Truth Table ................................................................ 102
Table 68: Current State Bank n to Command to Bank m Truth Table ............................................................... 104
Table 69: DM Truth Table .............................................................................................................................. 107
Table 70: Absolute Maximum DC Ratings ...................................................................................................... 107
Table 71: Switching for CA Input Signals ........................................................................................................ 108
Table 72: Switching for IDD4R ......................................................................................................................... 108
Table 73: Switching for IDD4W ........................................................................................................................ 109
Table 74: IDD Specification Parameters and Operating Conditions .................................................................. 110
Table 75: Recommended DC Operating Conditions ....................................................................................... 112
Table 76: Input Leakage Current ................................................................................................................... 112
Table 77: Operating Temperature Range ........................................................................................................ 112
Table 78: Single-Ended AC and DC Input Levels for CA and CS_n Inputs ......................................................... 113
Table 79: Single-Ended AC and DC Input Levels for CKE ................................................................................ 113
Table 80: Single-Ended AC and DC Input Levels for DQ and DM ..................................................................... 113
Table 81: Differential AC and DC Input Levels ................................................................................................ 117
Table 82: CK and DQS Time Requirements Before Ringback ( tDVAC) .............................................................. 118
Table 83: Single-Ended Levels for CK and DQS .............................................................................................. 119
Table 84: Crosspoint Voltage for Differential Input Signals (CK, CK_c, DQS_t, DQS_c) ..................................... 120
Table 85: Differential Input Slew Rate Definition ............................................................................................ 121
Table 86: Single-Ended AC and DC Output Levels .......................................................................................... 122
Table 87: Differential AC and DC Output Levels ............................................................................................. 122
Table 88: Single-Ended Output Slew Rate Definition ...................................................................................... 122
Table 89: Single-Ended Output Slew Rate ...................................................................................................... 123
Table 90: Differential Output Slew Rate Definition ......................................................................................... 124
Table 91: Differential Output Slew Rate ......................................................................................................... 124
Table 92: AC Overshoot/Undershoot Specification ......................................................................................... 125
Table 93: Output Driver DC Electrical Characteristics with ZQ Calibration ...................................................... 128
Table 94: Output Driver Sensitivity Definition ................................................................................................ 128
Table 95: Output Driver Temperature and Voltage Sensitivity ......................................................................... 129
Table 96: Output Driver DC Electrical Characteristics Without ZQ Calibration ................................................ 129
Table 97: I-V Curves ..................................................................................................................................... 129
Table 98: ODT DC Electrical Characteristics (RZQ Ω After Proper ZQ Calibration) ..................................... 133
Table 99: Definitions and Calculations .......................................................................................................... 134
Table 100: tCK(abs), tCH(abs), and tCL(abs) Definitions ................................................................................. 135
Table 101: Refresh Requirement Parameters (Per Density) .............................................................................. 138
Table 102: AC Timing .................................................................................................................................... 139
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Features
Table 103:
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Table 105:
Table 106:
Table 107:
Table 108:
Table 109:
Table 110:
Table 111:
CA Setup and Hold Base Values ..................................................................................................... 146
CS_n Setup and Hold Base Values ................................................................................................. 147
Derating Values for AC/DC-Based tIS/tIH (AC150) ......................................................................... 147
Derating Values for AC/DC-Based tIS/tIH (AC135) ......................................................................... 147
Required Time for Valid Transition – tVAC > V IH(AC) and < V IL(AC) ..................................................... 148
Data Setup and Hold Base Values .................................................................................................. 154
Derating Values for AC/DC-Based tDS/tDH (AC150) ....................................................................... 154
Derating Values for AC/DC-Based tDS/tDH (AC135) ....................................................................... 154
Required Time for Valid Transition – tVAC > V IH(AC) or < V IL(AC) ....................................................... 155
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9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Ball Assignments
Ball Assignments
Figure 2: 178-Ball Single-Channel FBGA – 2 x 4Gb Die, 12.0mm x 11.5mm
1
2
3
4
5
6
NU
NU
VDD1
VDD1
VDD1
NU
VSS
ZQ
NC
CA9
VSSCA
CA8
7
8
9
10
11
12
13
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
VSS
VSSQ
DQ31
DQ30
DQ29
DQ28
VSSQ
NU
NC
VSS
VSSQ
DQ27
DQ26
DQ25
DQ24
VDDQ
VSSCA
VDD2
VDD2
VDD2
DM3
DQ15 DQS3_t DQS3_c
VSSQ
CA7
CA6
VSS
VSS
VSSQ
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
VSSCA
VSS
VSSQ
DQ11
DQ10
DQ9
DQ8
VSSQ
VDDCA
VSSCA
VSSCA
VDD2
VSSQ
DM1
VSSQ
VDDCA VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSSQ
VDDQ
VDD2
A
B
C
D
E
F
G
DQS1_t DQS1_c VDDQ
H
VSS
J
CK_c
CK_t
VSSCA
VDD2
VDD2
ODT
VDDQ
VDDQ
VREFDQ
VSS
VSS
CKE0
CKE1
VDD2
VDD2
VDDQ
NC
VSSQ
VDDQ
VDD2
VDDCA
CS0_n
CS1_n
VDD2
VSS
DM0
VSSQ
VDDCA
CA4
VSSCA
VSS
VSSQ
DQ4
DQ5
DQ6
DQ7
VSSQ
CA2
CA3
VSS
VSS
VSSQ
VDDQ
DQ1
DQ2
DQ3
VDDQ
CA1
VSSCA
VDD2
VDD2
VDD2
DM2
DQ0
CA0
NC
VSS
VSS
VSSQ
DQ20
DQ21
DQ22
DQ23
VDDQ
NU
VSS
VSS
VSS
VSS
VSSQ
DQ16
DQ17
DQ18
DQ19
VSSQ
NU
NU
NU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
K
L
DQS0_t DQS0_c VDDQ
M
N
P
DQS2_t DQS2_c
VSSQ
R
T
U
(Top view)
PDF: 09005aef858e9dd3
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Ball Descriptions
Figure 3: 178-Ball Single-Channel FBGA – 4 x 4Gb Die, 13.0mm x 11.5mm
1
2
3
4
5
6
NU
NU
VDD1
VDD1
VDD1
NU
VSS
ZQ0
ZQ1
CA9
VSSCA
CA8
7
8
9
10
11
12
13
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
VSS
VSSQ
DQ31
DQ30
DQ29
DQ28
VSSQ
NU
NC
VSS
VSSQ
DQ27
DQ26
DQ25
DQ24
VDDQ
VSSCA
VDD2
VDD2
VDD2
DM3
DQ15 DQS3_t DQS3_c
VSSQ
CA7
CA6
VSS
VSS
VSSQ
VDDQ
DQ14
DQ13
DQ12
VDDQ
VDDCA
CA5
VSSCA
VSS
VSSQ
DQ11
DQ10
DQ9
DQ8
VSSQ
VDDCA
VSSCA
VSSCA
VDD2
VSSQ
DM1
VSSQ
VDDCA VREFCA
VDD2
VDD2
VDDQ
VDDQ
VSSQ
VDDQ
VDD2
A
B
C
D
E
F
G
DQS1_t DQS1_c VDDQ
H
VSS
J
CK_c
CK_t
VSSCA
VDD2
VDD2
ODT
VDDQ
VDDQ
VREFDQ
VSS
VSS
CKE0
CKE1
VDD2
VDD2
VDDQ
NC
VSSQ
VDDQ
VDD2
VDDCA
CS0_n
CS1_n
VDD2
VSS
DM0
VSSQ
VDDCA
CA4
VSSCA
VSS
VSSQ
DQ4
DQ5
DQ6
DQ7
VSSQ
CA2
CA3
VSS
VSS
VSSQ
VDDQ
DQ1
DQ2
DQ3
VDDQ
CA1
VSSCA
VDD2
VDD2
VDD2
DM2
DQ0
CA0
NC
VSS
VSS
VSSQ
DQ20
DQ21
DQ22
DQ23
VDDQ
NU
VSS
VSS
VSS
VSS
VSSQ
DQ16
DQ17
DQ18
DQ19
VSSQ
NU
NU
NU
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD1
VDDQ
NU
NU
K
L
DQS0_t DQS0_c VDDQ
M
N
P
DQS2_t DQS2_c
VSSQ
R
T
U
(Top view)
Ball Descriptions
The ball/pad description table below is a comprehensive list of signals for the device
family. All signals listed may not be supported on this device. See Ball Assignments for
information specific to this device.
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178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Ball Descriptions
Table 4: Ball/Pad Descriptions
Symbol
Type
Description
CA[9:0]
Input
Command/address inputs: Provide the command and address inputs according to the
command truth table.
CK_t, CK_c
Input
Clock: Differential clock inputs. All CA inputs are sampled on both rising and falling
edges of CK. CS and CKE inputs are sampled at the rising edge of CK. AC timings are referenced to clock.
CKE[1:0]
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is considered part of the command code. CKE is sampled on the rising edge of
CK.
CS[1:0]_n
Input
Chip select: Considered part of the command code and is sampled on the rising edge of
CK.
DM[3:0]
Input
Input data mask: Input mask signal for write data. Although DM balls are input-only,
the DM loading is designed to match that of DQ and DQS balls. DM[3:0] is DM for each of
the four data bytes, respectively.
ODT
Input
On-die termination: Enables and disables termination on the DRAM DQ bus according
to the specified mode register settings. For packages that do not support ODT, the ODT
signal may be grounded internally.
DQ[31:0]
I/O
Data input/output: Bidirectional data bus.
DQS[3:0]_t,
DQS[3:0]_c
I/O
Data strobe: Bidirectional (used for read and write data) and complementary (DQS_t
and DQS_c). It is edge-aligned output with read data and centered input with write data.
DQS[3:0]_t/DQS[3:0]_c is DQS for each of the four data bytes, respectively.
VDDQ
Supply
DQ power supply: Isolated on the die for improved noise immunity.
VSSQ
Supply
DQ ground: Isolated on the die for improved noise immunity.
VDDCA
Supply
Command/address power supply: Command/address power supply.
VSSCA
Supply
Command/address ground: Isolated on the die for improved noise immunity.
VDD1
Supply
Core power: Supply 1.
VDD2
Supply
Core power: Supply 2.
VSS
Supply
Common ground.
VREFCA, VREFDQ
Supply
Reference voltage: VREFCA is reference for command/address input buffers, VREFDQ is reference for DQ input buffers.
ZQ[1:0]
Reference
NU
–
Not usable: Do not connect.
NC
–
No connect: Not internally connected.
(NC)
–
No connect: Balls indicated as (NC) are no connects; however, they could be connected
together internally.
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
12
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Block Diagrams
Package Block Diagrams
Figure 4: Dual-Rank, Dual-Die, Single-Channel Package Block Diagram
VDD1 VDD2 VDDQVDDCA VSS VSSCA VSSQ
VREFCA
VREFDQ
CS1_n
CKE1
ZQ
CS0_n
RZQ
CKE0
CK_t
CK_c
DM[3:0]
LPDDR3
LPDDR3
Die 0
Die 1
CA[9:0]
ODT
PDF: 09005aef858e9dd3
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ODT
13
DQ[31:0], DQS[3:0]_t,
DQS[3:0]_c
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Block Diagrams
Figure 5: Dual-Rank, Quad-Die, Single-Channel Package Block Diagram
VDD1 VDD2 VDDQ VDDCA VSS VSSCA VSSQ
VREFCA
VREFDQ
ODT
ODT
LPDDR3
Die 0
CS1_n
CKE1
DM[1:0]
LPDDR3
Die 1
DM[3:2]
x16
DQ[15:0]
CK_t
x16
DQ[31:16]
CK_c
DM[3:0]
CA[9:0]
x16
DQ[31:16]
x16
DQ[15:0]
DM[1:0]
CKE0
CS0_n
ODT
Note:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
RZQ1
ZQ1
DQ[31:16],
DQS[3:2]_t, DQS[3:2]_c
DQ[15:0],
DQS[1:0]_t, DQS[1:0]_c
ZQ0
RZQ0
DM[3:2]
LPDDR3
Die 3
LPDDR3
Die 2
ODT
ODT
1. The ODT input is connected to rank 0. The ODT input to rank 1 is connected to VSS in the
package.
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Dimensions
Package Dimensions
Figure 6: 178-Ball FBGA (12.0mm x 11.5mm) – EDF8132A1MC
12.00 ±0.10
0.15 S B
11.50 ±0.10
Index mark
0.15 S A
0.80 ±0.10
0.10 S
S
0.08 S
0.22 ±0.05
178- 0.30 ±0.05
0.08 M S A B
0.65
B
10.40
A
Index mark
0.80
0.80
9.60
Notes:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
1. Package drawing: ECA-TS2-0457-01.
2. All dimensions are in millimeters.
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Package Dimensions
Figure 7: 178-Ball FBGA (13.0mm x 11.5mm) – EDFA232A1MA
13.00 ±0.10
0.15 S B
11.50 ±0.10
Index mark
0.15 S A
0.10 S
1.03 ±0.07
S
0.08 S
0.22 ±0.05
0.08 M S A B
178- 0.30 ±0.05
0.65
B
10.40
A
Index mark
0.80
0.80
9.60
Notes:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
1. Package drawing: ECA-TS2-0481-01.
2. All dimensions are in millimeters.
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
178-Ball Package – MR0–MR3, MR5–MR8, MR11 Contents
178-Ball Package – MR0–MR3, MR5–MR8, MR11 Contents
Table 5: Mode Register Contents
Part Number
Total
Density
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
MR0
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
OP6 = 0b indicates no support for WL set B
OP7 = 0b indicates that the option for RL3 is not supported
OP6 and OP7 = 0b for this package
MR1
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
OP[7:5] If nWRE (in MR2) = 0
100b: nWR = 6
110b: nWR = 8 (default)
111b: nWR = 9
If nWRE = 1
000b: nWR =10
001b: nWR = 11
010b: nWR =12
All others: Reserved
MR2
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
OP[3:0] RL and WL
0100b: RL = 6: WL = 3
0110b: RL = 8; WL = 4 (default)
0111b: RL = 9; WL = 5
1000b: RL = 10; WL = 6
1001b: RL = 11; WL = 6
1010b: RL = 12; WL = 6
All others: Reserved
OP4 nWRE
0b: Enable nWR programming ≤ 9 (default)
1b: Enable nWRE programming > 9
OP6 WL select
0b: Select WL Set A (default)
1b: Reserved
OP7 Write leveling
0b: Write leveling mode disabled (default)
1b: Write leveling mode enabled
MR3
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
OP[3:0] DS
0000b: Reserved
0001b: 34.3 Ohms TYP
0010b: 40 Ohms TYP (default)
0011b: 48 Ohms TYP
All others: Reserved
MR5
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
178-Ball Package – MR0–MR3, MR5–MR8, MR11 Contents
Table 5: Mode Register Contents (Continued)
Part Number
Total
Density
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Manufacturer ID = 0000 0011b:
MR6
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
Revision ID1 = 0000 00000b: Revision A
MR7
EDF8132A1MC
8Gb
Revision ID2 = (RFU)
EDFA232A1MA
16Gb
MR8
I/O Width/CS_n
CS0_n
CS1_n
Density
Type
EDF8132A1MC
8Gb
00b: x32
00b: x32
0110b: 4Gb
11b: S8
EDFA232A1MA
16Gb
01b: x16
01b: x16
0110b: 4Gb
11b: S8
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
OP[1:0]
DQ ODT
00b; Disabled (default)
01b: Reserved
10b: RZQ/2
11b: RZQ/1
MR11
OP2 PD control (power-down control)
0b: ODT disabled by DRAM during power-down
1b: ODT enabled by DRAM during power-down
Note:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
1. The contents of MR0–MR3, MR5–MR8, and MR11 will reflect information specific to
each in these packages.
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Dual Die, Single Channel
IDD Specifications – Dual Die, Single Channel
Table 6: IDD Specifications
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C
Speed
Symbol
Supply
1600
1333
Unit
Parameter/Condition
IDD01
VDD1
8.0
8.0
mA
IDD02
VDD2
60
60
IDD0,in
VDDCA + VDDQ
3.0
3.0
One device in operating one bank active-precharge,
Another in deep power-down;
tCK = tCK(avg) MIN; tRC = tRC (MIN); CKE is HIGH; CS_n
is HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
IDD2P1
VDD1
0.8
0.8
IDD2P2
VDD2
1.8
1.8
IDD2P,in
VDDCA + VDDQ
0.2
0.2
IDD2PS1
VDD1
0.8
0.8
IDD2PS2
VDD2
1.8
1.8
IDD2PS,in
VDDCA + VDDQ
0.2
0.2
IDD2N1
VDD1
0.8
0.8
IDD2N2
VDD2
26
22
IDD2N,in
VDDCA + VDDQ
6.0
6.0
IDD2NS1
VDD1
0.8
0.8
IDD2NS2
VDD2
8.0
8.0
IDD2NS,in
VDDCA + VDDQ
6.0
6.0
VDD1
1.4
1.4
IDD3P1
IDD3P2
VDD2
11
11
IDD3P,in
VDDCA + VDDQ
0.2
0.2
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
mA
All devices in idle power-down standby current
= tCK(avg) MIN; CKE is LOW; CS_n is HIGH;
All banks idle; CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
tCK
mA
All devices in idle power-down standby current with
clock stop
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in idle non power-down standby current
tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in idle non power-down standby current
with clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in active power-down standby current
= tCK(avg) MIN; CKE is LOW;
CS_n is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
tCK
19
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Dual Die, Single Channel
Table 6: IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C
Speed
Symbol
IDD3PS1
Supply
1600
1333
Unit
Parameter/Condition
VDD1
1.4
1.4
mA
All devices in active power-down standby current with
clock stop
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in active non power-down standby current
tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in active non power-down standby current
with clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
One device in operating burst read,
Another in deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CS_n is HIGH between valid commands;
One bank active; BL = 8; RL = RL (MIN);
CA bus inputs are SWITCHING;
50% data change each burst transfer;
ODT is disabled
mA
One device in operating burst write,
Another in deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CS_n is HIGH between valid commands;
One bank active; BL = 8; WL = WL (MIN);
CA bus inputs are SWITCHING;
50% data change each burst transfer;
ODT is disabled
IDD3PS2
VDD2
11
11
IDD3PS,in
VDDCA + VDDQ
0.2
0.2
IDD3N1
VDD1
2.0
2.0
IDD3N2
VDD2
34
30
IDD3N,in
VDDCA + VDDQ
6.0
6.0
IDD3NS1
VDD1
2.0
2.0
IDD3NS2
VDD2
16
16
IDD3NS,in
VDDCA + VDDQ
6.0
6.0
IDD4R1
VDD1
2.0
2.0
IDD4R2
VDD2
230
200
IDD4R,in
VDDCA
3.0
3.0
IDD4W1
VDD1
2.0
2.0
IDD4W2
VDD2
240
210
IDD4W,in
VDDCA + VDDQ
3.0
3.0
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178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Dual Die, Single Channel
Table 6: IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C
Speed
Symbol
IDD51
Supply
1600
1333
Unit
Parameter/Condition
VDD1
28
28
mA
One device in all bank auto-refresh,
Another in deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CKE is HIGH between valid commands;
tRC = tRFCab (MIN); Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
One device in all bank auto-refresh,
Another in deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CKE is HIGH between valid commands;
tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
One device in per bank auto-refresh,
Another in deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CKE is HIGH between valid commands;
tRC = tREFIpb;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
μA
All devices in deep power-down
CK_t = LOW, CK _c = HIGH; CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
IDD52
VDD2
150
150
IDD5,in
VDDCA + VDDQ
3.0
3.0
IDD5AB1
VDD1
2.0
2.0
IDD5AB2
VDD2
18
16
IDD5AB,in
VDDCA + VDDQ
3.0
3.0
IDD5PB1
VDD1
2.0
2.0
IDD5PB2
VDD2
18
16
IDD5PB,in
VDDCA + VDDQ
3.0
3.0
IDD81
VDD1
32
32
IDD82
VDD2
12
12
IDD8,in
VDDCA + VDDQ
24
24
Notes:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Dual Die, Single Channel
Table 7: IDD6 Partial-Array Self Refresh Current at 45°C
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
Unit
Full array
1/2 array
1/4 array
1/8 array
VDD1
460
VDD2
1760
VDDCA + VDDQ
20
VDD1
300
VDD2
1000
VDDCA + VDDQ
20
VDD1
220
VDD2
600
VDDCA + VDDQ
20
VDD1
180
VDD2
420
VDDCA + VDDQ
20
Note:
μA
Parameter/Condition
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
1. IDD6 45°C is the typical of the distribution of the arithmetic mean.
Table 8: IDD6 Partial-Array Self Refresh Current at 85°C
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
Unit
Full array
1/2 array
1/4 array
1/8 array
VDD1
1900
VDD2
6000
VDDCA + VDDQ
24
VDD1
1500
VDD2
3600
VDDCA + VDDQ
24
VDD1
1300
VDD2
2600
VDDCA + VDDQ
24
VDD1
1200
VDD2
2000
VDDCA + VDDQ
24
Note:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
μA
Parameter/Condition
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
1. IDD6 85°C is the maximum of the distribution of the arithmetic mean.
22
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Quad Die, Single Channel
IDD Specifications – Quad Die, Single Channel
Table 9: IDD Specifications
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C
Speed
Symbol
Supply
1600
1333
Unit
Parameter/Condition
IDD01
VDD1
16
16
mA
IDD02
VDD2
120
120
IDD0,in
VDDCA + VDDQ
6.0
6.0
Two devices in operating one bank active-precharge,
Two devices in deep power-down
tCK = tCK(avg) MIN;tRC = tRC (MIN); CKE is HIGH; CS_n is
HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
IDD2P1
VDD1
1.6
1.6
mA
All devices in idle power-down standby current tCK =
MIN; CKE is LOW; CS_n is HIGH;
All banks idle; CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
IDD2P2
VDD2
3.6
3.6
IDD2P,in
VDDCA + VDDQ
0.4
0.4
IDD2PS1
VDD1
1.6
1.6
IDD2PS2
VDD2
3.6
3.6
IDD2PS,in
VDDCA + VDDQ
0.4
0.4
IDD2N1
VDD1
1.6
1.6
IDD2N2
VDD2
52
44
IDD2N,in
VDDCA + VDDQ
12
12
IDD2NS1
VDD1
1.6
1.6
IDD2NS2
VDD2
16
16
IDD2NS,in
VDDCA + VDDQ
12
12
VDD1
2.8
2.8
IDD3P1
IDD3P2
VDD2
22
22
IDD3P,in
VDDCA + VDDQ
0.4
0.4
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
tCK(avg)
mA
All devices in idle power-down standby current with
clock stop
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in idle non power-down standby current
tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in idle non power-down standby current
with clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in active power-down standby current
= tCK(avg) MIN; CKE is LOW;
CS_n is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
tCK
23
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Quad Die, Single Channel
Table 9: IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C
Speed
Symbol
IDD3PS1
Supply
1600
1333
Unit
Parameter/Condition
VDD1
2.8
2.8
mA
All devices in active power-down standby current with
clock stop
CK_t = LOW, CK_c = HIGH; CKE is LOW;
CS_n is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in active non power-down standby current
tCK = tCK(avg) MIN; CKE is HIGH;
CS_n is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
All devices in active non power-down standby current
with clock stop
CK_t = LOW, CK_c = HIGH; CKE is HIGH;
CS_n is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
mA
Two devices in operating burst read, Two devices in
deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CS_n is HIGH between valid commands;
One bank active; BL = 8; RL = RL (MIN);
CA bus inputs are SWITCHING;
50% data change each burst transfer;
ODT is disabled
mA
Two devices in operating burst write, Two devices in
deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CS_n is HIGH between valid commands;
One bank active; BL = 8; WL = WL (MIN);
CA bus inputs are SWITCHING;
50% data change each burst transfer;
ODT is disabled
IDD3PS2
VDD2
22
22
IDD3PS,in
VDDCA + VDDQ
0.4
0.4
IDD3N1
VDD1
4.0
4.0
IDD3N2
VDD2
68
60
IDD3N,in
VDDCA + VDDQ
12
12
IDD3NS1
VDD1
4.0
4.0
IDD3NS2
VDD2
32
32
IDD3NS,in
VDDCA + VDDQ
12
12
IDD4R1
VDD1
4.0
4.0
IDD4R2
VDD2
340
300
IDD4R,in
VDDCA
6.0
6.0
IDD4W1
VDD1
4.0
4.0
IDD4W2
VDD2
360
320
IDD4W,in
VDDCA + VDDQ
6.0
6.0
PDF: 09005aef858e9dd3
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24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Quad Die, Single Channel
Table 9: IDD Specifications (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –30°C to +85°C
Speed
Symbol
IDD51
Supply
1600
1333
Unit
Parameter/Condition
VDD1
56
56
mA
Two devices in all bank auto-refresh, Two devices in
deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CKE is HIGH between valid commands;
tRC = tRFCab (MIN); Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
Two devices in all bank auto-refresh, Two devices in
deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CKE is HIGH between valid commands;
tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
mA
Two devices in per bank auto-refresh, Two devices in
deep power-down
Conditions for operating devices are:
tCK = tCK(avg) MIN; CKE is HIGH between valid commands;
tRC = tREFIpb;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
ODT is disabled
μA
All devices in deep power-down
CK_t = LOW, CK _c = HIGH; CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
IDD52
VDD2
300
300
IDD5,in
VDDCA + VDDQ
6.0
6.0
IDD5AB1
VDD1
4.0
4.0
IDD5AB2
VDD2
36
32
IDD5AB,in
VDDCA + VDDQ
6.0
6.0
IDD5PB1
VDD1
4.0
4.0
IDD5PB2
VDD2
36
32
IDD5PB,in
VDDCA + VDDQ
6.0
6.0
IDD81
VDD1
64
64
IDD82
VDD2
24
24
IDD8,in
VDDCA + VDDQ
48
48
Notes:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
1. Published IDD values are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
IDD Specifications – Quad Die, Single Channel
Table 10: IDD6 Partial-Array Self Refresh Current at 45°C
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
Unit
Full array
1/2 array
1/4 array
1/8 array
VDD1
920
VDD2
3520
VDDCA + VDDQ
40
VDD1
600
VDD2
2000
VDDCA + VDDQ
40
VDD1
440
VDD2
1200
VDDCA + VDDQ
40
VDD1
360
VDD2
840
VDDCA + VDDQ
40
Note:
μA
Parameters/Conditions
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
1. IDD6 45°C is the typical of the distribution of the arithmetic mean.
Table 11: IDD6 Partial-Array Self Refresh Current at 85°C
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
PASR
Supply
Value
Unit
Full array
1/2 array
1/4 array
1/8 array
VDD1
3800
VDD2
12000
VDDCA + VDDQ
48
VDD1
3000
VDD2
7200
VDDCA + VDDQ
48
VDD1
2600
VDD2
5200
VDDCA + VDDQ
48
VDD1
2400
VDD2
4000
VDDCA + VDDQ
48
Note:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
μA
Parameters/Conditions
All devices in self refresh
CK_t = LOW, CK_c = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
ODT is disabled
1. IDD6 85°C is the maximum of the distribution of the arithmetic mean.
26
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Pin Capacitance
Pin Capacitance
Table 12: Input/Output Capacitance
Part Number
Density
EDF8132A1MC
8Gb
EDFA232A1MA
16Gb
EDF8132A1MC
8Gb
EDFA232A1MA
Symbol
Min
Max
Unit
Notes
Input capacitance,
CK_t and CK_c
CCK
1.5
3.5
pF
1, 2
3.0
6.0
CI1
1.5
3.5
pF
1, 2
16Gb
Input capacitance, all other input-only pins except CS_n, CKE, and ODT
3.0
6.0
EDF8132A1MC
8Gb
CS_n, CKE, and ODT
CI2
0.5
2.5
pF
1, 2
EDFA232A1MA
16Gb
1.5
4.0
EDF8132A1MC
8Gb
CIO
2.5
5.0
pF
1, 2, 3
EDFA232A1MA
16Gb
Input/output capacitance, DQ, DM,
DQS_t, DQS_c
2.0
5.7
EDF8132A1MC
8Gb
Input/output capacitance, ZQ
CZQ
0.0
6.0
pF
1, 2, 3
EDFA232A1MA
16Gb
0.0
6.0
Notes:
Parameter
1. This parameter is not subject to production testing. It is verified by design and characterization.
2. These parameters are measured on f = 100 MHz, VOUT = VDDQ/2, TA = +25 °C.
3. DOUT circuits are disabled.
Table 13: AC Timing Addendum for ODT
Parameter
Symbol
Min/Max
Asynchronous RTT turn-on delay
from ODT input
tODTon
MIN
1.0
MAX
2.25
Asynchronous RTT turn-off delay
from ODT input
tODToff
MIN
1.0
MAX
Automatic RTT turn-on delay after
read data
tAODTon
MAX
Automatic RTT turn-off prior to
read data
tAODToff
MIN
Note:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
1600
1333
Units
ns
ns
2.25
tDQSCK
+ 1.4 × tDQSQmax + tCK(avg, min)
tDQSCKmin
- 300 - 0.5tCK(avg, max)
ps
ps
1. The values provided here reflect the information specific to each of these packages.
27
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
LPDDR3 Array Configuration
LPDDR3 Array Configuration
The 4Gb Mobile Low-Power DDR3 SDRAM (LPDDR3) is a high-speed CMOS, dynamic
random-access memory containing 4,294,967,296-bits. The device is internally configured as an eight-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as
16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit banks is organized as 16,384 rows by 1024 columns by 32 bits.
General Notes
Throughout the data sheet, figures and text refer to DQs as “DQ.” DQ should be interpreted as any or all DQ collectively, unless specifically stated otherwise.
“DQS” and “CK” should be interpreted as DQS_t, DQS_c and CK_t, CK_c, respectively,
unless specifically stated otherwise. “BA” and "CA" include all BA and CA pins, respectively, used for a given density.
Complete functionality may be described throughout the entire document. Any page or
diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
Timing diagrams reflect a single-channel device.
In timing diagrams, “CMD” is used as an indicator only. Actual signals occur on CA[9:0].
VREF indicates V REFCA and V REFDQ.
Any specific requirement takes precedence over a general statement.
Any functionality not specifically stated herein is considered undefined, illegal, is not
supported, and will result in unknown operation.
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28
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Functional Description
Functional Description
Mobile LPDDR3 is a high-speed SDRAM internally configured as an 8-bank memory device. LPDDR3 uses a double data rate architecture on the command/address (CA) bus
to reduce the number of input pins in the system. The 10-bit CA bus is used to transmit
command, address, and bank information. Each command uses one clock cycle, during
which command information is transferred on both the rising and falling edges of the
clock.
LPDDR3 uses a double data rate architecture on the DQ pins to achieve high-speed operation. The double data rate architecture is essentially an 8n prefetch architecture with
an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins.
A single read or write access for LPDDR3 effectively consists of a single 8n-bit-wide,
one-clock-cycle data transfer at the internal SDRAM core and eight corresponding nbit-wide, one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVATE command followed by a READ or
WRITE command. The address and BA bits registered coincident with the ACTIVATE
command are used to select the row and bank to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the
starting column location for the burst access.
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Functional Description
CK_t
CK_c
CKE
Clock
generator
Figure 8: Functional Block Diagram
CA[9:0]
Row
address
buffer
and
refresh
counter
Row decoder
Mode
register
Memory cell array
Bank 0
Sense amp.
Control logic
CS_n
Address/command decoder
Bank n
Column decoder
Column
address
buffer
and
burst
counter
Data control circuit
Latch circuit
Input and Output buffer
DQS_t, DQS_c
DM
ODT
DQ
PDF: 09005aef858e9dd3
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Simplified Bus Interface State Diagram
Simplified Bus Interface State Diagram
The state diagram provides a simplified illustration of the bus interface, supported state
transitions, and the commands that control them. For a complete description of device
behavior, use the information provided in the state diagram with the truth tables and
timing specifications. The truth tables describe device behavior and applicable restrictions when considering the actual state of all banks. For command descriptions, see the
Commands and Timing section.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Simplified Bus Interface State Diagram
Figure 9: Simplified State Diagram
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3RZHURQ
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5HVHWWLQJ
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5
055
5()
,GOH
5HIUHVKLQJ
0
;
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3
5:
,GOH
05UHDGLQJ
65
(7
(6
;
3'
5HVHWWLQJ
SRZHUGRZQ
()
;
3'
65
()
5HVHWWLQJ
05UHDGLQJ
&RPPDQGVHTXHQFH
7
,GOH
SRZHUGRZQ
05ZULWLQJ $&7
$FWLYH
SRZHUGRZQ
$FWLYH
05UHDGLQJ
3'
;
3'
3535$
5
05
$FWLYH
5'
:5
:5
5' :
:ULWLQJ
:5$ :5,7(ZLWKDXWRSUHFKDUJH
3535$
5'$ 5($'ZLWKDXWRSUHFKDUJH
5(6(7 5(6(7LVDFKLHYHGWKURXJK
:5$
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35$ 35(&+$5*($//
5HDGLQJ
5'$
05:FRPPDQG
05: 02'(5(*,67(5:5,7(
055 02'(5(*,67(55($'
3' (QWHUSRZHUGRZQ
3'; ([LWSRZHUGRZQ
:ULWLQJ
ZLWK
DXWRSUHFKDUJH
5HDGLQJ
ZLWK
DXWRSUHFKDUJH
65() (QWHUVHOIUHIUHVK
65(); ([LWVHOIUHIUHVK
3UHFKDUJLQJ
'3' (QWHUGHHSSRZHUGRZQ
'3'; ([LWGHHSSRZHUGRZQ
5() 5()5(6+
Notes:
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
1. All banks are precharged in the idle state.
2. In the case of using MRW to enter CA training mode or write leveling mode, the state
machine will not automatically return to the idle state. In these cases, an additional
MRW command is required to exit either operating mode and return to the idle state.
See the CA Training Mode or Write Leveling Mode sections.
32
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Up and Initialization
3. Terminated bursts are not allowed. For these state transitions, the burst operation must
be completed before a transition can occur.
4. The state diagram is intended to provide a floorplan of the possible state transitions
and commands used to control them, but it is not comprehensive. In particular, situations involving more than one bank are not captured in full detail.
Power-Up and Initialization
The device must be powered up and initialized in a predefined manner. Power-up and
initialization by means other than those specified will result in undefined operation.
Voltage Ramp and Device Initialization
The following sequence must be used to power up the device. Unless specified otherwise, this procedure is mandatory.
1. Voltage Ramp: While applying power (after Ta), CKE must be held LOW, and all other
inputs must be between V ILmin and V IHmax. The device outputs remain at High-Z while
CKE is held LOW.
Following completion of the of the voltage ramp (Tb), CKE must be held LOW. DQ, DM
and DQS voltage levels must be between V SSQ and V DDQ during voltage ramp to avoid
latch-up. CK, CS_n, and CA input levels must be between V SSCA and V DDCA during voltage ramp to avoid latch-up. Voltage ramp power supply requirements are provided in
the table below.
Table 14: Voltage Ramp Conditions
After
Applicable Conditions
Ta is reached
VDD1 must be greater than VDD2 - 200mV
VDD1 and VDD2 must be greater than VDDCA - 200mV
VDD1 and VDD2 must be greater than VDDQ - 200mV
VREF must always be less than all other supply voltages
1. Ta is the point when any power supply first reaches 300mV.
2. Noted conditions apply between Ta and power-down (controlled or uncontrolled).
3. Tb is the point at which all supply and reference voltages are within their defined operating ranges.
4. For supply and reference voltage operating conditions, see the Recommended DC Operating Conditions table.
5. The voltage difference between any VSS, VSSQ, and VSSCA pins must not exceed 100mV.
Notes:
Beginning at Tb, CKE must remain LOW for at least tINIT1, after which CKE can be asserted HIGH. The clock must be stable at least tINIT2 prior to the first CKE LOW-toHIGH transition (Tc). CKE, CS_n, and CA inputs must observe setup and hold requirements (tIS, tIH) with respect to the first rising clock edge and to subsequent falling and
rising edges.
If any MRRs are issued, the clock period must be within the range defined for tCKb.
MRWs can be issued at normal clock frequencies as long as all AC timings are met.
Some AC parameters (for example, tDQSCK) could have relaxed timings (such as
tDQSCKb) before the system is appropriately configured. While keeping CKE HIGH,
NOP commands must be issued for at least tINIT3 (Td). The ODT input signal may be in
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Up and Initialization
an undefined state until tIS before CKE is registered HIGH. When CKE is registered
HIGH, the ODT input signal must be statically held either LOW or HIGH. The ODT input signal remains static until the power-up initialization sequence is finished, including the expiration of tZQINIT.
2. RESET Command: After tINIT3 is satisfied, the MRW RESET command must be issued (Td). An optional PRECHARGE ALL command can be issued prior to the MRW RESET command. Wait at least tINIT4 while keeping CKE asserted and issuing NOP commands. Only NOP commands are allowed during tINIT4.
3. MRRs and Device Auto Initialization (DAI) Polling: After tINIT4 is satisfied (Te), only
MRR commands and POWER-DOWN ENTRY/EXIT commands are supported, and CKE
can go LOW in alignment with power-down entry and exit specifications (see PowerDown). MRR commands are valid at this time only when the CA bus does not need to be
trained. CA training can begin only after time Tf.
The MRR command can be initiated to poll the DAI bit, which indicates whether device
auto initialization is complete. When the bit indicates completion, the device is in an
idle state. The device is also in an idle state after tINIT5 (MAX) has expired, regardless
whether the DAI bit has been read by the MRR command. Because the memory output
buffers are not properly configured by Te, some AC parameters must use relaxed timing
specifications before the system is appropriately configured.
After the DAI bit (MR0, DAI) is set to zero by the memory device (DAI complete), the
device is in the idle state (Tf). DAI status can be determined by issuing the MRR command to MR0. The device sets the DAI bit no later than tINIT5 after the RESET command. The controller must wait at least tINIT5 (MAX) or until the DAI bit is set before
proceeding.
4. ZQ Calibration: If CA training is not required, the MRW INITIALIZATION CALIBRATION (ZQ_CAL) command can be issued to the memory (MR10) after Tf. No other CA
commands (other than RESET or NOP) may be issued prior to the completion of CA
training. After the completion of CA training (Tf'), the MRW INITIALIZATION CALIBRATION (ZQ_CAL) command can be issued to the memory.
This command is used to calibrate output impedance over process, voltage, and temperature. In systems where more than one LPDDR3 device exists on the same bus, the
controller must not overlap MRW ZQ_CAL commands. The device is ready for normal
operation after tZQINIT.
5. Normal Operation: AftertZQINIT (Tg), MRW commands must be used to properly
configure the memory (for example, output buffer drive strength, latencies, and so on).
Specifically, MR1, MR2, and MR3 must be set to configure the memory for the target frequency and memory configuration.
After the initialization sequence is complete, the device is ready for any valid command.
After Tg, the clock frequency can be changed using the procedure described in the Input Clock Frequency Changes and Clock Stop Events section.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Up and Initialization
Figure 10: Voltage Ramp and Initialization Sequence
Ta
Tb
tINIT2
Tc
Td
Te
Tf
Tf’
Tg
CK_t/CK_c
tINIT0
Supplies
tINIT1
tINIT3
CKE
tINIT4
tISCKE
CA
RESET
tZQINIT
tINIT5
MRR
CA
Training
MRW
ZQ_CAL
Valid
DQ
Static HIGH or LOW
ODT
Valid
1. High-Z on the CA bus indicates a valid NOP.
2. For tINIT values, see the Initialization Timing Parameters table.
3. After RESET command time (Tf), RTT is disabled until ODT function is enabled by MRW to
MR11 following Tg.
4. CA training is optional.
Notes:
Table 15: Initialization Timing Parameters
Parameter
Min
Max
Unit
tINIT0
Comment
–
20
ms
Maximum voltage ramp time (Note 1)
tINIT1
100
–
ns
Minimum CKE LOW time after completion of voltage ramp
tINIT2
5
–
tCK
Minimum stable clock before first CKE HIGH
tINIT3
200
–
μs
Minimum idle time after first CKE assertion
tINIT4
1
–
μs
Minimum idle time after RESET command
tINIT5
–
10
μs
Maximum duration of device auto initialization (Note 2)
tZQINIT
1
–
μs
ZQ initial calibration
tCKb
18
100
ns
Clock cycle time during boot
1. The tINIT0 maximum specification is not a tested limit and should be used as a general
guideline. For voltage ramp times exceeding tINIT0 MAX, please contact the factory.
2. If the DAI bit is not read via MRR, the device will be in the idle state after tINIT5 (MAX)
has expired.
Notes:
Initialization After Reset (Without Voltage Ramp)
If the RESET command is issued before or after the power-up initialization sequence,
the reinitialization procedure must begin at Td.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Off Sequence
Power-Off Sequence
The following procedure is required to power off the device.
While powering off, CKE must be held LOW; all other inputs must be between V ILmin
and V IHmax. The device outputs remain at High-Z while CKE is held LOW.
DQ, DM, and DQS voltage levels must be between V SSQ and V DDQ during the power-off
sequence to avoid latch-up. CK, CS_n, and CA input levels must be between V SSCA and
VDDCA during the power-off sequence to avoid latch-up.
Tx is the point where any power supply drops below the minimum value specified in
the Recommended DC Operating Conditions table.
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off.
Table 16: Power Supply Conditions
Between...
Applicable Conditions
Tx and Tz
VDD1 must be greater than VDD2 - 200mV
VDD1 must be greater than VDDCA - 200mV
VDD1 must be greater than VDDQ - 200mV
VREF must always be less than all other supply voltages
1. The voltage difference between any VSS, VSSQ, and VSSCA pins must not exceed 100mV.
2. For supply and reference voltage operating conditions, see Recommended DC Operating
Conditions table.
Notes:
Uncontrolled Power-Off Sequence
When an uncontrolled power-off occurs, the following conditions must be met.
• At Tx, when the power supply drops below the minimum values specified in the Recommended DC Operating Conditions table, all power supplies must be turned off and
all power supply current capacity must be at zero, except for any static charge remaining in the system.
• After Tz (the point at which all power supplies first reach 300mV), the device must
power off. During this period, the relative voltage between power supplies is uncontrolled. V DD1 and V DD2 must decrease with a slope lower than 0.5 V/μs between Tx
and Tz.
An uncontrolled power-off sequence can occur a maximum of 400 times over the life of
the device.
Table 17: Power-Off Timing
Parameter
Maximum power-off ramp time
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36
Symbol
Min
Max
Unit
tPOFF
–
2
sec
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Standard Mode Register Definition
For LPDDR3, a set of mode registers is used for programming device operating parameters, reading device information and status, and for initiating special operations such as
DQ calibration, ZQ calibration, and device reset.
Mode Register Assignments and Definitions
Mode register definitions are provided in the Mode Register Assignments table. An "R"
in the access column of the table indicates read-only; "W" indicates write-only; "R/W"
indicates read- or write-capable or enabled. The MRR command is used to read from a
register. The MRW command is used to write to a register.
Table 18: Mode Register Assignments
Notes 1–5 apply to entire table
MR#
MA[7:0]
Function
Access
OP7
OP6
OP5
RL3
WL-B
RFU
OP4
OP3
OP2
RZQI
OP1
RFU
OP0
DAI
Link
Go to MR0
0
00h
Device info
R
1
01h
Device feature 1
W
2
02h
Device feature 2
W
3
03h
I/O config-1
W
4
04h
SDRAM refresh
rate
R
5
05h
Basic config-1
R
Manufacturer ID
Go to MR5
6
06h
Basic config-2
R
Revision ID1
Go to MR6
7
07h
Basic config-3
R
Revision ID2
Go to MR7
8
08h
Basic config-4
R
9
09h
Test mode
W
10
0Ah
I/O calibration
W
11
0Bh
ODT
W
12–15
0Ch–0Fh
Reserved
–
RFU
Go to MR12
16
10h
PASR_Bank
W
PASR bank mask
Go to MR16
RFU
nWR (for AP)
WR
Lev
WL
Select
RFU
nWRE
BL
Go to MR1
RL and WL
Go to MR2
DS
Go to MR3
RFU
RFU
TUF
I/O width
Refresh rate
Density
Type
Vendor-specific test mode
PD ctl
Go to MR8
Go to MR9
Calibration code
RFU
Go to MR4
Go to MR10
DQ ODT
Go to MR11
17
11h
PASR_Seg
W
PASR segment mask
Go to MR17
18–31
12h–1Fh
Reserved
–
RFU
Go to
MR18–MR31
32
20h
DQ calibration
pattern A
R
See Data Calibration Pattern Description
33–39
21h–27h
Do not use
–
40
28h
DQ calibration
pattern B
R
See Data Calibration Pattern Description
41
29h
CA training 1
W
See MRW - CA Training Mode
42
2Ah
CA training 2
W
See MRW - CA Training Mode
43–47
2Bh–2Fh
Do not use
–
CA training 3
W
See MRW - CA Training Mode
Reserved
–
RFU
48
30h
49–62
31h–3Eh
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Go to MR33
Go to MR43
37
Go to MR49
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 18: Mode Register Assignments (Continued)
Notes 1–5 apply to entire table
MR#
MA[7:0]
Function
63
3Fh
64–255
40h–FFh
Access
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Link
RESET
W
X
Go to MR63
Reserved
–
RFU
Go to MR64
Notes:
1. RFU bits must be set to 0 during MRW.
2. RFU bits must be read as 0 during MRR.
3. For Reads to a write-only or RFU register, DQS is toggled and undefined data is returned.
4. RFU mode registers must not be written.
5. Writes to read-only registers must have no impact on the functionality of the device.
Table 19: MR0 Device Feature 0 (MA[7:0] = 00h)
OP7
OP6
OP5
RL3
WL-B
RFU
OP4
OP3
OP2
RZQI
OP1
RFU
OP0
DAI
Table 20: MR0 Op-Code BIt Definitions
Register
Information
Tag
Type
OP
Definition
DAI
Read-only
OP0
0b: DAI complete
1b: DAI in progress
Built-in self-test for
RZQ information
RZQI1
Read-only
OP[4:3]
WL Set B support
WL-B
Read-only
OP[6]
0b: Device does not support WL Set B
1b: Device supports WL Set B
RL3
Read-only
OP[7]
0b: Device does not support RL = 3, nWR = 3, WL = 1
1b: Device supports RL= 3, nWR = 3, WL = 1 for frequencies ≤166 MHz
Device auto initialization status
RL3 support
Notes:
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00b: RZQ self-test not supported
01b: ZQ pin can connect to VDDCA or float
10b: ZQ pin can short to GND
11b: ZQ pin self-test completed, no error condition
detected (ZQ pin must not float; connect to VDD or
short to GND
1. RZQI will be set upon completion of the MRW ZQ INITIALIZATION CALIBRATION command.
2. If ZQ is connected to VDDCA to set default calibration, OP[4:3] must be set to 01. If ZQ is
not connected to VDDCA, either OP[4:3] = 01 or OP[4:3] = 10 may indicate a ZQ pin assembly error.
3. In the case of a possible assembly error, the device will default to factory trim settings
for RON and will ignore ZQ CALIBRATION commands. In either case, the system may not
function as intended.
4. If the ZQ self-test returns a value of 11b, it indicates that the device has detected a resistor connection to the ZQ pin. However, that result cannot be used to validate the ZQ
resistor value or that the ZQ resistor tolerance meets the specified limit of 240Ω 
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 21: MR1 Device Feature 1 (MA[7:0] = 01h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
RFU
nWR (for AP)
OP0
BL
Table 22: MR1 Op-Code Bit Definitions
Feature
Type
OP
BL
Write-only
OP[2:0]
011b: BL8 (default)
All others: Reserved
nWR
Write-only
OP[7:5]
If nWR (MR2 OP[4]) = 0
001b: nWR = 3
100b: nWR = 6
110b: nWR = 8
111b: nWR = 9
If nWR (MR2 OP[4]) = 1
000b: nWR = 10 (default)
001b: nWR = 11
010b: nWR = 12
100b: nWR = 14
110b: nWR = 16
All others: Reserved
Notes:
Definition
Notes
1, 2
1. The programmed value in the nWR register is the number of clock cycles that determine
when to start the internal precharge operation for a WRITE burst with AP enabled. It is
determined by RU (tWR/tCK).
2. The range of nWR is extended (MR2 OP[4] = 1) by using an extra bit (nWRE) in MR2.
Table 23: Burst Sequence
Burst Cycle Number and Burst Address Sequence
C2
C1
C0
0b
0b
0b
0b
1b
0b
1b
0b
0b
1b
1b
0b
Note:
BL
8
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
2
3
4
5
6
7
0
1
4
5
6
7
0
1
2
3
6
7
0
1
2
3
4
5
1. C0 input is not present on CA bus; it is implied zero.
Table 24: MR2 Device Feature 2 (MA[7:0] = 02h)
OP7
OP6
OP5
OP4
WR Lev
WL Sel
RFU
nWRE
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OP3
OP2
OP1
OP0
RL and WL
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 25: MR2 Op-Code Bit Definitions
Feature
RL and WL
Type
OP
Write-only
OP[3:0]
Definition
If OP[6] = 0 (default, WL Set A)
0001b: RL3/WL1 (≤166 MHz)1
0100b: RL6/WL3 (≤400 MHz)
0110b: RL8/WL4 (≤533 MHz)
0111b: RL9/WL5 (≤600 MHz)
1000b: RL10/WL6 (≤667 MHz, default)
1001b: RL11/WL6 (≤733 MHz)
1010b: RL12/WL6 (≤800 MHz)
1100b: RL14/WL8 (≤933 MHz)
1110b: RL16/WL8 (≤1066 MHz)
All others: Reserved
If OP[6] = 1 (WL Set B)
0001b: RL3/WL1 (≤166 MHz)1
0100b: RL6/WL3 (≤400 MHz)
0110b: RL8/WL4 (≤533 MHz)
0111b: RL9/WL5 (≤600 MHz)
1000b: RL10/WL8 (≤667 MHz, default)
1001b: RL11/WL9 (≤733 MHz)
1010b: RL12/WL9 (≤800 MHz)
1100b: RL14/WL11 (≤933 MHz)
1110b: RL16/WL13 (≤1066 MHz)
All others: Reserved
nWRE
Write-only
OP[4]
0b: Enable nWRE programming ≤9
1b: Enable nWRE programming >9 (default)
WL select
Write-only
OP[6]
0b: Use WL Set A (default)
1b: Use WL Set B2
WR Lev
Write-only
OP[7]
0b: Disable write leveling (default)
1b: Enable write leveling
1. See MR0 OP7.
2. See MR0 OP6.
Notes:
Table 26: LPDDR3 READ and WRITE Latency
Data Rate
(Mb/p/s)
333
800
1066
1200
1333
1466
1600
1866
2133
tCK(ns)
6
2.5
1.875
1.67
1.5
1.36
1.25
1.071
0.938
RL
3
6
8
9
10
11
12
14
16
WL (Set A)
1
3
4
5
6
6
6
8
8
WL (Set B)
1
3
4
5
8
9
9
11
13
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 27: MR3 I/O Configuration 1 (MA[7:0] = 03h)
OP7
OP6
OP5
OP4
OP3
OP2
RFU
OP1
OP0
OP1
OP0
DS
Table 28: MR3 Op-Code Bit Definitions
Feature
DS
Type
OP
Write-only
OP[3:0]
Definition
0001b: 34.3Ω typical
0010b: 40Ω typical (default)
0011b: 48Ω typical
0100b: Reserved
0110b: Reserved
1001b: 34.3Ω pull-down, 40Ω pull-up
1010b: 40Ω pull-down, 48Ω pull-up
1011b: 34.3Ω pull-down, 48Ω pull-up
All others: Reserved
Table 29: MR4 Device Temperature (MA[7:0] = 04h)
OP7
OP6
OP5
OP4
OP3
RFU
TUF
OP2
SDRAM refresh rate
Table 30: MR4 Op-Code Bit Definitions
Notes 1–8 apply to entire table
Feature
Type
OP
SDRAM refresh
rate
Read-only
OP[2:0]
Temperature update flag (TUF)
Read-only
OP7
Notes:
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Definition
000b: SDRAM low-temperature operating limit exceeded
001b: 4 × tREFI, 4 × tREFIpb, 4 × tREFW
010b: 2 × tREFI, 2 × tREFIpb, 2 × tREFW
011b: 1 × tREFI, 1 × tREFIpb, 1 × tREFW (≤85˚C)
100b: 0.5 × tREFI, 0.5 × tREFIpb, 0.5 × tREFW, no AC timing derating
101b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, no AC timing derating
110b: 0.25 × tREFI, 0.25 × tREFIpb, 0.25 × tREFW, timing derating required
111b: SDRAM high-temperature operating limit exceeded
0b: OP[2:0] value has not changed since last read of MR4
1b: OP[2:0] value has changed since last read of MR4
1.
2.
3.
4.
5.
6.
A mode register read from MR4 will reset OP7 to 0.
OP7 is reset to 0 at power-up.
If OP2 = 1, the device temperature is greater than 85˚C.
OP7 is set to 1 if OP[2:0] has changed at any time since the last MR4 read.
The device might not operate properly when OP[2:0] = 000b or 111b.
For the specified operating temperature range and maximum operating temperature,
refer to the Operating Temperature Range table.
7. LPDDR3 devices must be derated by adding 1.875ns to the following core timing parameters: tRCD, tRC, tRAS, tRP, and tRRD. The tDQSCK parameter must be derated as speci-
41
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
fied in the AC Timing table. Prevailing clock frequency specifications and related setup
and hold timings remain unchanged.
8. The recommended frequency for reading MR4 is provided in the Temperature Sensor
section.
Table 31: MR5 Basic Configuration 1 (MA[7:0] = 05h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP1
OP0
OP2
OP1
OP0
OP2
OP1
Manufacturer ID
Table 32: MR5 Op-Code Bit Definitions
Feature
Manufacturer ID
Type
OP
Definition
Read-only
OP[7:0]
0000 0011b:
All others: Reserved
Table 33: MR6 Basic Configuration 2 (MA[7:0] = 06h)
OP7
OP6
OP5
OP4
OP3
OP2
Revision ID1
Note:
1. MR6 is vendor-specific.
Table 34: MR6 Op-Code Bit Definitions
Feature
Revision ID1
Type
OP
Definition
Read-only
OP[7:0]
0000 0000b: Revision A
0000 0001b: Revision B
0000 0010b: Revision C
Table 35: MR7 Basic Configuration 3 (MA[7:0] = 07h)
OP7
OP6
OP5
OP4
OP3
Revision ID2
Table 36: MR7 Op-Code Bit Definitions
Feature
Revision ID2
Note:
Type
OP
Read-only
OP[7:0]
Definition
RFU
1. MR7 is vendor-specific.
Table 37: MR8 Basic Configuration 4 (MA[7:0] = 08h)
OP7
OP6
OP5
OP4
OP3
I/O width
Density
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42
OP0
Type
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 38: MR8 Op-Code Bit Definitions
Feature
Type
OP
Type
Read-only
OP[1:0]
Definition
11b: LPDDR3
All other states reserved
Density
Read-only
OP[5:2]
0110b: 4Gb
1110b: 6Gb
0111b: 8Gb
1101b: 12Gb
1000b: 16Gb
1001b: 32Gb
All others: Reserved
I/O width
Read-only
OP[7:6]
00b: x32
01b: x16
All others: Reserved
Table 39: MR9 Test Mode (MA[7:0] = 09h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP2
OP1
OP0
Vendor-specific test mode
Table 40: MR10 Calibration (MA[7:0] = 0Ah)
OP7
OP6
OP5
OP4
OP3
Calibration code
Table 41: MR10 Op-Code Bit Definitions
Notes 1–4 apply to entire table
Feature
Type
Calibration code
Write-only
Notes:
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OP
OP[7:0]
Definition
0xFF: CALIBRATION command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQ reset
All others: Reserved
1. The device ignores calibration commands when a reserved value is written into MR10.
2. See AC Timing table for the calibration latency.
3. If ZQ is connected to VSSCA through RZQ, either the ZQ calibration function (see MRW ZQ
CALIBRATION Command) or default calibration (through the ZQ RESET command) is supported. If ZQ is connected to VDDCA, the device operates with default calibration and ZQ
CALIBRATION commands are ignored. In both cases, the ZQ connection must not change
after power is supplied to the device.
4. Devices that do not support calibration ignore the ZQ CALIBRATION command.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 42: MR11 ODT Control (MA[7:0] = 0Bh)
OP7
OP6
OP5
OP4
OP3
Reserved
OP2
OP1
PD CTL
OP0
DQ ODT
Table 43: MR11 Op-Code Bit Definitions
Feature
Type
OP
DQ ODT
Write-only
OP[1:0]
PD control
Write-only
OP[2]
Note:
Definition
00b: Disable (default)
01b: RZQ/4 (Note1)
10b: RZQ/2
11b: RZQ/1
00b: ODT disabled by DRAM during power-down (default)
01b: ODT enabled by DRAM during power-down
1. RZQ/4 is supported for LPDDR3-1866 and LPDDR3-2133 devices. RZQ/4 support is optional for LPDDR3-1333 and LPDDR3-1600 devices. Consult Micron specifications for RZQ/4
support for LPDDR3-1333 and LPDDR3-1600.
Table 44: MR16 PASR Bank Mask (MA[7:0] = 010h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
PASR bank mask
Table 45: MR16 Op-Code Bit Definitions
Feature
Bank[7:0] mask
Type
OP
Write-only
OP[7:0]
Definition
0b: Refresh enable to the bank = unmasked (default)
1b: Refresh blocked = masked
Table 46: MR17 PASR Segment Mask (MA[7:0] = 011h)
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
PASR segment mask
Table 47: MR17 PASR Segment Mask Definitions
Feature
Segment[7:0] mask
Type
OP
Write-only
OP[7:0]
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Definition
0b: Refresh enable to the segment = unmasked (default)
1b: Refresh blocked = masked
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Standard Mode Register Definition
Table 48: MR17 PASR Row Address Ranges in Masked Segments
4Gb
6Gb2, 8Gb,
12Gb2 & 16Gb
32Gb
R[13:11]
R[14:12]
TBD
Segment
OP
Segment Mask
0
0
XXXXXXX1
000b
1
1
XXXXXX1X
001b
2
2
XXXXX1XX
010b
3
3
XXXX1XXX
011b
4
4
XXX1XXXX
100b
5
5
XX1XXXXX
101b
6
6
X1XXXXXX
110b
7
7
1XXXXXXX
111b
Notes:
1. X = “Don’t Care” for the designated segment.
2. No memory present at addresses with R13 = R14 = HIGH. Segment masks 6 and 7 are ignored.
Table 49: MR63 RESET (MA[7:0] = 3Fh) – MRW Only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
X or 0xFCh
Note:
1. For additional information on MRW RESET, see the Mode Register Write (MRW) section.
Table 50: Reserved Mode Registers
Mode
Register
MA
Address
Restriction
MR[12:15]
MA[7:0]
0Ch-0Fh
Reserved
Reserved
MR[18:31]
12h–1Fh
Reserved
Reserved
MR[33:39]
21h–27h
DNU
DNU
MR[43:47]
2Bh–2Fh
DNU
DNU
MR[49:62]
31h–3Eh
Reserved
Reserved
MR[64:255]
40h–FFh
Reserved
Reserved
Note:
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OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
1. DNU = Do not use; RVU = Reserved for vendor use.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Commands and Timing
Commands and Timing
The setup and hold timings shown in the figures below apply for all commands.
Figure 11: Command and Input Setup and Hold
T0
T1
T2
T3
tIS tIH
tIS tIH
CK_c
CK_t
CS_n
VIL(DC)
VIL(AC)
VIH(AC)
tIS tIH
CA[9:0]
CA
rise
CA
fall
CA
rise
NOP
CMD
VIH(DC)
tIS tIH
CA
fall
Command
CA
rise
CA
fall
NOP
Don’t Care
CA
rise
CA
fall
Command
Transitioning data
1. Setup and hold conditions also apply to the CKE pin. For timing diagrams related to the
CKE pin, see the Power-Down section.
Note:
Figure 12: CKE Input Setup and Hold
T0
T1
Tx
Tx + 1
CK_c
CK_t
tIHCKE
CKE
VIHCKE
tISCKE
tIHCKE
VILCKE
VILCKE
tISCKE
VIHCKE
HIGH or LOW, but defined
Notes:
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1. After CKE is registered LOW, the CKE signal level is maintained below VILCKE for tCKE
specification (LOW pulse width).
2. After CKE is registered HIGH, the CKE signal level is maintained above VIHCKE for tCKE
(HIGH pulse width).
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
ACTIVATE Command
ACTIVATE Command
The ACTIVATE command is issued by holding CS_n LOW, CA0 LOW, and CA1 HIGH at
the rising edge of the clock. The bank addresses BA[2:0] are used to select the desired
bank. Row addresses are used to determine which row to activate in the selected bank.
The ACTIVATE command must be applied before any READ or WRITE operation can be
executed. The device can accept a READ or WRITE command at tRCD after the ACTIVATE command is issued. After a bank has been activated, it must be precharged before
another ACTIVATE command can be applied to the same bank. The bank active and
precharge times are defined as tRAS and tRP, respectively. The minimum time interval
between successive ACTIVATE commands to the same bank is determined by the RAS
cycle time of the device (tRC). The minimum time interval between ACTIVATE commands to different banks is tRRD.
Figure 13: ACTIVATE Command
CK_c
CK_t
CA[9:0]
Bank n
row addr Row addr
Bank m
Bank n
row addr Row addr col addr
Col addr
Bank n
row addr Row addr
Bank n
tRRD
tRCD
tRP
tRAS
tRC
CMD
ACTIVATE
ACTIVATE
NOP
READ
PRECHARGE
NOP
NOP
ACTIVATE
1. A PRECHARGE ALL command uses tRPab timing, and a single-bank PRECHARGE command uses tRPpb timing. In this figure, tRP denotes either an all-bank PRECHARGE or a
single-bank PRECHARGE.
Note:
8-Bank Device Operation
Certain restrictions must be taken into consideration when operating 8-bank devices;
one restricts the number of sequential ACTIVATE commands that can be issued and
one provides additional RAS precharge time for a PRECHARGE ALL command.
The 8-Bank Device Sequential Bank Activation Restriction: No more than four banks
can be activated (or refreshed, in the case of REFpb) in a rolling tFAW window. The
number of clocks in a tFAW period depends on the clock frequency, which may vary. If
the clock frequency is not changed over this period, convert to clocks by dividing
tFAW[ns] by tCK[ns] and then rounding up to the next integer value. As an example of
the rolling window, if RU(tFAW/tCK) is 10 clocks, and an ACTIVATE command is issued
in clock n, no more than three further ACTIVATE commands can be issued at or between clock n + 1 and n + 9. REFpb also counts as bank activation for purposes of tFAW.
If the clock is changed during the tFAW period, the rolling tFAW window may be calculated in clock cycles by adding together the time spent in each clock period. The tFAW requirement is met when the previous n clock cycles exceeds the tFAW time.
The 8-Bank Device PRECHARGE ALL Provision: tRP for a PRECHARGE ALL command
must equal tRPab, which is greater than tRPpb.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Read and Write Access Modes
Figure 14: tFAW Timing
Tn
Tn+
Tm
Tm+
Tx
Tx+
Ty
Ty + 1
Ty + 2
Tz
Tz + 1
Tz + 2
CK_c
CK_t
CA[9:0]
Bank Bank
A
A
Bank Bank
B
B
tRRD
CMD ACTIVATE
NOP
Bank Bank
C
C
tRRD
ACTIVATE
NOP
Bank Bank
D
D
Bank Bank
E
E
tRRD
ACTIVATE
NOP
ACTIVATE
NOP
NOP
NOP
ACTIVATE
NOP
tFAW
Read and Write Access Modes
After a bank is activated, a READ or WRITE command can be issued with CS_n LOW,
CA0 HIGH, and CA1 LOW at the rising edge of the clock. CA2 must also be defined at
this time to determine whether the access cycle is a READ operation (CA2 HIGH) or a
WRITE operation (CA2 LOW). A single READ or WRITE command initiates a burst
READ or burst WRITE operation on successive clock cycles. Burst interrupts are not allowed.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Burst READ Command
The burst READ command is initiated with CS_n LOW, CA0 HIGH, CA1 LOW, and CA2
HIGH at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. The read latency (RL)
is defined from the rising edge of the clock on which the READ command is issued to
the rising edge of the clock from which the tDQSCK delay is measured. The first valid
data is available RL × tCK + tDQSCK + tDQSQ after the rising edge of the clock when the
READ command is issued. The data strobe output is driven LOW tRPRE before the first
valid rising strobe edge. The first bit of the burst is synchronized with the first rising
edge of the data strobe. Each subsequent data-out appears on each DQ pin, edgealigned with the data strobe. The RL is programmed in the mode registers. Pin input
timings for the data strobe are measured relative to the crosspoint of DQS_t and its
complement, DQS_c.
Figure 15: READ Output Timing
RL-1
tCH
tCL
RL
RL + BL/ 2
CK_c
CK_t
tHZ(DQS)
tDQSCK
tLZ(DQS)
tRPST
tRPRE
DQS_c
DQS_t
tQH
tQH
tDQSQmax
tDQSQmax
DOUT
DQ
DOUT
DOUT
DOUT
tLZ(DQ)
DOUT
DOUT
DOUT
DOUT
tHZ(DQ)
Transitioning data
Note:
1. tDQSCK can span multiple clock periods.
Figure 16: Burst READ – RL = 12, BL = 8, tDQSCK > tCK
T0
T1
T2
T12
Ta-1
Ta
Ta+1
Ta+2
Ta+3
Ta+4
CK_c
CK_t
RL = 12
CA[9:0]
CMD
Bank n
col addr
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning data
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 17: Burst READ – RL = 12, BL = 8, tDQSCK < tCK
T0
T1
T2
T12
T13
T14
T15
T16
T17
CK_c
CK_t
RL = 12
CA[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCK
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3 DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning data
Figure 18: Burst READ Followed by Burst WRITE – RL = 12, WL = 6, BL = 8
T0
T1
T2
T12
Ta - 1
Ta
Ta + 1
Ta + 2
Ta + 3
Ta + 4
Ta + 9
Ta + 10
CK_c
CK_t
RL = 12
CA[9:0]
CMD
Bank n
col addr
BL/2
WL = 6
Bank n
col addr
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Col addr
WRITE
tDQSCK
NOP
NOP
NOP
tDQSSmin
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DIN A0
DIN A1
DIN
Transitioning Data
The minimum time from the burst READ command to the burst WRITE command is
defined by the read latency (RL) and the burst length (BL). Minimum READ-to-WRITE
latency is RL + RU(tDQSCK(MAX)/tCK) + BL/2 + 1 - WL clock cycles.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 19: Seamless Burst READ – RL = 6, BL = 8, tCCD = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK_c
CK_t
RL = 6
CA[9:0]
tCCD
CMD
Bank n
Col addr b
col addr b
Bank n
Col addr a
col addr a
READ
tCCD
=4
NOP
NOP
NOP
READ
Bank n
Col addr c
col addr c
Bank n
Col addr d
col addr d
=4
NOP
NOP
NOP
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DOUTB0
DOUTB1
DOUTB2
DOUTB3
DOUTB4
DOUTB5
DOUTB6
DOUTB7
DOUTC0
DOUTC1
Transitioning data
The seamless burst READ operation is supported by enabling a READ command at every fourth clock cycle for BL = 8 operation. This operation is supported as long as the
banks are activated, whether the accesses read the same or different banks.
tDQSCK
Delta Timing
To allow the system to track variations in tDQSCK output across multiple clock cycles,
three parameters are provided: tDQSCKDL (delta long), tDQSCKDM (delta medium),
and tDQSCKDS (delta short). Each of these parameters defines the change in tDQSCK
over a short, medium, or long rolling window, respectively. The definition for each
tDQSCK-delta parameter is shown in the figures below.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 20: tDQSCKDL Timing
Tn
Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 12
CK_c
CK_t
RL = 10
CA
[9:0]
Bankn
Col addr
col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2 DOUTA3 DOUTA4
32ms maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bankn
Col addr
col addr
CMD
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2 DOUTA3 DOUTA4
…32ms maximum
Transitioning data
1
Notes:
PDF: 09005aef858e9dd3
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1. tDQSCKDL = (tDQSCKn - tDQSCKm).
2. tDQSCKDL (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 32ms rolling window.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 21: tDQSCKDM Timing
Tn
Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
1.6μs maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
…1.6μs maximum
Transitioning data
1
Notes:
PDF: 09005aef858e9dd3
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1. tDQSCKDM = (tDQSCKn - tDQSCKm).
2. tDQSCKDM (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair within any 1.6μs rolling window.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst READ Command
Figure 22: tDQSCKDS Timing
Tn
Tn + 1
Tn + 2
Tn + 9
Tn + 10
Ta
Ta + 1
Ta + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKn
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3 DOUTA4
160ns maximum…
1
Tm
Tm + 1
Tm + 2
Tm + 9
Tm + 10
Tb
Tb + 1
Tb + 2
CK_c
CK_t
RL = 10
CA
[9:0]
Bank n
col addr
CMD
Col addr
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tDQSCKm
DQS_c
DQS_t
DQ
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
DOUTA0
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
…160ns maximum
Transitioning data
1
Notes:
PDF: 09005aef858e9dd3
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1. tDQSCKDS = (tDQSCKn - tDQSCKm).
2. tDQSCKDS (MAX) is defined as the maximum of ABS (tDQSCKn - tDQSCKm) for any
(tDQSCKn, tDQSCKm) pair for READs within a consecutive burst, within any 160ns rolling
window.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Burst WRITE Command
The burst WRITE command is initiated with CS_n LOW, CA0 HIGH, CA1 LOW, and CA2
LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is
defined from the rising edge of the clock on which the WRITE command is issued to the
rising edge of the clock from which the tDQSS delay is measured. The first valid data
must be driven WL × tCK + tDQSS from the rising edge of the clock from which the
WRITE command is issued. The data strobe signals (DQS) must be driven as shown in
Figure 25 (page 56). The burst cycle data bits must be applied to the DQ pins tDS prior
to the associated edge of the DQS and held valid until tDH after that edge. Burst data is
sampled on successive edges of the DQS_t until the burst length is completed. After a
burst WRITE operation, tWR must be satisfied before a PRECHARGE command to the
same bank can be issued. Pin input timings are measured relative to the crosspoint of
DQS_t and its complement, DQS_c.
Figure 23: Data Input (WRITE) Timing
tDQSL
tDQSH
tDQSL
tWPST
DQS_c
DQS_t
tWPRE
VIH(AC)
DQ
VIH(AC)
VIH(DC)
DIN
VIL(AC) tDS
tDH
DIN
VIL(DC)
tDS
tDH
DIN
tDS
tDH
VIH(DC)
DIN
VIL(AC) tDS
VIH(AC)
VIH(DC)
VIH(AC)
VIH(DC)
VIL(AC)
VIL(DC)
VIL(AC)
VIL(DC)
tDH
VIL(DC)
DM
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55
Don’t Care
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Figure 24: Burst WRITE
T0
Ta
Ta + 1
...
Ta + 5
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
WL
CA[9:0]
CMD
Bank n
col addr
Col addr
WRITE
NOP
Case 1: tDQSS (MAX)
DQS_c
DQS_t
NOP
tDQSS
DIN A0
tDQSS
(MIN)
DQ
NOP
tDSS
(MAX)
DQ
Case 2: tDQSS (MIN)
DQS_c
DQS_t
Bank n Row addr
row addr
Bank n
tDSH
DIN A0
NOP
tDSS
DIN A1
DIN A6
NOP
PRECHARGE
ACTIVATE
NOP
Completion of burst WRITE
tWR
tRP
tWR
tRP
DIN A7
tDSH
DIN A1
DIN A2
DIN A7
Don’t Care
Transitioning Data
Figure 25: Method for Calculating tWPRE Transitions and Endpoints
CK_t
VTT
CK_c
T1
begins
tWPRE
DQS_t - DQS_c
0V
tWPRE
T2
Resulting differential
signal relevant for
tWPRE specification
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tWPRE
56
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Figure 26: Method for Calculating tWPST Transitions and Endpoints
CK_t
VTT
CK_c
tWPST
DQS_t - DQS_c
0V
Resulting differential
signal relevant for
tWPST specification
T1
begins
tWPST
T2
ends
tWPST
Figure 27: Burst WRITE Followed by Burst READ
T0
Tx
Tx + 1
Tx + 2
Tx + 5
Tx + 9
Tx + 10
Tx + 11
CK_c
CK_t
RL
WL
CA[9:0]
Bank m
Col addr a
col addr a
Bank n
Col addr b
col addr b
tWTR
CMD
WRITE
NOP
NOP
NOP
NOP
NOP
READ
NOP
NOP
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A7
Don’t Care
Notes:
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Transitioning Data
1. The minimum number of clock cycles from the burst WRITE command to the burst READ
command for any bank is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. tWTR starts at the rising edge of the clock after the last valid input data.
57
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Burst WRITE Command
Figure 28: Seamless Burst WRITE – WL = 4, BL = 8, tCCD = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
CK_c
CK_t
WL = 4
CA[9:0]
Bankm
Col addr a
col addr a
tCCD
CMD
WRITE
Bankn
Col addr b
col addr b
Bankn
Col addr c
col addr c
Bankn
Col addr d
col addr d
=4
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
WRITE
NOP
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DIN A4
DIN A5
DIN A6
DIN A7
DIN B0
DIN B1
DIN B2
DIN B3
DIN B4
DIN B5
Don’t Care
Note:
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DIN B6
DIN B7
DIN C0
DIN C1
Transitioning Data
1. The seamless burst WRITE operation is supported by enabling a WRITE command every
four clocks for BL = 8 operation. This operation is supported for any activated bank.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Write Data Mask
Write Data Mask
LPDDR3 devices support one write data mask (DM) pin for each data byte (DQ), which
is consistent with LPDDR2 devices. Each DM can mask its respective DQ for any given
cycle of the burst. Data mask timings match data bit timing, but are inputs only. Internal data mask loading is identical to data bit loading to ensure matched system timing.
Figure 29: Data Mask Timing
DQS_c
DQS_t
DQ
tDS
VIH(AC)
tDH
VIH(DC) VIH(AC)
tDS
tDH
VIH(DC)
DM
VIL(AC)
VIL(DC) VIL(AC)
VIL(DC)
Don’t Care
Figure 30: Write Data Mask – Second Data Bit Masked
CK_c
CK_t
tWR
tWTR
WL
CMD
Case 1:
WRITE
t DQSS
(MIN)
tDQSS
(MIN)
DQS_t
DQS_c
DOUT 1
DQ
DOUT 0
DOUT 2 DOUT 3
DOUT 4 DOUT 5 DOUT 6
DOUT 7
DM
Case 2: t DQSS (MAX)
tDQSS
(MAX)
DQS_t
DQS_c
DOUT 1
DQ
DOUT 0
DOUT 2 DOUT 3 DOUT 4
DOUT 5 DOUT 6 DOUT 7
DM
Don’t Care
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
PRECHARGE Command
The PRECHARGE command is used to precharge or close a bank that has been activated. The PRECHARGE command is initiated with CS_n LOW, CA0 HIGH, CA1 HIGH,
CA2 LOW, and CA3 HIGH at the rising edge of the clock. The PRECHARGE command
can be used to precharge each bank independently or all banks simultaneously. The AB
flag and the bank address bits BA0, BA1, and BA2 are used to determine which bank(s)
to precharge. The precharged bank(s) will be available for subsequent row access tRPab
after an all-bank PRECHARGE command is issued, or tRPpb after a single-bank PRECHARGE command is issued.
To ensure that LPDDR3 devices can meet the instantaneous current demand required
to operate, the row precharge time (tRP) for an all bank PRECHARGE (tRPab) will be longer than the row precharge time for a single-bank PRECHARGE (tRPpb). ACTIVATE to
PRECHARGE timing is shown in the ACTIVATE Command figure.
Table 51: Bank Selection for PRECHARGE by Address Bits
AB (CA4r)
BA2 (CA9r)
BA1 (CA8r)
BA0 (CA7r)
Precharged Bank(s)
8-Bank Device
0
0
0
0
Bank 0 only
0
0
0
1
Bank 1 only
0
0
1
0
Bank 2 only
0
0
1
1
Bank 3 only
0
1
0
0
Bank 4 only
0
1
0
1
Bank 5 only
0
1
1
0
Bank 6 only
0
1
1
1
Bank 7 only
1
Don’t Care
Don’t Care
Don’t Care
All banks
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Burst READ Operation Followed by PRECHARGE
For the earliest possible precharge, the PRECHARGE command can be issued BL/2
clock cycles after a READ command. A new bank ACTIVATE command can be issued to
the same bank after the row precharge time (tRP) has elapsed. A PRECHARGE command cannot be issued until after tRAS is satisfied.
For LPDDR3 devices, the minimum READ-to-PRECHARGE time (tRTP) must also satisfy
a minimum analog time from the rising clock edge that initiates the last 8-bit prefetch
of a READ command. tRTP begins BL/2 - 4 clock cycles after the READ command. For
LPDDR3 READ-to-PRECHARGE timings, see the PRECHARGE and Auto Precharge Clarification table.
Figure 31: Burst READ Followed by PRECHARGE – BL = 8, RU(tRTP(MIN)/tCK) = 2
T0
T1
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_c
CK_t
RL
CA[9:0]
Bank m
col addr a Col addr a
Bank m
Row addr
row addr
Bank m
tRP
tRTP
CMD
READ
NOP
NOP
PRECHARGE
NOP
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
DQ
DOUTA0
DOUTA1
DOUTA2
DOUTA3
DOUTA4
DOUTA5
DOUTA6
DOUTA7
Transitioning Data
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Burst WRITE Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time ( tWR) must be provided before a PRECHARGE
command can be issued. This delay is referenced from the last valid burst input data to
the completion of the burst WRITE. The PRECHARGE command must not be issued
prior to the tWR delay. For LPDDR3 WRITE-to-PRECHARGE timings, see the PRECHARGE and Auto Precharge Clarification table.
LPDDR3 devices write data to the array in prefetch multiples (prefetch = 8). An internal
WRITE operation can begin only after a prefetch group has been completely latched, so
tWR starts at prefetch bondaries.
The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL +
BL/2 + 1 + RU(tWR/tCK) clock cycles.
Figure 32: Burst WRITE Followed by PRECHARGE – BL = 8
T0
Tx
Tx + 1
Tx + 4
Tx + 5
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr
Col addr
• tRP
tWR
CMD
WRITE
Case 1: t DQSS (MAX)
Bankn Row addr
row addr
Bankn
NOP
NOP
tDQSS
NOP
NOP
(MAX)
PRECHARGE
NOP
ACTIVATE
NOP
Completion of burst WRITE
DQS_c
DQS_t
DQ
Case 2: t DQSS (MIN)
tDQSS
DIN A0
DIN A5
DIN A6
DIN A1
DIN A6
DIN A7
DIN A7
(MIN)
DQS_c
DQS_t
DQ
DIN A0
Don’t Care
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62
Transitioning Data
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Auto Precharge
Before a new row can be opened in an active bank, the active bank must be precharged
using either the PRECHARGE command or the auto precharge function. When a READ
or WRITE command is issued to the device, the AP bit (CA0f) can be set to enable the
active bank to automatically begin precharge at the earliest possible moment during the
burst READ or WRITE cycle.
If AP is LOW when the READ or WRITE command is issued, a normal READ or WRITE
burst operation is executed and the bank remains active at the completion of the burst.
If AP is HIGH when the READ or WRITE command is issued, the auto precharge function is engaged. This feature enables the PRECHARGE operation to be partially or completely hidden during burst READ cycles (dependent upon READ or WRITE latency),
thus improving system performance for random data access.
Burst READ with Auto Precharge
If AP (CA0f) is HIGH when a READ command is issued, the READ with auto precharge
function is engaged. The device starts an auto precharge on the rising edge of the clock,
BL/2 or BL/2 - 4 + RU(tRTP/tCK) clock cycles later than the READ with auto precharge
command, whichever is greater. For LPDDR3 auto precharge calculations, see the PRECHARGE and Auto Precharge Clarification table.
Following an auto precharge operation, an ACTIVATE command can be issued to the
same bank if the following two conditions are satisfied simultaneously:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Figure 33: LPDDR3 – Burst READ with Auto Precharge
T0
T1
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_c
CK_t
RL
CA[9:0]
Bankm
Col addr a
col addr a
Bankm
Row addr
row addr
tRTP
CMD
READ w/AP
NOP
• tRPpb
NOP
NOP
NOP
NOP
NOP
ACTIVATE
NOP
DQS_c
DQS_t
DQ
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A4
DOUT A5
DOUT A6
DOUT A7
Transitioning Data
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Burst WRITE with Auto Precharge
If AP (CA0f) is HIGH when a WRITE command is issued, the WRITE with auto precharge
function is engaged. The device starts an auto precharge at the clock rising edge tWR
cycles after the completion of the burst WRITE.
Following a WRITE with auto precharge, an ACTIVATE command can be issued to the
same bank if the following two conditions are met:
• The RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins.
• The RAS cycle time (tRC) from the previous bank activation has been satisfied.
Figure 34: Burst WRITE with Auto Precharge – BL = 8
T0
Tx
Tx + 1
...
Tx + 5
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr
Bankn Row addr
row addr
Col addr
tWR
CMD
WRITE
NOP
NOP
NOP
NOP
• tRPpb
NOP
NOP
ACTIVATE
NOP
DQS_t
DQS_c
DQ
DIN A0
DIN A1
DIN A6
DIN A7
Don’t Care
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64
Transitioning Data
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
PRECHARGE Command
Table 52: PRECHARGE and Auto Precharge Clarification
From
Command
READ
READ w/AP
WRITE
WRITE w/AP
To Command
BL/2 + MAX (4,
RU(tRTP/tCK))
-4
PRECHARGE ALL
BL/2 + MAX (4,
RU(tRTP/tCK))
-4
PRECHARGE to same bank as READ w/AP
BL/2 + MAX (4, RU(tRTP/tCK)) - 4
PRECHARGE ALL
BL/2 + MAX(4, RU(tRTP/tCK)) - 4
PRECHARGE to same bank as READ
-4+
Notes
CLK
1
CLK
1, 2
1
1
RU(tRPpb/
BL/2 + MAX(4,
tCK)
WRITE or WRITE w/AP (same bank)
Illegal
3
WRITE or WRITE w/AP (different bank)
RL + BL/2 + RU(tDQSCKmax/tCK) - WL + 1
3
READ or READ w/AP (same bank)
Illegal
3
READ or READ w/AP (different bank)
BL/2
1
3
RU(tWR/tCK)
+1
PRECHARGE to same bank as WRITE
WL + BL/2 +
PRECHARGE ALL
WL + BL/2 + RU(tWR/tCK) + 1
CLK
1
1
PRECHARGE to same bank as WRITE w/AP WL + BL/2 + RU(tWR/tCK) + 1
CLK
1
WL + BL/2 +
RU(tWR/tCK)
ACTIVATE to same bank as WRITE w/AP
WL + BL/2 +
RU(tWR/tCK)
WRITE or WRITE w/AP (same bank)
Illegal
3
WRITE or WRITE w/AP (different bank)
BL/2
3
READ or READ w/AP (same bank)
Illegal
READ or READ w/AP (different bank)
PRECHARGE
ALL
RU(tRTP/tCK))
Unit
ACTIVATE to same bank as READ w/AP
PRECHARGE ALL
PRECHARGE
Minimum Delay Between Commands
PRECHARGE ALL
1
PRECHARGE
1
PRECHARGE ALL
1
Notes:
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+1+
1
RU(tRPpb/tCK)
1
3
WL + BL/2 +
PRECHARGE to same bank as PRECHARGE 1
+1
RU(tWTR/tCK)
+1
3
CLK
1
1
CLK
1
1
1. For a given bank, the PRECHARGE period should be counted from the latest PRECHARGE
command, which will be either a one-bank PRECHARGE command or a PRECHARGE ALL
command, issued to that bank. The PRECHARGE period is satisfied after tRP, depending
on the latest PRECHARGE command issued to that bank.
2. Any command issued during the specified minimum delay time is illegal.
3. After a READ with auto precharge command, seamless READ operations to different
banks are supported. After a WRITE with auto precharge command, seamless WRITE operations to different banks are supported. READ with auto precharge and WRITE with
auto precharge commands must not be interrupted or truncated.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
REFRESH Command
The REFRESH command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, and CA2
HIGH at the rising edge of the clock. Per-bank REFRESH is initiated with CA3 LOW at
the rising edge of the clock. All-bank REFRESH is initiated with CA3 HIGH at the rising
edge of the clock.
A per-bank REFRESH command (REFpb) performs a per-bank REFRESH operation to
the bank scheduled by the bank counter in the memory device. The bank sequence for
per-bank REFRESH is fixed to be a sequential round-robin: 0-1-2-3-4-5-6-7-0-1-.... The
bank count is synchronized between the controller and the SDRAM by resetting the
bank count to zero. Synchronization can occur upon issuing a RESET command or at
every exit from self refresh.
A bank must be idle before it can be refreshed. The controller must track the bank being
refreshed by the per-bank REFRESH command.
The REFpb command must not be issued to the device until the following conditions
have been met (see the REFRESH Command Scheduling Separation Requirements table):
•
•
•
•
tRFCab
has been satisfied after the prior REFab command
has been satisfied after the prior REFpb command
tRP has been satisfied after the prior PRECHARGE command to that bank
tRRD has been satisfied after the prior ACTIVATE command (if applicable, for example after activating a row in a different bank than the one affected by the REFpb command)
tRFCpb
The target bank is inaccessible during per-bank REFRESH cycle time (tRFCpb); however, other banks within the device are accessible and can be addressed during the cycle.
During the REFpb operation, any of the banks other than the one being refreshed can
be maintained in an active state or accessed by a READ or WRITE command. When the
per-bank REFRESH cycle has completed, the affected bank will be in the idle state.
After issuing REFpb, the following conditions must be met (see the REFRESH Command Scheduling Separation Requirements table):
•
•
•
•
tRFCpb
must be satisfied before issuing a REFab command
must be satisfied before issuing an ACTIVATE command to the same bank
tRRD must be satisfied before issuing an ACTIVATE command to a different bank
tRFCpb must be satisfied before issuing another REFpb command
tRFCpb
An all-bank REFRESH command (REFab) issues a REFRESH command to all banks. All
banks must be idle when REFab is issued (for instance, by issuing a PRECHARGE ALL
command prior to issuing an all-bank REFRESH command). REFab also synchronizes
the bank count between the controller and the SDRAM to zero. The REFab command
must not be issued to the device until the following conditions have been met (see the
REFRESH Command Scheduling Separation Requirements table):
• tRFCab has been satisfied following the prior REFab command
• tRFCpb has been satisfied following the prior REFpb command
• tRP has been satisfied following the prior PRECHARGE commands
When an all-bank REFRESH cycle has completed, all banks will be idle. After issuing REFab:
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
• tRFCab latency must be satisfied before issuing an ACTIVATE command
• tRFCab latency must be satisfied before issuing a REFab or REFpb command
Table 53: REFRESH Command Scheduling Separation Requirements
Symbol
Minimum
Delay From
tRFCab
REFab
To
Notes
REFab
ACTIVATE command to any bank
REFpb
tRFCpb
REFpb
REFab
ACTIVATE command to same bank as REFpb
REFpb
tRRD
REFpb
ACTIVATE command to a different bank than REFpb
ACTIVATE
REFpb
1
ACTIVATE command to a different bank than the prior ACTIVATE command
1. A bank must be in the idle state before it is refreshed, so following an ACTIVATE command REFab is prohibited. REFpb is supported only if it affects a bank that is in the idle
state.
Note:
In general, an all bank REFRESH command needs to be issued to the device regularly
every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided for postponing
and pulling in the refresh command. A maximum of eight REFRESH commands can be
postponed during operation of the device, but at no point in time are more than a total
of eight REFRESH commands allowed to be postponed. In the case where eight REFRESH commands are postponed in a row, the resulting maximum interval between the
surrounding REFRESH commands is limited to 9 × tREFI. A maximum of eight additional REFRESH commands can be issued in advance (pulled in), with each one reducing
the number of regular REFRESH commands required later by one. Note that pulling in
more than eight REFRESH commands in advance does not reduce the number of regular REFRESH commands required later; therefore, the resulting maximum interval between two surrounding REFRESH commands is limited to 9 x tREFI. At any given time, a
maximum of 16 REFRESH commands can be issued within 2 x tREFI.
For per bank refresh, a maximum of 8 × 8 per bank REFRESH commands can be postponed or pulled in for scheduling efficiency. At any given time, a maximum of 2 × 8 per
bank REFRESH commands may be issued within 2 × tREFI.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
Figure 35: REFRESH Command Timing
T0
T1
REF
NOP
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Vaild
Vaild
Vaild
Vaild
Tc0
Tc1
Tc2
Tc3
REF
Vaild
Vaild
Vaild
CK_c
CK_t
CMD
NOP
REF
tRFC
NOP
tRFC
NOP
Vaild
(MIN)
tREFI
(MAX 9  tREF)
DRAM must be idle
DRAM must be idle
1. Only NOP commands are allowed after the REFRESH command is registered until tRFC
(MIN) expires.
2. The time interval between two REFRESH commands may be extended to a maximum of
9 ×tREFI.
Notes:
Figure 36: Postponing REFRESH Commands
tREFI
9
tREFI
t
8 REFRESH commands postponed
Figure 37: Pulling In REFRESH Commands
tREFI
9
tREFI
t
8 REFRESH commands pulled-in
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
REFRESH Requirements
Minimum REFRESH Commands
LPDDR3 requires a minimum number, R, of REFRESH (REFab) commands within any
rolling refresh window (tREFW = 32ms @ MR4[2:0] = 011 or T C ≤ 85˚C). For actual values
per density and the resulting average refresh interval (tREFI), see the Refresh Requirement Parameters (Per Density) table.
For tREFW and tREFI refresh multipliers at different MR4 settings, see the MR4 Device
Temperature (MA[7:0] = 04h) and the MR4 Op-Code Bit Definitions tables.
When using per-bank REFRESH, a REFab command can be replaced by a full cycle of
eight REFpb commands.
REFRESH Requirements and Self Refresh
Self refresh mode may be entered with a maximum of eight REFRESH commands being
postponed. After exiting self refresh mode with one or more REFRESH commands postponed, additional REFRESH commands may be postponed, but the total number of
postponed refresh commands (before and after the self refresh) must never exceed
eight. During self refresh mode, the number of postponed or pulled-in REFRESH commands does not change.
An internally timed refresh event can be missed when CKE is raised for exit from self
refresh mode. After exiting self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
REFRESH Command
Figure 38: All-Bank REFRESH Operation
T0
T1
T2
T3
T4
Tx
Tx + 1
Ty
Ty + 1
CK_c
CK_t
CA[9:0]
CMD
AB
PRECHARGE
NOP
NOP
REFab
• tRPab
NOP
NOP
REFab
• tRFCab
Any
• tRFCab
Figure 39: Per-Bank REFRESH Operation
T0
T1
Tx
Tx + 1
Tx + 2
Ty
Ty + 1
Tz
Tz + 1
CK_c
CK_t
CA[9:0]
CMD
Bank 1
Row A
AB
PRECHARGE
NOP
NOP
•tRPab
REFpb
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•tRFCpb
REFRESH to bank 1
REFRESH to bank 0
Notes:
ACTIVATE
REFpb
•tRFCpb
Row A
ACTIVATE command
to bank 1
1. In the beginning of this example, the REFpb bank counter points to bank 0.
2. Operations to banks other than the bank being refreshed are supported during the
tRFCpb period.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
SELF REFRESH Operation
SELF REFRESH Operation
The SELF REFRESH command can be used to retain data in the array, even if the rest of
the system is powered-down. When in the self refresh mode, the device retains data
without external clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF REFRESH command is executed by taking CKE LOW, CS_n
LOW, CA0 LOW, CA1 LOW, and CA2 HIGH at the rising edge of the clock. CKE must be
HIGH during the clock cycle preceding a SELF REFRESH command. CKE must not go
LOW while MRR, MRW, READ, or WRITE operations are in progress.
To ensure that there is enough time to account for internal delay on the CKE signal
path, two NOP commands are required after CKE is driven LOW; this timing period is
defined as tCPDED. CKE LOW will result in deactivation of input receivers after tCPDED
has expired. After the power-down command is registered, CKE must be held LOW to
keep the device in self refresh mode.
Mobile LPDDR3 devices can operate in self refresh mode in both the standard and extended temperature ranges. These devices also manage self refresh power consumption
when the operating temperature changes, resulting in the lowest possible power consumption across the operating temperature range. See the IDD Specification Parameters
and Operating Conditions table for details.
After the device has entered self refresh mode, all external signals other than CKE are
“Don’t Care.” For proper SELF REFRESH operation, power supply pins (VDD1, V DD2,
VDDQ, and V DDCA) must be at valid levels. V DDQ can be turned off during self refresh. If
VDDQ is turned off, V REFDQ must also be turned off. Prior to exiting self refresh, both
VDDQ and V REFDQ must be within their respective minimum/maximum operating ranges (see AC and DC Operating Conditions). V REFDQ can be at any level between 0 and
VDDQ; V REFCA can be at any level between 0 and V DDCA during self refresh.
Before exiting self refresh, V REFDQ and V REFCA must be within specified limits (see the AC
and DC Logic Input Measurement Levels for Single-Ended Signals section). After entering self refresh mode, the device initiates at least one all-bank REFRESH command internally during tCKESR. The clock is internally disabled during SELF REFRESH operation to save power. The device must remain in self refresh mode for at least tCKESR. The
user can change the external clock frequency or halt the external clock one clock after
self refresh entry is registered; however, the clock must be restarted and stable before
the device can exit SELF REFRESH operation.
Exiting self refresh requires a series of commands. First, the clock must be stable prior
to CKE returning HIGH. After the self refresh exit is registered, a minimum delay, at least
equal to the self refresh exit interval (tXSR), must be satisfied before a valid command
can be issued to the device. This provides completion time for any internal refresh in
progress. For proper operation, CKE must remain HIGH throughout tXSR. NOP commands must be registered on each rising clock edge during tXSR. For the description of
ODT operation and specifications during self-refresh entry and exit, see "On Die Termination" section.
Using self refresh mode introduces the possibility that an internally timed refresh event
could be missed when CKE is driven HIGH for exit from self refresh mode. Upon exiting
self refresh, at least one REFRESH command (one all-bank command or eight per-bank
commands) must be issued before issuing a subsequent SELF REFRESH command.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
SELF REFRESH Operation
Figure 40: SELF REFRESH Operation
2 tCK (MIN)
CK
tCPDED
tIHCKE
Input clock frequency can be changed
or clock can be stopped during self refresh.
tIHCKE
CKE
tISCKE
tISCKE
CS_n
tCKESR (MIN)
CMD
Valid Enter
SR
tXSR (MIN)
Exit
SR
NOP NOP
Enter self refresh mode
NOP NOP Valid
Exit self refresh mode
Don’t Care
1. Input clock frequency can be changed or stopped during self refresh, provided that
upon exiting self-refresh, a minimum of two cycles of stable clocks are provided, and the
clock frequency is between the minimum and maximum frequencies for the particular
speed grade.
2. The device must be in the all-banks-idle state prior to entering self refresh mode.
3. tXSR begins at the rising edge of the clock after CKE is driven HIGH.
4. A valid command can be issued only after tXSR is satisfied. NOPs must be issued during
tXSR.
Notes:
Partial-Array Self Refresh (PASR) – Bank Masking
LPDDR3 SDRAMs comprise eight banks. Each bank can be configured independently
whether or not a SELF REFRESH operation will occur in that bank. One 8-bit mode register (accessible via the MRW command) is assigned to program the bank-masking status of each bank up to eight banks. For bank-masking bit assignments, see the MR16
PASR Bank Mask (MA[7:0] = 010h) and MR16 Op-Code Bit Definitions tables.
The mask bit to the bank enables or disables a refresh operation of the entire memory
space within the bank. If a bank is masked using the bank-mask register, a REFRESH
operation to the entire bank is blocked, and bank data retention is not guaranteed in
self refresh mode. To enable a REFRESH operation to a bank, the corresponding bank
mask bit must be programmed as “unmasked.” When a bank mask bit is unmasked, the
array space being refreshed within that bank is determined by the programmed status
of the segment mask bits.
Partial-Array Self Refresh – Segment Masking
Programming segment-mask bits is similar to programming bank-mask bits. Eight segments are used for masking (see the MR17 PASR Segment Mask (MA[7:0] = 011h) and
MR17 PASR Segment Mask Definitions tables). A mode register is used for programming
segment-mask bits up to eight bits.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
SELF REFRESH Operation
When the mask bit to an address range (represented as a segment) is programmed as
“masked,” a REFRESH operation to that segment is blocked. Conversely, when a segment mask bit to an address range is unmasked, refresh to that segment is enabled.
A segment-masking scheme can be used in place of or in combination with a bankmasking scheme. Each segment mask bit setting is applied across all banks. For segment-masking bit assignments, see the MR17 PASR Segment Mask (MA[7:0] = 011h) and
MR17 PASR Segment Mask Definitions tables.
Table 54: Bank- and Segment-Masking Example
Segment Mask (MR17) Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Bank Mask (MR16)
0
1
0
0
0
0
0
1
Segment 0
0
–
M
–
–
–
–
–
M
Segment 1
0
–
M
–
–
–
–
–
M
Segment 2
1
M
M
M
M
M
M
M
M
Segment 3
0
–
M
–
–
–
–
–
M
Segment 4
0
–
M
–
–
–
–
–
M
Segment 5
0
–
M
–
–
–
–
–
M
Segment 6
0
–
M
–
–
–
–
–
M
Segment 7
1
M
M
M
M
M
M
M
M
Note:
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1. This table provides values for an eight-bank device with REFRESH operations masked to
banks 1 and 7 and to segments 2 and 7.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
MODE REGISTER READ
The MODE REGISTER READ (MRR) command is used to read configuration and status
data from SDRAM mode registers. The MRR command is initiated with CS_n LOW, CA0
LOW, CA1 LOW, CA2 LOW, and CA3 HIGH at the rising edge of the clock. The mode register is selected by CA1f–CA0f and CA9r–CA4r. The mode register contents are available
on the first data beat of DQ[7:0] after RL × tCK + tDQSCK + tDQSQ and following the rising edge of the clock where MRR is issued. Subsequent data beats contain valid but undefined content, except in the case of the DQ calibration function, where subsequent
data beats contain valid content as described in the Data Calibration Pattern Description table. All DQS are toggled for the duration of the mode register READ burst.
The MRR command has a burst length of eight. MRR operation (consisting of the MRR
command and the corresponding data traffic) must not be interrupted. The MRR command period is tMRR.
Figure 41: MRR Timing
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK_c
CK_t
RL = 8
CA[9:0]
Register
A
Register
A
Register
B
Register
B
tMRR
tMRR
CMD
MRR1
NOP2
NOP2
NOP2
MRR1
NOP2
NOP2
NOP2
Valid
Valid
Valid
Valid
Valid
Valid
Valid
DQS_c
DQS_t
DQ[7:0]3
DOUTA
DOUTB
DQ[MAX:8]
Transitioning data
Undefined
1. MRRs to DQ calibration registers MR32 and MR40 are described in the DQ Calibration
section.
2. Only the NOP command is supported during tMRR.
3. Mode register data is valid only on DQ[7:0] on the first beat. Subsequent beats contain
valid but undefined data. DQ[MAX:8] contain valid but undefined data for the duration
of the MRR burst.
4. Minimum MRR to write latency is RL + RU(tDQSCK (MAX)/tCK) + 8/2 + 1 - WL clock cycles.
5. Minimum MRR to MRW latency is RL + RU(tDQSCK (MAX)/tCK) + 8/2 + 1 clock cycles.
6. In this example, RL = 8 for illustration purposes only.
Notes:
After a prior READ command, the MRR command must not be issued before BL/2 clock
cycles have completed. Following a WRITE command, the MRR command must not be
issued before WL + 1 + BL/2 + RU( tWTR/tCK) clock cycles have completed, as READ
bursts and WRITE bursts must not be truncated my MRR.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
Figure 42: READ to MRR Timing
T0
T1
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Tx+7
Tx+8
Tx+9
CK_c
CK_t
RL
CA[9:0]
Bankm Col addr
col addr a
a
Register
B
Register
B
tMRR
CMD
READ
NOP1
NOP1
NOP1
NOP1
MRR
NOP1
NOP1
Valid
DQS_c
DQS_t
DQ[7:0]
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DQ[MAX:8]
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT B
Transitioning data
Notes:
Undefined
1. The minimum number of clock cycles from the burst READ command to the MRR command is BL/2.
2. Only the NOP command is supported during tMRR.
Figure 43: Burst WRITE Followed by MRR
T0
Tx
Tx+1
Tx+2
Tx+3
Tx+4
Tx+5
Tx+6
Ty
Ty+1
Ty+2
CK_c
CK_t
WL
CA[9:0]
Bankn
col addr a
RL
Col
addr a
Register
B
Register
B
t WTR
CMD
Valid
WRITE
tMRR
MRR1
NOP2
NOP2
DQS_c
DQS_t
DQ
DIN A0
DIN A1
DIN A2
DIN A3
DIN A4
DIN A5
DIN A6
DIN A7
Transitioning data
Notes:
1. The minimum number of clock cycles from the burst WRITE command to the MRR command is [WL + 1 + BL/2 + RU(tWTR/tCK)].
2. Only the NOP command is supported during tMRR.
MRR Following Idle Power-Down State
Following the idle power-down state, an additional time, tMRRI, is required prior to issuing the MODE REGISTER READ (MRR) command. This additional time (equivalent to
tRCD) is required in order to maximize power-down current savings by allowing more
power-up time for the MRR data path after exit from the idle power-down state.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
Figure 44: MRR After Idle Power-Down Exit
CK
tIHCKE
tCKE (MIN)
CKE
tISCKE
CS_n
tXP(MIN)
CMD
Exit
PD
tMRRI
NOP
NOP
Valid1
Valid1 Valid1
tMRR
MRR
Valid
Valid
Don’t Care
Exit power-down mode
1. Any valid command except MRR.
Note:
Temperature Sensor
LPDDR3 devices feature a temperature sensor whose status can be read from MR4. This
sensor can be used to determine an appropriate refresh rate, determine whether AC
timing derating is required in the extended temperature range, and/or monitor the operating temperature. Either the temperature sensor or the device operating temperature
can be used to determine whether operating temperature requirements are being met
(see the Operating Temperature Range table).
Temperature sensor data can be read from MR4 using the mode register read protocol.
Upon exiting self-refresh or power-down, the device temperature status bits will be no
older than tTSI.
When using the temperature sensor, the actual device case temperature may be higher
than the operating temperature specification that applies for the standard or extended
temperature ranges (see the Operating Temperature Range table). For example, T CASE
could be above 85°C when MR4[2:0] equals 011b.
To ensure proper operation using the temperature sensor, applications must accommodate the following table.
Table 55: Temperature Sensor Definitions and Operating Conditions
Parameter
Description
Symbol
Min/Max
Value
Unit
System temperature
gradient
Maximum temperature gradient experienced by the memory device at the temperature of interest over a range of 2°C
TempGradient
MAX
System-dependent
°C/s
MR4 READ interval
Time period between MR4 READs from the
system
ReadInterval
MAX
System-dependent
ms
Temperature sensor
interval
Maximum delay between internal updates
of MR4
tTSI
MAX
32
ms
System response
delay
Maximum response time from an MR4 READ
to the system response
SysRespDelay
MAX
System-dependent
ms
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER READ
Table 55: Temperature Sensor Definitions and Operating Conditions (Continued)
Parameter
Description
Device temperature
margin
Margin above maximum temperature to
support controller response
Symbol
Min/Max
Value
Unit
TempMargin
MAX
2
°C
These devices accommodate the temperature margin between the point at which the
device temperature enters the extended temperature range and the point at which the
controller reconfigures the system accordingly. To determine the required MR4 polling
frequency, the system must use the maximum TempGradient and the maximum response time of the system according to the following equation:
TempGradient × (ReadInterval + tTSI + SysRespDelay) ≤ 2°C
For example, if TempGradient is 10˚C/s, and the SysRespDelay is 1ms:
10°C × (ReadInterval + 32ms + 1ms) ≤ 2°C
s
In this case, ReadInterval must not exceed 167ms.
Figure 45: Temperature Sensor Timing
Temp
< (tTSI + ReadInterval + SysRespDelay)
Device
Temp
Margin
ient
Grad
Temp
2°C
MR4
Trip Level
tTSI
MR4 = 0x03
MR4 = 0x86
MR4 = 0x86
MR4 = 0x86
MR4 = 0x06
Time
Temperature sensor update
ReadInterval
Host MR4 READ
MRR MR4 = 0x03
SysRespDelay
MRR MR4 = 0x86
DQ Calibration
LPDDR3 devices feature a DQ calibration function that outputs one of two predefined
system timing calibration patterns. An MRR operation to MR32 (pattern A) or and MRR
operation to MR40 (pattern B) will return the specified pattern on DQ0 and DQ8—for
x32 devices, on DQ0, DQ8, DQ16 and DQ24.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
For x16 devices, DQ[7:1] and DQ[15:9] drive the same information as DQ0 during the
MRR burst. For x32 devices, DQ[7:1], DQ[15:9], DQ[23:17], and DQ[31:25] drive the
same information as DQ0 during the MRR burst. MRR DQ calibration commands can
occur only in the idle state.
Figure 46: MR32 and MR40 DQ Calibration Timing
T0
T1
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK_c
CK_t
RL = 6
CA[9:0] Reg 32 Reg 32
Reg 40 Reg 40
tMRR
CMD
MRR
tMRR
=4
NOP1
NOP1
NOP1
=4
NOP1
NOP
MRR
NOP1
NOP1
DQS_c
DQS_t
Pattern A
Pattern B
DQ0
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ[7:1]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ8
1
0
1
0
0
0
1
1
0
0
1
1
0
0
1
1
DQ[15:9]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ16
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ[23:17]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ24
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
DQ[31:25]
1
0
1
0
1
0
1
0
0
0
1
1
0
0
1
1
x16
x32
Transitioning data
Optionally driven the same as DQ0 or 0b
Table 56: Data Calibration Pattern Description
Pattern
MR#
Bit
Time
0
Bit
Time
1
Bit
Time
2
Bit
Time
3
Bit
Time
4
Bit
Time
5
Bit
Time
6
Bit
Time
7
Pattern
A
MR32
1
0
1
0
1
0
1
0
Reads to MR32 return DQ calibration pattern A
Pattern
B
MR40
0
0
1
1
0
0
1
1
Reads to MR40 return DQ calibration pattern B
MODE REGISTER WRITE
The MRW command is used to write configuration data to the mode registers. The
MRW command is initiated with CS_n LOW, CA0 LOW, CA1 LOW, CA2 LOW, and CA3
LOW at the rising edge of the clock. The mode register is selected by CA1f–CA0f, CA9r–
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
CA4r. The data to be written to the mode register is contained in CA9f–CA2f. The MRW
command period is defined by tMRW. Mode register writes to read-only registers have
no impact on the functionality of the device.
Figure 47: MODE REGISTER WRITE Timing
T0
T1
T2
Tx
Tx + 1
Tx + 2
Ty 1
Ty + 1
Ty + 2
CK_c
CK_t
tMRW
CA[9:0]
CMD
tMRW
MR addr MR data
MRW
MR addr MR data
NOP2
NOP2
NOP2
MRW
NOP2
Valid
1. At time Ty, the device is in the idle state.
2. Only the NOP command is supported during tMRW.
Notes:
MRW can be issued only when all banks are in the idle precharge state. One method of
ensuring that the banks are in this state is to issue a PRECHARGE ALL command.
MRW RESET Command
The MRW RESET command brings the device to the device auto initialization (resetting) state in the power-on initialization sequence (see the Voltage Ramp and Device Initialization section). The MRW RESET command can be issued from the idle state. This
command resets all mode registers to their default values. After MRW RESET, boot timings must be observed until the device initialization sequence is complete, and the device is in the idle state. Array data is undefined after the MRW RESET command.
If the initialization is to be performed at-speed (greater than the recommended boot
clock frequency), then CA training may be necessary to ensure setup and hold timings.
As the MRW RESET command is required prior to CA Training, an alternate MRW RESET command with an op-code of 0xFCh should be used. This encoding ensures that
no transitions occur on the CA bus. Prior to CA training, it is recommended to hold the
CA bus stable for one cycle prior to, and one cycle after, the issuance of the MRW RESET
command to ensure setup and hold timings on the CA bus.
For MRW RESET timing, see the figure below and see the Voltage Ramp and Initialization Sequence figure.
Table 57: Truth Table for MRR and MRW
Current State
Command
Intermediate State
Next State
MRR
Reading mode register, all banks idle
All banks idle
MRW
Writing mode register, all banks idle
All banks idle
MRW (RESET)
Resetting, device auto initialization
All banks idle
All banks idle
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Table 57: Truth Table for MRR and MRW (Continued)
Current State
Command
Intermediate State
Next State
Bank(s) active
MRR
Reading mode register, bank(s) active
Bank(s) active
MRW
Not allowed
Not allowed
MRW (RESET)
Not allowed
Not allowed
Figure 48: MODE REGISTER WRITE Timing for MRW RESET
Td
Td’
Te
CK_t
CK_c
CKE
CA[9:0]
FCh
CMD
FCh
FCh
Reg
B
FCh
MRW
(Optional)
MRW
Reg
B
MRR
tINIT3
tINIT4
CS_n
Optional CA/CMD
CMD not allowed
Optional CS_n
1. Optional MRW RESET command and optional CS_n assertion are allowed. When the optional MRW RESET command is used, tINIT4 starts at Td'.
Note:
MRW ZQ Calibration Commands
The MRW command is used to initiate a ZQ calibration command that calibrates output
driver impedance across process, temperature, and voltage. LPDDR3 devices support
ZQ calibration.
There are four ZQ calibration commands and related timings: tZQINIT, tZQRESET,
tZQCL, and tZQCS. tZQINIT is used for initialization calibration; tZQRESET is used for
resetting ZQ to the default output impedance; tZQCL is used for long calibration(s); and
tZQCS is used for short calibration(s). See the MR10 Calibration (MA[7:0] = 0Ah) table
for ZQ calibration command code definitions.
The initialization ZQ calibration (ZQINIT) must be performed for LPDDR3. ZQINIT provides an output impedance accuracy of ±15%. After initialization, the ZQ calibration
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
long (ZQCL) can be used to recalibrate the system to an output impedance accuracy of
±15%. A ZQ calibration short (ZQCS) can be used periodically to compensate for temperature and voltage drift in the system.
ZQRESET resets the output impedance calibration to a default accuracy of ±30% across
process, voltage, and temperature. This command is used to ensure output impedance
accuracy to ±30% when ZQCS and ZQCL commands are not used.
One ZQCS command can effectively correct at least 1.5% (ZQ correction) of output impedance errors within tZQCS for all speed bins, assuming the maximum sensitivities
specified in the Output Driver Sensitivity Definition and Output Driver Temperature
and Voltage Sensitivity tables are met. The appropriate interval between ZQCS commands can be determined using these tables and system-specific parameters.
LPDDR3 devices are subject to temperature drift rate (Tdriftrate) and voltage drift rate
(Vdriftrate) in various applications. To accommodate drift rates and calculate the necessary interval between ZQCS commands, apply the following formula:
ZQcorrection
(Tsens × Tdriftrate ) + (Vsens × Vdriftrate )
Where T sens = MAX (dRONdT) and V sens = MAX (dRONdV) define temperature and voltage sensitivities.
For example, if T sens = 0.75%/˚C, V sens = 0.20%/mV, T driftrate = 1˚C/sec, and V driftrate =
15 mV/sec, then the interval between ZQCS commands is calculated as:
1.5
= 0.4s
(0.75 × 1) + (0.20 × 15)
A ZQ calibration command can be issued only when the device is in the idle state with
all banks precharged.
No other activities can be performed on the data bus during calibration periods
(tZQINIT, tZQCL, or tZQCS). The quiet time on the data bus helps to accurately calibrate
output impedance. There is no required quiet time after the ZQRESET command. If
multiple devices share a single ZQ resistor, only one device can be calibrating at any given time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power
consumption.
In systems sharing a ZQ resistor among devices, the controller must prevent tZQINIT,
and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the
ZQ resistor is absent from the system, ZQ must be connected to V DDCA. In this situation,
the device must ignore ZQ calibration commands, and the device will use the default
calibration settings.
tZQCS,
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Figure 49: ZQ Timings
T0
T1
T2
T3
T4
T5
Tx
Tx + 1
Tx + 2
CK_c
CK_t
CA[9:0]
MR addr MR data
ZQINIT
tZQINIT
CMD
MRW
NOP
NOP
NOP
NOP
NOP
Valid
NOP
NOP
Valid
NOP
NOP
Valid
NOP
NOP
Valid
ZQCS
tZQCS
CMD
MRW
NOP
NOP
NOP
ZQCL
tZQCL
CMD
MRW
NOP
NOP
NOP
ZQRESET
tZQRESET
CMD
MRW
NOP
Notes:
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NOP
NOP
1. Only the NOP command is supported during ZQ calibration.
2. CKE must be registered HIGH continuously during the calibration period.
3. All devices connected to the DQ bus should be High-Z during the calibration process.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
ZQ External Resistor Value, Tolerance, and Capacitive Loading
To use the ZQ calibration function, a 240Ω (±1% tolerance) external resistor must be
connected between the ZQ pin and ground. A single resistor can be used for each device, or one resistor can be shared among multiple devices if the ZQ calibration timings
for each device do not overlap. The total capacitive loading on the ZQ pin must be limited (see the Input/Output Capacitance table).
MRW – CA Training Mode
Because CA inputs operate as double data rate, it may be difficult for the memory controller to satisfy CA input setup/hold timings at higher frequency. A CA training mechanism is provided.
CA Training Sequence
1. CA training mode entry: MODE REGISTER WRITE command to MR41
2. CA training session: Calibrate CA0, CA1, CA2, CA3, CA5, CA6, CA7 and CA8 (see the
CA Training Mode Enable [MR41] table)
3. CA to DQ mapping change: MODE REGISTER WRITE command to MR48
4. Additional CA training session: Calibrate remaining CA pins (CA4 and CA9) (see
the CA Training Mode Enable [MR48] table)
5. CA training mode exit: MODE REGISTER WRITE command to MR42
Figure 50: CA Training Timing
CK_t
CK_c
MRW#41, #48 MRW#41, #48 MRW#41, #48
(optional)4 (CA cal.Entry) (optional)4
MRW#42
(optional)4
CAx CAx CAx CAx
R
R#
R
R#
CA[9:0]
MRW#42
(CA cal.Exit)
MRW#42
(optional)4
CAy CAy CAx CAx
R
R#
R
R#
CS_n
CKE
tCACKEL
tCAMRD
tCAENT
tCACD
tADR
tADR
tCACKEH
tCAEXT
tMRZ
Even
DQ
CAx
R
CAy
R
Odd
DQ
CAx
R#
CAy
R#
Optional CA
Notes:
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Optional CS_n
Don’t Care
1. Unused DQ must be valid HIGH or LOW during data output period. Unused DQ may
transition at the same time as the active DQ. DQS must remain static and not transition.
2. CA to DQ mapping change via MR 48 omitted here for clarity of the timing diagram.
Both MR41 and MR48 training sequences must be completed before exiting the training
mode (MR42). To enable a CA to DQ mapping change, CKE must be driven HIGH prior to
issuance of the MRW 48 command. (See the steps in the CA Training Sequence section
for details.)
3. Because data-out control is asynchronous and will be an analog delay from when all the
CA data is available, tADR and tMRZ are defined from the falling edge of CK.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
4. It is recommended to hold the CA bus stable for one cycle prior to and one cycle after
the issuance of the MRW CA TRAINING ENTRY command to ensure setup and hold timings on the CA bus.
5. Optional MRW 41, 48, 42 commands and the CA CALIBRATION command are allowed.
To complement these optional commands, optional CS_n assertions are also allowed. All
timing must comprehend these optional CS_n assertions: a) tADR starts at the falling
clock edge after the last registered CS_n assertion; b) tCACD, tCACKEL, and tCAMRD start
with the rising clock edge of the last CS_n assertion; c) tCAENT and tCAEXT need to be
met by the first CS_n assertion; and d) tMRZ will be met after the falling clock edge following the first CS_n assertion with exit (MRW42) command.
6. Clock phase may be adjusted in CA training mode while CS_n is HIGH and CKE is LOW,
resulting in an irregular clock with shorter/longer periods and pulse widths.
The device may not properly recognize a MODE REGISTER WRITE command at normal
operation frequency before CA training is finished. Special encodings are provided for
CA training mode enable/disable.
MR41 and MR42 encodings are selected so that rising-edge and falling-edge values are
the same. The device will recognize MR41 and MR42 at normal operation frequency
even before CA timing adjustments have been made. Calibration data will be output
through DQ pins. CA to DQ mapping is described in the CA to DQ mapping (CA training
mode enabled with MR41) table.
After timing calibration with MR41 is finished, issue MRW to MR48 and calibrate the remaining CA pins (CA4 and CA9) using (DQ0/DQ1and DQ8/DQ9) as calibration data
output pins (see the CA to DQ mapping (CA training mode enabled with MR48) table).
Table 58: CA Training Mode Enable (MR41 (29H, 0010 1001b), OP = A4H (1010 0100b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
L
L
L
L
H
L
L
H
L
H
CK falling edge
L
L
L
L
H
L
L
H
L
H
Table 59: CA Training Mode Disable (MR42 (2AH, 0010 1010b), OP = A8H(1010 1000b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
L
L
L
L
L
H
L
H
L
H
CK falling edge
L
L
L
L
L
H
L
H
L
H
Table 60: CA to DQ Mapping (CA Training Mode Enabled with MR41)
Clock Edge
CA0
CA1
CA2
CA3
CA5
CA6
CA7
CA8
CK rising edge
DQ0
DQ2
DQ4
DQ6
DQ8
DQ10
DQ12
DQ14
CK falling edge
DQ1
DQ3
DQ5
DQ7
DQ9
DQ11
DQ13
DQ15
Note:
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1. Other DQs must have valid output (either HIGH or LOW).
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Table 61: CA Training Mode Enable (MR48 (30H, 0011 0000b), OP = C0H (1100 0000b))
Clock Edge
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK rising edge
L
L
L
L
L
L
L
L
H
H
CK falling edge
L
L
L
L
L
L
L
L
H
H
Table 62: CA to DQ Mapping (CA Training Mode Enabled with MR48)
Clock Edge
CA4
CA9
CK rising edge
DQ0
DQ8
CK falling edge
DQ1
DQ9
1. Other DQs must have valid output (either HIGH or LOW).
Note:
MRW - Write Leveling Mode
To improve signal integrity performance, the device provides a write-leveling feature to
compensate for timing skew, which affects timing parameters such as tDQSS, tDSS, and
tDSH.
The memory controller uses the write-leveling feature to receive feedback from the device, enabling it to adjust the clock-to-data strobe signal relationship for each DQS signal pair. The memory controller performing the leveling must have an adjustable delay
setting on the DQS signal pair to align the rising edge of DQS_t signals with that of the
clock signal at the DRAM pin. The device asynchronously feeds back CLK, sampled with
the rising edge of DQS_t signals. The controller repeatedly delays DQS_t signals until a
transition from 0 to 1 is detected. The DQS_t signal delay established through this exercise ensures the tDQSS specification can be met.
All data bits carry the leveling feedback to the controller (DQ[15:0] for x16 configuration, DQ[31:0] for x32 configuration). All DQS_t signals must be leveled independently.
The device enters write-leveling mode when mode register MR2[7] is set HIGH. When
entering write-leveling mode, the state of the DQ pins is undefined. During write-leveling mode, only NOP commands are allowed, or a MRW command to exit the write-leveling operation. Upon completion of the write-leveling operation, the device exits from
write-leveling mode when MR2[7] is reset LOW.
The controller drives DQS_t LOW and DQS_c HIGH after a delay of tWLDQSEN. After
time tWLMRD, the controller provides DQS_t signal input, which is used by the DRAM
to sample the clock signal driven from the controller. The delay time tWLMRD (MAX) is
controller-dependent. The DRAM samples the clock input with the rising edge of DQS_t
and provides asynchronous feedback on all the DQ bits after time tWLO. The controller
samples this information and either increments or decrements the DQS_t and/or
DQS_c delay settings and launches the next DQS_t/DQS_c pulse. The sample time and
trigger time are controller-dependent. After the following DQS_t/DQS_c transition is
sampled, the controller locks the strobe delay settings, and write leveling is achieved for
the device.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
MODE REGISTER WRITE
Figure 51: Write-Leveling Timing
tWLS
tWLH
tWLS
tWLH
CK_t
CK_c
CAs
CMD
CA
CA
MRW
CA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CA
MRW
NOP
NOP
NOP
Valid
tWLDQSEN
DQS_t
DQS_c
DQ
tWLMRD
tWLO
tDQSL
tWLO
tMRD
tDQSH
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
On-Die Termination (ODT)
On-die termination (ODT) is a feature that enables the device to enable/disable and
turn on/off termination resistance for each DQ, DQS, and DM signal via the ODT control pin. ODT is designed to improve signal integrity of the memory channel by enabling
the DRAM controller to independently turn on/off the internal termination resistance
for any or all DRAM devices. The ODT pin directly controls ODT operation and is not
sampled by the clock.
ODT is turned off and not supported in self refresh and deep power-down modes. The
device will also disable termination during READ operations. ODT operation can be enabled optionally during power-down mode via a mode register. Note that if ODT is enabled during power-down mode, V DDQ may not be turned off during power down. The
DRAM will also disable termination during READ operations.
A simple functional representation of the ODT feature is shown below.
Figure 52: Functional Representation of On-Die Termination
ODT
To other
circuitry
such as
RCV,
...
VDDQ
RTT
Switch
DQ, DQS, DM
The switch is enabled by the internal ODT control logic, which uses the external ODT
pin and other control information. The value of R TT (ODT termination resistance value)
is determined by the settings of several mode register bits. The ODT pin will be ignored
if MR11 is programmed to disable ODT in self refresh, in deep power-down, in CKE
power-down (mode register option), and during READ operations.
ODT Mode Register
ODT mode is enabled if MR11[1:0] are non-zero. In this case, the value of RTT is determined by the settings of those bits. ODT mode is disabled if MR11[1:0] are zero.
MR11[2] determines whether ODT will operate during power-down mode if enabled
through MR11[1:0].
Asychronous ODT
When enabled, the ODT feature is controlled asynchronously based on the status of the
ODT pin. ODT is off under any of the following conditions:
•
•
•
•
•
ODT is disabled through MR11[1:0]
Device is performing a READ operation (READ or MRR)
Device is in power-down mode and MR11[2] is zero
Device is in self refresh or deep power-down mode
Device is in CA training mode
In asynchronous ODT mode, the following timing parameters apply when ODT operation is controlled by the ODT pin tODToff, tODTon.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
Minimum RTT turn-on time (tODTon [MIN]) is the point in time when the device termination circuit leaves High-Z state and ODT resistance begins to turn on. Maximum RTT
turn-on time (tODTon,max) is the point in time when ODT resistance is fully on. tODTon (MIN) and tODTon (MAX) are measured from ODT pin HIGH.
Minimum RTT turn-off time (tODToff [MIN]) is the point in time when the device termination circuit starts to turn off the ODT resistance. Maximum ODT turn off time (tODToff [MAX]) is the point in time when the on-die termination has reached High-Z. tODToff,min and tODToff (MAX) are measured from ODT pin LOW.
ODT During READ Operations (READ or MRR)
During READ operations, the device will disable termination and disable ODT control
through the ODT pin. After READ operations are completed, ODT control is resumed
through the ODT pin (if ODT mode is enabled).
ODT During Power-Down
When MR11[2] is zero, termination control through the ODT pin will be disabled when
the DRAM enters power-down. After a power-down entry is registered, termination will
be disabled within a time window specified by tODTd (MIN) (MAX). ODT pin control is
resumed when power-down is exited (if ODT mode is enabled). Between the POWERDOWN EXIT command and until tXP is satisfied, termination will transition from disabled to control by the ODT pin. When tXP is satisfied, the ODT pin is used to control
termination.
Minimum RTT disable time (tODTd [MIN]) is the point in time when the device termination circuit is no longer controlled by the ODT pin. Maximum ODT disable time (tODTd
[MAX]) is the point in time when ODT will be in High-Z.
When MR11[2] is enabled and MR11[1:0] are non-zero, ODT operation is supported
during CKE power-down with ODT control through the ODT pin.
ODT During Self Refresh
The device disables the ODT function during self refresh. After a SELF REFRESH command is registered, termination will be disabled within a time window specified by
tODTd (MIN) (MAX). During self refresh exit, ODT control through the ODT pin is resumed (if ODT mode is enabled). Between the SELF REFRESH EXIT command and until
tXSR is satisfied, termination will transition from disabled to control by the ODT pin.
When tXSR is satisfied, the ODT pin is used to control termination.
ODT During Deep Power-Down
The device disables the ODT function during deep power-down. After a DEEP POWERDOWN command is registered, termination will be disabled within a time window
specified by tODTd (MIN) (MAX).
ODT During CA Training and Write Leveling
During CA training mode, the device will disable ODT and ignore the state of the ODT
control pin. For ODT operation during write leveling mode, refer to the DRAM Termination Function in Write-Leveling Mode table for termination activation and deactivation
for DQ and DQS_t/DQS_c. If ODT is enabled, the ODT pin must be HIGH in write leveling mode.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
Table 63: DRAM Termination Function in Write-Leveling Mode
ODT Pin
DQS Termination
DQ Termination
De-asserted
OFF
OFF
Asserted
ON
OFF
Table 64: ODT States Truth Table
Write
Read/DQ
Calibration
ZQ
Calibration
CA
Training
Write
Leveling
DQ
termination
Enabled
Disabled
Disabled
Disabled
Disabled
DQS
termination
Enabled
Disabled
Disabled
Disabled
Enabled
Figure 53: Asynchronous ODT Timing – RL = 12
T0
T1
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CK_t,
CK_c
Col add
CA[9:0]
Bank n
Col add
CMD
READ
RL = 12
DQS_t,
DQS_c
DO
0
DQ
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
tDQSCK
ODT
DRAM_RTT
ODTon
ODToff
tODToff
tODTon
(MIN)
tODToff
(MIN)
tODTon
(MIN)
(MAX)
Don’t Care
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
On-Die Termination (ODT)
Figure 54: Automatic ODT Timing During READ Operation – RL = m
T0
T1
Tm-3
Tm-2
Tm-1
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+8
Tm+9
CK_t,
CK_c
Col add
CA[9:0]
Bank n
Col add
CMD
READ
RL = m
tHZ(DQS)
BL/2
DQS_t,
DQS_c
DO
0
DQ
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
tDQSCK
ODT
ODTon
DRAM_RTT
ODToff
tAODToff
ODTon
tAODTon
Don’t Care
Notes:
1. The automatic RTT turn-off delay, tAODToff, is referenced from the rising edge of RL - 2
clock at Tm-2.
2. The automatic RTT turn-on delay, tAODTon, is referenced from the rising edge of RL +
BL/2 clock at Tm+4.
Figure 55: ODT Timing During Power-Down, Self Refresh, Deep Power-Down Entry/Exit
T0
T1
T2
T3
Tm-1
Tm-2
Tm
Tm+1
Tm+2
Tn
CK_t,
CK_c
CKE
ODT
DRAM_RTT
ODTon
ODToff
tODTd
ODTon
tODTe
Don’t Care
Note:
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1. Upon exiting of deep power-down mode, a complete power-up initialization sequence
is required.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Power-Down
Power-down is entered synchronously when CKE is registered LOW and CS_n is HIGH
at the rising edge of clock. A NOP command must be driven in the clock cycle following
the POWER-DOWN command. CKE must not go LOW while MRR, MRW, READ, or
WRITE operations are in progress. CKE can go LOW while any other operations, such as
ROW ACTIVATION, PRECHARGE, AUTO PRECHARGE, or REFRESH are in progress, but
the power-down IDD specification is not applied until such operations are complete.
Entering power-down deactivates the input and output buffers, excluding CKE. To ensure enough time to account for internal delay on the CKE signal path, two NOP commands are required after CKE is driven LOW. this timing period is defined as tCPDED.
CKE LOW results in deactivation of input receivers after tCPDED has expired. In powerdown mode, CKE must be held LOW; all other input signals are “Don’t Care.” CKE LOW
must be maintained until tCKE is satisfied, and V REFCA must be maintained at a valid
level during power-down.
VDDQ can be turned off during power-down. If V DDQ is turned off, V REFDQ must also be
turned off. Prior to exiting power-down, both V DDQ and V REFDQ must be within their respective minimum/maximum operating ranges (see the AC and DC Operating Conditions section).
No refresh operations are performed in power-down mode. The maximum duration in
power-down mode is only limited by the refresh requirements outlined in the REFRESH
Command section.
The power-down state is exited when CKE is registered HIGH. The controller must drive
CS_n HIGH in conjunction with CKE HIGH when exiting the power-down state. CKE
HIGH must be maintained until tCKE is satisfied. A valid, executable command can be
applied with power-down exit latency tXP after CKE goes HIGH. Power-down exit latency is defined in the AC Timing table.
If power-down occurs when all banks are idle, this mode is referred to as idle powerdown; if power-down occurs when a row is active in any bank, this mode is referred to
as active power-down. For the description of ODT operation and specifications during
power-down entry and exit, see the On-Die Termination section.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 56: Power-Down Entry and Exit Timing
2 tCK (MIN)
CK
tCPDED
Input clock frequency can be changed
1
or the input clock can be stopped during power-down.
tIHCKE
tIHCKE
tCKE
(MIN)
CKE
tISCKE
tISCKE
CS_n
tCKE
tXP
(MIN)
Exit
PD
CMD Valid Enter
NOP NOP
PD
(MIN)
NOP NOP Valid
Exit power-down mode
Enter power-down mode
Don’t Care
Note:
1. Input clock frequency can be changed or the input clock stopped during power-down,
provided that the clock frequency is between the minimum and maximum specified frequencies for the speed grade in use and that prior to power-down exit, a minimum of
two stable clocks complete.
Figure 57: CKE Intensive Environment
CK_c
CK_t
tCKE
tCKE
tCKE
tCKE
CKE
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 58: REFRESH to REFRESH Timing in CKE Intensive Environments
CK_c
CK_t
tCKE
tCKE
tCKE
tCKE
CKE
tXP
tXP
tREFI
CMD
REFRESH
Note:
REFRESH
1. The pattern shown can repeat over an extended period of time. With this pattern, all
AC and DC timing and voltage specifications with temperature and voltage drift are ensured.
Figure 59: READ to Power-Down Entry
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
RL
tISCKE
CKE1, 2
CMD
READ
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS_c
DQS_t
Notes:
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1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at {RL + RU[tDQSCK(MAX)/tCK] + BL/2 + 1} clock cycles after
the clock on which the READ command is registered.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 60: READ with Auto Precharge to Power-Down Entry
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
Tx + 6
Tx + 7
Tx + 8
Tx + 9
CK_c
CK_t
tISCKE
BL/23
RL
CKE1, 2
CMD
PRE4
READ w/AP
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS_c
DQS_t
Notes:
1. CKE must be held HIGH until the end of the burst operation.
2. CKE can be registered LOW at [RL + RU(tDQSCK/tCK) + BL/2 + 1] clock cycles after the
clock on which the READ command is registered.
3. BL/2 with tRTP = 7.5ns and tRAS (MIN) is satisfied.
4. Start internal PRECHARGE.
Figure 61: WRITE to Power-Down Entry
T0
T1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
CK_c
CK_t
WL
tISCKE
BL/2
CKE1
tWR
CMD
WRITE
DIN
DQ
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQS_c
DQS_t
Note:
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1. CKE can be registered LOW at [WL + 1 + BL/2 + RU(tWR/tCK)] clock cycles after the clock
on which the WRITE command is registered.
94
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 62: WRITE with Auto Precharge to Power-Down Entry
T0
T1
Tm
Tm + 1
Tm + 2
Tm + 3
Tm + 4
Tm + 5
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
CK_c
CK_t
WL
tISCKE
BL/2
CKE1
tWR
CMD
PRE2
WRITE w/AP
DQ
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DQS_c
DQS_t
1. CKE can be registered LOW at [WL + 1 + BL/2 + RU(tWR/tCK) + 1] clock cycles after the
WRITE command is registered.
2. Start internal PRECHARGE.
Notes:
Figure 63: REFRESH Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
REFRESH
Note:
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1. CKE can go LOW tIHCKE after the clock on which the REFRESH command is registered.
95
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Power-Down
Figure 64: ACTIVATE Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
ACTIVATE
1. CKE can go LOW at tIHCKE after the clock on which the ACTIVATE command is registered.
Note:
Figure 65: PRECHARGE Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tIHCKE
CMD
PRE
Note:
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1. CKE can go LOW tIHCKE after the clock on which the PRECHARGE command is registered.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Deep Power-Down
Figure 66: MRR Power-Down Entry
CK_c
T0
T1
T2
Tx
Tx + 1
Tx + 2
Tx + 3
Tx + 4
Tx + 5
CK_t
Tx + 6
Tx + 7
Tx + 8
Tx + 9
tISCKE
RL
CKE1
CMD
MRR
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DQ
DQS_c
DQS_t
1. CKE can be registered LOW at [RL + RU(tDQSCK/tCK)+ BL/2 + 1] clock cycles after the
clock on which the MRR command is registered.
Note:
Figure 67: MRW Command to Power-Down Entry
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK_c
CK_t
tISCKE
CKE1
tMRW
CMD
MRW
1. CKE can be registered LOW tMRW after the clock on which the MRW command is registered.
Note:
Deep Power-Down
Deep power-down (DPD) is entered when CKE is registered LOW with CS_n LOW, CA0
HIGH, CA1 HIGH, and CA2 LOW at the rising edge of the clock. All banks must be in the
idle state with no activity on the data bus prior to entering DPD mode. During DPD,
CKE must be held LOW. The contents of the device will be lost upon entering DPD
mode.
In DPD mode, all input buffers except CKE, all output buffers, and the power supply to
internal circuitry are disabled within the device. To ensure that there is enough time to
account for internal delay on the CKE signal path, two NOP commands are required after CKE is driven LOW; this timing period is defined as tCPDED. CKE LOW will result in
deactivation of command and address receivers after tCPDED has expired. V REFDQ can
be at any level between 0 and V DDQ, and V REFCA can be at any level between 0 and V DDCA
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Input Clock Frequency Changes and Stop Events
during DPD. All power supplies, including V REF, must be within the specified limits prior to exiting DPD (see AC and DC Operating Conditions).
DPD mode is exited when CKE is registered HIGH while meeting tISCKE, and the clock
must be stable. The device must be fully reinitialized using the power-up initialization
sequence. For a description of ODT operation and specifications during DPD entry and
exit, see the ODT During Deep Power-Down section.
Figure 68: Deep Power-Down Entry and Exit Timing
CK
tIHCKE
tCPDED
Input clock frequency can be changed
or the input clock can be stopped during DPD.
2 tCK (MIN)
tINIT31, 2
CKE
tISCKE
tISCKE
CS_n
tRP
CMD
tDPD
NOP Enter
DPD NOP
Exit
DPD
NOP
Exit DPD mode
Enter DPD mode
NOP
RESET
Don’t Care
1. The initialization sequence can start at any time after Tx + 1.
2. tINIT3 and Tx + 1 refer to timings in the initialization sequence. For details, see the
Mode Register Definition section.
Notes:
Input Clock Frequency Changes and Stop Events
Input Clock Frequency Changes and Clock Stop with CKE LOW
During CKE LOW, the device supports input clock frequency changes and clock stop
under the following conditions:
• Refresh requirements are met
• Only REFab or REFpb commands can be in process
• Any ACTIVATE or PRECHARGE commands have completed prior to changing the frequency
• Related timing conditions, tRCD and tRP, have been met prior to changing the frequency
• The initial clock frequency must be maintained for a minimum of two clock cycles after CKE goes LOW
• The clock satisfies tCH(abs) and tCL(abs) for a minimum of two clock cycles prior to
CKE going HIGH
For input clock frequency changes, tCK (MIN) and tCK (MAX) must be met for each
clock cycle.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
NO OPERATION Command
After the input clock frequency changes and CKE is held HIGH, additional MRW commands may be required to set the WR, RL, and so on. These settings may require adjustment to meet minimum timing requirements at the target clock frequency.
For clock stop, CK_t is held LOW and CK_c is held HIGH.
Input Clock Frequency Changes and Clock Stop with CKE HIGH
During CKE HIGH, the device supports input clock frequency changes and clock stop
under the following conditions:
• Refresh requirements are met
• Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands have completed, including any associated data bursts, prior to changing the frequency
• Related timing conditions, tRCD, tWR, tWRA, tRP, tMRW, tMRR, and so on, are met
• CS_n must be held HIGH
• Only REFab or REFpb commands can be in process
The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs)
for a minimum of 2 × tCK + tXP.
After the input clock frequency changes, tCK (MIN) and tCK (MAX) must be met for
each clock cycle.
After the input clock frequency changes, additional MRW commands may be required
to set the WR, RL, and so on. These settings may require adjustment to meet minimum
timing requirements at the target clock frequency.
For clock stop, CK_t is held LOW and CK_c is held HIGH.
NO OPERATION Command
The NO OPERATION (NOP) command prevents the device from registering any unwanted commands issued between operations. A NOP command can be issued only at
clock cycle n when the CKE level is constant for clock cycle n - 1 and clock cycle n. A
NOP command has two possible encodings:
1. CS_n HIGH at the clock rising edge n.
2. CS_n LOW with CA0, CA1, CA2 HIGH at the clock rising edge n.
The NOP command does not terminate a previous operation that is still in process,
such as a READ burst or WRITE burst cycle.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Truth Tables
Truth tables provide complementary information to the state diagram. They also clarify
device behavior and applicable restrictions when considering the actual state of the
banks.
Unspecified operations and timings are illegal. To ensure proper operation after an illegal event, the device must be powered down and then restarted using the specified initialization sequence before normal operation can continue.
Table 65: Command Truth Table
Notes 1–13 apply to entire table
Command Pins
CKE
Command
MRW
MRR
CK(n-1)
CK(n)
CS_
n
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
H
H
L
L
L
L
L
MA0
MA1
MA2
MA3
MA4
MA5
X
MA6
MA7
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
L
L
L
L
H
MA0
MA1
MA2
MA3
MA4
MA5
X
MA6
MA7
L
L
L
H
REFRESH
(per bank)
H
REFRESH
(all banks)
H
Enter self refresh
H
ACTIVATE
(bank)
H
WRITE (bank)
H
READ (bank)
H
H
H
L
H
L
X
X
L
L
H
H
X
X
L
X
H
H
ENTER DPD
H
L
X
L
L
H
H
H
H
X
L
L
H
R8
R9
R10
R11
R12
BA0
BA1
BA2
X
R0
R1
R2
R3
R4
R5
R6
R7
R13
R14
L
H
L
L
RFU
RFU
C1
C2
BA0
BA1
BA2
X
AP
C3
C4
C5
C6
C7
C8
C9
C10
C11
L
H
L
H
RFU
RFU
C1
C2
BA0
BA1
BA2
X
AP
C3
C4
C5
C6
C7
C8
C9
C10
C11
L
H
H
L
H
AB
X
X
BA0
BA1
BA2
X
L
X
H
L
X
H
H
L
X
H
L
L
NOP
H
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L
H
L
X
X
H
H
H
X
MAINTAIN PD,
SREF, DPD
(NOP)
X
X
H
CK
Edge
X
X
PRECHARGE
(per bank, all
banks)
NOP
CA Pins
X
X
H
H
H
X
X
X
H
X
X
X
100
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 65: Command Truth Table (Continued)
Notes 1–13 apply to entire table
Command Pins
CKE
CA Pins
CK(n-1)
CK(n)
CS_
n
MAINTAIN PD,
SREF, DPD
L
L
X
X
X
X
ENTER POWER-DOWN
H
H
X
X
X
Exit PD, SREF,
DPD
L
H
X
X
X
Command
L
X
H
X
Notes:
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK
Edge
1. All commands are defined by the current state of CS_n, CA0, CA1, CA2, CA3, and CKE at
the rising edge of the clock.
2. Bank addresses (BA) determine which bank will be operated upon.
3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur
to the bank associated with the READ or WRITE command.
4. X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L).
For PD, SREF and DPD, CS_n, CK can be floated after tCPDED has been met and until the
required exit procedure is initiated as described in their respective entry/exit procedures.
5. Self refresh exit and DPD exit are asynchronous.
6. VREF must be between 0 and VDDQ during SREF and DPD operation.
7. CAxr refers to command/address bit “x” on the rising edge of clock.
8. CAxf refers to command/address bit “x” on the falling edge of clock.
9. CS_n and CKE are sampled on the rising edge of the clock.
10. The least significant column address C0 is not transmitted on the CA bus, and is inferred
to be zero.
11. AB HIGH during a PRECHARGE command indicates that an all-bank precharge will occur.
In this case, bank address is a "Don't Care."
12. RFU needs to input H or L (defined logic level).
13. When CS_n is HIGH, the CA bus can be floated.
Table 66: CKE Truth Table
Notes 1–5 apply to entire table; L = LOW; H = HIGH; X = “Don’t Care”
Command
n
Current State
CKEn-1
CKEn
CS_n
Active
power-down
Idle power-down
Resetting idle
power-down
L
L
X
X
L
H
H
NOP
L
L
X
X
L
H
H
NOP
L
L
X
X
L
H
H
NOP
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Operation n
Maintain active power-down
Exit active power-down
Maintain idle power-down
Exit idle power-down
Maintain resetting power-down
Exit resetting power-down
101
Next State
Notes
Active
power-down
Active
6, 7
Idle
power-down
Idle
6, 7
Resetting
power-down
Idle or resetting 6, 7, 8
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 66: CKE Truth Table (Continued)
Notes 1–5 apply to entire table; L = LOW; H = HIGH; X = “Don’t Care”
Command
n
Current State
CKEn-1
CKEn
CS_n
Deep powerdown
Self refresh
L
L
X
X
L
H
H
NOP
Operation n
Next State
Maintain deep power-down
Exit deep power-down
Deep
power-down
Power-on
9
L
L
X
X
L
H
H
NOP
Exit self refresh
Bank(s) active
H
L
H
NOP
Enter active power-down
Active
power-down
All banks idle
H
L
H
NOP
Enter idle power-down
Idle
power-down
12
H
L
L
Self refresh
12
H
L
L
DPD
Enter deep power-down
Deep
power-down
12
Resetting
H
L
H
NOP
Enter resetting power-down
Resetting
power-down
Other states
H
H
Notes:
Maintain self refresh
Notes
Self refresh
Idle
ENTER SELF Enter self refresh
REFRESH
10, 11
Refer to the command truth table
1. Current state is the state of the device immediately prior to clock edge n.
2. All states and sequences not shown are illegal or reserved unless explicitly described
elsewhere in this document.
3. CKEn is the logic state of CKE at clock rising edge n; CKEn-1 was the state of CKE at the
previous clock edge.
4. CS_n is the logic state of CS_n at the clock rising edge n.
5. Command n is the command registered at clock edge n, and operation n is a result of
command n.
6. Power-down exit time (tXP) must elapse before any command other than NOP is issued.
7. The clock must toggle at least twice prior to the tXP period.
8. Upon exiting the resetting power-down state, the device will return to the idle state if
tINIT5 has expired.
9. The DPD exit procedure must be followed as described in Deep Power-Down.
10. Self refresh exit time (tXSR) must elapse before any command other than NOP is issued.
11. The clock must toggle at least twice prior to the tXSR time.
12. In the case of ODT disabled, all DQ output must be High-Z. In the case of ODT enabled,
all DQ must be terminated to VDDQ.
Table 67: Current State Bank n to Command to Bank n Truth Table
Notes 1–5 apply to entire table
Current State
Command
Any
NOP
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Operation
Next State
Continue previous operation
102
Notes
Current state
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 67: Current State Bank n to Command to Bank n Truth Table (Continued)
Notes 1–5 apply to entire table
Current State
Command
Idle
ACTIVATE
REFRESH (all banks)
Active
Begin to refresh
Refreshing (per bank)
6
Begin to refresh
Refreshing (all banks)
7
MR writing
7
Load value to mode register
MRR
Read value from mode register
Idle, MR reading
RESET
Begin device auto initialization
Resetting
7, 8
9, 10
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
READ
Select column and start read burst
Reading
WRITE
Select column and start write burst
Writing
Read value from mode register
PRECHARGE
Writing
Notes
MRW
MRR
Reading
Next State
Select and activate row
REFRESH (per bank)
Row active
Operation
Active MR reading
Precharging
9
READ
Deactivate row(s) in bank or banks
Select column and start new read burst
Reading
11, 12
WRITE
Select column and start write burst
Writing
11, 12, 13
WRITE
Select column and start new write burst
Writing
11, 12
READ
Select column and start read burst
Reading
11, 12, 14
Power-on
MRW RESET
Begin device auto initialization
Resetting
7, 9
Resetting
MRR
Read value from mode register
Resetting MR reading
Notes:
1. Values in this table apply when both CKEn -1 and CKEn are HIGH, and after tXSR or tXP
has been met, if the previous state was power-down.
2. All states and sequences not shown are illegal or reserved.
3. Current state definitions:
State
Definition
Idle
The bank or banks have been precharged, and tRP has been met.
Active
A row in the bank has been activated, and tRCD has been met. No data bursts or accesses, and no register accesses, are in progress.
Reading
A READ burst has been initiated with auto precharge disabled, and
has not yet terminated.
Writing
A WRITE burst has been initiated with auto precharge disabled, and
has not yet terminated.
4. The states listed below must not be interrupted by a command issued to the same bank.
NOP commands or supported commands to the other bank should be issued on any
clock edge occurring during these states. Supported commands to the other banks are
determined by that bank’s current state, and the definitions given in the table: Current
State Bank n to Command to Bank m.
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Ends
when...
State
Starts with...
Precharging
Registration of a PRECHARGE command
Row activating
Registration of an ACTIVATE tRCD is met
command
103
tRP
is met
Notes
After tRP is met, the bank is
in the idle state.
After tRCD is met, the bank
is in the active state.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Ends
when...
State
Starts with...
READ with
AP enabled
Registration of a READ com- tRP is met
mand with auto precharge
enabled
WRITE with
AP enabled
Registration of a WRITE
command with auto precharge enabled
tRP
is met
Notes
After tRP is met, the bank is
in the idle state.
After tRP is met, the bank is
in the idle state.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied to each positive clock edge during these states.
State
6.
7.
8.
9.
10.
11.
12.
13.
14.
Ends
when...
Starts with...
Refreshing
(per bank)
Registration of a REFRESH
(per bank) command
tRFCpb
Refreshing
(all banks)
Registration of a REFRESH
(all banks) command
tRFCab
Notes
is met After tRFCpb is met, the
bank is in the idle state.
is met After tRFCab is met, the device is in the all banks idle
state.
Idle MR read- Registration of the MRR
ing
command
tMRR
is met
After tMRR is met, the device is in the all banks idle
state.
Resetting MR Registration of the MRR
reading
command
tMRR
is met
After tMRR is met, the device is in the all banks idle
state.
Active MR
reading
Registration of the MRR
command
tMRR
is met
After tMRR is met, the bank
is in the active state.
MR writing
Registration of the MRW
command
tMRW
Precharging
all
Registration of a PRECHARGE ALL command
tRP
is met After tMRW is met, the device is in the all banks idle
state.
is met
After tRP is met, the device
is in the all banks idle state.
Bank-specific; requires that the bank is idle and no bursts are in progress.
Not bank-specific; requires that all banks are idle and no bursts are in progress.
Not bank-specific.
This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
If a PRECHARGE command is issued to a bank in the idle state, tRP still applies.
A command other than NOP should not be issued to the same bank while a READ or
WRITE with auto precharge is enabled.
The new READ or WRITE command could be auto precharge enabled or auto precharge
disabled.
A WRITE command can be issued only after the completion of the READ burst.
A READ command can be issued only after completion of the WRITE burst.
Table 68: Current State Bank n to Command to Bank m Truth Table
Notes 1–6 apply to entire table
Current State
of Bank n
Command to Bank m
Operation
Next State for Bank m
Any
NOP
Continue previous operation
Idle
Any
Any command supported to bank m
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104
Notes
Current state of bank m
–
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
Table 68: Current State Bank n to Command to Bank m Truth Table (Continued)
Notes 1–6 apply to entire table
Current State
of Bank n
Command to Bank m
Row activating,
active, or precharging
ACTIVATE
Writing
(auto precharge
disabled)
Reading with
auto precharge
Writing with
auto precharge
Next State for Bank m
Notes
Active
6
Select and activate row in bank m
READ
Select column and start READ burst
from bank m
Reading
7
WRITE
Select column and start WRITE burst to
bank m
Writing
7
Precharging
8
Idle MR reading or active
MR reading
9, 10, 11
PRECHARGE
Reading
(auto precharge
disabled)
Operation
Deactivate row(s) in bank or banks
MRR
READ value from mode register
READ
Select column and start READ burst
from bank m
Reading
7
WRITE
Select column and start WRITE burst to
bank m
Writing
7, 12
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
READ
Select column and start READ burst
from bank m
Reading
7, 13
WRITE
Select column and start WRITE burst to
bank m
Writing
7
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
READ
Select column and start READ burst
from bank m
Reading
7, 14
WRITE
Select column and start WRITE burst to
bank m
Writing
7, 12, 14
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
READ
Select column and start READ burst
from bank m
Reading
7, 13, 14
WRITE
Select column and start WRITE burst to
bank m
Writing
7, 14
ACTIVATE
Select and activate row in bank m
Active
PRECHARGE
Deactivate row(s) in bank or banks
Precharging
8
Power-on
MRW RESET
Begin device auto initialization
Resetting
15, 16
Resetting
MRR
Read value from mode register
Resetting MR reading
Notes:
1. This table applies when:
• The previous state was self refresh or power-down;
• After tXSR or tXP has been met; and
• When both CKEn -1 and CKEn are HIGH.
2. All states and sequences not shown are illegal or reserved.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Truth Tables
3. Current state definitions:
State
Condition
And…
Idle
The bank has been precharged
tRP
And…
Active
A row in the bank has been
activated
tRCD
Reading
A READ burst has been initi- The READ
has not yet
ated with auto precharge
terminated
disabled
Writing
A WRITE burst has been ini- The WRITE
tiated with auto precharge has not yet
disabled
terminated
is met
is met
No data bursts/accesses and
no register accesses are in
progress.
4. Refresh, self refresh, and MRW commands can only be issued when all banks are idle.
5. The states listed below must not be interrupted by any executable command. NOP commands must be applied during each clock cycle while in these states:
State
Ends
when...
Starts with...
Notes
Idle MR read- Registration of the MRR
ing
command
tMRR
is met
After tMRR is met, the device is in the all banks idle
state.
Resetting MR Registration of the MRR
reading
command
tMRR
is met
After tMRR is met, the device is in the all banks reset
state.
Active MR
reading
Registration of the MRR
command
tMRR
is met
After tMRR is met, the bank
is in the active state.
MR writing
Registration of the MRW
command
tMRW
is met After tMRW is met, the device is in the all banks idle
state.
6. tRRD must be met between the ACTIVATE command to bank n and any subsequent
ACTIVATE command to bank m.
7. READs or WRITEs listed in the command column include READs and WRITEs with or
without auto precharge enabled.
8. This command may or may not be bank-specific. If all banks are being precharged, they
must be in a valid state for precharging.
9. MRR is supported in the row-activating state.
10. MRR is supported in the precharging state.
11. The next state for bank m depends on the current state of bank m (idle, row-activating,
precharging, or active).
12. A WRITE command can be issued only after the completion of the READ burst.
13. A READ command can be issued only after the completion of the WRITE burst.
14. A READ with auto precharge enabled or a WRITE with auto precharge enabled can be
followed by any valid command to other banks, provided that the timing restrictions in
the PRECHARGE and Auto Precharge Clarification table are met.
15. Not bank-specific; requires that all banks are idle and no bursts are in progress.
16. RESET command is achieved through the MODE REGISTER WRITE command.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Absolute Maximum Ratings
Table 69: DM Truth Table
Functional Name
DM
DQ
Notes
Write enable
L
Valid
1
Write inhibit
H
X
1
1. Used to mask write data; provided simultaneously with the corresponding input data.
Note:
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these conditions, or any other conditions outside those indicated in the operational sections of this document, is
not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
Table 70: Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Unit
Notes
VDD1 supply voltage relative to VSS
VDD1
–0.4
2.3
V
1
VDD2 supply voltage relative to VSS
VDD2
–0.4
1.6
V
1
VDDCA supply voltage relative to VSSCA
VDDCA
–0.4
1.6
V
1, 2
VDDQ supply voltage relative to VSSQ
VDDQ
–0.4
1.6
V
1, 3
VIN, VOUT
–0.4
1.6
V
TSTG
–55
125
˚C
Voltage on any ball relative to VSS
Storage temperature
Notes:
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4
1. For information about relationships between power supplies, see the Power-Up and Initialization section.
2. VREFCA ≤ 0.6 × VDDCA; however, VREFCA may be ≥ VDDCA, provided that VREFCA ≤ 300mV.
3. VREFDQ ≤ 0.7 × VDDQ; however, VREFDQ may be ≥ VDDQ, provided that VREFDQ ≤ 300mV.
4. Storage temperature is the case surface temperature on the center/top side of the device. For measurement conditions, refer to the JESD51-2 standard.
107
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
Electrical Specifications – IDD Measurements and Conditions
The following definitions and conditions are used in the IDD measurement tables unless
stated otherwise:
•
•
•
•
LOW: V IN ≤ V IL(DC)max
HIGH: V IN ≥ V IH(DC)min
STABLE: Inputs are stable at a HIGH or LOW level
SWITCHING: See the following three tables
Table 71: Switching for CA Input Signals
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
CK_t
(Rising)/
CK_c
(Falling)
CK_t
(Falling)/
CK_c
(Rising)
Cycle
N
N+1
N+2
N+3
CS_n
HIGH
HIGH
HIGH
HIGH
CA0
H
L
L
L
L
CA1
H
H
H
L
L
CA2
H
L
L
L
L
CA3
H
H
H
L
L
CA4
H
L
L
L
L
CA5
H
H
H
L
L
CA6
H
L
L
L
L
CA7
H
H
H
L
L
CA8
H
L
L
L
CA9
H
H
H
L
Notes:
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
L
L
H
H
H
H
L
L
H
L
H
H
H
L
L
L
H
1. CS_n must always be driven HIGH.
2. For each clock cycle, 50% of the CA bus is changing between HIGH and LOW.
3. The noted pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measurement for IDD values that require switching on the CA bus.
Table 72: Switching for IDD4R
Clock
CKE
CS_n
Clock Cycle
Number
Command
CA[2:0]
CA[9:3]
All DQ
Rising
H
L
N
Read_Rising
HLH
LHLHLHL
L
Falling
H
L
N
Read_Falling
LLL
LLLLLLL
L
Rising
H
H
N+1
NOP
LLL
LLLLLLL
H
Falling
H
H
N+1
NOP
LLL
LLLLLLL
L
Rising
H
H
N+2
NOP
LLL
LLLLLLL
H
Falling
H
H
N+2
NOP
LLL
LLLLLLL
H
Rising
H
H
N+3
NOP
LLL
LLLLLLL
H
Falling
H
H
N+3
NOP
HLH
LHLLHLH
L
Rising
H
L
N+4
Read_Rising
HLH
LHLLHLH
H
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
Table 72: Switching for IDD4R (Continued)
Clock
CKE
CS_n
Clock Cycle
Number
Command
CA[2:0]
CA[9:3]
All DQ
Falling
H
L
N+4
Read_Falling
HHL
HHHHHHH
H
Rising
H
H
N+5
NOP
HHH
HHHHHHH
H
Falling
H
H
N+5
NOP
HHH
HHHHHHH
L
Rising
H
H
N+6
NOP
HHH
HHHHHHH
L
Falling
H
H
N+6
NOP
HHH
HHHHHHH
L
Rising
H
H
N+7
NOP
HHH
HHHHHHH
H
Falling
H
H
N+7
NOP
HLH
LHLHLHL
L
Notes:
1. Data strobe (DQS_t) is changing between HIGH and LOW with every clock cycle.
2. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.
Table 73: Switching for IDD4W
Clock
CKE
CS_n
Clock Cycle
Number
Rising
H
L
Falling
H
L
Rising
H
Falling
Command
CA[2:0]
CA[9:3]
All DQ
N
Write_Rising
LLH
LHLHLHL
L
N
Write_Falling
LLL
LLLLLLL
L
H
N+1
NOP
LLL
LLLLLLL
H
H
H
N+1
NOP
LLL
LLLLLLL
L
Rising
H
H
N+2
NOP
LLL
LLLLLLL
H
Falling
H
H
N+2
NOP
LLL
LLLLLLL
H
Rising
H
H
N+3
NOP
LLL
LLLLLLL
H
Falling
H
H
N+3
NOP
LLH
LHLLHLH
L
Rising
H
L
N+4
Write_Rising
LLH
LHLLHLH
H
Falling
H
L
N+4
Write_Falling
HHL
HHHHHHH
H
Rising
H
H
N+5
NOP
HHH
HHHHHHH
H
Falling
H
H
N+5
NOP
HHH
HHHHHHH
L
Rising
H
H
N+6
NOP
HHH
HHHHHHH
L
Falling
H
H
N+6
NOP
HHH
HHHHHHH
L
Rising
H
H
N+7
NOP
HHH
HHHHHHH
H
Falling
H
H
N+7
NOP
LLH
LHLHLHL
L
Notes:
1. Data strobe (DQS_t) is changing between HIGH and LOW with every clock cycle.
2. Data masking (DM) must always be driven LOW.
3. The noted pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W.
IDD Specifications
IDD values are for the entire operating voltage range, and all of them are for the entire
standard range, with the exception of IDD6ET, which is for the entire extended temperature range.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
Table 74: IDD Specification Parameters and Operating Conditions
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Notes 1, 2, 3, and 5 apply to entire table; Note 4 applies to all "in" values
Parameter/Condition
tCK
tCK
=
Operating one bank active-precharge current:
(MIN); tRC = tRC (MIN); CKE is HIGH; CS_n is HIGH between valid
commands; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle power-down standby current: tCK = tCK (MIN); CKE is
LOW; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle power-down standby current with clock stop: CK_t =
LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; All banks are idle;
CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current: tCK = tCK (MIN); CKE is
HIGH; CS_n is HIGH; All banks are idle; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Idle non-power-down standby current with clock stopped:
CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS_n is HIGH; All banks
are idle; CA bus inputs are stable; Data bus inputs are stable; ODT
is disabled
Active power-down standby current: tCK = tCK (MIN); CKE is
LOW; CS_n is HIGH; One bank is active; CA bus inputs are switching; Data bus inputs are stable; ODT is disabled
Active power-down standby current with clock stop: CK_t =
LOW, CK_c = HIGH; CKE is LOW; CS_n is HIGH; One bank is active;
CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current: tCK = tCK (MIN);
CKE is HIGH; CS_n is HIGH; One bank is active; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
Active non-power-down standby current with clock stopped: CK_t = LOW, CK_c = HIGH; CKE is HIGH; CS_n is HIGH; One
bank is active; CA bus inputs are stable; Data bus inputs are stable; ODT is disabled
Operating burst READ current: tCK = tCK (MIN); CS_n is HIGH
between valid commands; One bank is active; BL = 8; RL = RL
(MIN); CA bus inputs are switching; 50% data change each burst
transfer; ODT is disabled
Operating burst WRITE current: tCK = tCK (MIN); CS_n is HIGH
between valid commands; One bank is active; BL = 8; WL = WL
(MIN); CA bus inputs are switching; 50% data change each burst
transfer; ODT is disabled
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110
Symbol
Power
Supply
IDD01
VDD1
IDD02
VDD2
IDD0,in
VDDCA, VDDQ
IDD2P1
VDD1
IDD2P2
VDD2
IDD2P,in
VDDCA, VDDQ
IDD2PS1
VDD1
IDD2PS2
VDD2
IDD2PS,in
VDDCA, VDDQ
IDD2N1
VDD1
IDD2N2
VDD2
IDD2N,in
VDDCA, VDDQ
IDD2NS1
VDD1
IDD2NS2
VDD2
IDD2NS,in
VDDCA, VDDQ
IDD3P1
VDD1
IDD3P2
VDD2
IDD3P,in
VDDCA, VDDQ
IDD3PS1
VDD1
IDD3PS22
VDD2
IDD3PS,in
VDDCA, VDDQ
IDD3N1
VDD1
IDD3N2
VDD2
IDD3N,in
VDDCA, VDDQ
IDD3NS1
VDD1
IDD3NS2
VDD2
IDD3NS,in
VDDCA, VDDQ
IDD4R1
VDD1
IDD4R2
VDD2
IDD4R,in
VDDCA
IDD4W1
VDD1
IDD4W2
VDD2
IDD4W,in
VDDCA, VDDQ
Notes
2
2
2
2
2
2
3
3
3
3
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Electrical Specifications – IDD Measurements and Conditions
Table 74: IDD Specification Parameters and Operating Conditions (Continued)
VDD2, VDDQ, VDDCA = 1.14–1.30V; VDD1 = 1.70–1.95V
Notes 1, 2, 3, and 5 apply to entire table; Note 4 applies to all "in" values
Parameter/Condition
tCK
tCK
=
(MIN); CKE is HIGH
All-bank REFRESH burst current:
between valid commands; tRC = tRFCab (MIN); Burst refresh; CA
bus inputs are switching; Data bus inputs are stable; ODT is disabled
All-bank REFRESH average current: tCK = tCK (MIN); CKE is
HIGH between valid commands; tRC = tREFI; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
tCK
tCK
=
(MIN); CKE is
Per-bank REFRESH average current:
HIGH between valid commands; tRC = tREFI/8; CA bus inputs are
switching; Data bus inputs are stable; ODT is disabled
Self refresh current (–30˚C to +85˚C): CK_t = LOW, CK_c =
HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are
stable; Maximum 1x self refresh rate; ODT is disabled
Self refresh current (+85˚C to +105˚C): CK_t = LOW, CK_c =
HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are
stable; ODT is disabled
Deep power-down current: CK_t = LOW, CK_c = HIGH; CKE is
LOW; CA bus inputs are stable; Data bus inputs are stable; ODT is
disabled
Notes:
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Symbol
Power
Supply
IDD51
VDD1
IDD52
VDD2
IDD5,in
VDDCA, VDDQ
IDD5AB1
VDD1
IDD5AB2
VDD2
IDD5AB,in
VDDCA, VDDQ
IDD5PB1
VDD1
Notes
3
3
IDD5PB2
VDD2
IDD5PB,in
VDDCA, VDDQ
3
IDD61
VDD1
4, 5
IDD62
VDD2
4, 5
IDD6,in
VDDCA, VDDQ
3, 4
IDD6ET1
VDD1
5, 6
IDD6ET2
VDD2
5, 6
IDD6ET,in
VDDCA, VDDQ
3, 5, 6
IDD81
VDD1
IDD82
VDD2
IDD8,in
VDDCA, VDDQ
3
1.
2.
3.
4.
ODT disabled: MR11[2:0] = 000b.
IDD current specifications are tested after the device is properly initialized.
Measured currents are the summation of VDDQ and VDDCA.
The 1x self refresh rate is the rate at which the device is refreshed internally during self
refresh before going into the elevated temperature range.
5. This is the general definition that applies to full-array self-refresh.
6. IDD6ET is a typical value, is sampled only, and is not tested.
7. For all IDD measurements, VIHCKE = 0.8 × VDDCA; VILCKE = 0.2 × VDDCA.
111
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Operating Conditions
AC and DC Operating Conditions
Operation or timing that is not specified is illegal. To ensure proper operation, the device must be initialized properly.
Table 75: Recommended DC Operating Conditions
Note 1 applies to entire table
Symbol
Min
Typ
Max
DRAM
Unit
Notes
2
VDD1
1.70
1.80
1.95
Core power 1
V
VDD2
1.14
1.20
1.30
Core power 2
V
VDDCA
1.14
1.20
1.30
Input buffer power
V
VDDQ
1.14
1.20
1.30
I/O buffer power
V
Notes:
1. The voltage range is for DC voltage only. DC is defined as the voltage supplied at the
DRAM and is inclusive of all noise up to 1 MHz at the DRAM package ball.
2. VDD1 uses significantly less power than VDD2.
Table 76: Input Leakage Current
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input leakage current: For CA, CKE, CS_n, CK; Any input 0V ≤ VIN ≤ VDDCA; (All other pins not under test = 0V)
II
–2
2
μA
1
VREF supply leakage current: VREFDQ = VDDQ/2, or VREFCA = VDDCA/2; (All other pins not under test = 0V)
IVREF
–1
1
μA
2
Notes:
1. Although DM is for input only, the DM leakage must match the DQ and DQS output
leakage specification.
2. The minimum limit requirement is for testing purposes. The leakage current on VREFCA
and VREFDQ pins should be minimal.
Table 77: Operating Temperature Range
Notes 1 and 2 apply to entire table
Parameter/Condition
Symbol
Min
Max
Unit
Standard (WT) temperature range
TCASE1
–30
85
˚C
–30
105
˚C
Wide temperature range
Notes:
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1. Operating temperature is the case surface temperature at the center of the top side of
the device. For measurement conditions, refer to the JESD51-2 standard.
2. Either the device operating temperature or the temperature sensor can be used to set
an appropriate refresh rate, determine the need for AC timing derating, and/or monitor
the operating temperature (see Temperature Sensor). When using the temperature sensor, the actual device case temperature may be higher than the TCASE rating that applies
for the operating temperature range. For example, TCASE could be above +85˚C when
the temperature sensor indicates a temperature of less than +85˚C.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
AC and DC Logic Input Measurement Levels for Single-Ended Signals
Table 78: Single-Ended AC and DC Input Levels for CA and CS_n Inputs
Parameter
Symbol
1333/1600
Min
1866/2133
Max
Min
Max
Unit
Notes
AC input logic HIGH
VIHCA(AC)
VREF + 0.150
Note 2
VREF + 0.135
Note 2
V
1, 2
AC input logic LOW
VILCA(AC)
Note 2
VREF - 0.150
Note 2
VREF - 0.135
V
1, 2
DC input logic HIGH
VIHCA(DC)
VREF + 0.100
VDDCA
VREF + 0.100
VDDCA
V
1
DC input logic LOW
VILCA(DC)
VSSCA
VREF - 0.100
VSSCA
VREF - 0.100
V
1
VREFCA(DC)
0.49 × VDDCA
0.51 × VDDCA
0.49 × VDDCA
0.51 × VDDCA
V
3, 4
Reference voltage for CA
and CS_n inputs
Notes:
1. For CA and CS_n input-only pins. VREF = VREFCA(DC).
2. See figure: Overshoot and Undershoot Definition.
3. The AC peak noise on VREFCA could prevent VREFCA from deviating more than ±1% VDDCA
from VREFCA(DC) (for reference, approximately ±12mV).
4. For reference, approximately VDDCA/2 ±12mV.
Table 79: Single-Ended AC and DC Input Levels for CKE
Parameter
Symbol
Min
Max
Unit
Notes
CKE input HIGH level
VIHCKE
0.65 × VDDCA
Note 1
V
1
CKE input LOW level
VILCKE
Note 1
0.35 × VDDCA
V
1
Note:
1. See figure: Overshoot and Undershoot Definition.
Table 80: Single-Ended AC and DC Input Levels for DQ and DM
Parameter
Symbol
AC input logic HIGH
VIHDQ(AC)
1333/1600
1866/2133
Min
Max
Min
Max
Unit Notes
VREF + 0.150
Note 2
VREF + 0.135
Note 2
V
1, 2, 5
AC input logic LOW
VILDQ(AC)
Note 2
VREF - 0.150
Note 2
VREF - 0.135
V
1, 2, 5
DC input logic HIGH
VIHDQ(DC)
VREF + 0.100
VDDQ
VREF + 0.100
VDDQ
V
1
DC input logic LOW
VILDQ(DC)
VSSQ
VREF - 0.100
VSSQ
VREF - 0.100
V
1
Reference voltage
for DQ and DM inputs
VREFDQ(DC)
0.49 × VDDQ
0.51 × VDDQ
0.49 × VDDQ
0.51 × VDDQ
V
3, 4
VODTR/2 - 0.01 ×
VDDQ
VODTR/2 + 0.01 ×
VDDQ
VODTR/2 - 0.01 ×
VDDQ
VODTR/2 + 0.01 ×
VDDQ
V
3, 5, 6
Reference voltage
for DQ and DM inputs (DQ ODT enabled)
VREFDQ(DC)
DQODT,enabled
Notes:
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1. For DQ input-only pins. VREF = VREFDQ(DC).
2. See figure: Overshoot and Undershoot Definition.
3. The AC peak noise on VREFDQ could prevent VREFDQ from deviating more than ±1% VDDQ
from VREFDQ(DC) (for reference, approximately ±12mV).
4. For reference, approximately VDDQ/2 ±12mV.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
5. For reference, approximately VODTR/2 ±12mV.
6. The nominal mode register programmed values for RODT and the nominal controller output impedance RON are used for the calculation of VODTR. For testing purposes, a controller RON value of 50Ω is used.
VODTR=
2RON + RTT
× VDDQ
RON + RTT
VREF Tolerances
The DC tolerance limits and AC noise limits for the reference voltages V REFCA and
VREFDQ are shown below. This figure shows a valid reference voltage V REF(t) as a function
of time. V DD is used in place of V DDCA for V REFCA, and V DDQ for V REFDQ. V REF(DC) is the
linear average of V REF(t) over a very long period of time (for example, 1 second), and is
specified as a fraction of the linear average of V DDQ or V DDCA, also over a very long period of time (for example, 1 second). This average must meet the MIN/MAX requirements
in the table: Single-Ended AC and DC Input Levels for CA and CS_n Inputs. Additionally,
VREF(t) can temporarily deviate from V REF(DC) by no more than ±1% V DD. V REF(t) cannot
track noise on V DDQ or V DDCA if doing so would force V REF outside these specifications.
Figure 69: VREF DC Tolerance and VREF AC Noise Limits
VDD
Voltage
VREF(AC) noise
VREF(t)
VREF(DC)max
VREF(DC)
VREF(DC)nom
VREF(DC)min
VSS
Time
The voltage levels for setup and hold time measurements V IH(AC), V IH(DC), V IL(AC), and
VIL(DC) are dependent on V REF. V REF shall be understood as V REF(DC), as defined in the
Single-Ended Requirements for Differential Signals figure.
VREF DC variations affect the absolute voltage a signal must reach to achieve a valid
HIGH or LOW, as well as the time from which setup and hold times are measured.
System timing and voltage budgets must account for V REF deviations outside this range.
The setup/hold specification and derating values must include time and voltage associated with V REF AC noise. Timing and voltage effects due to AC noise on V REF up to the
specified limit (±1% V DD) are included in device timings and associated deratings.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Input Signal
Figure 70: LPDDR3-1600 to LPDDR3-1333 Input Signal
VIL and VIH levels with ringback
1.550V
VDD + 0.35V
narrow pulse width
1.200V
VDD
0.750V
VIH(AC)
0.700V
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.500V
VIL(DC)
0.450V
VIL(AC)
0.000V
VSS
Minimum VIL and VIH levels
0.750V
0.700V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
0.500V
VIL(DC)
0.450V
VIL(AC)
VSS - 0.35V
narrow pulse width
–0.350V
Notes:
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1. Numbers reflect typical values.
2. For CA[9:0], CK, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS, and ODT, VDD stands
for VDDQ.
3. For CA[9:0], CK, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS, and ODT, VSS stands
for VSSQ.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Single-Ended
Signals
Figure 71: LPDDR3-2133 to LPDDR3-1866 Input Signal
VIL and VIH levels with ringback
1.550V
VDD + 0.35V
narrow pulse width
1.200V
VDD
0.735V
VIH(AC)
0.700V
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.500V
VIL(DC)
0.565V
VIL(AC)
0.000V
VSS
Minimum VIL and VIH levels
0.735V
0.700V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
0.500V
VIL(DC)
0.565V
VIL(AC)
VSS - 0.35V
narrow pulse width
–0.350V
Notes:
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1. Numbers reflect typical values.
2. For CA[9:0], CK, and CS_n, VDD stands for VDDCA. For DQ, DM, DQS, and ODT, VDD stands
for VDDQ.
3. For CA[9:0], CK, and CS_n, VSS stands for VSSCA. For DQ, DM, DQS, and ODT, VSS stands
for VSSQ.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
AC and DC Logic Input Measurement Levels for Differential Signals
Figure 72: Differential AC Swing Time and tDVAC
tDVAC
Differential Voltage
VIH,diff(AC)min
VIH,diff(DC)min
CK
DQS
0.0
VIL,diff(DC)max
tDVAC
1/2 cycle
VIL,diff(AC)max
Time
Table 81: Differential AC and DC Input Levels
For CK, VREF = VREFCA(DC); For DQS, VREF = VREFDQ(DC)
LPDDR3
Parameter
Symbol
Min
Max
Unit
Notes
Differential input HIGH AC
VIH,diff(AC)
2 × (VIH(AC) - VREF)
Note 1
V
2
Differential input LOW AC
VIL,diff(AC)
Note 1
2 × (VIL(AC) - VREF)
V
2
Differential input HIGH DC
VIH,diff(DC)
2 × (VIH(DC) - VREF)
Note 1
V
3
Differential input LOW DC
VIL,diff(DC)
Note 1
2 × (VIL(DC) - VREF)
V
3
Notes:
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1. These values are not defined; however, the single-ended signals CK and DQS must be
within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals, and must comply with the specified limitations for overshoot and undershoot (see figure: Overshoot
and Undershoot Definition).
2. For CK, use VIH/VIL(AC) of CA and VREFCA; for DQS, use VIH/VIL(AC) of DQ and VREFDQ. If a
reduced AC HIGH or AC LOW is used for a signal group, the reduced voltage level also
applies.
3. Used to define a differential signal slew rate.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
Table 82: CK and DQS Time Requirements Before Ringback (tDVAC)
tDVAC
(ps) @ VIH/
VIL,diff(AC) =
300mV1333 Mb/s
Slew Rate
(V/ns)
tDVAC
(ps) @ VIH/
VIL,diff(AC) =
300mV1600 Mb/s
tDVAC
(ps) @ VIH/VIL,diff(AC)
= 270mV1866 Mb/s
tDVAC
(ps) @ VIH/VIL,diff(AC)
= 270mV2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>8.0
58
–
48
–
40
–
34
–
8.0
58
–
48
–
40
–
34
–
7.0
56
–
46
–
39
–
33
–
6.0
53
–
43
–
36
–
30
–
5.0
50
–
40
–
33
–
27
–
4.0
45
–
35
–
29
–
23
–
3.0
37
–
27
–
21
–
15
–
<3.0
37
–
27
–
21
–
15
–
Single-Ended Requirements for Differential Signals
Each individual component of a differential signal (CK and DQS) must also comply with
certain requirements for single-ended signals.
CK must meet V SEH(AC)min/VSEL(AC)max in every half cycle. DQS must meet V SEH(AC)min/
VSEL(AC)max in every half cycle preceding and following a valid transition.
The applicable AC levels for CA and DQ differ by speed bin.
Figure 73: Single-Ended Requirements for Differential Signals
VDDCA or VDDQ
VSEH(AC)
Differential Voltage
VSEH(AC)min
VDDCA/2 or VDDQ/2
CK_t or DQS_t
VSEL(AC)max
VSEL(AC)
VSSCA or VSSQ
Time
Note: While CA and DQ signal requirements are referenced to V REF, the single-ended
components of differential signals also have a requirement with respect to V DDQ/2 for
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
DQS, and V DDCA/2 for CK.
The transition of single-ended signals through the AC levels is used to measure setup
time. For single-ended components of differential signals, the requirement to reach
VSEL(AC)max or V SEH(AC)min has no bearing on timing; however, this requirement adds a
restriction on the common mode characteristics of these signals (see tables: SingleEnded AC and DC Input Levels for CA and CS_n Inputs; Single-Ended AC and DC Input
Levels for DQ and DM).
Table 83: Single-Ended Levels for CK and DQS
Parameter
Value
Symbol
Single-ended HIGH level for
strobes
VSEH(AC150)
Single-ended HIGH level for
CK
Single-ended LOW level for
strobes
Unit
Notes
Note 1
V
2, 3
(VDDCA/2) + 0.150
Note 1
V
2, 3
Note 1
(VDDQ/2) - 0.150
V
2, 3
Note 1
(VDDCA/2) - 0.150
V
2, 3
(VDDQ/2) + 0.135
Note 1
V
2, 3
(VDDCA/2) + 0.135
Note 1
V
2, 3
Note 1
(VDDQ/2) + 0.135
V
2, 3
Note 1
(VDDCA/2) + 0.135
V
2, 3
Min
Max
(VDDQ/2) + 0.150
VSEL(AC150)
Single-ended LOW level for CK
Single-ended HIGH level for
strobes
VSEH(AC135)
Single-ended HIGH level for
CK
Single-ended LOW level for
strobes
VSEL(AC135)
Single-ended LOW level for CK
1. These values are not defined; however, the single-ended signals CK and DQS[3:0] must
be within the respective limits (VIH(DC)max, VIL(DC)min) for single-ended signals, and must
comply with the specified limitations for overshoot and undershoot (see figure: Overshoot and Undershoot Definition).
2. For CK, use VSEH/VSEL(AC) of CA; for strobes (DQS[3:0]), use
VIH/VIL(AC) of DQ.
3. VIH(AC) and VIL(AC) for DQ are based on VREFDQ; VSEH(AC) and VSEL(AC) for CA are based on
VREFCA. If a reduced AC HIGH or AC LOW is used for a signal group, the reduced level
applies.
Notes:
Differential Input Crosspoint Voltage
To ensure tight setup and hold times, as well as output skew parameters with respect to
clock and strobe, each crosspoint voltage of differential input signals (CK, CK_c, DQS_t,
and DQS_c) must meet the specifications in the table above. The differential input
crosspoint voltage (VIX) is measured from the actual crosspoint of the true signal and its
and complement to the midlevel between V DD and V SS.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
Figure 74: VIX Definition
VDDCA, VDDQ
VDDCA, VDDQ
CK_c, DQS_c
CK_c, DQS_c
X
VIX
VIX
VDDCA/2,
VDDQ/2
VDDCA/2,
X
X
VDDQ/2
VIX
VIX
X
CK_t, DQS_t
CK_t, DQS_t
VSSCA, VSSQ
VSSCA, VSSQ
Table 84: Crosspoint Voltage for Differential Input Signals (CK, CK_c, DQS_t, DQS_c)
Parameter
Symbol
Min
Max
Unit
Notes
Differential input crosspoint voltage relative to
VDDCA/2 for CK
VIXCA(AC)
–120
120
mV
1, 2
Differential input crosspoint voltage relative to
VDDQ/2 for DQS
VIXDQ(AC)
–120
120
mV
1, 2
Notes:
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1. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and it is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross.
2. For CK, VREF = VREFCA(DC). For DQS, VREF = VREFDQ(DC).
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC and DC Logic Input Measurement Levels for Differential
Signals
Input Slew Rate
Table 85: Differential Input Slew Rate Definition
Measured1
Description
From
To
Defined By
Differential input slew rate for rising edge
(CK and DQS)
VIL,diff,max
VIH,diff,min
(VIH,diff,min - VIL,diff,maxΔTRdiff
Differential input slew rate for falling
edge (CK and DQS)
VIH,diff,min
VIL,diff,max
(VIH,diff,min - VIL,diff,maxΔTFdiff
Note:
1. The differential signals (CK and DQS) must be linear between these thresholds.
Differential input voltage (CK, DQS)
Figure 75: Differential Input Slew Rate Definition for CK and DQS
∆TFdiff
∆TRdiff
VIH,diff,min
0
VIL,diff,max
Time
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Characteristics and Operating Conditions
Output Characteristics and Operating Conditions
Table 86: Single-Ended AC and DC Output Levels
Parameter
Symbol
Value
Unit
VOH(AC)
VREF + 0.12
V
AC output HIGH measurement level (for output slew rate)
Notes
AC output LOW measurement level (for output slew rate)
VOL(AC)
VREF - 0.12
V
DC output HIGH measurement level (for I-V curve linearity)
VOH(DC)
0.9 × VDDQ
V
1
DC output LOW measurement level (for I-V curve linearity)
VOL(DC)
0.1 × VDDQ
V
2
DC output LOW measurement level (for I-V curve linearity); ODT enabled DQS_t
VOL(DC)ODT,enabled
VDDQ × {0.1 + 0.9 ×
[RON / (RTT + RON)]}
V
3
Output leakage current (DQ, DM, DQS); DQ, DQS are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
–5 (MIN)
μA
Delta output impedance between pull-up and pull-down
for DQ/DM
MMPUPD
5 (MAX)
–15 (MIN)
%
15 (MAX)
1. IOH = –0.1mA.
2. IOL = 0.1mA.
3. The minimum value is derived when using RTT,min and RON,max (±30% uncalibrated, ±15%
calibrated).
Notes:
Table 87: Differential AC and DC Output Levels
Parameter
Symbol
Value
Unit
Notes
AC differential output HIGH measurement level (for output SR)
VOH,diff(AC)
0.2 × VDDQ
V
1
AC differential output LOW measurement level (for output SR)
VOL,diff(AC)
–0.2 × VDDQ
V
2
1. IOH = –0.1mA.
2. IOL = 0.1mA.
Notes:
Single-Ended Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and
rising edges is defined and measured between V OL(AC) and V OH(AC) for single-ended signals.
Table 88: Single-Ended Output Slew Rate Definition
Measured
Description
From
To
Defined by
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)ΔTRSE
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)ΔTFSE
Note:
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1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Characteristics and Operating Conditions
Figure 76: Single-Ended Output Slew Rate Definition
ΔTRSE
Single-Ended Output Voltage (DQ)
ΔTFSE
VOH(AC)
VREF
VOL(AC)
Time
Table 89: Single-Ended Output Slew Rate
Notes 1–5 apply to entire table
Value
Parameter
Single-ended output slew rate (output impedance = 40Ω 
Output slew-rate-matching ratio (pull-up to pull-down)
Notes:
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Symbol
Min
Max
Unit
SRQSE
1.5
4.0
V/ns
–
0.7
1.4
–
1. Definitions: SR = Slew rate; Q = Query output (similar to DQ = Data-in, query output); SE
= Single-ended signals.
2. Measured with output reference load.
3. The ratio of pull-up to pull-down slew rate is specified for the same temperature and
voltage over the entire temperature and voltage range. For a given output, the ratio
represents the maximum difference between pull-up and pull-down drivers due to process variation.
4. The output slew rate for falling and rising edges is defined and measured between
VOL(AC) and VOH(AC).
5. Slew rates are measured under typical simultaneous switching output (SSO) conditions,
with one half of DQ signals per data byte driving HIGH and one half of DQ signals per
data byte driving LOW.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Characteristics and Operating Conditions
Differential Output Slew Rate
With the reference load for timing measurements, the output slew rate for falling and
rising edges is defined and measured between V OL,diff(AC) and V OH,diff(AC) for differential
signals.
Table 90: Differential Output Slew Rate Definition
Measured
Description
From
To
Defined by
Differential output slew rate for rising edge
VOL,diff(AC)
VOH,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)ΔTRdiff
Differential output slew rate for falling edge
VOH,diff(AC)
VOL,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)ΔTFdiff
Note:
1. Output slew rate is verified by design and characterization and may not be subject to
production testing.
Figure 77: Differential Output Slew Rate Definition
∆TRdiff
Differential Output Voltage (DQS)
∆TFdiff
VOH,diff(AC)
0
VOL,diff(AC)
Time
Table 91: Differential Output Slew Rate
Parameter
Differential output slew rate (output impedance = 40Ω 
Notes:
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Symbol
Min
Max
Unit
SRQdiff
3.0
8.0
V/ns
1. Definitions: SR = Slew rate; Q = Query output (similar to DQ = Data-in, query output);
diff = Differential signals.
2. Measured with output reference load.
3. The output slew rate for falling and rising edges is defined and measured between
VOL(AC) and VOH(AC).
4. Slew rates are measured under typical simultaneous switching output (SSO) conditions,
with one half of the DQ signals per data byte driving HIGH and one half of the DQ signals per data byte driving LOW.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Characteristics and Operating Conditions
Table 92: AC Overshoot/Undershoot Specification
Parameter
2133
1866
1600
1333
Unit
Maximum peak amplitude provided for overshoot
area
0.35
0.35
0.35
0.35
V
Maximum peak amplitude provided for undershoot
area
0.35
0.35
0.35
0.35
V
Maximum area above VDD
0.10
0.10
0.10
0.12
V-ns
1
Maximum area below VSS
0.10
0.10
0.10
0.12
V-ns
2
Notes:
Notes
1. VDD = VDDCA for CA[9:0], CK, CS_n, and CKE. VDD stands for VDDQ for DQ, DM, DQS, and
ODT.
2. VSS = VSSCA for CA[9:0], CK, CS_n, and CKE. VSS stands for VSSQ for DQ, DM, DQS, and
ODT.
3. Maximum peak amplitude values are referenced from actual VDD and VSS values.
4. Maximum area values are referenced from maximum operating VDD and VSS values.
Figure 78: Overshoot and Undershoot Definition
Maximum amplitude
Volts (V)
Overshoot area
VDD
Time (ns)
VSS
Undershoot area
Maximum amplitude
Notes:
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1.
2.
3.
4.
VDD = VDDCA for CA[9:0], CK, CS_n, and CKE. VDD = VDDQ for DQ, DM, DQS, and ODT.
VSS = VSSCA for CA[9:0], CK, CS_n, and CKE. VSS = VSSQ for DQ, DM, DQS, and ODT.
Maximum peak amplitude values are referenced from actual VDD and VSS values.
Maximum area values are referenced from maximum operating VDD and VSS values.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Characteristics and Operating Conditions
HSUL_12 Driver Output Timing Reference Load
The timing reference loads are not a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load
to a system environment. Manufacturers correlate to their production test conditions,
generally with one or more coaxial transmission lines terminated at the tester electronics.
Figure 79: HSUL_12 Driver Output Reference Load for Timing and Slew Rate
LPDDR3
VREF
0.5 × VDDQ
50Ω
VTT = 0.5 × VDDQ
Output
CLOAD = 5pF
Note:
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1. All output timing parameter values (tDQSCK, tDQSQ, tHZ, tRPRE, etc.) are reported with
respect to this reference load. This reference load is also used to report slew rate.
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Output Driver Impedance
Output Driver Impedance
Output driver impedance is selected by a mode register during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is
performed. Output specifications refer to the default output drive unless specifically
stated otherwise. The output driver impedance R ON is defined by the value of the external reference resistor RZQ as follows:
RONPU = VDDQ - VOUT
ABS(IOUT)
When RONPD is turned off.
RONPD =
VOUT
ABS(IOUT)
When RONPU is turned off.
Figure 80: Output Driver
Chip in Drive Mode
Output Driver
VDDQ
To other
circuitry
(RCV, etc.)
IPU
RONPU
DQ
IOUT
RONPD
VOUT
IPD
VSSQ
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Output Driver Impedance
Output Driver Impedance Characteristics with ZQ Calibration
Output driver impedance is defined by the value of the external reference resistor RZQ.
Typical RZQ is 240Ω
Table 93: Output Driver DC Electrical Characteristics with ZQ Calibration
Notes 1–4 apply to entire table
RONnom
Resistor
Ω
Ω
Ω
Mismatch between
pull-up and pull-down
VOUT
Min
Typ
Max
Unit
RON34PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/7
RON34PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/7
RON40PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/6
RON40PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/6
RON48PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/5
RON48PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/5
MMPUPD
–
–15.00
–
15.00
%
Notes
5
1. Applies across entire operating temperature range after calibration.
2. RZQ Ω
3. The tolerance limits are specified after calibration, with fixed voltage and temperature.
For behavior of the tolerance limits if temperature or voltage changes after calibration,
see Output Driver Temperature and Voltage Sensitivity.
4. Pull-down and pull-up output driver impedances should be calibrated at 0.5 x VDDQ.
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:
Measure RONPU and RONPD, both at 0.5 × VDDQ:
Notes:
MMPUPD =
RONPU – RONPD
× 100
RON,nom
For example, with MMPUPD (MAX) = 15% and RONPD = 0.85, RONPU must be less than 1.0.
Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen.
Table 94: Output Driver Sensitivity Definition
Notes 1 and 2 apply to entire table
Resistor
VOUT
RONPD
Min
Max
Unit
0.5 × VDDQ
85 - (dRONdT × |ΔT|) - (dRONdV × |ΔV|)
115 + (dRONdT × |ΔT|) + (dRONdV × |ΔV|)
%
0.5 × VDDQ
85 - (dRTTdT × |ΔT|) - (dRTTdV × |ΔV|)
115 + (dRTTdT × |ΔT|) + (dRTTdV × |ΔV|)
%
RONPU
RTT
Notes:
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1. ΔT = T - T (at calibration). ΔV = V - V (at calibration).
2. dRONdT and dRONdV, and dRTTdT and dRTTdV are not subject to production testing; they
are verified by design and characterization.
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Output Driver Impedance
Table 95: Output Driver Temperature and Voltage Sensitivity
Symbol
Parameter
Min
Max
Unit
0
0.75
%/˚C
dRONdT
RON temperature sensitivity
dRONdV
RON voltage sensitivity
0
0.20
%/mV
dRTTdT
RTT temperature sensitivity
0
0.75
%/˚C
dRTTdV
RTT voltage sensitivity
0
0.20
%/mV
Output Impedance Characteristics Without ZQ Calibration
Output driver impedance is defined by design and characterization as the default setting.
Table 96: Output Driver DC Electrical Characteristics Without ZQ Calibration
Notes 1 and 2 apply to entire table
RON,nom
Resistor
VOUT
Min
Typ
Max
Unit
RON34PD
0.5 × VDDQ
0.70
1.00
1.30
RZQ/7
RON34PU
0.5 × VDDQ
0.70
1.00
1.30
RZQ/7
Ω
RON40PD
0.5 × VDDQ
0.70
1.00
1.30
RZQ/6
RON40PU
0.5 × VDDQ
0.70
1.00
1.30
RZQ/6
Ω
RON48PD
0.5 × VDDQ
0.70
1.00
1.30
RZQ/5
RON48PU
0.5 × VDDQ
0.70
1.00
1.30
RZQ/5
Ω
1. Applies across entire operating temperature range without calibration.
2. RZQ Ω
Notes:
Table 97: I-V Curves
RON Ω (RZQ)
Pull-Down
Pull-Up
Current (mA) / RON Ω
Default Value after
ZQRESET
Current (mA) / RON Ω
With Calibration
Default Value after
ZQRESET
With Calibration
Voltage (V)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
0.00
0.00
0.00
N/A
N/A
0.00
0.00
N/A
N/A
0.05
0.17
0.35
N/A
N/A
–0.17
–0.35
N/A
N/A
0.10
0.34
0.70
N/A
N/A
–0.34
–0.70
N/A
N/A
0.15
0.50
1.03
N/A
N/A
–0.50
–1.03
N/A
N/A
0.20
0.67
1.39
N/A
N/A
–0.67
–1.39
N/A
N/A
0.25
0.83
1.73
N/A
N/A
–0.83
–1.73
N/A
N/A
0.30
0.97
2.05
N/A
N/A
–0.97
–2.05
N/A
N/A
0.35
1.13
2.39
N/A
N/A
–1.13
–2.39
N/A
N/A
0.40
1.26
2.71
N/A
N/A
–1.26
–2.71
N/A
N/A
0.45
1.39
3.01
N/A
N/A
–1.39
–3.01
N/A
N/A
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Driver Impedance
Table 97: I-V Curves (Continued)
RON Ω (RZQ)
Pull-Down
Pull-Up
Current (mA) / RON Ω
Current (mA) / RON Ω
Default Value after
ZQRESET
With Calibration
Default Value after
ZQRESET
With Calibration
Voltage (V)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
Min (mA)
Max (mA)
0.50
1.51
3.32
N/A
N/A
–1.51
–3.32
N/A
N/A
0.55
1.63
3.63
N/A
N/A
–1.63
–3.63
N/A
N/A
0.60
1.73
3.93
2.17
2.94
–1.73
–3.93
–2.17
–2.94
0.65
1.82
4.21
N/A
N/A
–1.82
–4.21
N/A
N/A
0.70
1.90
4.49
N/A
N/A
–1.90
–4.49
N/A
N/A
0.75
1.97
4.74
N/A
N/A
–1.97
–4.74
N/A
N/A
0.80
2.03
4.99
N/A
N/A
–2.03
–4.99
N/A
N/A
0.85
2.07
5.21
N/A
N/A
–2.07
–5.21
N/A
N/A
0.90
2.11
5.41
N/A
N/A
–2.11
–5.41
N/A
N/A
0.95
2.13
5.59
N/A
N/A
–2.13
–5.59
N/A
N/A
1.00
2.17
5.72
N/A
N/A
–2.17
–5.72
N/A
N/A
1.05
2.19
5.84
N/A
N/A
–2.19
–5.84
N/A
N/A
1.10
2.21
5.95
N/A
N/A
–2.21
–5.95
N/A
N/A
1.15
2.23
6.03
N/A
N/A
–2.23
–6.03
N/A
N/A
1.20
2.25
6.11
N/A
N/A
–2.25
–6.11
N/A
N/A
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Driver Impedance
Figure 81: Output Impedance = 240Ω
Ω, I-V Curves After ZQRESET
6
PD (MAX)
PD (MIN)
PU (MIN)
4
PU (MAX)
mA
2
0
–2
–4
–6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Voltage
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Driver Impedance
Figure 82: Output Impedance = 240Ω
Ω, I-V Curves After Calibration
6
PD (MAX)
PD (MIN)
PU (MIN)
4
PU (MAX)
mA
2
0
–2
–4
–6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Voltage
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Output Driver Impedance
ODT Levels and I-V Characteristics
ODT effective resistance, RTT, is defined by mode register MR11[1:0]. ODT is applied to
the DQ, DM, and DQS pins. A functional block diagram of the on-die termination is
shown in the figure below. RTT is defined by the following formula: RTTPU = (VDDQ VOUT) / |IOUT|
Figure 83: ODT Functional Block Diagram
ODT
VDDQ
To other
circuitry
IPU
VDDQ - VOUT
RTTPU
IOUT
DQ
VOUT
VSS
Table 98: ODT DC Electrical Characteristics (RZQ Ω After Proper ZQ Calibration)
IOUT
RTT Ω
VOUT
Min (mA)
Max (mA)
RZQ/1
0.6
–2.17
–2.94
RZQ/2
0.6
–4.34
–5.88
RZQ/4
0.6
–8.68
–11.76
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Clock Specification
Clock Specification
The specified clock jitter is a random jitter with Gaussian distribution. Input clocks violating minimum or maximum values may result in device malfunction.
Table 99: Definitions and Calculations
Symbol
tCK(avg)
Description
and
nCK
Calculation
The average clock period across any consecutive
200-cycle window. Each clock period is calculated tCK(avg) =
from rising clock edge to rising clock edge.
Unit tCK(avg) represents the actual clock average
tCK(avg) of the input clock under operation. Unit
nCK represents one clock cycle of the input clock,
counting from actual clock edge to actual clock
edge.
Notes
N
Σ tCKj /N
j=1
Where N = 200
tCK(avg)can change no more than ±1% within a
100-clock-cycle window, provided that all jitter
and timing specifications are met.
tCK(abs)
The absolute clock period, as measured from one
rising clock edge to the next consecutive rising
clock edge.
tCH(avg)
The average HIGH pulse width, as calculated
across any 200 consecutive HIGH pulses.
1
N
tCH(avg) =
Σ tCHj
/(N × tCK(avg))
j=1
Where N = 200
tCL(avg)
The average LOW pulse width, as calculated
across any 200 consecutive LOW pulses.
N
tCL(avg) =
Σ tCL
j
/(N × tCK(avg))
j=1
Where N = 200
tJIT(per)
The single-period jitter defined as the largest detJIT(per) = min/max of tCK – tCK(avg)
i
viation of any signal tCK from tCK(avg).
1
Where i = 1 to 200
tJIT(per),act
The actual clock jitter for a given system.
tJIT(per),
The specified clock period jitter allowance.
allowed
tJIT(cc)
The absolute difference in clock periods between
t
tJIT(cc) = max of tCK
i + 1 – CKi
two consecutive clock cycles. tJIT(cc) defines the
cycle-to-cycle jitter.
1
tERR(nper)
The cumulative error across n multiple consecutive cycles from tCK(avg).
1
i+n–1
tERR(nper) =
Σ
tCK – (n × tCK(avg))
j
j=i
tERR(nper),act
The actual cumulative error over n cycles for a
given system.
tERR(nper),
allowed
The specified cumulative error allowance over n
cycles.
tERR(nper),min
The minimum tERR(nper).
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tERR(nper),min = (1 + 0.68LN(n)) × tJIT(per),min
134
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Clock Period Jitter
Table 99: Definitions and Calculations (Continued)
Symbol
Description
Calculation
tERR(nper),max
The maximum tERR(nper).
tERR(nper),max = (1 + 0.68LN(n)) × tJIT(per),max
tJIT(duty)
Defined with absolute and average specifications tJIT(duty),min =
for tCH and tCL, respectively.
MIN((tCH(abs),min – tCH(avg),min),
Notes
2
(tCL(abs),min – tCL(avg),min)) × tCK(avg)
tJIT(duty),max
=
MAX((tCH(abs),max – tCH(avg),max),
(tCL(abs),max – tCL(avg),max)) × tCK(avg)
1. Not subject to production testing.
2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
Notes:
tCK(abs), tCH(abs),
and tCL(abs)
These parameters are specified with their average values; however, the relationship between the average timing and the absolute instantaneous timing (defined in the following table) is applicable at all times.
Table 100: tCK(abs), tCH(abs), and tCL(abs) Definitions
Parameter
Symbol
Absolute clock period
tCK(abs)
tCK(avg),min
Minimum
+
Absolute clock HIGH pulse width
tCH(abs)
tCH(avg),min
+ tJIT(duty),min2/tCK(avg)min
tCK(avg)
Absolute clock LOW pulse width
tCL(abs)
tCL(avg),min
+ tJIT(duty),min2/tCK(avg)min
tCK(avg)
tJIT(per),min
Unit
ps1
1. tCK(avg),min is expressed in ps for this table.
2. tJIT(duty),min is a negative value.
Notes:
Clock Period Jitter
LPDDR3 devices can tolerate some clock period jitter without core timing parameter
derating. This section describes device timing requirements with clock period jitter
(tJIT(per)) in excess of the values found in the AC Timing table. Calculating cycle time
derating and clock cycle derating are also described.
Clock Period Jitter Effects on Core Timing Parameters
Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) extend across multiple clock cycles. Clock period jitter impacts these parameters when
measured in numbers of clock cycles. Within the specification limits, the device is characterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device operation where clock jitter is outside specification limits, the number of clocks, or
tCK(avg), may need to be increased based on the values for each core timing parameter.
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Clock Period Jitter
Cycle Time Derating for Core Timing Parameters
For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed
cycle time derating may be required for core timing parameters.
tERR(tnPARAM),allowed,
t
t
t
t
t
CycleTimeDerating = max PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tCK(avg) , 0
tnPARAM
Cycle time derating analysis should be conducted for each core timing parameter. The
amount of cycle time derating required is the maximum of the cycle time deratings determined for each individual core timing parameter.
Clock Cycle Derating for Core Timing Parameters
For each core timing parameter and a given number of clocks (tnPARAM), clock cycle
derating should be specified with tJIT(per).
For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) exceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the
equation below results in a positive value for a core timing parameter (tCORE), the required clock cycle derating will be that positive value (in clocks).
t
t
t
t
t
ClockCycleDerating = RU PARAM + ERR( nPARAM),act – ERR( nPARAM),allowed – tnPARAM
tCK(avg)
Cycle-time derating analysis should be conducted for each core timing parameter.
Clock Jitter Effects on Command/Address Timing Parameters
Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb,
tIHCKEb) are measured from a command/address signal (CKE, CS, or CA[9:0]) transition edge to its respective clock signal (CK_t/CK_c) crossing. The specification values
are not affected by the tJIT(per) applied, because the setup and hold times are relative to
the clock signal crossing that latches the command/address. Regardless of clock jitter
values, these values must be met.
Clock Jitter Effects on Read Timing Parameters
tRPRE Parameter
When the device is operated with input clock jitter, tRPRE must be derated by the
tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output deratings are relative to the input clock:
tRPRE(min,derated) = 0.9 – tJIT(per),act,max – tJIT(per),allowed,max
tCK(avg)
For example, if the measured jitter into a LPDDR3-1600 device has tCK(avg) = 1250ps,
tJIT(per),act,min = –92ps, and tJIT(per),act,max = +134ps, then tRPRE,min,derated = 0.9
- (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (134 - 100)/1250 = 0.8728
tCK(avg).
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Clock Period Jitter
tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) Parameters
These parameters are measured from a specific clock edge to a data signal transition
(DMn or DQm, where: n = 0, 1, 2, or 3; and m = DQ[31:0]), and specified timings must be
met with respect to that clock edge. Therefore, they are not affected by tJIT(per).
tQSH, tQSL Parameters
These parameters are affected by duty cycle jitter, represented by tCH(abs)min and
tCL(abs)min. These parameters determine the absolute data-valid window at the device
pin. The absolute minimum data-valid window at the device pin = min [( tQSH(abs)min
× tCK(avg)min - tDQSQmax - tQHSmax), (tQSL(abs)min × tCK(avg)min - tDQSQmax tQHSmax)]. This minimum data valid window must be met at the target frequency regardless of clock jitter.
tRPST Parameter
tRPST
is affected by duty cycle jitter, represented by tCL(abs). Therefore, tRPST(abs)min
can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min.
Clock Jitter Effects on Write Timing Parameters
tDS, tDH Parameters
These parameters are measured from a data signal (DMn or DQm, where n = 0, 1, 2, 3;
and m = DQ[31:0]) transition edge to its respective data strobe signal crossing (DQSn_t,
DQSn_c: n = 0,1,2,3). The specification values are not affected by the amount of
tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values
must be met.
tDSS, tDSH Parameters
These parameters are measured from a data strobe signal crossing (DQSx_t, DQSx_c) to
its clock signal crossing (CK_t/CK_c). The specification values are not affected by the
amount of tJIT(per)) applied, because the setup and hold times are relative to the clock
signal crossing that latches the command/address. Regardless of clock jitter values,
these values must be met.
tDQSS Parameter
tDQSS
is measured from the clock signal crossing (CK_t/CK_c) to the first latching data
strobe signal crossing (DQSx_t, DQSx_c). When the device is operated with input clock
jitter, this parameter must be derated by the actual tJIT(per),act of the input clock in excess of tJIT(per),allowed.
tDQSS(min,derated) = 0.75 - tJIT(per),act,min – tJIT(per),allowed, min
tCK(avg)
tDQSS(max,derated) = 1.25 – tJIT(per),act,max – tJIT(per),allowed, max
tCK(avg)
For example, if the measured jitter into an LPDDR3-1600 device has tCK(avg) = 1250ps,
= -93ps, and tJIT(per),act,max = +134ps, then:
tJIT(per),act,min
tDQSS,(min,derated)
= 0.75 - (tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) =
0.75 - (-93 + 100)/1250 = 0.7444 tCK(avg), and
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Refresh Requirements
tDQSS,(max,derated)
= 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) =
1.25 - (134 - 100)/1250 = 1.2228 tCK(avg).
Refresh Requirements
Table 101: Refresh Requirement Parameters (Per Density)
Parameter
Symbol
Number of banks
4Gb
6Gb
–
8Gb
16Gb
8
32Gb
Unit
TBD
Refresh window: TCASE ≤ 85˚
tREFW
32
TBD
ms
Refresh window: 1/2 rate
tREFW
16
TBD
ms
Refresh window: 1/4 rate
tREFW
8
TBD
ms
R
8192
TBD
Required number of REFRESH
commands (MIN)
Average time between
REFRESH commands
(for reference only)
TCASE ≤ 85˚C
REFab
tREFI
3.9
TBD
μs
REFpb
tREFIpb
0.4875
TBD
μs
Refresh cycle time
tRFCab
130
210
TBD
TBD
ns
Per-bank REFRESH cycle time
tRFCpb
60
90
TBD
TBD
ns
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AC Timing
AC Timing
Table 102: AC Timing
Notes 1–3 apply to all parameters and conditions
Parameter
Data Rate
Symbol
Min/Max
1333
1600
1866
2133
Unit
–
–
667
800
933
1066
MHz
Average clock period
tCK(avg)
MIN
1.5
1.25
1.071
0.938
ns
Average HIGH pulse width
tCH(avg)
Average LOW pulse width
tCL(avg)
Absolute clock period
tCK(abs)
Absolute clock HIGH pulse
width
tCH(abs)
Absolute clock LOW pulse
width
tCL(abs)
Maximum frequency
Notes
Clock Timing
MAX
100
MIN
0.45
MAX
0.55
MIN
0.45
MAX
Clock period jitter (with supported jitter)
tJIT(per),
Maximum clock jitter between two consecutive clock
cycles (with allowed jitter)
tJIT(cc),
Duty cycle jitter (with supported jitter)
al-
tCK(avg)
tCK(avg)
0.55
tCK(avg)
MIN
MIN + tJIT(per) MIN
MIN
0.43
MAX
0.57
MIN
0.43
MAX
0.57
ns
tCK(avg)
tCK(avg)
MIN
–80
–70
-60
-50
MAX
80
70
60
50
allowed
MAX
160
140
120
100
tJIT(duty),
MIN
min((tCH(abs),min - tCH(avg),min),
(tCL(abs),min - tCL(avg),min)) × tCK(avg)
lowed
allowed
MAX
ps
ps
ps
max((tCH(abs),max - tCH(avg),max),
- tCL(avg),max)) × tCK(avg)
(tCL(abs),max
Cumulative errors across 2 cycles
tERR(2per),
MIN
allowed
MAX
118
103
88
74
Cumulative errors across 3 cycles
tERR(3per),
MIN
–140
–122
-105
-87
allowed
MAX
140
122
105
87
Cumulative errors across 4 cycles
tERR(4per),
MIN
–155
–136
-117
-97
allowed
MAX
155
136
117
97
Cumulative errors across 5 cycles
tERR(5per),
MIN
–168
–147
-126
-105
allowed
MAX
168
147
126
105
Cumulative errors across 6 cycles
tERR(6per),
MIN
–177
–155
-133
-111
allowed
MAX
177
155
133
111
Cumulative errors across 7 cycles
tERR(7per),
MIN
–186
–163
-139
-116
allowed
MAX
186
163
139
116
Cumulative errors across 8 cycles
tERR(8per),
MIN
–193
–169
-145
-121
allowed
MAX
193
169
145
121
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–118
139
–103
-88
-74
ps
ps
ps
ps
ps
ps
ps
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC Timing
Table 102: AC Timing (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter
Data Rate
Symbol
Min/Max
tERR(9per),
MIN
allowed
MAX
200
175
150
125
Cumulative errors across 10
cycles
tERR(10per),
MIN
–205
–180
-154
-128
allowed
MAX
205
180
154
128
Cumulative errors across 11
cycles
tERR(11per),
MIN
–210
–184
-158
-132
allowed
MAX
210
184
158
132
Cumulative errors across 12
cycles
tERR(12per),
MIN
–215
–188
-161
-134
allowed
MAX
215
188
161
134
Cumulative errors across n =
13, 14, 15…, 19, 20 cycles
tERR(nper),
Cumulative errors across 9 cycles
MIN
1333
1600
1866
2133
Unit
–200
–175
-150
-125
ps
tERR(nper),allowed
tJIT(per),
allowed
MAX
tERR
MIN = (1 + 0.68ln(n)) ×
allowed MIN
Notes
ps
ps
ps
ps
(nper), allowed MAX = (1 + 0.68ln(n)) ×
tJIT(per), allowed MAX
ZQ Calibration Parameters
tZQINIT
MIN
1
μs
Long calibration time
tZQCL
MIN
360
ns
Short calibration time
tZQCS
MIN
90
ns
Calibration RESET time
tZQRESET
MIN
MAX (50ns, 3nCK)
ns
tDQSCK
MIN
2500
ps
Initialization calibration time
READ
Parameters4
DQS output access time from
CK
MAX
5500
DQSCK delta short
tDQSCKDS
MAX
265
220
190
165
ps
5
DQSCK delta medium
tDQSCKDM
MAX
593
511
435
380
ps
6
DQSCK delta long
tDQSCKDL
MAX
733
614
525
460
ps
7
tDQSQ
MAX
165
135
115
100
DQS output HIGH pulse
width
tQSH
MIN
tCH(abs)
- 0.05
tCK(avg)
DQS output LOW pulse
width
tQSL
MIN
tCL(abs)
- 0.05
tCK(avg)
DQ/DQS output hold time
from DQS
tQH
MIN
MIN (tQSH, tQSL)
ps
READ preamble
tRPRE
MIN
0.9
tCK(avg)
8, 9
READ postamble
tRPST
MIN
0.3
tCK(avg)
8, 10
tLZ(DQS)
MIN
tDQSCK
(MIN) - 300
ps
8
(MIN) - 300
ps
8
(MAX) - 100
ps
8
(MAX) + (1.4 × tDQSQ (MAX))
ps
8
DQS-DQ skew
DQS Low-Z from clock
DQ Low-Z from clock
DQS High-Z from clock
DQ High-Z from clock
tLZ(DQ)
MIN
tDQSCK
tHZ(DQS)
MAX
tDQSCK
tHZ(DQ)
MAX
tDQSCK
ps
WRITE Parameters4
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AC Timing
Table 102: AC Timing (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter
Symbol
Min/Max
DQ and DM input hold time
(VREF based)
tDH
DQ and DM input setup time
(VREF based)
Data Rate
1333
1600
1866
2133
Unit
Notes
MIN
175
150
130
115
ps
tDS
MIN
175
150
130
115
ps
DQ and DM input pulse
width
tDIPW
MIN
0.35
tCK(avg)
Write command to first DQS
latching transition
tDQSS
MIN
0.75
tCK(avg)
MAX
1.25
DQS input high-level width
tDQSH
MIN
0.4
tCK(avg)
DQS input low-level width
tDQSL
MIN
0.4
tCK(avg)
DQS rising edge to CK falling
edge and DQS falling edge
to CK rising edge setup time
tDSS
MIN
0.2
tCK(avg)
CK rising edge to DQS falling
edge and CK falling edge to
DQS rising edge hold time
tDSH
MIN
0.2
tCK(avg)
Write postamble
tWPST
MIN
0.4
tCK(avg)
Write preamble
tWPRE
MIN
0.8
tCK(avg)
tCKE
MIN
MAX (7.5ns, 3nCK)
tCK(avg)
CKE input setup time
tISCKE
MIN
0.25
tCK(avg)
11
CKE input hold time
tIHCKE
MIN
0.25
tCK(avg)
12
Command path disable delay
tCPDED
2
tCK(avg)
CKE Input Parameters
CKE minimum pulse width
(HIGH and LOW pulse width)
Command Address Input
MIN
Parameters4
Address and control input
setup time
tISCA
MIN
175
150
130
115
ps
13
Address and control input
hold time
tIHCA
MIN
175
150
130
115
ps
13
CS_n input setup time
tISCS
MIN
290
270
230
205
ps
13
CS_n input hold time
tIHCS
MIN
290
270
230
205
ps
13
Address and control input
pulse width
CS_n input pulse width
Boot Parameters (10–55
tIPWCA
MIN
0.35
tCK(avg)
tIPWCS
MIN
0.7
tCK(avg)
MAX
100
ns
MHz)14, 15, 16
Clock cycle time
tCKb
MIN
18
CKE input setup time
tISCKEb
MIN
2.5
ns
CKE input hold time
tIHCKEb
MIN
2.5
ns
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AC Timing
Table 102: AC Timing (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter
Data Rate
Symbol
Min/Max
Address and control input
setup time
tISb
MIN
1150
ps
Address and control input
hold time
tIHb
MIN
1150
ps
tDQSCKb
MIN
2
ns
DQS output data access time
from CK
1333
1600
1866
2133
Unit
MAX
10
tDQSQb
MAX
1.2
ns
MODE REGISTER WRITE command period (MRW command to MRW command interval)
tMRW
MIN
10
tCK(avg)
MODE REGISTER SET command delay (MRW command
to non-MRW command interval)
tMRD
MIN
MAX (14nx, 10nCK)
ns
MODE REGISTER READ command period
tMRR
MIN
4
tCK(avg)
Additional time after tXP has
expired until MRR command
may be issued
tMRRI
MIN
READ latency
RL
MIN
10
12
14
16
tCK(avg)
WRITE latency (set A)
WL
MIN
6
6
8
8
tCK(avg)
WRITE latency (set B)
WL
MIN
8
9
11
13
tCK(avg)
ACTIVATE-to- ACTIVATE command period
tRC
MIN
Data strobe edge to output
data edge
Notes
Mode Register Parameters
tRCD
(MIN)
ns
Core Parameters17
tRAS
tRAS
+ tRPab (with all-bank precharge)
+ tRPpb (with per-bank precharge)
ns
tCKESR
MIN
MAX (15ns, 3nCK)
ns
tXSR
MIN
MAX (tRFCab + 10ns, 2nCK)
ns
tXP
MIN
MAX (7.5ns, 2nCK)
ns
CAS-to-CAS delay
tCCD
MIN
4
tCK(avg)
Internal READ to PRECHARGE command delay
tRTP
MIN
MAX (7.5ns, 4nCK)
ns
RAS-to-CAS delay
tRCD
MIN
MAX (18ns, 3nCK)
ns
CKE minimum pulse width
during SELF REFRESH (low
pulse width during SELF REFRESH)
SELF REFRESH exit to next
valid command delay
Exit power-down to next valid command delay
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AC Timing
Table 102: AC Timing (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter
Data Rate
Symbol
Min/Max
tRPpb
MIN
MAX (18ns, 3nCK)
ns
tRPpab
MIN
MAX (21ns, 3nCK)
ns
Row active time
tRAS
MIN
MAX (42ns, 3nCK)
ns
MAX
70
μs
WRITE recovery time
tWR
MIN
MAX (15ns, 3nCK)
ns
Internal WRITE-to- READ
command delay
tWTR
MIN
MAX (7.5ns, 4nCK)
ns
Active bank A to active bank
B
tRRD
MIN
MAX (10ns, 2nCK)
ns
Four-bank ACTIVATE window
tFAW
MIN
MAX (50ns, 8nCK)
ns
Minimum deep power-down
time
tDPD
MIN
500
μs
Asynchronous RTT turn-on dely from ODT input
tODTon
MIN
1.75
ns
MAX
3.5
Asynchronous RTT turn-off
delay from ODT input
tODToff
MIN
1.75
Automatic RTT turn-on delay
after READ data
tAODTon
MAX
Automatic RTT turn-off delay
after READ data
tAODToff
MIN
RTT disable delay from power-down, self refresh, and
deep power-down entry
tODTd
MAX
12
ns
RTT enable delay from power-down and self refresh exit
tODTe
MAX
12
ns
First CA calibration command
following CA training entry
tCAMRD
MIN
20
tCK(avg)
First CA calibration command
following CKE LOW
tCAENT
MIN
10
tCK(avg)
CA calibration exit command
following CKE HIGH
tCAEXT
MIN
10
tCK(avg)
CKE LOW following CA calibration mode entry
tCACKEL
MIN
10
tCK(avg)
CKE HIGH following last CA
calibration results
tCACKEH
MIN
10
tCK(avg)
Row precharge time (single
bank)
Row precharge time (all
banks)
1333
1600
1866
2133
Unit
Notes
ODT Parameters
MAX
ns
3.5
tDQSCK
+ 1.4 × tDQSQmax + tCK(avg,min)
tDQSCKmin
- 300
ps
ps
CA Training Parameters
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
AC Timing
Table 102: AC Timing (Continued)
Notes 1–3 apply to all parameters and conditions
Parameter
Data Rate
Symbol
Min/Max
Data out delay after CA
training calibration command entry
tADR
MAX
20
ns
MRW CA exit command to
DQ tri-state
tMRZ
MIN
3
ns
tCACD
MIN
RU(tADR/tCK) + 2
tCK(avg)
tWLDQSEN
MIN
25
ns
CA calibration command to
CA calibration command delay
1333
1600
1866
2133
Unit
Notes
Write Leveling Parameters
DQS delay after write leveling mode is programmed
First DQS edge after write
leveling mode is programmed
tWLMRD
MAX
–
MIN
40
MAX
–
MIN
0
MAX
20
ns
Write leveling output delay
tWLO
Write leveling hold time
tWLH
MIN
205
175
150
135
ps
Write leveling setup time
tWLS
MIN
205
175
150
135
ps
ns
Temperature Derating Parameters
DQS output access time from
CK (derated)
RAS-to-CAS delay (derated)
ACTIVATE-to- ACTIVATE command period (derated)
Row active time (derated)
Row precharge time (derated)
Active bank A to active bank
B (derated)
Notes:
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tDQSCK
MAX
tRCD
MIN
tRCD
tRC
MIN
tRC
tRAS
MIN
tRAS
tRP
MIN
tRP
tRRD
MIN
tRRD
5620
+ 1.875
+ 1.875
+ 1.875
+ 1.875
+ 1.875
ps
ns
ns
ns
ns
ns
1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities.
2. All AC timings assume an input slew rate of 2 V/ns.
3. Measured with 4 V/ns differential CK_t/CK_c slew rate and nominal VIX.
4. READ, WRITE, and input setup and hold values are referenced to VREF.
5. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.
tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is
<10˚C/s. Values do not include clock jitter.
6. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 1.6μs rolling window. tDQSCKDM is not tested and is
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AC Timing
guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include
clock jitter.
7. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is
guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include
clock jitter.
8. For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point
when the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur in
the same access time (with respect to clock) as valid data transitions. These parameters
are not referenced to a specific voltage level but to the time when the device output is
no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE,
tLZ(DQS) and tLZ(DQ)). The figure below shows a method to calculate the point when
the device is no longer driving tHZ(DQS) and tHZ(DQ) or begins driving tLZ(DQS) and
tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters tRPRE and tRPST are determined from the differential signal DQS.
Output Transition Timing
VOH
VTT + Y mV
VOH - X mV
VOH - 2x X mV
tLZ(DQS), tLZ(DQ)
actual wave
rm
fo
VTT
X
2x X
VTT + 2x Y mV
tHZ(DQS), tHZ(DQ)
VTT
Y
2x Y
VTT - Y mV
VOL + 2x X mV
VTT - 2x Y mV
VOL + X mV
T1 T2
Start driving point = 2 × T1 - T2
VOL
T1 T2
End driving point = 2 × T1 - T2
9. Measured from the point when DQS begins driving the signal, to the point when DQS
begins driving the first rising strobe edge.
10. Measured from the last falling strobe edge of DQS to the point when DQS finishes driving the signal.
11. CKE input setup time is measured from CKE reaching a HIGH/LOW voltage level to
CK crossing.
12. CKE input hold time is measured from CK crossing to CKE reaching a HIGH/LOW voltage
level.
13. Input setup/hold time for signal (CA[9:0], CS_n).
14. To ensure device operation before the device is configured, a number of AC boot timing
parameters are defined in this table. Boot parameter symbols have the letter b appended (for example, tCK during boot is tCKb).
15. Mobile LPDDR3 devices set some mode register default values upon receiving a RESET
(MRW) command, as specified in Mode Register Definition.
16. The output skew parameters are measured with default output impedance settings using the reference load.
17. The minimum tCK column applies only when tCK is greater than 6ns.
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CA and CS_n Setup, Hold, and Derating
CA and CS_n Setup, Hold, and Derating
For all input signals (CA and CS_n), the total required setup time (tIS) and hold time
(tIH) is calculated by adding the data sheet tIS (base) and tIH (base) values to the ΔtIS
and ΔtIH derating values, respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS.
(See the series of tables following this section.)
The typical setup slew rate (tIS) for a rising signal is defined as the slew rate between the
last crossing of V REF(DC) and the first crossing of V IH(AC)min. The typical setup slew rate
for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and
the first crossing of V IL(AC)max. If the actual signal is consistently earlier than the typical
slew rate line between the shaded V REF(DC)-to-(AC) region, use the typical slew rate for
the derating value (see the Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to
Clock figure). If the actual signal is later than the typical slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for the derating value (see the Tangent Line
– tIS for CA and CS_n Relative to Clock figure).
The hold (tIH) typical slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V REF(DC). The hold ( tIH) typical slew
rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min
and the first crossing of V REF(DC). If the actual signal is consistently later than the typical
slew rate line between the shaded DC-to-VREF(DC) region, use the typical slew rate for
the derating value (see the Typical Slew Rate – tIH for CA and CS_n Relative to Clock figure). If the actual signal is earlier than the typical slew rate line anywhere between the
shaded DC-to-VREF(DC) region, the slew rate of a tangent line to the actual signal from
the DC level to V REF(DC) level is used for the derating value (see the Tangent Line – tIH
for CA and CS_n Relative to Clock figure).
For a valid transition, the input signal must remain above or below V IH/VIL(AC) for a
specified time, tVAC (see the Required Time for Valid Transition – tVAC > V IH(AC) and <
VIL(AC) table).
For slow slew rates, the total setup time could be a negative value (that is, a valid input
signal will not have reached V IH/VIL(AC) at the time of the rising clock transition). A valid
input signal is still required to complete the transition and reach V IH/VIL(AC).
For slew rates between the values listed in the Derating Values for AC/DC-Based tIS/tIH
(AC150) table, the derating values are obtained using linear interpolation. Slew rate values are not typically subject to production testing. They are verified by design and characterization.
Table 103: CA Setup and Hold Base Values
Data Rate
Parameter
tISCA
tISCA
tIHCA
1333
1600
(base)
100
75
–
–
VIH/VIL(AC) = VREF(DC) ±150mV
(base)
–
–
62.5
47.5
VIH/VIL(AC) = VREF(DC) ±135mV
(base)
125
100
80
65
VIH/VIL(DC) = VREF(DC) ±100mV
Note:
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1866
2133
Reference
1. AC/DC referenced for 2 V/ns CA slew rate and 4 V/ns differential CK slew rate.
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CA and CS_n Setup, Hold, and Derating
Table 104: CS_n Setup and Hold Base Values
Data Rate
Parameter
1333
1600
1866
2133
Reference
tISCS
(base)
215
195
–
–
VIH/VIL(AC) = VREF(DC) ±150mV
tISCS
(base)
–
–
162.5
137.5
VIH/VIL(AC) = VREF(DC) ±135mV
tIHCS
(base)
240
220
180
155
VIH/VIL(DC) = VREF(DC) ±100mV
Note:
1. AC/DC referenced for 2 V/ns CS_n slew rate, and 4 V/ns differential CK slew rate.
Table 105: Derating Values for AC/DC-Based tIS/tIH (AC150)
ΔtIS, ΔtIH derating in ps
ΔtIS, ΔtIH Derating in [ps] AC/DC-based
AC150 Threshold -> VIH(ac) = VREF(dc)+150mV, VIL(ac) = VREF(dc) - 150mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
CK_t, CK_c Differential Slew Rate
8.0 V/ns
CA, CS_n slew rate
V/ns
4.0
ΔtIS
ΔtIH
38
25
3.0
7.0 V/ns
ΔtIS
6.0 V/ns
ΔtIH
ΔtIS
ΔtIH
ΔtIH
4.0 V/ns
ΔtIS
ΔtIH
3.0 V/ns
ΔtIS
ΔtIH
38
25
38
25
38
25
38
25
25
17
25
17
25
17
25
17
38
29
0
0
0
0
0
0
13
13
–25
–17
–25
–17
–12
–4
2.0
1.5
Note:
5.0 V/ns
ΔtIS
1. Shaded cells are not supported.
Table 106: Derating Values for AC/DC-Based tIS/tIH (AC135)
ΔtIS, ΔtIH derating in ps
ΔtIS, ΔtIH Derating in [ps] AC/DC-based
AC135 Threshold -> VIH(ac) = VREF(dc)+135mV, VIL(ac) = VREF(dc) - 135mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
CK_t, CK_c Differential Slew Rate
8.0 V/ns
CA, CS_n slew rate
V/ns
4.0
3.0
7.0 V/ns
6.0 V/ns
3.0 V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
34
25
34
25
34
25
34
25
34
25
23
17
23
17
23
17
23
17
34
29
0
0
0
0
0
0
11
13
–23
–17
–23
–17
–12
–4
1.5
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4.0 V/ns
ΔtIH
2.0
Note:
5.0 V/ns
ΔtIS
ΔtIS
ΔtIH
1. Shaded cells are not supported.
147
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
CA and CS_n Setup, Hold, and Derating
Table 107: Required Time for Valid Transition – tVAC > VIH(AC) and < VIL(AC)
Slew
Rate
(V/ns)
tVAC
at 150mV (ps)
1333 Mb/s
tVAC
at 150mV (ps)
1600 Mb/s
tVAC
at 135mV (ps)
1866 Mb/s
tVAC
at 135mV (ps)
2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>4.0
58
–
48
–
40
–
34
–
4.0
58
–
48
–
40
–
34
–
3.5
56
–
46
–
39
–
33
–
3.0
53
–
43
–
36
–
30
–
2.5
50
–
40
–
33
–
27
–
2.0
45
–
35
–
29
–
23
–
1.5
37
–
27
–
21
–
15
–
<1.5
37
–
27
–
21
–
15
–
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148
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 84: Typical Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock
CK_c
CK_t
tIS
tIS
tIH
tIH
VDDCA
VIH(AC)min
tVAC
VREF to AC
region
VIH(DC)min
Typical
slew rate
VREF(DC)
Typical
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSSCA
ǻ7)
ǻ75
VREF(DC) - VIL(AC)max
Setup slew rate
=
falling signal
ǻ7)
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149
VIH(AC)min - VREF(DC)
Setup slew rate
=
rising signal
ǻ75
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 85: Typical Slew Rate – tIH for CA and CS_n Relative to Clock
CK_c
CK_t
tIS
tIS
tIH
tIH
VDDCA
VIH(AC)min
VIH(DC)min
DC to VREF
region
Typical slew rate
VREF(DC)
Typical slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSSCA
ǻ75
Hold slew rate VIH(DC)min - VREF(DC)
falling signal =
ǻ7)
PDF: 09005aef858e9dd3
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150
ǻ7)
Hold slew rate VREF(DC) - VIL(DC)max
rising signal =
ǻ75
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 86: Tangent Line – tIS for CA and CS_n Relative to Clock
CK_c
CK_t
tIS
tIH
tIS
tIH
VDDCA
VIH(AC)min
tVAC
VREF to AC
region
Typical
line
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
Typical
line
VREF to AC
region
VIL(AC)max
ΔTF
ΔTR
tVAC
VSSCA
Setup slew rate tangent line [VREF(DC) - VIL(AC)]max]
falling signal =
ǻ7)
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
Setup slew rate tangent line [VIH(AC)min - VREF(DC)]
=
rising signal
ǻ75
151
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
CA and CS_n Setup, Hold, and Derating
Figure 87: Tangent Line – tIH for CA and CS_n Relative to Clock
CK_c
CK_t
tIS
tIS
tIH
tIH
VDDCA
VIH(AC)min
Typical
line
VIH(DC)min
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Typical line
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSSCA
ǻTR
Hold slew rate tangent line [VIH(DC)min - VREF(DC)]
falling signal =
ǻTF
PDF: 09005aef858e9dd3
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152
ǻTF
tangent line [VREF(DC) - VIL(DC)max]
Hold slew rate
=
rising signal
ǻTR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Data Setup, Hold, and Slew Rate Derating
For all input signals (DQ, DM) calculate the total required setup time (tDS) and hold
time (tDH) by adding the data sheet tDS(base) and tDH(base) values (see the Data Setup
and Hold Base Values table) to the ΔtDS and ΔtDH derating values, respectively (see the
Derating Values for AC/DC-Based tDS/tDH (AC150) table). Example: tDS = tDS(base) +
ΔtDS.
The typical tDS slew rate for a rising signal is defined as the slew rate between the last
crossing of V REF(DC) and the first crossing of V IH(AC)min. The typical tDS slew rate for a
falling signal is defined as the slew rate between the last crossing of V REF(DC) and the
first crossing of V IL(AC)max (see the Typical Slew Rate and tVAC – tDS for DQ Relative to
Strobe figure).
If the actual signal is consistently earlier than the typical slew rate line in the Typical
Slew Rate and tVAC – tIS for CA and CS_n Relative to Clock figure in the area shaded gray
between the V REF(DC) region and the AC region, use the typical slew rate for the derating
value. If the actual signal is later than the typical slew rate line anywhere between the
shaded V REF(DC) region and the AC region, the slew rate of a tangent line to the actual
signal from the AC level to the DC level is used for the derating value (see the Tangent
Line – tIS for CA and CS_n Relative to Clock figure).
The typical tDH slew rate for a rising signal is defined as the slew rate between the last
crossing of V IL(DC)max and the first crossing of V REF(DC). The typical tDH slew rate for a
falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the
first crossing of V REF(DC) (see the Typical Slew Rate – tDH for DQ Relative to Strobe figure).
If the actual signal is consistently later than the typical slew rate line between the shaded DC-level-to-VREF(DC) region, use the typical slew rate for the derating value. If the
actual signal is earlier than the typical slew rate line anywhere between shaded DC-toVREF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to
the V REF(DC) level is used for the derating value (see the Tangent Line – tDH for DQ with
Respect to Strobe figure).
For a valid transition, the input signal must remain above or below V IH/VIL(AC) for the
specified time, tVAC (see the Required Time for Valid Transition – tVAC > V IH(AC) or <
VIL(AC) table).
The total setup time for slow slew rates could be negative (that is, a valid input signal
may not have reached V IH/VIL(AC) at the time of the rising clock transition). A valid input
signal is still required to complete the transition and reach V IH/VIL(AC).
For slew rates between the values listed in the following table, the derating values can
be obtained using linear interpolation. Slew rate values are not typically subject to production testing. They are verified by design and characterization.
PDF: 09005aef858e9dd3
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153
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© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Table 108: Data Setup and Hold Base Values
Data Rate
Parameter
1333
1600
(base)
100
75
(base)
–
–
125
100
80
tDS
tDS
tDH
(base)
Note:
1866
2133
Reference
–
–
VIH/VIL(AC) = VREF(DC) ±150mV
62.5
47.5
VIH/VIL(AC) = VREF(DC) ±135mV
65
VIH/VIL(DC) = VREF(DC) ±100mV
1. AC/DC referenced for 2 V/ns DQ, DM slew rate, and 4 V/ns differential DQS slew rate and
nominal VIX .
Table 109: Derating Values for AC/DC-Based tDS/tDH (AC150)
ΔtDS, ΔtDH derating in ps
ΔtDS, ΔtDH Derating in [ps] AC/DC-based
AC150 Threshold -> VIH(ac) = VREF(dc) + 150mV, VIL(ac) = VREF(dc) - 150mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
DQS_t, DQS_c Differential Slew Rate
8.0 V/ns
DQ, DM slew rate
V/ns
4.0
ΔtIS
ΔtIH
38
25
3.0
7.0 V/ns
ΔtIS
ΔtIH
6.0 V/ns
ΔtIS
ΔtIH
ΔtIH
4.0 V/ns
ΔtIS
ΔtIH
3.0 V/ns
ΔtIS
ΔtIH
38
25
38
25
38
25
38
25
25
17
25
17
25
17
25
17
38
29
0
0
0
0
0
0
13
13
–25
–17
–25
–17
–12
–4
2.0
1.5
Note:
5.0 V/ns
ΔtIS
1. Shaded cells are not supported.
Table 110: Derating Values for AC/DC-Based tDS/tDH (AC135)
ΔtDS, ΔtDH derating in ps
ΔtDS, ΔtDH Derating in [ps] AC/DC-based
AC135 Threshold -> VIH(ac) = VREF(dc) + 135mV, VIL(ac) = VREF(dc) - 135mV
DC100 Threshold -> VIH(dc) = VREF(dc) + 100mV, VIL(dc) = VREF(dc) - 100mV
DQS_t, DQS_c Differential Slew Rate
8.0 V/ns
DQ, DM slew rate
V/ns
4.0
3.0
7.0 V/ns
6.0 V/ns
3.0 V/ns
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
34
25
34
25
34
25
34
25
34
25
23
17
23
17
23
17
23
17
34
29
0
0
0
0
0
0
11
13
–23
–17
–23
–17
–12
–4
1.5
PDF: 09005aef858e9dd3
178b_8-16gb_2c0f_mobile_lpddr3.pdf – Rev. D 9/14 EN
4.0 V/ns
ΔtIH
2.0
Note:
5.0 V/ns
ΔtIS
ΔtIS
ΔtIH
1. Shaded cells are not supported.
154
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178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Table 111: Required Time for Valid Transition – tVAC > VIH(AC) or < VIL(AC)
Slew
Rate
(V/ns)
tVAC
at 150mV (ps)
1333 Mb/s
tVAC
at 150mV (ps)
1600 Mb/s
tVAC
at 135mV (ps)
1866 Mb/s
tVAC
at 135mV (ps)
2133 Mb/s
Min
Max
Min
Max
Min
Max
Min
Max
>4.0
58
–
48
–
40
–
34
–
4.0
58
–
48
–
40
–
34
–
3.5
56
–
46
–
39
–
33
–
3.0
53
–
43
–
36
–
30
–
2.5
50
–
40
–
33
–
27
–
2.0
45
–
35
–
29
–
23
–
1.5
37
–
27
–
21
–
15
–
<1.5
37
–
27
–
21
–
15
–
PDF: 09005aef858e9dd3
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155
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 88: Typical Slew Rate and tVAC – tDS for DQ Relative to Strobe
DQS_c
DQS_t
tDS
tDS
tDH
tDH
VDDQ
VIH(AC)min
tVAC
VREF to AC
region
VIH(DC)min
Typical
slew rate
VREF(DC)
Typical
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
tVAC
VSSQ
¨TF
¨TR
VREF(DC) - VIL(AC)max
Setup slew rate
=
falling signal
¨TF
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156
VIH(AC)min - VREF(DC)
Setup slew rate
=
rising signal
¨TR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 89: Typical Slew Rate – tDH for DQ Relative to Strobe
DQS_c
DQS_t
tDS
tDS
tDH
tDH
VDDQ
VIH(AC)min
VIH(DC)min
DC to VREF
region
Typical
slew rate
VREF(DC)
Typical
slew rate
DC to VREF
region
VIL(DC)max
VIL(AC)max
VSSQ
¨TR
VIH(DC)min - VREF(DC)
Hold slew rate
falling signal =
¨TF
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157
¨TF
VREF(DC) - VIL(DC)max
Hold slew rate
=
rising signal
¨TR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 90: Tangent Line – tDS for DQ with Respect to Strobe
DQS_c
DQS_t
tDS
tDS
tDH
tDH
VDDQ
VIH(AC)min
tVAC
Typical
line
VREF to AC
region
VIH(DC)min
Tangent line
VREF(DC)
Tangent line
VIL(DC)max
Typical line
VREF to AC
region
VIL(AC)max
¨TR
¨TF
tVAC
VSSQ
Setup slew rate tangent line [VREF(DC) - VIL(AC)max]
falling signal =
¨TF
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158
Setup slew rate tangent line [VIH(AC)min - VREF(DC)]
=
rising signal
¨TR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Data Setup, Hold, and Slew Rate Derating
Figure 91: Tangent Line – tDH for DQ with Respect to Strobe
DQS_c
DQS_t
tDS
tDS
tDH
tDH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Typical line
DC to VREF
region
VIL(DC)max
VIL(DC)max
VSSQ
¨TR
Hold slew rate
falling signal =
PDF: 09005aef858e9dd3
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tangent line [VIH(DC)min - VREF(DC)]
¨TF
159
¨TF
Hold slew rate
=
rising signal
tangent line [VREF(DC) - VIL(DC)max]
¨TR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
178-Ball, Single-Channel Mobile LPDDR3 SDRAM
Revision History
Revision History
Rev. D – 9/14
• Updated AC timing
Rev. C – 7/14
• Changed block diagram for 4 die
Rev. B – 5/14
• Added BJ = FBGA package information
Rev. A – 3/14
• Initial release
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www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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