Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp AD822 Data Sheet CONNECTION DIAGRAM True single-supply operation Output swings rail-to-rail Input voltage range extends below ground Single-supply capability from 5 V to 30 V Dual-supply capability from ±2.5 V to ±15 V High load drive Capacitive load drive of 350 pF, G = +1 Minimum output current of 15 mA Excellent ac performance for low power 800 µA maximum quiescent current per amplifier Unity-gain bandwidth: 1.8 MHz Slew rate of 3 V/μs Good dc performance 800 µV maximum input offset voltage 2 µV/°C typical offset voltage drift 25 pA maximum input bias current Low noise 13 nV/√Hz at 10 kHz No phase inversion 8 V+ OUT1 1 –IN1 2 7 OUT2 +IN1 3 6 –IN2 V– 4 AD822 5 +IN2 00874-001 FEATURES Figure 1. 8-Lead PDIP (N Suffix); 8-Lead MSOP (RM Suffix); and 8-Lead SOIC_N (R Suffix) APPLICATIONS Battery-powered precision instrumentation Photodiode preamps Active filters 12-bit to 14-bit data acquisition systems Medical instrumentation Low power references and regulators GENERAL DESCRIPTION Rev. J 10 1 10 100 1k FREQUENCY (Hz) 10k 00874-002 Offset voltage of 800 µV maximum, offset voltage drift of 2 µV/°C, input bias currents below 25 pA, and low input voltage noise provide dc precision with source impedances up to a gigaohm. The 1.8 MHz unity-gain bandwidth, –93 dB total harmonic distortion (THD) at 10 kHz, and 3 V/µs slew rate are provided with a low supply current of 800 µA per amplifier. 100 INPUT VOLTAGE NOISE (nV/√Hz) The AD822 is a dual precision, low power FET input op amp that can operate from a single supply of 5 V to 30 V or from dual supplies of ±2.5 V to ±15 V. It has true single-supply capability with an input voltage range extending below the negative rail, allowing the AD822 to accommodate input signals below ground while in the single-supply mode. Output voltage swing extends to within 10 mV of each rail, providing the maximum output dynamic range. Figure 2. Input Voltage Noise vs. Frequency Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1993–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD822 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Applications Information .............................................................. 18 Connection Diagram ....................................................................... 1 Input Characteristics .................................................................. 18 General Description ......................................................................... 1 Output Characteristics............................................................... 18 Revision History ............................................................................... 2 Single-Supply Voltage to Frequency Converter ..................... 19 Specifications..................................................................................... 4 Absolute Maximum Ratings .......................................................... 10 Single-Supply Programmable Gain Instrumentation Amplifier ..................................................................................... 20 Thermal Resistance .................................................................... 10 Low Dropout Bipolar Bridge Driver ........................................ 20 Maximum Power Dissipation ................................................... 10 Outline Dimensions ....................................................................... 21 ESD Caution ................................................................................ 10 Ordering Guide .......................................................................... 22 REVISION HISTORY 9/15—Rev. I to Rev. J Changes to Figure 12 ...................................................................... 12 1/10—Rev. H to Rev. I Changes to Features Section and General Description Section . 1 Changes to Endnote 1, Table 1 ........................................................ 5 Changes to Endnote 1, Table 2 ........................................................ 7 Changes to Endnote 1, Table 3 ........................................................ 9 Deleted Table 4; Renumbered Sequentially................................. 10 Changes to Table 5 .......................................................................... 12 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 Deleted 3 V, Single-Supply Stereo Headphone Driver Section. 22 Deleted Figure 50; Renumbered Sequentially............................. 22 8/08—Rev. G to Rev H. Changes to Features Section and General Description Section . 1 Changed VO to VOUT Throughout ................................................... 4 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 Changes to Table 3 ............................................................................ 8 Changes to Table 5 .......................................................................... 12 Added Table 6; Renumbered Sequentially .................................. 12 Changes to Figure 13 Caption....................................................... 14 Changes to Figure 29, Figure 31, and Figure 35 ......................... 17 Changes to Figure 36 ...................................................................... 18 Changed Application Notes Section to Applications Information Section ....................................................................... 20 Changes to Figure 46 and Figure 47............................................. 21 Changes to Figure 49 ...................................................................... 22 Changes to Figure 51 ...................................................................... 23 10/05—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Outline Dimensions .................................................. 24 Updated Ordering Guide .............................................................. 24 1/03—Rev. D to Rev. E Edits to Specifications .......................................................................2 Edits to Figure 10 ............................................................................ 16 Updated Outline Dimensions ....................................................... 17 10/02—Rev. C to Rev. D Edits to Features.................................................................................1 Edits to Ordering Guide ...................................................................6 Updated SOIC Package Outline ................................................... 17 8/02—Rev. B to Rev. C All Figures Updated ........................................................... Universal Edits to Features.................................................................................1 Updated All Package Outlines ...................................................... 17 7/01—Rev. A to Rev. B All Figures Updated ........................................................... Universal CERDIP References Removed .......................................1, 6, and 18 Additions to Product Description ...................................................1 8-Lead SOIC and 8-Lead MSOP Diagrams Added ......................1 Deletion of AD822S Column ...........................................................2 Edits to Absolute Maximum Ratings and Ordering Guide .........6 Removed Metallization Photograph ...............................................6 7/93—Revision 0: Initial Version 6/06—Rev. F to Rev. G Changes to Features.......................................................................... 1 Changes to Table 4 .......................................................................... 10 Changes to Table 5 .......................................................................... 12 Changes to Table 6 .......................................................................... 22 Rev. J | Page 2 of 24 Data Sheet AD822 The AD822 drives up to 350 pF of direct capacitive load as a follower and provides a minimum output current of 15 mA. This allows the amplifier to handle a wide range of load conditions. Its combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single-supply user. 1V 100 5V 20µs 90 . VOUT The AD822 is available in two performance grades. The A grade and B grade are rated over the industrial temperature range of −40°C to +85°C. 10 0% 0V (GND) .... .... .... .... .... .... .... .... .... .... 1V Figure 3. Gain of 2 Amplifier; VS = 5 V, 0 V, VIN = 2.5 V Sine Centered at 1.25 V, RL = 100 Ω Rev. J | Page 3 of 24 00874-003 The AD822 is offered in three varieties of 8-lead packages: PDIP, MSOP, and SOIC_N. 1V .... .... .... .... .... .... .... .... .... .... AD822 Data Sheet SPECIFICATIONS VS = 0 V, 5 V at TA = 25°C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted. Table 1. Parameter DC PERFORMANCE Initial Offset Maximum Offset Over Temperature Offset Drift Input Bias Current At TMAX Input Offset Current At TMAX Open-Loop Gain Test Conditions/Comments A Grade Typ 0.1 0.5 2 2 0.5 2 0.5 VCM = 0 V to 4 V VOUT = 0.2 V to 4 V RL = 100 kΩ TMIN to TMAX RL = 10 kΩ TMIN to TMAX RL = 1 kΩ TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise f = 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity-Gain Frequency Full Power Response Slew Rate Settling Time To 0.1% To 0.01% MATCHING CHARACTERISTICS Initial Offset Maximum Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz Crosstalk @ f = 100 kHz Min 500 400 80 80 15 10 Max Min 0.8 1.2 0.1 0.5 2 2 0.5 2 0.5 25 5 20 1000 500 400 80 80 15 10 150 30 B Grade Typ Max Unit 0.4 0.9 mV mV µV/°C pA nA pA nA 10 2.5 10 1000 V/mV V/mV V/mV V/mV V/mV V/mV 150 30 2 25 21 16 13 2 25 21 16 13 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 18 0.8 18 0.8 fA p-p fA/√Hz −93 −93 dB VOUT p-p = 4.5 V 1.8 210 3 1.8 210 3 MHz kHz V/µs VOUT = 0.2 V to 4.5 V VOUT = 0.2 V to 4.5 V 1.4 1.8 1.4 1.8 µs µs RL = 10 kΩ to 2.5 V VOUT = 0.25 V to 4.75 V 1.0 1.6 3 0.5 1.3 3 20 RL = 5 kΩ RL = 5 kΩ −130 −93 Rev. J | Page 4 of 24 10 –130 –93 mV mV µV/°C pA dB dB Data Sheet Parameter INPUT CHARACTERISTICS Input Voltage Range 1, TMIN to TMAX Common-Mode Rejection Ratio (CMRR) TMIN to TMAX Input Impedance Differential Common Mode OUTPUT CHARACTERISTICS Output Saturation Voltage 2 VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL – VEE TMIN to TMAX VCC − VOH TMIN to TMAX Operating Output Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Quiescent Current, TMIN to TMAX Power Supply Rejection TMIN to TMAX AD822 Test Conditions/Comments Min VCM = 0 V to 2 V VCM = 0 V to 2 V −0.2 66 66 A Grade Typ Max Min +4 −0.2 69 66 80 1013||0.5 1013||2.8 ISINK = 20 µA 5 ISOURCE = 20 µA 10 ISINK = 2 mA 40 ISOURCE = 2 mA 80 ISINK = 15 mA 300 ISOURCE = 15 mA 800 7 10 14 20 55 80 110 160 500 1000 1500 1900 15 12 66 66 Max Unit +4 80 V dB dB 1013||0.5 1013||2.8 Ω||pF Ω||pF 5 10 40 80 300 800 7 10 14 20 55 80 110 160 500 1000 1500 1900 mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF 1.6 mA dB dB 15 12 350 V+ = 5 V to 15 V B Grade Typ 1.24 80 350 1.6 70 70 1.24 80 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. 2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). 1 Rev. J | Page 5 of 24 AD822 Data Sheet VS = ±5 V at TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted. Table 2. Parameter DC PERFORMANCE Initial Offset Maximum Offset Over Temperature Offset Drift Input Bias Current At TMAX Input Offset Current At TMAX Open-Loop Gain Test Conditions/Comments VOUT = −4 V to +4 V RL = 100 kΩ RL = 10 kΩ TMIN to TMAX RL = 1 kΩ A Grade Typ 0.1 0.5 2 2 0.5 2 0.5 VCM = −5 V to +4 V TMIN to TMAX TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise f = 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity-Gain Frequency Full Power Response Slew Rate Settling Time to 0.1% to 0.01% MATCHING CHARACTERISTICS Initial Offset Maximum Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz Crosstalk @ f = 100 kHz INPUT CHARACTERISTICS Input Voltage Range 1, TMIN to TMAX Common-Mode Rejection Ratio (CMRR) TMIN to TMAX Input Impedance Differential Common Mode Min 400 400 80 80 20 10 Max Min 0.8 1.5 0.1 0.5 2 2 0.5 2 0.5 25 5 20 1000 400 400 80 80 20 10 150 30 B Grade Typ Max Unit 0.4 1 mV mV µV/°C pA nA pA nA 10 2.5 10 1000 V/mV V/mV V/mV V/mV V/mV V/mV 150 30 2 25 21 16 13 2 25 21 16 13 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 18 0.8 18 0.8 fA p-p fA/√Hz −93 −93 dB VOUT p-p = 9 V 1.9 105 3 1.9 105 3 MHz kHz V/µs VOUT = 0 V to ±4.5 V VOUT = 0 V to ±4.5 V 1.4 1.8 1.4 1.8 µs µs RL = 10 kΩ VOUT = ±4.5 V 1.0 3 0.5 2 3 3 25 RL = 5 kΩ RL = 5 kΩ 10 −130 −93 VCM = −5 V to +2 V VCM = −5 V to +2 V −5.2 66 66 +4 80 1013||0.5 1013||2.8 Rev. J | Page 6 of 24 −130 −93 −5.2 69 66 +4 mV mV µV/°C pA dB dB 80 V dB dB 1013||0.5 1013||2.8 Ω||pF Ω||pF Data Sheet Parameter OUTPUT CHARACTERISTICS Output Saturation Voltage 2 VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX Operating Output Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Quiescent Current, TMIN to TMAX Power Supply Rejection TMIN to TMAX 1 2 AD822 Test Conditions/Comments Min A Grade Typ ISINK = 20 µA 5 ISOURCE = 20 µA 10 ISINK = 2 mA 40 ISOURCE = 2 mA 80 ISINK = 15 mA 300 ISOURCE = 15 mA 800 Max Min 7 10 14 20 55 80 110 160 500 1000 1500 1900 15 12 5 10 40 80 300 800 66 66 Max Unit 7 10 14 20 55 80 110 160 500 1000 1500 1900 mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF 1.6 mA dB dB 15 12 350 VSY = ±5 V to ±15 V B Grade Typ 1.3 80 350 1.6 70 70 1.3 80 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. J | Page 7 of 24 AD822 Data Sheet VS = ±15 V at TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted. Table 3. Parameter DC PERFORMANCE Initial Offset Maximum Offset Over Temperature Offset Drift Input Bias Current At TMAX Input Offset Current At TMAX Open-Loop Gain Test Conditions/Comments A Grade Typ 0.4 0.5 2 2 40 0.5 2 0.5 VCM = 0 V VCM = −10 V VCM = 0 V VOUT = −10 V to +10 V RL = 100 kΩ TMIN to TMAX RL = 10 kΩ TMIN to TMAX RL = 1 kΩ TMIN to TMAX NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz Input Current Noise f = 0.1 Hz to 10 Hz f = 1 kHz Harmonic Distortion f = 10 kHz DYNAMIC PERFORMANCE Unity-Gain Frequency Full Power Response Slew Rate Settling Time to 0.1% to 0.01% MATCHING CHARACTERISTICS Initial Offset Maximum Offset Over Temperature Offset Drift Input Bias Current Crosstalk @ f = 1 kHz Crosstalk @ f = 100 kHz INPUT CHARACTERISTICS Input Voltage Range 1, TMIN to TMAX Common-Mode Rejection Ratio (CMRR) TMIN to TMAX Input Impedance Differential Common Mode Min 500 500 100 100 30 20 Max Min 2 3 0.3 0.5 2 2 40 0.5 2 0.5 25 5 20 2000 500 500 100 100 30 20 500 45 B Grade Typ Max Unit 1.5 2.5 mV mV µV/°C pA pA nA pA nA 12 2.5 12 2000 V/mV V/mV V/mV V/mV V/mV V/mV 500 45 2 25 21 16 13 2 25 21 16 13 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 18 0.8 18 0.8 fA p-p fA/√Hz −85 −85 dB VOUT p-p = 20 V 1.9 45 3 1.9 45 3 MHz kHz V/µs VOUT = 0 V to ±10 V VOUT = 0 V to ±10 V 4.1 4.5 4.1 4.5 µs µs RL = 10 kΩ VOUT = ±10 V 3 4 2 2.5 3 3 25 RL = 5 kΩ RL = 5 kΩ 12 −130 −93 VCM = −15 V to +12 V VCM = −15 V to +12 V −15.2 70 70 +14 80 1013||0.5 1013||2.8 Rev. J | Page 8 of 24 −130 −93 −15.2 74 74 +14 mV mV µV/°C pA dB dB 90 V dB dB 1013||0.5 1013||2.8 Ω||pF Ω||pF Data Sheet Parameter OUTPUT CHARACTERISTICS Output Saturation Voltage 2 VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX VOL − VEE TMIN to TMAX VCC − VOH TMIN to TMAX Operating Output Current TMIN to TMAX Capacitive Load Drive POWER SUPPLY Quiescent Current, TMIN to TMAX Power Supply Rejection TMIN to TMAX 1 2 AD822 Test Conditions/Comments Min A Grade Typ ISINK = 20 µA 5 ISOURCE = 20 µA 10 ISINK = 2 mA 40 ISOURCE = 2 mA 80 ISINK = 15 mA 300 ISOURCE = 15 mA 800 Max Min 7 10 14 20 55 80 110 160 500 1000 1500 1900 20 15 5 10 40 80 300 800 70 70 Max Unit 7 10 14 20 55 80 110 160 500 1000 1500 1900 mV mV mV mV mV mV mV mV mV mV mV mV mA mA pF 1.8 mA dB dB 20 15 350 VSY = ±5 V to ±15 V B Grade Typ 1.4 80 350 1.8 70 70 1.4 80 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ − 1 V) to V+. Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply. VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. J | Page 9 of 24 AD822 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Internal Power Dissipation 8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) Input Voltage1 Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range (N) Storage Temperature Range (R, RM) Operating Temperature Range A Grade and B Grade Lead Temperature (Soldering, 60 sec) 1 θJA is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating ±18 V Observe derating curves Observe derating curves Observe derating curves ((V+) + 0.2 V) to ((V−) − 20 V) Indefinite ±30 V –65°C to +125°C –65°C to +150°C –40°C to +85°C 260°C See the Input Characteristics section. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 5. Thermal Resistance Package Type 8-lead PDIP (N) 8-lead SOIC_N (R) 8-lead MSOP (RM) θJA 90 160 190 Unit °C/W °C/W °C/W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD822 is limited by the associated rise in junction temperature. For plastic packages, the maximum safe junction temperature is 145°C. If these maximums are exceeded momentarily, proper circuit operation is restored as soon as the die temperature is reduced. Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the derating curves shown in Figure 27. While the AD822 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. With power supplies ±12 V or less at an ambient temperature of 25°C or less, if the output node is shorted to a supply rail, then the amplifier is not destroyed, even if this condition persists for an extended period. ESD CAUTION Rev. J | Page 10 of 24 Data Sheet AD822 TYPICAL PERFORMANCE CHARACTERISTICS 70 5 VS = 0V, 5V INPUT BIAS CURRENT (pA) NUMBER OF UNITS 60 50 40 30 20 0 VS = 0V, +5V AND ±5V VS = ±5V –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 OFFSET VOLTAGE (mV) 0.3 0.4 0.5 –5 –5 00874-004 0 –0.5 Figure 4. Typical Distribution of Offset Voltage (390 Units) –3 –2 –1 0 1 2 COMMON-MODE VOLTAGE (V) 4 3 5 Figure 7. Input Bias Current vs. Common-Mode Voltage; VS = 5 V, 0 V, and VS = ±5 V 16 1k VS = ±5V VS = ±15V 14 INPUT BIAS CURRENT (pA) 12 10 % IN BIN –4 00874-007 10 8 6 4 100 10 1 –8 –2 –6 –4 0 2 4 6 OFFSET VOLTAGE DRIFT (µV/°C) 8 10 0.1 –16 Figure 5. Typical Distribution of Offset Voltage Drift (100 Units) –12 –8 –4 0 4 8 COMMON-MODE VOLTAGE (V) 12 16 00874-008 0 –12 –10 00874-005 2 Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = ±15 V 50 100k 45 10k INPUT BIAS CURRENT (pA) 35 30 25 20 15 1k 100 10 10 1 0 0 1 2 3 4 5 6 7 INPUT BIAS CURRENT (pA) 8 9 10 0.1 20 Figure 6. Typical Distribution of Input Bias Current (213 Units) 40 60 80 100 TEMPERATURE (°C) 120 140 Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0 V Rev. J | Page 11 of 24 00874-009 5 00874-006 NUMBER OF UNITS 40 AD822 Data Sheet 40 INPUT ERROR VOLTAGE (µV) OPEN-LOOP GAIN (V/V) 10M VS = ±15V 1M VS = 0V, +5V VS = 0V, +3V 100k RL = 20kΩ 20 POS RAIL RL = 2kΩ NEG RAIL POS RAIL 0 POS RAIL –20 NEG RAIL RL = 100kΩ 100k NEG RAIL –40 60 120 180 240 OUTPUT VOLTAGE FROM SUPPLY RAILS (mV) 300 Figure 13. Input Error Voltage with Output Voltage Within 300 mV of Either Supply Rail for Various Resistive Loads; VS = ±5 V Figure 10. Open-Loop Gain vs. Load Resistance 1k RL = 100kΩ INPUT VOLTAGE NOISE (nV/√Hz) 10M OPEN-LOOP GAIN (V/V) 0 00874-013 1k 10k LOAD RESISTANCE (Ω) 00874-010 10k 100 VS = ±15V 1M VS = 0V, +5V RL = 10kΩ VS = ±15V VS = 0V, +5V 100k VS = ±15V RL = 600Ω 100 10 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 1 00874-011 10k –60 300 –40 200 –50 1k 10k RL = 10kΩ ACL = –1 –60 RL = 10kΩ RL = 100kΩ THD (dB) INPUT ERROR VOLTAGE (mV) 100 FREQUENCY (Hz) Figure 14. Input Voltage Noise vs. Frequency Figure 11. Open-Loop Gain vs. Temperature 100 10 1 00874-014 VS = 0V, +5V 0 –70 VS = 0V, +3V; VOUT = 2.5V p-p –80 VS = ±15V; VOUT = 20V p-p –100 –90 RL = 600Ω –200 VS = ±5V; VOUT = 9V p-p –100 –8 –4 0 4 OUTPUT VOLTAGE (V) 8 12 16 Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads –110 100 1k 10k FREQUENCY (Hz) Figure 15. THD vs. Frequency Rev. J | Page 12 of 24 100k 00874-015 –12 00874-012 VS = 0V, +5V; VOUT = 4.5V p-p –300 –16 Data Sheet AD822 100 100 80 80 90 GAIN 40 40 20 20 0 0 VS = ±15V 70 60 50 40 30 20 1k 10k 100k FREQUENCY (Hz) 1M –20 10M 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 00874-019 100 Figure 16. Open-Loop Gain and Phase Margin vs. Frequency Figure 19. Common-Mode Rejection vs. Frequency 1k 5 COMMON-MODE ERROR VOLTAGE (mV) ACL = +1 VS = ±15V 100 OUTPUT IMPEDANCE (Ω) VS = 0V, +5V VS = 0V, +3V 10 RL = 2kΩ CL = 100pF –20 10 COMMON-MODE REJECTION (dB) 60 60 PHASE MARGIN (Degrees) PHASE 00874-016 10 1 0.1 NEGATIVE RAIL 4 POSITIVE RAIL 3 +25°C 2 +125°C –55°C 1 –55°C 10k 100k FREQUENCY (Hz) 1k 1M 10M 0 –1 00874-017 0.01 100 3 Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage from Supply Rails (VS − VCM) Figure 17. Output Impedance vs. Frequency 1000 16 8 OUTPUT SATURATION VOLTAGE (mV) 12 1% 4 0.01% ERROR 0.1% 0 0.01% –4 1% –8 –12 –16 0 1 2 3 SETTLING TIME (µs) 4 5 100 VS – VOH VOL – VS 10 0 0.001 00874-018 OUTPUT SWING FROM 0 TO ±VOLTS 0 1 2 COMMON-MODE VOLTAGE FROM SUPP LY RAILS (V) 00874-020 +125°C 0.01 0.1 1 LOAD CURRENT (mA) 10 Figure 21. Output Saturation Voltage vs. Load Current Figure 18. Output Swing and Error vs. Settling Time Rev. J | Page 13 of 24 100 00874-021 OPEN-LOOP GAIN (dB) 80 AD822 Data Sheet 100 1000 90 POWER SUPPLY REJECTION (dB) OUTPUT SATURATION VOLTAGE (mV) I SOURCE = 10mA I SINK = 10mA 100 I SOURCE = 1mA I SINK = 1mA 10 I SOURCE = 10µA I SINK = 10µA 80 70 +PSRR 60 50 40 –PSRR 30 20 –40 –20 0 60 20 40 80 TEMPERATURE (°C) 100 140 120 0 10 00874-022 1 –60 100 10k 100k FREQUENCY (Hz) 1M 10M Figure 25. Power Supply Rejection vs. Frequency Figure 22. Output Saturation Voltage vs. Temperature 30 80 70 VS = ±15V RL = 2kΩ 25 VS = ±15V 60 50 OUTPUT VOLTAGE (V) SHORT-CIRCUIT CURRENT LIMIT (mA) 1k 00874-025 10 –OUT VS = ±15V 40 VS = 0V, +5V 30 + VS = 0V, +3V – – 20 VS = 0V, +5V 10 + + VS = 0V, +3V 20 15 10 5 VS = 0V, +5V 0 –20 40 60 80 20 TEMPERATURE (°C) 100 120 140 00874-023 –40 0 10k 100k 1M FREQUENCY (Hz) 10M 00874-026 VS = 0V, +3V 0 –60 Figure 26. Large Signal Frequency Response Figure 23. Short-Circuit Current Limit vs. Temperature 2.4 1600 T = +125°C 2.2 1400 TOTAL POWER DISSIPATION (W) T = –55°C 1000 800 600 400 200 1.8 8-LEAD PDIP 8-LEAD SOIC 1.6 1.4 1.2 1.0 0.8 0.6 8-LEAD MSOP 0.4 0 4 8 12 16 20 24 28 TOTAL SUPPLY VOLTAGE (V) 32 36 Figure 24. Quiescent Current vs. Supply Voltage vs. Temperature 0 –60 –40 –20 0 20 40 AMBIENT TEMPERATURE (°C) 60 80 00874-027 0 2.0 0.2 00874-024 QUIESCENT CURRENT (µA) T = +25°C 1200 Figure 27. Maximum Power Dissipation vs. Temperature for Packages Rev. J | Page 14 of 24 Data Sheet AD822 –70 5V 5µs –80 100 90 CROSSTALK (dB) –90 –100 –110 –120 10 0% –140 300 1k 3k 10k 30k FREQUENCY (Hz) 100k 300k 00874-028 00874-032 –130 1M Figure 32. Large Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ Figure 28. Crosstalk vs. Frequency V+ 10mV 500ns 0.01µF 100 8 + VIN 90 1/2 AD822 VOUT 100pF RL – 0.01µF 00874-029 4 10 Figure 29. Unity-Gain Follower 00874-033 0% 5V 10µs Figure 33. Small Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ 100 90 1V 2µs 100 90 10 00874-030 0% 10 Figure 30. 20 V p-p, 25 kHz Sine Wave Input; Unity-Gain Follower; VS = ±15 V, RL = 600 Ω Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step V+ 20kΩ AD822 7 1 3 + 5kΩ 1/2 AD822 5kΩ 6 0.01µF 8 VIN + 1/2 AD822 5 RL – 100pF 4 CROSSTALK = 20 log VOUT 10VIN 0.1µF V– 1µF 00874-031 VIN Figure 31. Crosstalk Test Circuit Rev. J | Page 15 of 24 VOUT 00874-035 8 1/2 20V p-p V+ 1µF + 2 – 2.2kΩ – 0.1µF 0% 00874-034 VOUT GND Figure 35. Unity-Gain Follower AD822 VIN Data Sheet 10kΩ 20kΩ 10mV VOUT V+ 2µs 0.01µF 100 8 90 – 1/2 AD822 + 100pF 00874-036 RL 4 Figure 36. Gain of 2 Inverter 10 1V 0% 00874-039 GND 2µs Figure 39. VS = 5 V, 0 V; Gain of 2 Inverter Response to 20 mV Step, Centered 20 mV Below Ground, RL = 10 kΩ 100 90 1V 2µs 100 90 10 0% 00874-037 GND 10 Figure 37. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step 0% 00874-040 GND 10mV Figure 40. VS = 5 V, 0 V; Gain of 2 Inverter Response to 2.5 V Step, Centered −1.25 V Below Ground, RL = 10 kΩ 2µs 100 90 500mV 10µs 100 90 10 0% 00874-038 GND 10 GND 00874-041 Figure 38. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mV Step, Centered 40 mV above Ground, RL = 10 kΩ 0% Figure 41. VS = 3 V, 0 V; Gain of 2 Inverter, VIN = 1.25 V, 25 kHz, Sine Wave Centered at −0.75 V, RL = 600 Ω Rev. J | Page 16 of 24 Data Sheet AD822 1V 100 10µs .... .... .... .... .... .... .... .... .... .... 90 10 GND 0% .... .... .... .... .... .... .... .... .... .... 1V (a) 1V +Vs 100 10µs 1V .... .... .... .... ... ... .... .... .... .... 90 10 0% .... .... .... .... .... .... .... .... .... .... 1V (b) 5V RP VIN VOUT 00874-042 GND Figure 42. (a) Response with RP = 0; VIN from 0 V to +VS (b) VIN = 0 V to +VS + 200 mV VOUT = 0 V to +VS RP = 49.9 kΩ Rev. J | Page 17 of 24 AD822 Data Sheet APPLICATIONS INFORMATION INPUT CHARACTERISTICS 100k Because the input stage uses N-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than +VS − 0.4 V, then the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 7. A current-limiting resistor should be used in series with the input of the AD822 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mV, or if an input voltage is applied to the AD822 when +VS or −VS = 0 V. The amplifier is damaged if left in that condition for more than 10 seconds. A 1 kΩ resistor allows the amplifier to withstand up to 10 V of continuous overvoltage and increases the input voltage noise by a negligible amount. Input voltages less than −VS are different. The amplifier can safely withstand input voltages 20 V below the negative supply voltage if the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoampere (pA) level input currents across that input voltage range. The AD822 is designed for 13 nV/√Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to Figure 14). This noise performance, along with the AD822 low input current and current noise, means that the AD822 contributes negligible noise for applications with source resistances greater than 10 kΩ and signal bandwidths greater than 1 kHz. This is illustrated in Figure 43. WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. 1kHz 1k RESISTOR JOHNSON NOISE 100 10 10Hz 1 AMPLIFIER-GENERATED NOISE 0.1 10k 100k 10M 100M 1M SOURCE IMPEDANCE (Ω) 1G 10G 00874-043 The AD822 does not exhibit phase reversal for input voltages up to and including +VS. Figure 42 shows the response of an AD822 voltage follower to a 0 V to 5 V (+VS) square wave input. The input and output are superimposed. The output tracks the input up to +VS without phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output waveform. For input voltages greater than +VS, a resistor in series with the AD822 noninverting input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 42. 10k INPUT VOLTAGE NOISE (µV) In the AD822, N-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input commonmode voltage extends from 0.2 V below −VS to 1 V less than +VS. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figure 34 and Figure 37) and increased common-mode voltage error as illustrated in Figure 20. Figure 43. Total Noise vs. Source Impedance OUTPUT CHARACTERISTICS The AD822 unique bipolar rail-to-rail output stage swings within 5 mV of the negative supply and 10 mV of the positive supply with no external resistive load. The approximate output saturation resistance of the AD822 is 40 Ω sourcing and 20 Ω sinking, which can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing 5 mA, the saturation voltage to the positive supply rail is 200 mV; when sinking 5 mA, the saturation voltage to the negative rail is 100 mV. The open-loop gain characteristic of the amplifier changes as a function of resistive load, as shown in Figure 10 to Figure 13. For load resistances over 20 kΩ, the AD822 input error voltage is virtually unchanged until the output voltage is driven to 180 mV of either supply. If the AD822 output is overdriven so that either of the output devices are saturated, the amplifier recovers within 2 μs of the input returning to the linear operating region of the amplifier. Direct capacitive loads interact with the effective output impedance of the amplifier to form an additional pole in the amplifier feedback loop, which can cause excessive peaking on the pulse response or loss of stability. The worst case occurs when the amplifier is used as a unity-gain follower. Figure 44 shows the AD822 pulse response as a unity-gain follower driving 350 pF. This amount of overshoot indicates approximately 20° of phase margin—the system is stable, but nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, are much less sensitive to capacitance load effects. Rev. J | Page 18 of 24 Data Sheet AD822 20mV 100 SINGLE-SUPPLY VOLTAGE TO FREQUENCY CONVERTER 2µs .... .... .... .... .... .... .... .... .... .... The circuit shown in Figure 47 uses the AD822 to drive a low power timer that produces a stable pulse of width t1. The positive going output pulse is integrated by R1 and C1 and used as one input to the AD822 that is connected as a differential integrator. The other input (nonloading) is the unknown voltage, VIN. The AD822 output drives the timer trigger input, closing the overall feedback loop. 90 10 0% .... .... .... .... .... .... .... .... .... .... C5 0.1µF Figure 44. Small Signal Response of AD822 as Unity-Gain Follower Driving 350 pF 6 5 3 Figure 45 is a plot of noise gain vs. capacitive load that results in a 20° phase margin for the AD822. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. R2 499kΩ 1% VIN R1 499kΩ 1% C2 0.01µF 2% 0V TO 2.5V FULL SCALE RF R1 4 CMOS 74HCO4 U3B 3 4 RSCALE 10kΩ 4 5 NOISE GAIN 1+ 2 U4 REF02 VREF = 5V U3A 2 1 OUT1 U2 CMOS 555 0.01µF, 2% U1 + 1/2 C1 AD822B – R3 116kΩ OUT2 C3 0.1µF 4 6 2 7 R THR 8 V+ OUT TR DIS GND 1 CV 3 5 C4 0.01µF NOTES 1. fOUT = VIN/(VREF × t1), t1 = 1.1 × R3 × C6. = 25kHz fS AS SHOWN. 2. R3 = 1% METAL FILM <50ppm/°C TC. 3. RSCALE = 10% 20T FILM <100ppm/°C TC. 4. t1 = 33µF FOR fOUT = 20kHz @ VIN = 2.0V. 3 2 Figure 47. Single-Supply Voltage to Frequency Converter 1 300 1k 3k 10k CAPACITIVE LOAD FOR 20° PHASE MARGIN (pF) Typical AD822 bias currents of 2 pA allow MΩ range source impedances with negligible dc errors. Linearity errors on the order of 0.01% full scale can be achieved with this circuit. This performance is obtained with a 5 V single supply that delivers less than 1 mA to the entire circuit. 30k CL RF 00874-045 R1 Figure 45. Noise Gain vs. Capacitive Load Tolerance Figure 46 shows a method for extending capacitance load drive capability for a unity-gain follower. With these component values, the circuit drives 5000 pF with a 10% overshoot. V+ 0.01µF 8 VIN + 1/2 100Ω AD822 – 4 VOUT 0.01µF CL 20pF 20kΩ 00874-046 V– Figure 46. Extending Unity-Gain Follower Capacitive Load Capability Beyond 350 pF Rev. J | Page 19 of 24 00874-047 00874-044 10V AD822 Data Sheet SINGLE-SUPPLY PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER R1 90kΩ + An array of precision thin film resistors sets the in-amp gain to be either 10 or 100. These resistors are laser trimmed to ratio match to 0.01% and have a maximum differential temperature coefficient of 5 ppm/°C. VREF VS = 3 V, 0 V 74 dB −0.2 V to +2 V VS = ±5 V 80 dB −5.2 V to +4 V 180 kHz 18 kHz 180 kHz 18 kHz 2 µs 5 µs 270 nV/√Hz 2.2 µV/√Hz 1.10 mA 270 nV/√Hz 2.2 µV/√Hz 1.15 mA G = 10 100 R5 9kΩ OHMTEK PART # 1043 R6 90kΩ G = 100 G = 10 G = 100 V+ 0.1µF 2 6 – – 1/2 RP 1kΩ VIN1 1/2 1 AD822 + 7 AD822 3 + 5 + – 4 VOUT RP 1kΩ VIN2 ( ( (G = 10) VOUT = (VIN1 – VIN2) 1+ R6 R4 + R5 (G = 100) VOUT = (VIN1 – VIN2) 1+ ) ) +VREF R5 + R6 R4 +VREF Figure 49. A Single-Supply Programmable Instrumentation Amplifier LOW DROPOUT BIPOLAR BRIDGE DRIVER The AD822 can be used for driving a 350 Ω Wheatstone bridge. Figure 50 shows one half of the AD822 being used to buffer the AD589, a 1.235 V low power reference. The output of 4.5 V can be used to drive an analog-to-digital converter (ADC) front end. The other half of the AD822 is configured as a unity-gain inverter and generates the other bridge input of −4.5 V. Resistor R1 and Resistor R2 provide a constant current for bridge excitation. The AD620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. The gain of the AD620 is programmed using an external resistor (RG) and determined by G= 5µs .... .... .... .... ... R4 1kΩ – Table 6. In-Amp Performance Parameters CMRR Common-Mode Voltage Range 3 dB BW G = 10 G = 100 tSETTLING 2 V Step 5 V Step Noise @ f = 1 kHz G = 10 G = 100 ISUPPLY (Total) R3 1kΩ 00874-049 The AD822 can be configured as a single-supply instrumentation amplifier that is able to operate from single supplies down to 3 V or dual supplies up to ±15 V. Using only one AD822 rather than three separate op amps, this circuit is cost and power efficient. The 2 pA bias currents of the AD822 FET inputs minimize offset errors caused by high, unbalanced source impedances. R2 9kΩ 49.9 kΩ ... .... .... .... .... RG +1 V+ 90 49.9kΩ +1.235V 3 8 R1 20Ω + 1/2 + AD589 AD822 2 – – 1 TO A/D CONVERTER REFERENCE INPUT +VS 25.4kΩ 1% 10 1V 350Ω 350Ω 350Ω Figure 48. Pulse Response of In-Amp to a 500 mV p-p Input Signal; VS = 5 V, 0 V; Gain = 0 350Ω 1/2 AD822 5 + 5 4 VREF –VS 6 – 10kΩ 1% 6 AD620 + RG 3 10kΩ 1% 7 2 – 4 7 –4.5V R2 20Ω V– V+ + 0.1μF + GND + 0.1μF + V– Figure 50. Low Dropout Bipolar Bridge Driver Rev. J | Page 20 of 24 +5V 1μF 1μF –5V 00874-051 .... .... .... .... .... .... .... .... .... .... 00874-048 0% 10kΩ 1% Data Sheet AD822 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 4 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070606-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 51. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. J | Page 21 of 24 012407-A 8 4.00 (0.1574) 3.80 (0.1497) AD822 Data Sheet 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.80 0.55 0.40 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 100709-B 0.15 0.05 COPLANARITY 0.10 Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model1 AD822AN AD822ANZ AD822AR AD822AR-REEL AD822AR-REEL7 AD822ARZ AD822ARZ-REEL AD822ARZ-REEL7 AD822ARMZ AD822ARMZ-REEL AD822BR AD822BR-REEL AD822BR-REEL7 AD822BRZ AD822BRZ-REEL AD822BRZ-REEL7 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked. SPICE model is available at www.analog.com. Rev. J | Page 22 of 24 Package Option N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 Branding #B4A #B4A Data Sheet AD822 NOTES Rev. J | Page 23 of 24 AD822 Data Sheet NOTES ©1993–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00874-0-9/15(J) Rev. J | Page 24 of 24