Application Note

Application Note
Multi-band LTE/CDMA/WCDMA/HSPA
Power Amplifier
Rev 0
Relevant product
• ALT6526 For LTE, WCDMA/HSPA Wireless
Handsets and Data Devices
General Description
These ANADIGICS 5 mm x 7 mm hetero-junction
bipolar transistor (HBT) power amplifier modules
are designed for Multi-band LTE/WCDMA/HSPA
and CDMA/EVDO handsets, smartphones, modems
and modules with operating frequency in 850/900
and 1700/1900/2100 MHz. These PA’s have built-in
directional couplers for each band with a common
coupler output part CPL_OUT. The amplifier inputs
and outputs are matched to provide optimum
performance in a 50 Ω system, and minimal external
components are required for proper RF bypassing.
Table 1: Pin Description
PIN
NAME
DESCRIPTION
PIN
NAME
1
RFIN_HI
2
RF Input for
1700/1800/1900 MHz
Bands
12
RFOUT_900
RF Output for 900 MHz
Band
GND
Ground
13
RFOUT_850
RF Output for 850 MHz
Band
3
VBATT
Battery Voltage
14
GND
Ground
4
VCC1
Supply Voltage
15
VCC
Supply Voltage
5
VEN_HI
Enable Voltage for High
Bands
16
VCC
Supply Voltage
6
VBAND0
Low Band Select Voltage
17
VCC
Supply Voltage
7
VBAND1
High Band Select
Voltage
18
CPL_OUT
8
VMODE
Mode Control Voltage
19
GND
9
VEN_LO
Enable Voltage for Low
Bands
20
RFOUT_1900
RF Output for 1900 MHz
Band
10
GND
Ground
21
RFOUT_1700
RF Output for 1700 MHz
Band
11
RFIN_LO
RF input for 850/900
MHz Bands
22
RFOUT_2100
RF Output for 2100 MHz
Band
03/2012
DESCRIPTION
Coupler Output Port
Ground
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
APPLICATION INFORMATION
68pF
VBATT
1
2
C1
3
4
Vcc1
5
68pF
6
7
8
9
10
11
RFIN_HI
RFOUT_B2100
GND
RFOUT_B1700
VBATT
RFOUT_B1900
Vcc1
GND
VEN_HI
CPLOUT
VBAND0
VCC
VBAND1
VCC
VMODE
VCC
VEN_LO
GND
GND
RFOUT_B850
RFIN_LO
RFOUT_B900
22
21
20
19
18
VCC
17
C2
C3
C2
68pF
.1 uF
2.2u
F
16
15
14
13
12
GND
SLUG
Figure 1 : Application Schematic
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Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
EVALUATION BOARD
The evaluation board, shown in Figure 2, was designed on ROGERS (R04003) material with 8 mils
thickness.
IMTOUT
AWSOUT
SERIAL #
GND
RFIN HI
1.700
VBAT
VCC1
C3
VEN HI
VBAND0
VBAND1
VMODE
VEN LO
RFIN LO
GND
PCSOUT
C1
C2
C4
RFIN_HI
0.550
RFOUT_1
GND
RFOUT_2
VBAT
RFOUT_3
GND
VCC1
CPL_OUT
VEN_HI
VBAND0
VCC
VBAND1
VCC
VMODE
VCC
VEN_LO
GND
GND
RFOUT_4
RFIN_LO
RFOUT_5
C5
C6
CP OUT
C8
C7
W=0.016
008 4003
EGSMOUT
ALT6526EV1
VCC
GND
CELLOUT
1.400
Figure 2: Evaluation Board Layout
Notes:
(1) Relative dielectric constant is 3.38 at 1 GHz.
(2) Dielectric thicknes is 8.0 mils.
Table 2: Evaluation Board Parts List
ALT6526 DUT CARD BOM (ALT6526EV1)
Component
Qty
Item
C1, C3, C8
C2, C7
C4
C6
C5
J1-J8
3
3
2
1
1
0
8
Type
Material
Size
Value
Voltage
Capacitor
Capacitor
Capacitor
Capacitor
Ceramic
Ceramic
Ceramic
Ceramic
0805
0402
0402
2.2uF
.01uF
68pF
68pF
none
25
0201
25
SMA
Conector
Manufacturer
Murata
Panasonic
TDK
Murata
Johnson
Application Note - Rev 0
03/2012
Manufacturer's Part #
GRM219R61E225KA12D
ECJ-0EB1E103K
C1005COG1H680JT
GRM0335C1E680JD01D
142-0701-841
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
Sig. Gen.
REF
Trig.
Power
Meter 1
4 CH Power
Supply
Vcc
RF
Ven Vm1
Vm2
Trig.
Ch A
Ch B
RFin
VMODE2
VMODE1
BP Filter
VCC
Isolator
VEN
Ch A RF Input Power
Ch B RF Output Power
DUT
X
RFout
-20 dB
50
C pl _o ut
Directional Coupler
Power
Meter 2
Trig.
Ch A
Directional Coupler
50
Spectrum
Analyzer
Ch A RF input reflection
Ch B Cpl_out
Trig
RF
Ch B
Figure 3: Test Setup Diagram
Test Setup Notes:
(1) Figure 3 shows minimum equipment required for proper power amplifier operation.
(2) Depending upon the power sensor, 10 to 20 dB attenuator is sufficient to prevent overloading of the power meter or
the spectrum analyzer.
Test Equipment
The following test equipment is recommended for
testing of CDMA/LTE Cell/PCS evaluation boards.
•
•
•
•
•
•
One RF CDMA/WCDMA/CDMA 2000/LTE signal
generator capable of delivering at least +5 dBm
of output power at the operating frequency band
(Agilent E4432B or MXG).
One RF power meter capable of measuring up to
+30 dBm at the operating frequency band (Agilent
E4419B).
One RF power sensor capable of measuring RF
power in the range from -50 dBm to +30 dBm at
the operating frequency band (Agilent E9301H).
One RF spectrum analyzer capable of measuring
ACP in operating frequency band and covering up
to the 3rd harmonic of the highest frequency in
band (Rohde & Schwarz FSP).
One DC power supply capable of delivering 1.5
A at +4 V and 500 mA at +3 V (Agilent 6624A)
One SMA 20 dB attenuator capable of handling
2 watts.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Test Setup
1. With evaluation board disconnected, set DC
power supply to +3.4 V (for VBATT and VCC), +1.8
V (for VEN), and 0 V (for VMODE1 and VMODE2).
2. Set power meter measured frequency to center
frequency for each band of operation - (All 5
4
12.
bands), based on datasheet, and its calibration
factor to correspond to the set frequency.
Set power meter offset value equal to the total
loss of the attenuator, directional coupler, and
connecting cables.
Set spectrum analyzer center frequency to center frequency for each band of operation - (All 5
bands), based on datasheet, and enable CDMA
(3 GPP) measuring personality.
Select and enable CDMA/WCDMA/LTE digital
signal on the signal generator.
Set signal generator frequency to center
frequency for each band of operation - (All 5
bands), based on datasheet, and output power
to -10 dBm.
Ensure DC power supply is disabled and RF
output of the signal generator is OFF.
Connect evaluation board to the test setup as
shown.
Turn on DC power supply and measure the idle
current.
Switch RF output of the signal generator to ON.
Increase amplitude of the signal generator to
the desired output power level (according to the
corresponding data sheet).
Measure and record ACP, Gain (as a difference
between Input and Output power levels) and
total current consumption.
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
Vcontrols
Venable/Vmode(s)
On Sequence Start
T_0N = 0µ
Rise/Fall Max 1µS
Defined at 10% to 90%
of Min/Max Voltage
Off Sequence Start
T_0FF = 0µ
ON Sequence
OFF Sequence
RFIN_HI, LOW
notes 1,2
VEN_HI, LOW
VCC, VCC1
note 1
T_0N+1µS
T_0N+3µS
Referenced After 90% of Rise
Time
T_0FF+2µS T_0FF+3µS
Referenced Before10% of Fall
Time
Figure 4: Recommended Timing Diagram
Test sequence (Recommended PA turn-on and turn-off sequences):
Turn-on sequence:
1. Connect DUT according to the setup shown on Figure 3. Do not turn on DC power supply before
connecting DUT to RF input and output cables (make sure that RF output of a signal generator is OFF
before connecting RF cables to DUT).
2. Turn on VBATT and VCC first and then turn on VEN and VMODE1,2..
3. Turn RF output of a signal generator ON and make measurements.
Turn-off sequence:
1. Turn RF output of a signal generator OFF. Do not disconnect DUT from RF input and output
cables before turning off DC power supply.
2. Turn off VEN and VMODE1,2, and then VBATT
and VCC.
3. Disconnect DUT from the test setup.
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Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
PCB Board Design Guidelines
Figure 5: PCB Board Layout
6
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
2.2uF .01uF
From
Battery
2.2uF
68pF
From DC/DC
68pF .01uF 2.2uF
VCC1 trace represent ~2nH inductance
Figure 6: Recommended Connections for VCC1 and VCC Pins
Notes:
(1) VCC1 trace line doesn’t need to be very wide, it only carries ~50mA.
(2) VCC1 trace can run under different layer to avoid any coupling between
RFOUT and VCC1 trace.
(3) Bypass caps should be placed as close to the PA as possible.
7
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
Summary
This application note shows recommended modified circuit for drop-in replacement of ALT6526 and
AWT6521 parts. The ALT6526 is a multiband PA similar to AWT6521, but it also provides independent access to the collector terminal of the driver stages (VCC1) for possible low voltage operation at the lower power
levels. Basically, there are only 2 pins (4 and 5) in ALT6526 pin-out that are changing function as compared
to AWT6521 pin-out as shown in Figure 2. The new VCC1 pin will occupy the pin 4 location on ALT6526. The
VEN_HI (pin 4 on the AWT6521 pin-out) is moved to pin 5 locations on ALT6526. Pin 5 on AWT6521 is GND
pin.
Recommended PCB Footprint for Drop-in Replacement of ALT6526 and AWT6521
Figure 1 shows the recommended modified PCB footprint that can be implemented to be compatible for both
PAs (AWT6521 and ALT6526). Red rectangular boxes labeled with “Jx” represent “jumpers or 0 Ohm resistors”, where “x” is used for numbering.
The diagram shown below is based on AWT6521 PCB layout modified for ALT6526. Below is the procedure:
1. If customer would like to use AWT6521 then J1 and J3 are off; so VEN_HI goes to Pin4 via J2, an GND is connected via J4 to Pin5
2. If customer would like to use ALT6526 then J2 and J4 are off; so VEN_HI goes to Pin5 via J3, and VCC1 is connector via J1 to Pin4.
1
2
3
Vcc1
VEN_HI
J1
4
J2
5
J3
J
4
6
7
8
9
10
11
RFIN_HI
RFOUT_2100
GND
RFOUT_1700
VBATT
RFOUT_1900
VEN_HI
CPLOUT
GND
GND
VBAND0 AWT6521 Vcc
VBAND1
Vcc
VMODE
Vcc
VEN_LO
GND
GND
RFOUT_850
RFIN_LO
RFOUT_900
22
21
20
19
18
17
16
15
14
13
12
GND
SLUG
Figure 7: Modified circuit for ALT6526 and AWT6521 compatability on same PCB footprint.
Notes:
(1) J1-J4 represents jumpers or 0 Ohm resistors.
(2) Refer to individual device datasheets for recommended application circuit
and device operation.
8
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
Pin-out Diagrams for ALT6526 and AWT6521
1
2
3
4
5
6
7
8
9
10
11
RFIN_HI
RFOUT_2100
GND
RFOUT_1700
VBATT
RFOUT_1900
VEN_HI
CPLOUT
GND
GND
VBAND0 AWT6521 Vcc
VBAND1
Vcc
VMODE
Vcc
VEN_LO
GND
GND
RFOUT_850
RFIN_LO
RFOUT_900
GND
SLUG
(a)
(b)
Figure 8: Pinout diagrams of (a) ALT6526 and (b) AWT6521
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Application Note - Rev 0
03/2012
22
21
20
19
18
17
16
15
14
13
12
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
Layout Considerations
A sufficient number of vias (QTY 12 - 0.2 mm diameter plated through hole) should be placed under
the module in order to channel the heat properly. In
addition, contact should be made between the PA
slug located under the amplifier and the board. For
hand assembly of the board, place sufficient bonding
paste so that contact is made between the PA and
ground. For large volume assembly, please refer to
the solder profile recommendations application note.
For RFIN and RFOUT, provide 50 V transmission
lines.
Application Information
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE pads.
10
Bias Modes
The power amplifier may be placed in either a Low
Medium or a High Bias mode by applying the appropriate logic level (see operating Ranges table)
to VMODE pin. The Bias Control tables 3 & 4 list the
recommended modes of operation for various applications.
Three operating modes are available to optimize
current consumption. For CDMA, High Bias/High
power operating mode is for POUT levels > 16 dBm.
At around 16 dBm output power, the PA should be
“Mode Switched” to Medium/Low power mode. For
POUT levels < ~10 dBm the PA could be switched to
Low power mode for extremely low current consumption. For LTE, the switchpoints are 1 dBm
lower.
Output Power/VSWR Mandatory
Output Power at antenna port of the phone board
should not exceed the power level specified on the
data sheet (PA Max. output power - Front-end loss).
All VSWR value at PA output port toward the antenna port should be lower than 8:1 under 28 dBm
Cellular (28 dBm PCS) POUT condition.
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
Thermal Considerations
In PA module very little heat is dissipated to the air
through the top surface of the mold compound. The
major thermal path for heat dissipation from the heat
sources on the device is the path from the die to the
package substrate to the PCB, and through the PCB
surfaces to the air.
The efficiency of heat dissipation (measured by the
device junction temperature) is largely dependent on
the thermal resistance of the package and the PCB
(including the thermal resistance of the PCB to the
ambient air):
Tj = T ja + Ta = P (R Pkg + R PCB) + Ta
where,
-Tj is the junction temperature of the PA
-Tja is the temperature difference between the
junction and the ambient
-Ta is the ambient temperature
-P is the total power dissipation from the PA
-RPkg is the thermal resistance of the PA package
-RPCB is the thermal resistance of the PCB and PCB
to ambient air.
For a given maximum junction temperature, Tj max,
the maximum power that can be dissipated through
the package and the PCB to the ambient air is
determined by:
Pmax = Tj, max - Ta
RPkg + R PCB
This shows that in order to reduce the junction
temperature or to dissipate more power from the
device, the thermal resistance of the package, the
PCB, and the PCB to ambient air must be minimized.
Thermal resistance of the package is determined by
the package size, materials, and structures. High
thermal conductivity die attach materials are used.
Thermal vias and large metal pads are implemented
in the substrate to minimize the thermal resistance
and enhance the efficiency of the heat dissipation
from the device to the PCB.
When assembled onto a PCB, the package center
ground pad for an effective thermal path. Almost all
the heat generated from the package must eventually
dissipate through the PCB to the air.
11
Since the PCB-to-air thermal resistance is the major
portion of the overall thermal resistance, appropriate
design of the system PCB and proper assembly of the
package onto the PCB are crucial to overall system
thermal performance.
The following guidelines should be considered for
PCB designs and board level assembly:
Optimize the board level attachment process and
minimize the voids in the solder joints.
Maximize the common ground copper planes in the
PCB at the top and bottom surface. More copper
content in the inner layers of the PCB can also help
reduce the thermal resistance of the PCB.
Ensure sufficient thermal vias connect the top and
bottom ground copper planes in the PCB. These are
most effective when as many as possible are placed
under the PA ground pad. Effectiveness of thermal
vias diminishes the farther from the package ground
pad they are placed.
Minimize the interaction of the PA package with other
heat sources on the PCB. Heat sources near the
package can increase the PCB temperature and thus
increase the ambient temperature. This is especially
critical for the double-sided assembly where
placement of heat sources should be avoided in the
PCB area opposite to the PA. Conversely, passive
components on the PCB can increase the efficiency
of heat dissipation from the PCB to the air. Passive
components placed near the PA package on either
side of the PCB can improve the efficiency of heat
dissipation from the PA package.
Increase the contact areas between the PCB and the
case, such as the phone case. Heat transfer is much
more efficient via conduction than convection. More
contact area increases the heat dissipation to the
case and eventually to the air.
In general, a larger PCB area is better for heat
dissipation through the PCB to the ambient air. A
large PCB should be used to allowable by the system
design.
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
Thermal Vias
To improve thermal and electrical performance of a
mounted PA module, an array of thermal vias placed
on the ground pad should be connected to the internal
and bottom common ground copper planes of the
PCB. The number of vias is based on via configuration
and the thermal and electrical requirements of the
particular module under consideration. In general,
there is a direct correlation between the thermal via
cross-sectional area and the heat dissipation rate.
However, the heat dissipation rate through thermal
vias can be easily saturated once it is greater than
that of solder joint or package heat sink. Large and
excessive thermal vias may introduce more voids
in the solder joint and actually reduce overall heat
dissipation performance.
Recommended thermal vias are 0.30 mm to 0.33 mm
in diameter, via barrels should be plated with 1 oz. of
copper to plug the vias. The thermal via array should
be arranged evenly with a pitch of 0.5 mm to 1.2 mm,
depending on the form factor of the package. For
the exposed region of the ground pad, if the plating
thickness is not sufficient to effectively plug the barrel
of the via when plated, solder, mask should be used
to cap the vias with minimum dimension equal to the
via diameter plug 0.1 mm. This will prevent solder
wicking through the thermal via during the soldering
process, resulting in voiding.
inner layer to GND. Microvias will go from the large
GND pad under the PA to the area on the inner layer
and buried or through vias will go the rest of the way
to the ground plane in the center for the board. See
Figure 5.
PA
Components
Signal
Signal
GND
Power
GND
Signal
Keypad
Figure 9: Example of PCB Stack with Microvias on
Top and Bottom Layers, Buried Vias From Layers 2
to 7, and through Vias from Layers 1 to 8.
Another way to plug thermal vias uses solder mask
tenting on the bottom of the copper plane. Solder
mask tenting must completely cover the vias.
GROUNDING
Good grounding is crucial for best performance.
“Local ground planes” only connected to the board
GND plane using a few microvias is not adequate.
All GND planes must be connected to the main GND
layer (one designated inner layer of the PCB) using
a lot of through vias. Besides being the reference
for the all RF and other signals, the GND plane is
also used to distribute the heat dissipated by the PA
and should therefore be sufficient size and with many
through vias to spread the heat to other copper layers.
In order to establish a good ground connection for the
PA, it is necessary to assign an area on the first
12
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
REFLOW SPECIFICATIONS
The reflow profile is a critical part of the PCB
assembly process. A proper reflow profile must
provide adequate time for flux volatilization, proper
peak temperature, time above liquidous, ramp up
and cool down rates. The profile used has a direct
bearing on manufacturing yield solder joint integrity,
and the reliability of the assembly [2,3]. A typical
reflow profile is made up of four distinct zones: the
preheat zone, the soak zone/flux activation zone, the
reflow zone, and the cooling zone.
Preheat Zone
Typically the heating rate in the preheat zone should
be 2 8C to 4 8C/second and the peak temperature in the
zone should be 100 8C to 125 8C. If the temperature
ramp is too fast, the solder paste may splatter and
cause solder balls. Also, to avoid thermal shock to
sensitive components such as ceramic chip resistors,
the maximum heating rate should be controlled.
Soak Zone
The soak zone is intended to allow the board
and components to reach a uniform temperature,
minimizing thermal gradients. The soak zone also
acts to activate the flux within the solder paste. The
ramp rate in this zone is very low and the temperature
is raised near the melting point of solder. The
consequences of being at too high a temperature
in the soak zone are solder balls due to insufficient
fluxing (when the ramp is too fast) and solder splatter
due to excessive oxidation of paste (when the ramp
rate is too slow).
resistance.
Additionally high temperature can
promote oxide growth, depending upon the furnace
atmosphere which can degrade solder wetting.
Cooling Zone
The cooling rate of the solder joint after reflow is
also important. For a given solder system, the
cooling rate is directly associated with the resulting
microstructure which in turn, affects the mechanical
behavior of solder joints. The faster the cooling rate,
the smaller the grain size of the solder will be, and
hence the higher the fatigue resistance of the solder
joint. Conversely, rapid cooling will result in residual
stresses between TCE mismatched components.
Therefore, the cooling rate needs to be optimized.
The profile of choice can affect any of the following
areas to a different degree by one of more of the
profile zones [2].
•Temperature distribution across the assembly
•Plastic IC package cracking
•Solder balling
•Solder beading
•Wetting ability
•Residue cleanability
•Residue appearance and characteristics
•Solder joint voids
•Metallurgical reactions between solder and substrate surface
•Board flatness
•Microstructure of solder joints
•Residual stress level of the assembly
Reflow Zone
In this zone the temperature is kept above the melting
point of the solder for 30 to 60 seconds. The peak
temperature in this zone should be high enough for
adequate flux action and to obtain good wetting.
The temperature, however, should not be so high
as to cause component damage, board damage,
discoloration or charring of the board. Extended
duration above the solder melting point will damage
temperature sensitive components and potentially
create excessive intermetallic growth between the
solder and the I/O pad metallization which makes the
solder joint brittle and reduces solder joint fatigue
13
Application Note - Rev 0
03/2012
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
REFLOW PROFILES
Table 2 provides a breakdown of the reflow conditions provided by the JEDEC standard J-STD-020C [5]
for leadfree solders. While this standard specifies a peak reflow temperature of 260 oC, the actual peak
temperature subjected to the part during reflow must not exceed 260 6 5 oC.
Table 3: Lead-free MSL Reflow Profile Breakdown
JEDEC
specifications
Avg. Ramp-up (TL to TP)(1), (2)
3 C/second max
Dwell Time (175 25 C)
60-120 seconds
Ramp-up 200 C to 217 C
3 C/second max
Time Above 217 C
60-150 seconds
Time Within 5 C of Peak
20-40 seconds max
Peak Temperature(3)
260 -5/+0 C
Average Ramp-down
6 C/second max
Notes:
(1) TL is the solder eutectic temperature
(2) TP is the peak temperature
(3) Actual peak temperature will be product dependent
300
240 Profile
260 Profile
250 Profile
250
Temperature (C)
200
150
100
50
0
0:00:00
0:01:00
0:02:00
0:03:00
0:04:00
0:05:00
Time (minutes)
Figure 10: Comparison of High Temperature Reflow Profiles
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Application Note - Rev 0
03/2012
0:06:00
Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
REWORK GUIDELINE
The most common method of repairing surface mount
devices is by using hot air devices. During this rework
process care should be taken to prevent thermal
damage to adjacent component or substrates. The
following guidelines should be used to prevent
thermal damage and to produce an acceptable solder
joint after repair/rework [1]:
· Characterize the rework process carefully so as
not to overheat and damage the device.
· Keep the number of times a part is removed
and replaced to a maximum of two.
· Preheat the substrate for about 30 minutes to
about 95 °C.
· Use an appropriate attachment to direct the flow
of hot air to the component to be removed or
replaced.
· Minimize the heat time to reduce the device
exposure to high temperatures.
Table 4: Moisture Sensitive Levels
Level
Floor Life
1
Unlimited
2
1 year
2a
4 weeks
3
168 hours (ANADIGICS product)
4
72 hours
5
48 hours
5a
24 hours
6
Time on Label
The following flowchart shows the flow of the tests
performed to determine the MSL Rating:
MSL (Moisture Sensitive Levels)
MSL levels are used to classify the sensitivity of a
microelectronic package to moisture. Packages can
be classified from level 1 (hermetic package) to level
6 (very sensitive). Knowledge of the MSL level of
a package is crucial during 2nd level solder reflow
for proper assembly of the product as these levels
dictate the duration that the package can be exposed
to the atmosphere before being exposed to solder
reflow temperatures. Once this time limit expires,
the package is at risk for catastrophic damage during
reflow. Table 4 summarizes the different MSL levels
as defined by JEDEC Standards J--STD-020B and
J-STD-020C [2,4].
Perform Pre-stress
electrical test and
Sonoscans
Pre-condition, Temp Cycle,
5 cycles
-40 8C to 60 8C
Dry bake for 24 hours at
125 8C
Soak Conditions
− 85 8C/85 RH for 168 hours (MSL-1) for leaded packages
− 85 8C/60 RH for 168 hours (MSL-2) for QFNs
− 30 8C/60 RH for 168 hours (MSL-3) for modules
Reflow parts at peak
temperature relevant to
package
Perform Post-stress
electrical test and
Sonoscans
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Multi-Band LTE/CDMA/WCDMA/HSPA Power Amplifier
REFERENCES
[1] Ray P. Prasad; Surface Mount Technology - Principles and Practice; Van Nostrand Reinhold - New
York; 1989; Pages 311 -328.
[2] Charles Harper; Electronic Packaging and
Interconnect Handbook; “Solder Technologies for
Electronic Packaging Assembly”; McGraw-Hill 2000;
Pages 6.1 -6.83
[3] http://www.ecd.com/emfg/instruments/tech1.asp
[4] JDEC Standard J-STD-020C. Mositure/Reflow
Sensitivity Classification for non-hermetic Solid
State Surface Mount Devices. July 2004.
[5] ANADIGICS Application Note: Soldering Guidelines for Module PCB Mounting Revision 12.
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
warning
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
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