HD74LVC16374A 16-bit D-type Flip Flops with 3-state Outputs REJ03D0367–0400Z (Previous ADE-205-122B (Z)) Rev.4.00 Jul. 30, 2004 Description The HD74LVC16374A has sixteen edge trigger D type flip flops with three state outputs in a 48 pin package. Data at the D inputs meeting set up requirements are transferred to the Q outputs on positive going transitions of the clock input. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and highspeed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • VCC = 2.0 V to 5.5 V • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±24 mA (@VCC = 3.0 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LVC16374ATEL TSSOP–48 pin TTP–48DBV T EL (1,000 pcs/reel) Function Table Inputs G CK D Output Q H L L L X ↑ ↑ L X L H X Z L H Q0 H: L: X: Z: ↑: Q0 : High level Low level Immaterial High impedance Low to high transition Level of Q before the indicated steady input conditions were established. Rev.4.00 Jul. 30, 2004 page 1 of 8 HD74LVC16374A Pin Arrangement 48 1CK 1G 1 1Q1 2 G Q CK D 47 1D1 1Q2 3 G Q CK D 46 1D2 G Q CK D 44 1D3 G Q CK D 43 1D4 1Q5 8 G Q CK D 1Q6 9 G Q CK D G Q CK D G Q CK D 2Q1 13 G Q CK D 36 2D1 2Q2 14 G Q CK D 35 2D2 G Q G Q CK D G Q G Q CK D G Q G Q CK D 27 2D7 CK D 26 2D8 GND 4 1Q3 5 1Q4 6 VCC 7 GND 10 1Q7 11 1Q8 12 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 45 GND CK D CK D GND 21 2Q7 22 2Q8 23 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 34 GND 33 2D3 32 2D4 31 VCC 30 2D5 29 2D6 28 GND 2G 24 25 2CK (Top view) Rev.4.00 Jul. 30, 2004 page 2 of 8 42 VCC HD74LVC16374A Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC Input diode current Input voltage Output diode current IIK VI IOK V mA V mA Output voltage VO Output current VCC, GND current / pin Storage temperature IO ICC or IGND Tstg –0.5 to 6.0 –50 –0.5 to 6.0 –50 50 –0.5 to VCC +0.5 –0.5 to 6.0 ±50 100 –65 to +150 V Conditions VI = –0.5 V VO = –0.5 V VO = VCC +0.5 V Output "H" or "L" Output "Z" or VCC:OFF mA mA °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Ratings Unit Conditions Supply voltage VCC 1.5 to 5.5 V Data hold Input / output voltage VI VO V V At operation G, CK, D Output "H" or "L" Output "Z" or VCC:OFF Operating temperature Output current Ta IOH IOL Input rise / fall time *1 tr, tf 2.0 to 5.5 0 to 5.5 0 to VCC 0 to 5.5 –40 to 85 –12 –24*2 12 24*2 10 °C mA mA ns/V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. 2. Duty cycle ≤ 50% Rev.4.00 Jul. 30, 2004 page 3 of 8 VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 2.7 V VCC = 3.0 V to 5.5 V HD74LVC16374A Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V) Min Max Unit Input voltage VIH 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 5.5 2.7 3.0 3.0 4.5 2.7 to 5.5 2.7 3.0 4.5 0 to 5.5 2.7 to 5.5 2.0 VCC×0.7 — — VCC–0.2 2.2 2.4 2.2 3.8 — — — — — — — — 0.8 VCC×0.3 — — — — — 0.2 0.4 0.55 0.55 ±5.0 ±5.0 V 0 2.7 to 3.6 2.7 to 5.5 3.0 to 3.6 — — — — 20 ±20 20 500 µA µA VIL Output voltage VOH VOL Input current Off state output current IIN IOZ Output leak current Quiescent supply current IOFF ICC ∆ICC Rev.4.00 Jul. 30, 2004 page 4 of 8 Test Conditions V V IOH = –100 µA IOH = –12 mA IOH = –24 mA V IOL = 100 µA IOL = 12 mA IOL = 24 mA µA µA VIN = 5.5 V or GND VIN = VCC, GND VOUT = 5.5 V or GND VIN / VOUT = 5.5 V VIN / VOUT = 3.6 to 5.5 V VIN = VCC or GND VIN = one input at(VCC–0.6)V, other inputs at VCC or GND µA HD74LVC16374A Switching Characteristics Ta = –40 to 85°C From (Input) To (Output) ns CK Q ns G Q ns G Q Item Symbol VCC (V) Min Typ Max Unit Maximum clock frequency fmax tPLH tPHL Output enable time tZH tZL Output disable time tHZ tLZ Setup time tsu Hold time th Pulse width tw 80.0 100.0 125.0 — 1.5 — — 1.5 — — 1.5 — 2.0 2.0 2.0 1.5 1.5 1.5 3.0 3.0 3.0 — — — — — — 150.0 — — — — — — — — — — — — — — — — — — — — — — 3.0 15.0 — — — 7.7 7.0 5.5 8.0 7.0 6.0 8.0 7.0 6.0 — — — — — — — — — — 1.0 1.0 — — MHz Propagation delay time 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 3.3±0.3 5.0±0.5 2.7 2.7 Between output pins skew tOSLH *1 tOSHL Input capacitance Output capacitance Note: CIN CO 1. This parameter is characterized but not tested. tosLH = | tPLHm – tPLHn |, tosHL = | tPHLm – tPHLn | Rev.4.00 Jul. 30, 2004 page 5 of 8 ns ns ns ns pF pF HD74LVC16374A Test Circuit VCC VCC Input 1G, 2G 1Q1 to 2Q8 Pulse Generator Zout = 50 Ω Input See Function Table Output 500 Ω S1 CL = 50 pF 450 Ω 50 Ω Scope 1D1 to 2D8 S1 Symbol Pulse Generator Vcc=2.7V, 3.3±0.3V Vcc=5.0±0.5V OPEN OPEN GND GND 6V 2×Vcc t PLH / t PHL 1CK, 2CK Zout = 50 Ω t su / t h / t w t ZH/ t HZ t ZL / t LZ Note: OPEN *1 See under table GND 1. CL includes probe and jig capacitance. Waveforms – 1 tf tr Vref Vref 10 % tr Input D 10 % tf GND VIH 90 % 90 % 10 % 10 % t PHL t PLH Output Q VIH 90 % 90 % Input CK GND VOH Vref Vref VOL Rev.4.00 Jul. 30, 2004 page 6 of 8 HD74LVC16374A Waveforms – 2 tf tr VIH 90 % 90 % Vref Vref Input CK 10 % tw tsu Vref 10 % tw GND th VIH Input D Vref Vref GND Waveforms – 3 tf Input G tr 90 % Vref 10 % VIH 90 % Vref 10 % t ZL GND t LZ ≈V OH1 Vref Waveform - A t ZH Waveform - B VOL + 0.3 V t HZ VOH – 0.3 V Vref VOL VOH ≈V OL1 TEST VIH Vref VOH1 VOL1 Notes: Vcc=2.7V, 3.3±0.3V Vcc=5.0±0.5V 2.7 V Vcc 1.5 V 3V 50%Vcc GND GND Vcc 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform : PRR = 10 MHz, duty cycle 50% 3. Waveform – A shows input conditions such that the output is "L" level when enable by the output control. 4. Waveform – B shows input conditions such that the output is "H" level when enable by the output control. Rev.4.00 Jul. 30, 2004 page 7 of 8 HD74LVC16374A Package Dimensions As of January, 2002 12.5 12.7 Max 48 Unit: mm 6.10 25 1 *0.19 ± 0.05 0.50 24 0.08 M 1.0 8.10 ± 0.20 0.65 Max *Pd plating Rev.4.00 Jul. 30, 2004 page 8 of 8 0.10 ± 0.05 0.10 *0.15 ± 0.05 1.20 Max 0˚ – 8˚ 0.50 ± 0.1 Package Code JEDEC JEITA Mass (reference value) TTP–48DBV — — 0.20 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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