1 IMP5241/42/43

IMP52 4 1/42/431
DATA COMMUNICATIONS
Key Features
9-Line Multimode LVD/SE
SCSI Terminator
The IMP5241/42/43 is a multimode SCSI terminator that conforms to the
SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10
standards committee for low voltage differential (LVD) termination,
while providing backwards compatibility to the SCSI, SCSI-2, and SPI
single-ended specifications. Multimode compatibility permits the use of
legacy devices on the bus without hardware alterations. Automatic mode
selection is achieved through voltage detection on the diffsense line.
The IMP5241/42/43 delivers the ultimate in SCSI bus performance while
saving component cost and board area. Elimination of the external capacitors also mitigates the need for a lengthy capacitor selection process. The
individual high bandwidth drivers also maximize channel separation
and reduce channel to channel noise and cross talk. The high bandwidth
architecture insures ULTRA2 performance while providing a clear migration path to ULTRA3 and beyond.
When the IMP5241/42/43 is enabled, the differential sense (DIFFSENSE)
pin supplies a voltage between 1.2V and 1.4V. In application, this pin is
tied to the DIFFSENSE input of the corresponding LVD transceivers. This
action enables the LVD transceiver function. DIFFSENSE is capable of
supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places
the IMP5241/42/43 in a high impedance state indicating the presence of
an HVD device. Tying the pin LOW places the part in a single-ended
mode while also signaling the multimode transceiver to operate in a single-ended mode.
Recognizing the needs of portable and configurable peripherals, the
IMP5241/42/43 have a TTL compatible sleep/disable mode. During this
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Auto-selectable LVD or single-ended termination
3.0pF maximum disabled output capacitance
Fast response, no external capacitors required
Compatible with active negation drivers
15µA supply current in disconnect mode
Logic command disconnects all termination lines
DIFFSENSE line driver
Ground driver integrated for single-ended
operation
Current limit and thermal protection
Hot-swap compatible (single-ended)
Compatible with SCSI 1, 2, 3, FAST-20, and the
pending SPI-2 LVD
Pin compatible with DS2118, UCC5630 and
LX5241/42/43
sleep/disable mode, power dissipation is reduced to a
meager 15µA while also placing all outputs in a high
impedance state. Also during sleep/disable mode, the
DIFFSENSE function is disabled and is placed in a high
impedance state.
Another key feature of the IMP5241/42/43 is the master/slave function. Driving this pin HIGH or floating the
pin enables the 1.3V DIFFSENSE reference. Driving the pin
LOW disables the on board DIFFSENSE reference and
enables use of an external master reference device.
Block Diagram
Internal VREF
1.30V
DISCONNECT
(IMP5241)
Power ON
SE
2.2V
DISCONNECT
(IMP5242)
1.07mA
LVD
1.25V
200
52.5
SE
DISC/HVD
LVD(-) / SE
SE
LVD
HVD
52.5
M/S
10mA
1.07mA
DIFFSENSE
1 of 9
SE 2.85V, 22.5mA
VTERM
MODE Control & Delay
SE
HVD
Window
Comp.
20kΩ
20
LVD
LVD(+) / SE
(Pseudo-GND)
Latch
SE
HVD
LVD
LVD
DIFF B
Power ON
Power ON & MODE Delay
5241/42_01.eps
© 2001 IMP, Inc.
Data Communications
1
IMP52 4 1/42/431
Pin Configuration
SSOP-36
TSSOP-28
NC
1
36 VTERM
NC
2
35 HVD
NC
34 LVD
3
1+
4
33 SE
1–
5
32 9 –
2+
6
31 9+
2–
7
30 8 –
HEATSINK
8
29 8+
HEATSINK
9
HEATSINK 10
IMP5241/42
28 HEATSINK
27 HEATSINK
26 HEATSINK
3+ 11
25 7–
3 – 12
4+ 13
24 7+
4 – 14
23 6 –
5+ 15
22 6+
5 – 16
21 DIFF B
TSSOP-24
NC
1
28 VTERM
1+
2
27 NC
1+
1
24 VTERM
1–
3
26 9–
1–
2
23 NC
2+
4
25 9+
2+
3
22 9 –
2–
5
24 8–
2–
4
21 9+
NC
6
23 8+
3+
5
20 8 –
3+
7
22 NC
3–
6
3–
8
21 7–
4+
7
18 7–
4+
9
20 7+
4–
8
17 7+
4 – 10
19 6–
5+
9
16 6 –
5+ 11
18 6+
5 – 10
15 6+
5 – 12
17 DIFF B
IMP5243
16 DIFFSENSE
DISCONNECT 13
15 MASTER/SLAVE
GND 14
IMP5241/42
19 8+
14 DIFFSENSE
DISCONNECT 11
13 MASTER/SLAVE
GND 12
DW Package
5241/42_03.eps
5243_02.eps
20 DIFFSENSE
DISCONNECT 17
19 MASTER/SLAVE
GND 18
DB Package
5241/42_02.eps
Ordering Information
Part Number
Note:
Temperature Range
Package
IMP5241CDB
0°C to 70°C
36-pin Plastic SSOP
IMP5242CDB
0°C to 70°C
36-pin Plastic SSOP
IMP5241CPW
0°C to 70°C
24-pin Plastic TSSOP
IMP5242CPW
0°C to 70°C
24-pin Plastic TSSOP
IMP5243CPW
0°C to 70°C
28-pin Plastic TSSOP
5241/42_t02.eps
For Tape and Reel, append the letter “T” to part number. (i.e. IMP5241CDBT)
Absolute Maximum Ratings1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V
Operating Junction Temperature
Plastic (DB, PW Packages) . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C
Note:
1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Thermal Data
DB Package:
Thermal Resistance Junction-to-Ambient, θJA . . . . . . 50°C/W
PW Package:
Thermal Resistance Junction-to-Ambient, θJA . . . . . . 100°C/W
2
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of
the device/pc-board system. No ambient airflow is assumed.
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© 2001 IMP, Inc.
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IMP52 4 1/42/431
Pin Description
Pin Name
1-, 2-, 3-, 4-, 5-, 6-, 7-, 8-, 9-
Function
Negative signal termination lines for LVD mode. Signal termination lines for SE mode.
1+, 2+, 3+, 4+, 5+, 6+, 7+, 8+, 9+ Positive signal termination lines for LVD mode. Pseudo-ground lines for SE mode.
VTERM
DISCONNECT (IMP5241)
DISCONNECT (IMP5242)
GND
MASTER / SLAVE
Power supply pin for terminator. Connect to SCSI bus TermPwr. Must be decoupled by one
4.7µF low-ESR capacitor for every three terminator devices. It is absolutely necessary to
connect this pin to the decoupling capacitor through a very low impedance (big traces on PCB).
Keeping distances very short from the decoupling capacitors to the VTERM pin is also critical.
The value of the decoupling capacitor is somewhat layout dependant and some applications
may benefit from an additional 0.1µF decoupling capacitor at the VTERM pin.
Enables / disables terminator. See Table 2 for logic levels.
Terminator ground pin. Connect to ground.
Sometimes referred to as M/S pin. Used to select which terminator is the controlling device.
MASTER/SLAVE pin HIGH or Open enables the DIFFSENSE output drive. See Table 1.
DIFFSENSE
This is a dual function pin. It drives the SCSI bus DIFFSENS line. It is also the sense pin to
detect the SCSI bus mode (LVD, SE or HVD). DIFFSENSE output drive can be disabled with a
LOW level on the MASTER/SLAVE pin. See Table 1 and Table 2. Internally connected to DIFF
B pin through 20kΩ resistor.
DIFF B
Internally connected to DIFFSENSE pin through 20kΩ resistor. It can be used as a mode sense
pin when the device is a non-controlling terminator (MASTER/SLAVE pin is LOW). An RC filter
(20kΩ / 0.1µF) is not required on the IMP5241/42, as it has an internal timer.
SE
Single-ended output. When HIGH, the terminator is operating in SE mode.
LVD
Low Voltage Differential output. When HIGH, the terminator is operating in LVD mode.
HVD
High Voltage Differential output. When HIGH, the terminator is operating in HVD mode.
HEATSINK
Attached to die mounting pad, but not bonded to GND pin. Pins should be considered a heat
sink only, and not a true ground connection. It is recommeneded that these pins be connected to
ground, but can be left floating.
5241/42_t08.at3
© 2001 IMP, Inc.
Data Communications
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IMP52 4 1/42/431
Recommended Operating Conditions2
Parameter
Max
Units
3.0
5.25
V
3.5
5.25
Signal Line Voltage
0
5.0
V
Disconnect Input Voltage
0
VTERM
V
Operating Virtual Junction Temperature Range —IMP5241C/5242C
0
70
TermPwr Voltage
LVD
Symbol
Min
VTERM
SE
Note:
Typ
°C
5241/42_t03.eps
2. Range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0°C ≤ TA ≤ 70°C. TermPwr = 4.75V.
DISCONNECT: IMP5241 = LOW, DISCONNECT: IMP5242 = HIGH. Low duty cycle pulse testing techniques are used which maintain
junction and case temperatures equal to the ambient temperature.
Parameter
Symbol Condition
LVD Terminator Section
TermPwr Supply Current
LVD ICC
Common Mode Voltage
Offset Voltage
Differential Terminator Impedance
Common Mode Impedance
Output Capacitance
VCM
VFSB
ZD
ZCM
CO
Output Leakage
ILEAK
Mode Change Delay
DIFFSENSE Section
DIFFSENSE Output Voltage
DIFFSENSE Output Source Current
DIFFSENSE Sink Current
DIFFSENSE Output Leakage
tDF
ISINK (DIFF)
ILEAK (DIFF)
Single-Ended Terminator Section
TermPwr Supply Current
SE ICC
VDIFF
IDIFF
Terminator Output High Voltage
Output Current
Note:
4
VO
IO
Min Typ Max Units
All terminator lines = Open
IMP5241/43: DISCONNECT > 2.0V
IMP5242: DISCONNECT < 0.8V
Open circuit between – and + (see Note 3)
VOUT differential = – 1V to 1V
0V to 2.5V
IMP5241/43: DISCONNECT > 2.0V
IMP5242: DISCONNECT < 0.8V
IMP5241/43: DISCONNECT > 2.0V
IMP5242: DISCONNECT < 0.8V
VLINE = 0V to 4V, TA = 25°C
IMP5241/43: DISCONNECT > 2.0V
IMP5242: DISCONNECT < 0.8V
VTERM = 0V, VLINE = 2.7V
DIFFSENSE = 1.4V to 0V
VDIFF = 0V
VDIFF = 2.75V
IMP5241/43: DISCONNECT > 2.0V
IMP5242: DISCONNECT < 0.8V
TA = 25°C
1.125
100
100
100
30
35
mA
µA
1.25
112
105
200
2.5
1.375
125
110
300
V
mV
Ω
Ω
pF
2
µA
1
115
1.2
5.0
All terminator lines = Open, MASTER/SLAVE = 0V
All terminator lines = 0.2V, MASTER/SLAVE = 0V
IMP5241/43: DISCONNECT > 2.0V
IMP5242: DISCONNECT < 0.8V
VOUT = 0.2V
25
15
2.6
21
1.3
ms
1.4
15.0
200
10
V
mA
7
214
15
10
226
35
mA
2.85
23
24
µA
µA
µA
V
mA
5241/42_t04.eps
3. Open circuit failsafe voltage.
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© 2001 IMP, Inc.
r
IMP52 4 1/42/431
Electrical Characteristics
Parameter
Symbol Condition
Min Typ Max Units
Single-Ended Terminator Section (cont.)
Sink Current
Output Capacitance
ISINK
CO
VOUT = 4V, all lines
45
IMP5241/43: DISCONNECT > 2.0V
65
mA
2.5
pF
IMP5242: DISCONNECT < 0.8V
Leakage Current
ILEAK
IMP5241/43: DISCONNECT > 2.0V
2
µA
IMP5242: DISCONNECT < 0.8V
VOUT = 0V to 4V, TA = 25°C
IMP5241/43: DISCONNECT > 2.0V
1
IMP5242: DISCONNECT < 0.8V
VTERM = 0V, VLINE = 2.7V, TA = 25°C
Ground Driver Impedance
ZG
I = 1mA
100
Thermal Shutdown
150
Ω
°C
DISCONNECT Section
DISCONNECT Thresholds
Input Current
0.8
VTH
2.0
IIL
IMP5241/43: DISCONNECT = 0V
IIL
IMP5242: DISCONNECT = 0V
100
10
IIH
IMP5241/43: DISCONNECT = 2.4V
100
IIH
IMP5242: DISCONNECT = 2.4V
V
µA
nA
10
nA
µA
MASTER/SLAVE Section
MASTER/SLAVE Thresholds
Input Current
0.8
VTH (MS)
IIL (MS)
MASTER/SLAVE = 0V
IIL (MS)
MASTER/SLAVE = 2.4V
2.0
10
100
V
µA
nA
5241/42_t05.at3
© 2001 IMP, Inc.
Data Communications
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IMP52 4 1/42/431
Application Information
VOD = V(–) – V(+), Logic = 0
NEGATED
V(+)
VCM
100mV
0V
V(–)
–100mV
5241/42_05.eps
5241/42_04.eps
Figure 1. Bus Voltage
Figure 2. VOD
–
IMP5241
–
+
+
IMP5241
5241/42_06.eps
Figure 3.
Table 1. MASTER/SLAVE Function Table
MASTER/SLAVE
DIFFSENSE Status
Output Current
L*
HiZ
0mA
H
1.3V
15mA Source
Open (Pull-up)
1.3V
15mA Source
5241/42_t06.at3
* When in the LOW state, the terminator will detect the DIFFSENSE line state.
Table 2. DIFFSENSE/Power Up/Power Down Function Table
IMP5241/5243
DISCONNECT
IMP5242
DISCONNECT
Outputs
DIFFSENSE
Status
Type
Current
L
H
L < 0.5V
Enable
SE
7mA
L
H
0.7V to 1.9V
Enable
LVD
21mA
L
H
H > 2.4V
Disable
Hi Z
1mA
H
L
X
Disable
Hi Z
10µA
Open
Open
X
Disable
Hi Z
10µA
5241/42_t07.eps
6
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© 2001 IMP, Inc.
r
IMP52 4 1/42/431
Application Information
HOST
PERIPHERAL
VTERM
TERMPOWER
1–
1–
1+
1+
IMP5241/43
IMP5242
Data Lines (9)
9–
9+
9+
DIFFSENSE
DISCONNECT
DISCONNECT
M/S
M/S
GND
GND
DIFF B*
+
4.7µF
VTERM
1–
1–
1+
VTERM
9–
IMP5241/43
IMP5242
9–
9+
9+
Data Lines (9)
DIFFSENSE
4.7µF
DISCONNECT
M/S
M/S
GND
GND
DIFF B*
DIFF B*
1–
1–
1+
IMP5241/43
IMP5242 9–
+
DIFFSENSE
DISCONNECT
VTERM
DISCONNECT
DIFF B*
1+
IMP5241/43
IMP5242
TERMPOWER
IMP5241/43
IMP5242
9–
DIFFSENSE
DISCONNECT
VTERM
VTERM
1+
Data Lines (9)
9+
DIFFSENSE
DISCONNECT
IMP5241/43
IMP5242
9–
9+
DIFFSENSE
DISCONNECT
M/S
M/S
GND
GND
DIFF B*
DIFF B*
* The DIFF B pin is not present on the IMP5241/5242 24-pin PW package.
The DIFFSENS signal must be connected to the DIFFSENSE pin on the PW package.
5241/42_07.eps
Figure 4. IMP Terminator Application Schematic
© 2001 IMP, Inc.
Data Communications
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IMP52 4 1/42/431
Application Information
HOST
PERIPHERAL
VTERM
TERMPOWER
1–
1–
1+
1+
IMP5241/43
IMP5242
9–
9–
9+
9+
DIFFSENSE
DISCONNECT
DISCONNECT
20k
20k
M/S
GND
DIFF B*
NC*
Pin
1
+
4.7µF*
0.1µF
4.7µF
VTERM
DISCONNECT
M/S
GND
+
TERMPOWER
IMP5241/43
IMP5242
Data Lines (9)
DIFFSENSE
DISCONNECT
VTERM
DIFF B*
+
+
0.1µF 4.7µF*
1–
1–
1+
1+
IMP5241/43
IMP5242
NC*
+ Pin 1
Data Lines (9)
VTERM
+
IMP5241/43
IMP5242
9–
9–
9+
9+
4.7µF
DIFFSENSE
DIFFSENSE
DISCONNECT
DISCONNECT
M/S
M/S
GND
GND
DIFF B*
DIFF B*
NC*
Pin
1
+
4.7µF*
NC*
+ Pin 1
4.7µF*
VTERM
1–
1–
1+
1+
IMP5241/43
IMP5242
Data Lines (9)
IMP5241/43
IMP5242
9–
9–
9+
9+
DIFFSENSE
VTERM
DIFFSENSE
DISCONNECT
DISCONNECT
M/S
M/S
GND
GND
DIFF B*
NC*
Pin
1
+
DIFF B*
NC*
Pin 1
+
4.7µF*
4.7µF*
* The capacitor on pin 1 can be placed on the IMP5241CDB, IMP5242CDB or the IMP5243CPW to be pin compatible with other devices.
This VREG/REF capacitor is not required with IMP devices.
5241/42_08.eps
Figure 5. Suggested IMP5241/5242/5243 Universal Application Schematic
(Please reference manufacture’s current data sheet to ensure compatibility)
8
408-432-9100/www.impweb.com
© 2001 IMP, Inc.
r
IMP52 4 1/42/431
Package Dimensions
DB
Inches
Millimeters
Min
Max
Min
Max
Plastic (SSOP) Widebody SOIC (36-Pin)
Plastic (SSOP) Widebody SOIC (36-Pin)
36
19
1
18
E
A
B
C
D
E
F
G
H
L
M
P
*LC
P
D
E
F
M
A
SEATING PLANE
B
H
L
G
C
36-Pin (SSOP).eps
PW
A
B
C
D
E
F
G
H
L
M
P
*LC
P
1 2 3
E
D
F
A H
SEATING PLANE B
M
L
G
C
28-Pin (TSSOP).eps
PW
Thin Small Shrink Outline (TSSOP) (24-Pin)
E
2.14
2.54
0.29
0.51
0.23
0.32
15.20
15.40
7.40
7.60
0.80 BSC
0.10
0.30
2.44
2.64
0.40
1.27
0°
8°
10.11
10.51
–
0.10
Thin Small Shrink Outline (TSSOP) (28-Pin)
Thin Small Shrink Outline (TSSOP) (28-Pin)
E
0.084
0.100
0.011
0.020
0.0091
0.0125
0.598
0.606
0.291
0.299
0.031 BSC
0.004
0.012
0.096
0.104
0.016
0.050
0°
8°
0.398
0.414
–
0.004
P
1 2 3
.032
.041
0.007
0.012
0.0035
0.0079
0.378
0.386
0.169
0.176
0.025 BSC
0.002
0.005
–
0.047
0.017
0.030
0°
8°
0.25 BSC
–
0.004
0.80
0.19
0.09
9.60
4.30
0.65 BSC
0.05
–
0.45
0°
0.15
1.20
0.75
8°
6.40 BSC
–
0.10
Thin Small Shrink Outline (TSSOP) (24-Pin)
A
.032
.041
B
0.007
0.012
C
0.0035
0.0079
D
0.303
0.311
E
0.169
0.176
F
0.025 BSC
G
0.002
0.005
H
–
0.047
L
0.017
0.030
M
0°
8°
P
0.246
0.256
*LC
–
0.004
* Lead Coplanarity.
0.80
0.19
0.09
7.70
4.30
1.05
0.30
0.20
7.90
4.5
0.65 BSC
0.05
–
0.45
0°
6.25
–
E
D
1.05
0.30
0.20
9.80
4.5
0.15
1.20
0.75
8°
6.50
0.10
5241/42_t01.eps
F
A H
SEATING PLANE B
G
L
M
C
24-Pin (TSSOP).eps
© 2001 IMP, Inc.
Data Communications
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IMP52 4 1/42/431
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Fax: 408-434-5904
e-mail: [email protected]
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
© 2001 IMP, Inc.
Printed in USA
Publication #: 7001
Revision:
C
Issue Date:
11/01/01
Type:
Product