TMDXEVM6670L_EVM _A102-1_DSN

5
4
3
2
1
D
D
TMS320C6670 EVM Board for TI
Product name : DSPM-8302E
C
C
Rev. A102-1
TOP
1.0 oz
L2_GND
1.0 oz
L3
0.5 oz
L4_PWR
1.0 oz
L5
0.5 oz
L6_GND
1.0 oz
3.6mils p.p
4mils
PCB PN : 19C2830201
Project Code :
4.8mils p.p
5mils
L7_GND
PCB Thickness : 62 mils(1.6mm)
12 Layers
L8
L10
B
4.5mils p.p
0.5 oz
BOT
A
DISCLAIMER: THIS CIRCUIT DESIGN IS
PROVIDED AS REFERENCE ONLY,
WITHOUT WARRANTY EXPRESSED OR
IMPLIED. THE USER IS ENCOURAGED
TO PERFORM ALL DUE DILIGENCE WITH
RESPECT TO DESIGN AND ANALYSIS.
Copyright (C) 2010, 2011 Texas Instruments Incorporated.
All rights reserved. This document is proprietary to TI
and is intended solely for use by TI and its customers.
This document is not to be reproduced, distributed, or
disclosed to other parties in its entirety or in part
without the express written consent of TI.
core
1.0 oz
4.8mils p.p
0.5 oz
4mils
L11_GND
core
1.0 oz
5mils
L9_PWR
core
4.5mils p.p
4mils
B
core
core
1.0 oz
3.6mils p.p
1.0 oz
TI Information - Selective Disclosure
Texas Instruments
20450 Century Blvd
Germantown, MD 20874
USA
A
Designed for TI by ADVANTECH
Title
COVER PAGE
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
1
of
36
5
4
3
2
1
TITLE & TABLE OF CONTENTS
Page
D
Description
Page
Description
01
COVER PAGE
31
FPGA_XC3S200AN_B
02
TITLE & TABLE OF CONTENTS
32
FPGA_XC3S200AN_C
03
BLOCK DIAGRAM_AMC
33
Power ucd9222_UCD7242
04
POWER SEQUENCE
34
Power_1.2V/1.8V/2.5V/0.75V
05
POWER CONSUMPTION
35
Power_VCC5 / VCC3_AUX
06
POWER DISTRIBUTION
36
36_Power_VCC1V5 / Fix_VCC1V0
07
CLOCK DIAGRAM
08
FPGA_BLOCK
09
Management Map
10
AMC GF
11
MMC
12
DSP_SRIO_SGMII_PCIE_MCM
13
DSP_DDR3
14
DSP_JTAG_EMU_AIF
15
DSP_MISC
16
DSP_CLOCK_Smart Reflex
17
DSP_POWERA
18
DSP_POWERB
19
DSP_POWERC
20
DSP_GND
D
C
C
B
A
21
CLOCK_GEN1
22
CLOCK_GEN2
23
CLOCK_GEN3
24
DDR3
25
DDR3_ECC
26
USB-JTAG
27
Gbs Ethernt PHY
28
RJ45
29
Connectors for MCM & Debug
30
FPGA_XC3S200AN_A
B
A
Designed for TI by ADVANTECH
Title
TITLE & TABLE OF CONTENTS
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
2
of
36
5
4
3
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1
TMS320C6670 EVM BLOCK DIAGRAM
JTAG
DDR3(ECC)
*1. 64M X 16 / 512MB
SPI EEPROM
SYSPG_D1 LED
2. 128M X 16 / 1GB
128k‐bit
AT25128B
D
1. 1Gb X 16 2. 1Gb X 8
DDR3 ‐1333
from MMC
HyperLink CONN.
AMC_State
CDCE62002
CLK#2
CLK1_SPI
CLK2_SPI
CLK3_SPI
CLK#3
NUMONYX
NAND512R3A2DZA6E
512Mb 64M X8
AIF CLK & FS
RP1/SYNC
MDIO
UART
DSP_UART
60‐Pin EMU CONN.
DSP_I2C(1.8V)
DSP_UART(3.3V)
DSP_SPI(1.8V)
GPIO[0:15](1.8V)
USB
AIFx6
DSP_I2C
I2C
EMU[2:17]
C
SRIOx4
AIFx6
TI_TMS320C6670
DSP_SGMII_P1 & MDIO
Miscellaneous I/O 80 Pin‐conn.
PCIEx2
SRIOx4
DSP
SWITCH
(TS3L301)
JTAG & EMU[0:1]
AMC_JTAG
CH‐A
USB‐JTAG
FT2232HL
CH‐B
SWITCH
(TS3L301)
B
A
PIN
PIN
Port mapping
POWER 12V
128k‐byte
ST_M24M01
Power
Power Control
RS232
MAX3221EAE
DSP_UART
PWR CONN
RAM
FPGA
PHY
Others
DSP
UCD9222
C
AMC_JTAG
Pin‐Header 3x1
2.54mm
Miscellaneous I/O 80 Pin conn. Signal
Port mapping
I2C
NU Resistors
EEPROM
DSP_SGMII_P1 & MDIO
PIN
D
SGMIIx1
PCIEx2
EMU[2:17] JTAG &
EMU[0:1]
88E1111‐B2
Mini‐USB
SGMII1 MAC0
Power Control
Sequence
Control
ENET PHY
Hyper Link
SPI
NAND FLASH
BM_GPIO(0~15) /
PCIESSEN / User define /
DSP_CORECLKSEL /
FPGA_PACLKSEL
XC3S200AN
(XILINX)
DDR3
GPIO
DIP SW
FPGA
CDCE62005
RJ45
SPI
GPIO[0:15]
DSP_SPI#1
DSP_GPIO
SW_GPIO
DEBUG_LED
CDCE62005
N25Q128A21BSF40F
MMC
MUX
CLK#1
ROM_SPI
(MSP430)
D1
D2
NOR 128M‐bit
JTAG
IPMB‐L
MMC
to FPGA
HyperLink
50Gbps
#0
SPI Flash
+V3.3_MP
iPass+HD
DDR3‐1333
w/ ECC
AMC_State
User controlled LED ‐ 4
JTAG
1
FPGA JTAG
AMC Board
SBW_MMC1
UCD9222_PMbus
AMC Port mapping
PIN
Port mapping
Port mapping
PIN
Port mapping
PIN
01
Gnd
41
44
03
SDA
43
06
46
05
SCL
45
08
48
07
47
10
50
GPIO00
09
49
12
52
GPIO01
11
51
14
54
GPIO02
13
53
16
56
GPIO03
15
55
TIMI0
18
58
GPIO04
17
57
TIMO0
20
60
GPIO05
19
59
TIMI1
22
62
GPIO06
21
61
TIMO1
24
64
GPIO07
23
63
SSPMISO
26
66
GPIO08
25
65
SSPMOSI
28
68
GPIO09
27
67
SSPCS1
30
70
GPIO10
29
69
SSPCK
32
72
GPIO11
31
71
UARTTXD
34
74
GPIO12
33
73
UARTRXD
36
76
GPIO13
35
75
UARTRTS
38
78
GPIO14
37
77
UARTCTS
Title
40
80
GPIO15
39
79
Gnd
Size
02
42
04
2
80
1
79
TCLKA
TCLKA
11
TCLKB
TCLKB
12
AIF_0
FCLKA
100MHz
13
AIF_1
SGMII
14
AIF_2
00
01
15
AIF_3
02
16
TCLKC TCLKD
17
AIF_4
03
04
PCI-E_1
18
AIF_5
05
PCI-E_2
19
AIF_CLK & FS
20
06
3
Expansion I2C & external RP1CLK
07
08
SRIO_1
09
SRIO_2
10
SRIO_3
JTAG
AMC_JTAG
A
Designed for TI by ADVANTECH
BLOCK DIAGRAM_AMC
Date:
4
SRIO_4
B
C
5
Port mapping
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
3
of
36
5
4
3
2
1
VCC3V3_MP_AMC
S0
Power Sequence
VCC3V3_MP
MMC
S1
VCC12
S2
D
Other
FT2232H XC3S200AN
VCC3V3_AUX
XC3S200AN
VCC1V8_AUX
XC3S200AN
VCC1V2
D
S3
S4
88E1111
S5
S6
DSP TMS320C6670
PMBUS &
UCD9222_ENA2
S8
VCC1V0
DSP TMS320C6670
5ms
CVDD
S7
S9
38ms
10ms
5ms
Power Sequence
control
only
10ms
VCC1V8_EN
S10
DSP TMS320C6670
S11
S12
C
62ms
PMBUS &
UCD9222_ENA1
500us
VCC1V8
8.4ms
VCC1V5_EN
DDR3
DSP TMS320C6670
S13
VCC0V75_EN
S14
DDR3 Vref
VCC0V75
DDR3
DSP TMS320C6670
3.5ms
DDR3 SDRAM
VCC1V5
C
5ms
14us
6ms
16ms
S15
VCC2V5_EN
S16
500us
VCC2V5
88E1111
S17
VCC5_EN
S18
VCC5
XDS560V2 Mazzenine Board
50ms
T=18mS
RESET#
including
peripherals.
T=5mS
POR#
Reset Sequence
T=5mS
RESETFULL#
B
B
by DSP chip
RESETSTAT#
REFCLKP&N
by REFCLK1_PD#
CLOCK1_PLL_LOCK
REFCLKP&N
by REFCLK2_PD#
CLK Sequence
CLOCK2_PLL_LOCK
DDRCLKP&N
by REFCLK3_PD#
When power down
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
VCC1V8
VCC_1V0 scaled
VDD
88E1111 (PHY)
Ther is no specific power-up nor
power-down sequence.
0.75V (DSP)
DSP
TMS320C6670
1.5V (DSP)
VCC1V0 Scaled/(CVDD)
VCC1V0 Fixed/(CVDD1)
VCC1V8/ (DVDD18)
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
VCC_1V0 Fixed
VCC1V8
DSP
TMS320C6670
1.5V/(DDR3_IO)
0.75V/(DDR3_Vref)
1.0V_scaled 1.0V_fixed
VCC1V8
A
VCC_1V0 Fixed
VCC_1V0 scaled
A
Designed for TI by ADVANTECH
2.5V/ 1.2V
VDD
CLOCK3_PLL_LOCK
XILINX_XC3S200AN
(AUX)
When power on
1.2V_AUX (VCCINT)
1.8V_AUX (VCC1V8_AUX)
3.3V_AUX (VCCAUX)
3.3V / 1.8V/ 1.2V
XILINX_XC3S200AN
Ther is no specific power-up nor
power-down sequence.
88E1111
Title
Power Sequence
2.5V
1.2V
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Thursday, May 26, 2011
Sheet
1
4
of
36
5
4
3
2
1
POWER CONSUMPTION
D
D
C
C
B
B
A
A
Designed for TI by ADVANTECH
Title
POWER CONSUMPTION
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
5
of
36
5
4
3
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1
POWER DISTRIBUTION
AMC Gold Finger
D
D
DC 12V Adapter
3.3V_MP(165uA)
VCC12(3.04A)
VCC3V3_MP_AMC
@ 165uA
0.315A
SmartReflex
Efficiency=90%
0.679A
0.49A
1.5 A
Efficiency=80%
Efficiency=90%
C
C
UCD9222 TPS54620
VCC1P5_EN
UCD9222_ENA[1:2]
VCC0P75_EN
VCC0P75
@0.25A
B
Efficiency=90%
PWM1
Vsense1
Isense1
Tsense1
TPS51200
(3.3Control)
TPS54231
TPS54620
VCC12
VCC_5V_EN
PWM2
Vsense2
Isense2
Tsense2
UCD74110
(15A)
UCD74106
(6A)
CVDD
@9.75A
VCC1V0
@ 4.52A
TPS73701DCQ
VCC2P5_EN
TPS73701DCQ
VCC1V5
@1.67A
B
TPS73701DCQ
VCC1P8_EN
TPS73701DCQ
VCC5
@1A
* DDR3
A
1.5V / 0.24A (VDD)*5 Total:1.2A
0.75V / 0.25A (Vref)
Quad Core DSP
RS232
EEPROM
3.3V
TI_TMS320C6670
VCC1V0 / 9.75A Scaled/(CVDD)
VCC1V0 / 4.52A Fixed/(CVDD1)
VCC1V8 / 0.15A (DVDD18)
1.5V / 0.47A (DDR3_IO)
0.75V/(DDR3_Vref)
XDS560V2
Mazzenine Board
5.0V / 1A
3.3V / 0.3A
3.3V
FT2232H(USB-JTAG)
3.3V / 0.21A
1.8V / 0.075A
VCC3V3_AUX
@1.2A
VCC1V8
@0.225A
MicronNAND FLASH
XILINX_XC3S200AN
1.8V / 0.02A
1.2V_AUX/ 0.125A (VCCINT)
3.3V_AUX/ 0.024A (VCCAUX)
NOR FLASH
Standyby mode 1.8V/80uA
VCC1V8_AUX
@0.3A
VCC2V5
@0.21A
VCC1V2
@0.38A
A
88E1111 (PHY)
Designed for TI by ADVANTECH
2.5V / 0.21A
1.2V / 0.25A
Title
POWER DISTRIBUTION
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
6
of
36
5
4
3
2
1
CLOCK DIAGRAM
D
D
Core Processor
PRI_REF
CDCE62002
GEN1
25.00MHz
U3
CDCE62005
DDR_CLKP/N
FPGA
U0
250.00MHz
LVDS
U1
250.00MHz
LVDS
U2
25MHZ
100.00MHz
LVDS IN2
100.00MHz HCSL
for PCIe ref.
GEN2
LVDS
CLK
TCLKA[p/n]
TCLKA
TCLKB[p/n]
TCLKB
TCLKC[p/n]
TCLKC
TCLKD[p/n]
TCLKD
MCM_CLKP/N
SRIO_SGMII_CLKP/N
PCIe_CLKP/N
HCSL
DSP
FCLK[p/n]
100.00MHz
for PCIe ref.
FCLK P/N
TI_TMS320C6670
IN1
SEL (CONTROL BY FPGA)
C
X'TAL
30.72MHZ
CDCE62005
U0
122.88MHz
LVDS
U1
122.88MHz
LVDS
GEN3
X'TAL
12MHZ
CORE_CLKP/N
PA_SS_CLKP/N
LVDS
30.72MHz
RP1CLK[p/n]
122.88MHz
U2
B
LVDS
AMC Gold Finger
X'TAL
66.667MHz
U0
U3
X'TAL
FT2232HL
25MHZ
LVDS
LVDS
RP1_CLKP/N
RP1CLK[p/n]
30.72MHz
for AIF
C
SYS_CLKP/N
B
88E1111
A
A
Designed for TI by ADVANTECH
Title
CLOCK DIAGRAM
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
7
of
36
4
3
FPGA_BLOCK
TI MMC
TI_MSP430F5435IPN
MMC_DETECT#
MMC_RESETSTAT#
MMC_POR#
MMC_WARM_RST#
Power Group
TI_TPS54620RGY x2
TI_TPS73701DRBT x4
TI_TPS54231D x1
MMC
Control
SPI_MMC_CS#
SPI_MMC_MISO
SPI_MMC_SCK
SPI_MMC_MOSI
TI_CDCE62002 #1
TI_CDCE62005 #2
TI_CDCE62005 #3
IDT557‐08
MULTIPLEXER
SPI ROM
ATMEL
AT25128B
VCC2V5_PGOOD
VCC0V75_PGOOD
VCC3V3_AUX_PGOOD
VCC5_PGOOD
VCC1V5_PGOOD
CS#
FPGA_ICS557_SEL
FPGA_ICS557_PD#
FPGA_ICS557_OE
SPI_FPGA_CS#
MISO
SPI_FPGA_MISO
CLK
SPI_FPGA_SCK
MOSI
SPI_FPGA_MOSI
UCD9222
Control
DSP
TDM CLK
SW_DSP_GPIO[0 : 15] DSP
Power
Sequences
Control
+V1.8
Boot & Device
configurations
+V1.8
PGUCD9222
UCD9222_RST
PG
RESET
UCD9222_PG1
UCD9222_ENA1
PG1
ENA1
CVDD
(UCD74110)
UCD9222_PG2
UCD9222_ENA2
PG2
ENA2
CVDD1
(UCD74106)
TI UCD9222
DSP_GPIO[0 : 15] NAND FLASH
Test Connector 80‐pin
(Female)
GPIO[0:15]
TIMI[0]
DSP_PORz
DSP_RESETFULLz
DSP_RESETz
DSP_PACLKSEL
DSP_LRRESETNMIENz
DSP_CORESEL[0..2]#
DSP_NMIz
DSP_LRESETz
DSP_DSPCLKSEL
DSP_EXTFRAMEEVENT
PORz
RESETFULLz
RESETz
PACLKSEL
LRRESETNMIENz
CORESEL[0:2]
NMIz
LRESETz
CLKSEL
EXTFRAMEEVENT
DSP_BOOTCOMPLETE
DSP_HOUT
DSP_SYSCLKOUT
BOOTCOMPLETE
HOUT
SYSCLKOUT
DSP
SPI_FPGA_CS1
SPISCS
SPI
SPI_FPGA_MISO
SPI_FPGA_SCK
SPI_FPGA_MOSI
SPIDOUT
SPICLK
SPIDIN
CLOCK
DSP
Configurations (1)
RESET &
Interrupts
Control
+V3.3
PCIe clk select
C
DSP
expansion I2C DATA
expansion I2C CLK
TI_TMS320C6670
SGMII_TXP/N[0]
SGMII_RXP/N[0]
PCIe_TXP/N[1:2]
PCIe_RXP/N[1:2]
SRIO_TXP/N[1:4]
+V3.3
SRIO_RXP/N[1:4]
FPGA
Storage
+V1.8
DSP
B
AIF_TXP/N[0:5]
AIF_RXP/N[0:5]
AMC_TDM_CLKA/B[p/n]
AMC_TDM_CLKC/D[p/n]
BSC_JTAG_TCK
BSC_JTAG_TMS
BSC_JTAG_RST#
FPGA
JTAG
Function SWITCH
FPGA_TDI
BSC_JTAG_TDO
FPGA_TDO
BSC_JTAG_TDI
+V3.3
+V3.3
WARM RESET
RESET
FULL RESET
A
D
Alert
Control
Clk
Data
TIMI0
+V3.3
+V1.8
PCIESSEN
User Switch
FPGA_PACLKSEL
DSP_DSPCLKSEL +V1.8
COLD RESET
PIN HEADER
PMBUS_ALT#
PMBUS_CTL
PMBUS_CLK
PMBUS_DAT
+V3.3
GPIO[0:3] GPIO[8:11]
GPIO[4:7] GPIO[12:15]
1
+V3.3
VCC2V5_EN
VCC0V75_EN
VCC1V8_EN1
VCC5_EN
VCC1V5_EN
SPI_CLK_CS#[1..3]
SPI_CLK_CK[1..3]
SPI_CLK_MOSI[1..3]
SPI_CLK_MISO[1..3]
REFCLK1_PD#[1..3]
PLL_LOCK[1..3]
CLOCK Group
+V3.3
+V3.3
AMC_TDM_CLKA/B[p/n]
AMC_TDM_CLKC/D[p/n]
B
PM BUS
Nyquist EVM (AMC)
XILINX_XC3S200AN‐4FTG256C
D
C
2
AMC Edge Connector
(Golden Finger)
5
PHY
PHY_INT#
Control
PHY_RST#
PHY_TDI
PHY_TDO
MARVELL 88E1111‐B2
Designed for TI by ADVANTECH
A
TRGRSTZ
60‐pin emulation
+V1.8
Title
(Female)
FPGA_BLOCK
Size
B
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
8
of
36
5
4
3
2
1
Management Map
EMU_DETz
MDC
ENET PHY MDI/O
(88E1111) JTAG
+V2.5
Level Shifter
PCA9306DCUT
SEL
MDC
MDI/O
MDC
MDI/O
+V1.8
JTAG
+V1.8
UART
DSP_RESETSTAT#
Level Shifter
SN74AVC4T245
UART
(128KB)
+V3.3
High-Speed
SWITCH
(TS3L301)
FT2232HL_RESET#
UART
+V3.3
(Jumper Option)
RS232
MAX3221EAE
SPI (CS1z)
RESETZ#
POR#
RESETFULLZ#
C
JTAG
AMC
AMC JTAG
+V3.3
edge connector
USB JTAG
+V3.3
SEL
I2C
(ST M24M01‐HRMN6TP)
EMU CONN.
+V1.8
D
JTAG
DSP
TMS320C6670
I2C
EMU_DET PIN
+V1.8
SWITCH
(TS3L301)
( 0X50h )
( 0X51h )
EEPROM
JTAG
High-Speed
JTAG
Level Shifter
D
MDC
MDI/O
USB
USB-JTAG
FT2232HL
RS232
Mini-USB
Console port
(Pin‐Header 3x1)
80-pin Header
C
MSP430 (MMC)
NU Resistors
SPI1
JTAG
PMBus
FPGA
(XILINX_XC3S200AN)
DSP_RESETSTAT#
SPI
The NU resistors on these connections to the MSP430 are for debug use only
and will be used only with the shunts removed from pins 1 and 2 of CN7
Power Sequences Control
GPIO
0‐ohm
SmartReflex
(UCD9222)
SPI1
CDCE62002
SPI2
CDCE62005
SPI3
JTAG and
Boundary Scan
CN10
JTAG
CDCE62005
TDO
TDI
B
B
Level Shifter
PCA9306DCUT
WARM_RESET_AMC#
AMC_DETECT#
FP_POR_IN_AMC#
MMC_RESETSTAT#
MMC
(MSP430)
TMS/TRSTn
TCK
PHY_TCK
EEPROM
(AT25128B)
(128Kb)
FPGA_TCK
TDI
JTAG
TDO
TDI
FPGA
XC3S200AN
IPMB-L
TDO
PHY (88E1111)
JTAG
JTAG
MMC_ENABLE_N
I2C
NU Resistors
A
A
AMC Gold Finger
Designed for TI by ADVANTECH
MMC_PS_N0
Title
MMC_PS_N1
Management Map
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
9
of
36
5
4
3
2
VCC12
AMC_JTAG_TDI
R266
10K
AMC_JTAG_TDO
R295
10K
AMC_JTAG_TMS
R6
10K
AMC_JTAG_TCK
R8
10K
AMC_JTAG_RST#
R308
10K
1
VCC3V3_AUX
AMC1
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
MMC_PS_N1
VCC3V3_MP_AMC
(11)
MMC_GA0
IN
(12)
(12)
AMC0_SGMII0_TX_DP
AMC0_SGMII0_TX_DN
IN
IN
(12)
(12)
AMC0_SGMII0_RX_DP
AMC0_SGMII0_RX_DN
MMC_GA0
Management Power
(11)
(11)
MMC_GA1
MMC_GA2
AMC0_SGMII0_TX_DP
AMC0_SGMII0_TX_DN
OUT
OUT
AMC0_SGMII0_RX_DP
AMC0_SGMII0_RX_DN
MMC_GA1
IN
MMC_GA2
IN
C
(11)
PCIe[2:1]
MMC_ENABLE_N
OUT
AMCC_P4_PCIe_TX1P
AMCC_P4_PCIe_TX1N
IN
IN
(12)
(12)
AMCC_P4_PCIe_RX1P
AMCC_P4_PCIe_RX1N
OUT
OUT
(12)
(12)
AMCC_P5_PCIe_TX2P
AMCC_P5_PCIe_TX2N
IN
IN
AMCC_P5_PCIe_RX2P
AMCC_P5_PCIe_RX2N
(11)
SMB_SCL_IPMBL
(11)
B
(16)
(16)
SMB_SDA_IPMBL
(30)
(30)
TCLKA_P
TCLKA_N
(30)
(30)
TCLKB_P
TCLKB_N
1
D9
ASD500V
100mA
AMCC_P4_PCIe_RX1P
AMCC_P4_PCIe_RX1N
0.1uF 16V P5_PCIe_TX2P
0.1uF 16V P5_PCIe_TX2N
C98
C109
OUT
OUT
OUT
AMCC_P5_PCIe_RX2P
AMCC_P5_PCIe_RX2N
SMB_SCL_IPMBL
SMB_SDA_IPMBL
BI
OUT
OUT
OUT
OUT
PCIE_REF_CLK_P
PCIE_REF_CLK_N
MMC_PS_N1
0.1uF 16V P4_PCIe_TX1P
0.1uF 16V P4_PCIe_TX1N
C85
C92
(12)
(12)
(12)
(12)
MMC_ENABLE_N
OUT
OUT
2
MMC_PS_N0
GND_1
PWR_12V_1
PS1
MP
GA0
RSRVD6
GND_2
RSRVD8
PWR_12V_2
GND_3
Tx0+
Tx0GND_4
Rx0+
Rx0GND_5
GA1
PWR_12V_3
GND_6
Tx1+
Tx1GND_7
Rx1+
Rx1GND_8
GA2
PWR_12V_4
GND_9
Tx2+
Tx2GND_10
Rx2+
Rx2GND_11
Tx3+
Tx3GND_12
Rx3+
Rx3GND_13
ENABLE
PWR_12V_5
GND_14
Tx4+
Tx4GND_15
Rx4+
Rx4GND_16
Tx5+
Tx5GND_17
Rx5+
Rx5GND_18
SCL_L
PWR_12V_6
GND_19
Tx6+
Tx6GND_20
Rx6+
Rx6GND_21
Tx7+
Tx7GND_22
Rx7+
Rx7GND_23
SDA_L
PWR_12V_7
GND_24
TCLKA+
TCLKAGND_25
TCLKB+
TCLKBGND_26
FCLKA+
FCLKAGND_27
PS0
PWR_12V_8
GND_28
GND_56
TDI
TDO
TRST
TMS
TCK
GND_55
Tx20+
Tx20GND_54
Rx20+
Rx20GND_53
Tx19+
Tx19GND_52
Rx19+
Rx19GND_51
Tx18+
Tx18GND_50
Rx18+
Rx18GND_49
Tx17+
Tx17GND_48
Rx17+
Rx17GND_47
TCLKD+
TCLKDGND_46
TCLKC+
TCLKCGND_45
Tx15+
Tx15GND_44
Rx15+
Rx15GND_43
Tx14+
Tx14GND_42
Rx14+
Rx14GND_41
Tx13+
Tx13GND_40
Rx13+
Rx13GND_39
Tx12+
Tx12GND_38
Rx12+
Rx12GND_37
Tx11+
Tx11GND_36
Rx11+
Rx11GND_35
Tx10+
Tx10GND_34
Rx10+
Rx10GND_33
Tx9+
Tx9GND_32
Rx9+
Rx9GND_31
Tx8+
Tx8GND_30
Rx8+
Rx8GND_29
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
AMC_JTAG_TDI
AMC_JTAG_TDO
AMC_JTAG_RST#
AMC_JTAG_TMS
AMC_JTAG_TCK
AMC_RP1CLKP
AMC_RP1CLKN
DSP_SCL_AMC
DSP_SDA_AMC
R321
R328
OUT
IN
OUT
OUT
OUT
AMC_JTAG_TDI
AMC_JTAG_TDO
AMC_JTAG_RST#
AMC_JTAG_TMS
AMC_JTAG_TCK
(26)
(26)
(26)
(26)
(26)
OUT
OUT
AMC_RP1CLKP
AMC_RP1CLKN
(16)
(16)
external RP1CLK
(15)
(15)
Expansion I2C
NL/0
NL/0
AMC_RP1FBP
AMC_RP1FBN
IN
BI
OUT
OUT
AMC_RP1FBP
AMC_RP1FBN
OUT
OUT
PHYSYNC
RADSYNC
AMCC_P18_AIF5_TXP
AMCC_P18_AIF5_TXN
IN
IN
AMCC_P18_AIF5_RXP
AMCC_P18_AIF5_RXN
OUT
OUT
AMCC_P17_AIF4_TXP
AMCC_P17_AIF4_TXN
IN
IN
AMCC_P17_AIF4_RXP
AMCC_P17_AIF4_RXN
OUT
OUT
(30)
(30)
IN
IN
OUT
OUT
AMCC_P13_AIF1_TXP
AMCC_P13_AIF1_TXN
IN
IN
AMCC_P13_AIF1_RXP
AMCC_P13_AIF1_RXN
OUT
OUT
AMCC_P12_AIF0_TXP
AMCC_P12_AIF0_TXN
IN
IN
AMCC_P12_AIF0_RXP
AMCC_P12_AIF0_RXN
OUT
OUT
AMCC_P11_SRIO4_TXP
AMCC_P11_SRIO4_TXN
AMCC_P11_SRIO4_RXP
AMCC_P11_SRIO4_RXN
IN
IN
OUT
OUT
AMCC_P10_SRIO3_TXP
AMCC_P10_SRIO3_TXN
AMCC_P10_SRIO3_RXP
AMCC_P10_SRIO3_RXN
IN
IN
OUT
OUT
AMCC_P9_SRIO2_TXP
AMCC_P9_SRIO2_TXN
IN
IN
AMCC_P9_SRIO2_RXP
AMCC_P9_SRIO2_RXN
OUT
OUT
AMCC_P8_SRIO1_TXP
AMCC_P8_SRIO1_TXN
IN
IN
AMCC_P8_SRIO1_RXP
AMCC_P8_SRIO1_RXN
AMCC_P17_AIF4_TXP
AMCC_P17_AIF4_TXN
(30)
(30)
OUT
OUT
(14)
(14)
(14)
(14)
(14)
(14)
(14)
(14)
AMCC_P12_AIF0_TXP
AMCC_P12_AIF0_TXN
AMCC_P12_AIF0_RXP
AMCC_P12_AIF0_RXN
(14)
(14)
(14)
(14)
AMCC_P11_SRIO4_TXP
AMCC_P11_SRIO4_TXN
(12)
(12)
AMCC_P11_SRIO4_RXP
AMCC_P11_SRIO4_RXN
(12)
(12)
AMCC_P10_SRIO3_TXP
AMCC_P10_SRIO3_TXN
(12)
(12)
AMCC_P10_SRIO3_RXP
AMCC_P10_SRIO3_RXN
AMCC_P9_SRIO2_TXP
AMCC_P9_SRIO2_TXN
C
(14)
(14)
AMCC_P13_AIF1_TXP
AMCC_P13_AIF1_TXN
AMCC_P13_AIF1_RXP
AMCC_P13_AIF1_RXN
AIF[0:5]
(14)
(14)
AMCC_P14_AIF2_TXP
AMCC_P14_AIF2_TXN
AMCC_P14_AIF2_RXP
AMCC_P14_AIF2_RXN
(14)
(14)
(14)
(14)
AMCC_P15_AIF3_TXP
AMCC_P15_AIF3_TXN
AMCC_P15_AIF3_RXP
AMCC_P15_AIF3_RXN
(14)
(14)
(14)
(14)
AMCC_P17_AIF4_RXP
AMCC_P17_AIF4_RXN
TCLKC_P
TCLKC_N
AMCC_P14_AIF2_TXP
AMCC_P14_AIF2_TXN
AMCC_P14_AIF2_RXP
AMCC_P14_AIF2_RXN
AMCC_P18_AIF5_TXP
AMCC_P18_AIF5_TXN
TCLKD_P
TCLKD_N
OUT
OUT
AIF CLK & FS
AMCC_P18_AIF5_RXP
AMCC_P18_AIF5_RXN
OUT
OUT
IN
IN
(15)
(15)
(15)
(15)
OUT
OUT
AMCC_P15_AIF3_TXP
AMCC_P15_AIF3_TXN
AMCC_P15_AIF3_RXP
AMCC_P15_AIF3_RXN
AMC_EXP_SCL
AMC_EXP_SDA
D
(12)
(12)
SRIO[1:4]
(12)
(12)
AMCC_P9_SRIO2_RXP
AMCC_P9_SRIO2_RXN
(12)
(12)
AMCC_P8_SRIO1_TXP
AMCC_P8_SRIO1_TXN
(12)
(12)
AMCC_P8_SRIO1_RXP
AMCC_P8_SRIO1_RXN
(12)
(12)
B
GF-AMC-B
DC FAN Connet for DSP
OVP: ~12.7V+0.6V = ~13.3V
Q9
AO3401
4.2A/30V
2
3
DC_IN1
10M
TRIP1
TRIP2
TRIP3
2
3
4
A
10M
1
R557
TRIP1
JACK_3H
<Characteristic>
C554
C181
0.1uF
50V
C182
1000pF
50V
D8
BZX84-C12
12.7V
1
R530
1uF
25V
100K
C510
10uF
16V
2
G
Q10
2N7002
300mA/60v
Q6
MMBT3904LT1
200mA
C552
0.1uF
50V
R525
100K
2
S
3
2
R497
100K
VCC12
C509
1uF
16V
A
D
1
1
C511
1uF
16V
R558
100K
R524
100K
R498
1K
ESD1
AMC-ESD-B
FAN1
WB_3V_2.0mm
1
2
3
VCC12
3
R556
3
NL/0
G
R526
1
3
2
S
NL/0
TP32
D
R533
1
Front panel and ESD Strip
Designed for TI by ADVANTECH
Title
AMC GF
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
10
of
36
5
4
3
2
1
Power for MSP430
VCC3V3_MP
D
RB751V40
1
200mA
VCC3V3_MP_AMC
D7
2
RB751V40
1
200mA
VCC3V3_AUX
R371
8.2K
R381
NL/10K
MMC_SBWTDIO
3
VCC3V3_MP
D6
2
C210
0.1uF
16V
D
D
Q7
2N7002
300mA/60v
G
1
MMC_ENABLE_N
IN
MMC_ENABLE_N
(10)
2
S
R382
10K
MMC_SBWTCK
MMC_SBWTDIO
MMC1
P6.3/A3
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI/SBWTDIO
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCLK
P5.3/XT2OUT
P5.2/XT2IN
DVSS4
DVCC4
P8.6/TA1.1
P8.5/TA1.0
P8.4/TA0.4
P8.3/TA0.3
P8.2/TA0.2
P8.1/TA0.1
C2
0.1uF
16V
SpyBiWire
C
MMC_XTAL1
22pF
50V
1
C235
4
3
C227
Y4
2 32.768KHz_12.5pF
<Characteristic>
22pF
50V
MMC_XTAL2
C255
0.1uF 16V
B21
120_100MHz
0.5A
VCC3V3_MP
MMC_XTAL1
MMC_XTAL2
VCC3V3_MP
(10)
(10)
(10)
MMC_GA0
MMC_GA1
MMC_GA2
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
P7.4/A12
P7.5/A13
P7.6/A14
P7.7/A15
P5.0/A8/VREF+/VeREF+
P5.1/A9/VREF-/VeREFAVCC
AVSS
P7.0/XIN
P7.1/XOUT
DVSS1
DVCC1
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
(RED LED)
VCC3V3_MP
R422
330
R467
330
1
D1
R
2
MMC_LED1
KP-1608EC
B
2
MMC_LED2
19-215SUBC/S280/TR8
1
D2
(BLUE LED)
TI_MSP430F5435IPN
P1.4/TA0.3
P1.5/TA0.4
P1.6/SMCLK
P1.7
P2.0/TA1CLK/MCLK
P2.1/TA1.0
P2.2/TA1.1
P2.3/TA1.2
P2.4/RTCCLK
DVSS3
DVCC3
P2.5
P2.6/ACLK
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
VCC3V3_MP
4
3
2
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
SBW_MMC1
W_4V_2.54mm
MMC_SBWTCK
MMC_SBWTDIO
VCC3V3_MP
C289
1000pF
50V
C
P8.0/TA0.0
P7.3/TA1.2
P7.2/TB0OUTH/SVMOUT
P5.7/UCA1RXD/UCA1SOMI
P5.6/UCA1TXD/UCA1SIMO
P5.5/UCB1CLK/UCA1STE
P5.4/UCB1SOMI/UCB1SCL
P4.7/TB0CLK/SMCLK
P4.6/TB0.6
DVCC2
DVSS2
VCORE
P4.5/TB0.5
P4.4/TB0.4
P4.3/TB0.3
P4.2/TB0.2
P4.1/TB0.1
P4.0/TB0.0
P3.7/UCB1SIMO/UCB1SDA
P3.6/UCB1STE/UCA1CLK
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
R353
R344
R339
NL/0
NL/0
NL/0
C231
0.47uF 10V
R320
NL/0
OUT
IN
IN
MMC_SPI_MISO (30)
MMC_SPI_MOSI (30)
MMC_SPI_STE (30)
VCC3V3_MP
MMC_P43
TP20
MMC_SCK
IN
MMC_SPI_SCK
(30)
The NU resistors on these connections to the MSP430 are for debug use only
and will be used only with the shunts removed from pins 1 and 2 of CN7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
B
R291
R258
MMC_GAPU
MMC_LED1
SPI I/F is for Advantech FPGA debugging.
MMC_MISO
MMC_MOSI
MMC_STE
TP7
NL/0
NL/0
IN
BI
MMC_LED2
OUT
IN
UART_FT_RX
UART_FT_TX
SMB_SCL_IPMBL
SMB_SDA_IPMBL
(10)
(10)
(15,26)
(15,26)
B
VCC3V3_MP
SMB_SCL_IPMBL
R302
33K
SMB_SDA_IPMBL
R311
33K
TP8
TP9
OUT
MMC_DETECT#
IN
IN
OUT
OUT
MMC_RESETSTAT# (30)
MMC_BOOTCOMPLETE (30)
MMC_POR_IN_AMC#
(30)
MMC_WR_AMC# (30)
(30)
VCC3V3_MP
MMC_GAPU
VCC3V3_MP
R317
3.3K
A
R301
3.3K
R299
3.3K
C218
0.1uF
16V
MMC_GA0
C240
0.1uF
16V
C290
0.1uF
16V
C199
0.1uF
16V
A
MMC_GA1
MMC_GA2
R316
NL/0
R300
NL/0
R259
NL/0
Designed for TI by ADVANTECH
Title
MMC
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
11
of
36
5
4
3
2
1
DSP1F
R376
SRIO
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
D
AMCC_P11_SRIO4_RXN
AMCC_P11_SRIO4_RXP
AMCC_P10_SRIO3_RXN
AMCC_P10_SRIO3_RXP
AMCC_P9_SRIO2_RXN
AMCC_P9_SRIO2_RXP
AMCC_P8_SRIO1_RXN
AMCC_P8_SRIO1_RXP
IN
IN
IN
IN
IN
IN
IN
IN
AMCC_P11_SRIO4_TXN
AMCC_P11_SRIO4_TXP
AMCC_P10_SRIO3_TXN
AMCC_P10_SRIO3_TXP
AMCC_P9_SRIO2_TXN
AMCC_P9_SRIO2_TXP
AMCC_P8_SRIO1_TXN
AMCC_P8_SRIO1_TXP
AMCC_P11_SRIO4_RXN
AMCC_P11_SRIO4_RXP
AMCC_P10_SRIO3_RXN
AMCC_P10_SRIO3_RXP
AMCC_P9_SRIO2_RXN
AMCC_P9_SRIO2_RXP
AMCC_P8_SRIO1_RXN
AMCC_P8_SRIO1_RXP
C38
C37
C22
C21
C35
C36
C33
C34
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
16V
16V
AE8
NL/0
AMCC_P11_SRIO4_TXN
AMCC_P11_SRIO4_TXP
AMCC_P10_SRIO3_TXN
AMCC_P10_SRIO3_TXP
AMCC_P9_SRIO2_TXN
AMCC_P9_SRIO2_TXP
AMCC_P8_SRIO1_TXN
AMCC_P8_SRIO1_TXP
AF6
AF7
AG7
AG8
AF9
AF10
AG11
AG10
AMCC_P11_SRIO4_RXN_C
AMCC_P11_SRIO4_RXP_C
AMCC_P10_SRIO3_RXN_C
AMCC_P10_SRIO3_RXP_C
AMCC_P9_SRIO2_RXN_C
AMCC_P9_SRIO2_RXP_C
AMCC_P8_SRIO1_RXN_C
AMCC_P8_SRIO1_RXP_C
AH6
AH7
AJ7
AJ8
AH10
AH9
AJ11
AJ10
RSV15
Caution!
RIOTXN3
RIOTXP3
RIOTXN2
RIOTXP2
RIOTXN1
RIOTXP1
RIOTXN0
RIOTXP0
"Place ALL SERDES DC-blocking
caps on top layer adjacent to the
DSP’s RX pins so that there are
no additional vias"
RIORXN3
RIORXP3
RIORXN2
RIORXP2
RIORXN1
RIORXP1
RIORXN0
RIORXP0
D
TI_TMS320C6670
<Characteristic>
SGMII
VCC1V8
VCC3V3_AUX
DSP1G
R357
AE5
NL/0
RSV17
MDCLK
MDIO
(27) DSP_SGMII_TXN
(27) DSP_SGMII_TXP
(10) AMC0_SGMII0_TX_DN
(10) AMC0_SGMII0_TX_DP
(27) DSP_SGMII_RXN
(27) DSP_SGMII_RXP
(10) AMC0_SGMII0_RX_DN
(10) AMC0_SGMII0_RX_DP
IN
IN
IN
IN
DSP_SGMII_RXN
DSP_SGMII_RXP
AMC0_SGMII0_RX_DN
AMC0_SGMII0_RX_DP
C24
C23
C26
C25
0.1uF
0.1uF
0.1uF
0.1uF
DSP_SGMII_TXN
DSP_SGMII_TXP
AMC0_SGMII0_TX_DN
AMC0_SGMII0_TX_DP
AG4
AG5
AF3
AF4
DSP_SGMII_RXN_C
DSP_SGMII_RXP_C
AMC0_SGMII0_RX_DN_C
AMC0_SGMII0_RX_DP_C
AJ4
AJ5
AH3
AH4
OUT
OUT
OUT
OUT
16V
16V
16V
16V
AF16
AG16
DSP_MDC
DSP_MDIO
C213
0.1uF
16V
SGMII1TXN
SGMII1TXP
SGMII0TXN
SGMII0TXP
U25
DSP_MDC
DSP_MDIO
SGMII1RXN
SGMII1RXP
SGMII0RXN
SGMII0RXP
VCC1V8
TI_TMS320C6670
<Characteristic>
C
R256
100K
R319
10K
R318
10K
1
2
3
4
GND
VREF1
SCL1
SDA1
EN
VREF2
SCL2
SDA2
8
7
6
5
C191
0.1uF
16V
DSP_MDC_1
DSP_MDIO_1
DSP_MDC_1
DSP_MDIO_1
OUT
BI
TI_PCA9306DCUT
R239
2K
R238
2K
(27)
(27)
VCC2V5
C
PCIE
DSP1P
R369
NL/0
AE14
RSV16
PCIETXN0
PCIETXP0
PCIERXN0
PCIERXP0
PCIETXN1
PCIETXP1
PCIERXN1
PCIERXP1
AG14
AG13
AMCC_P4_PCIe_TX1N
AMCC_P4_PCIe_TX1P
AJ14
AJ13
AMCC_P4_PCIe_RX1N_C
AMCC_P4_PCIe_RX1P_C
AF12
AF13
AMCC_P5_PCIe_TX2N
AMCC_P5_PCIe_TX2P
AH12
AH13
AMCC_P5_PCIe_RX2N_C
AMCC_P5_PCIe_RX2P_C
OUT
OUT
AMCC_P4_PCIe_TX1N
AMCC_P4_PCIe_TX1P
C17
C18
OUT
OUT
0.1uF 16V
0.1uF 16V
AMCC_P5_PCIe_TX2N
AMCC_P5_PCIe_TX2P
C20
C19
0.1uF 16V
0.1uF 16V
(10)
(10)
AMCC_P4_PCIe_RX1N
AMCC_P4_PCIe_RX1P
IN
IN
AMCC_P4_PCIe_RX1N
AMCC_P4_PCIe_RX1P
(10)
(10)
IN
IN
AMCC_P5_PCIe_RX2N
AMCC_P5_PCIe_RX2P
(10)
(10)
(10)
(10)
AMCC_P5_PCIe_RX2N
AMCC_P5_PCIe_RX2P
TI_TMS320C6670
<Characteristic>
B
B
“The HyperLink routes must
have a maximum of 2 vias and
no via stubs – top layer routing
recommended”
HyperLink
DSP1S
TP5
TP6
HyperLink_REFCLKOUTP
HyperLink_REFCLKOUTN
V2
V1
MCMREFCLKOUTP
MCMREFCLKOUTN
MCMTXPMDAT
MCMTXPMCLK
MCMTXFLDAT
MCMTXFLCLK
MCMTXP0
MCMTXN0
MCMTXP1
MCMTXN1
MCMTXP2
MCMTXN2
MCMTXP3
MCMTXN3
A
R418
NL/0
V4
RSV14
MCMRXPMDAT
MCMRXPMCLK
MCMRXFLDAT
MCMRXFLCLK
MCMRXP0
MCMRXN0
MCMRXP1
MCMRXN1
MCMRXP2
MCMRXN2
MCMRXP3
MCMRXN3
AA1
AA2 MCMTXPMCLK
Y2
Y1
R5
T5
P4
R4
M4
L4
N5
M5
R394
Y3
AA3
W3
V3
MCMRXFLCLK
R419
R2 HyperLink_RXP0_C
T2 HyperLink_RXN0_C
R1 HyperLink_RXP1_C
P1 HyperLink_RXN1_C
M1 HyperLink_RXP2_C
L1 HyperLink_RXN2_C
M2 HyperLink_RXP3_C
N2 HyperLink_RXN3_C
22
22
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
HyperLink_TXPMDAT
HyperLink_TXPMCLK
HyperLink_TXFLDAT
HyperLink_TXFLCLK
HyperLink_TXP0 (29)
HyperLink_TXN0 (29)
HyperLink_TXP1 (29)
HyperLink_TXN1 (29)
HyperLink_TXP2 (29)
HyperLink_TXN2 (29)
HyperLink_TXP3 (29)
HyperLink_TXN3 (29)
(29)
(29)
(29)
(29)
IN
IN
OUT
OUT
HyperLink_RXPMDAT
(29)
HyperLink_RXPMCLK
(29)
HyperLink_RXFLDAT
(29)
HyperLink_RXFLCLK
(29)
C73
C69
C79
C83
C103
C115
C96
C89
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
16V
16V
HyperLink_RXP0
HyperLink_RXN0
HyperLink_RXP1
HyperLink_RXN1
HyperLink_RXP2
HyperLink_RXN2
HyperLink_RXP3
HyperLink_RXN3
IN
IN
IN
IN
IN
IN
IN
IN
HyperLink_RXP0
HyperLink_RXN0
HyperLink_RXP1
HyperLink_RXN1
HyperLink_RXP2
HyperLink_RXN2
HyperLink_RXP3
HyperLink_RXN3
(29)
(29)
(29)
(29)
(29)
(29)
(29)
(29)
A
Designed for TI by ADVANTECH
TI_TMS320C6670
<Characteristic>
Title
DSP_SERDES_PORTS
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
12
of
36
5
4
2
1
DSP0_DDR3_ECC[0..7]
DSP0_DDR3_ECC0
DSP0_DDR3_ECC1
DSP0_DDR3_ECC2
DSP0_DDR3_ECC3
DSP0_DDR3_ECC4
DSP0_DDR3_ECC5
DSP0_DDR3_ECC6
DSP0_DDR3_ECC7
BI
(25)
3
C29
C28
B27
A27
B24
A24
B21
A21
B9
A9
A6
B6
A3
B3
C1
D1
B19
A19
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_1
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_3
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_5
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_7
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_8
DSP0_DDR3_EDQSP_8
DDRDQS0N
DDRDQS0P
DDRDQS1N
DDRDQS1P
DDRDQS2N
DDRDQS2P
DDRDQS3N
DDRDQS3P
DDRDQS4N
DDRDQS4P
DDRDQS5N
DDRDQS5P
DDRDQS6N
DDRDQS6P
DDRDQS7N
DDRDQS7P
DDRDQS8N
DDRDQS8P
(24,25)
(24,25)
(24,25)
C
OUT
OUT
OUT
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
(24)
DSP1J
(24,25)
DDRA00
DDRA01
DDRA02
DDRA03
DDRA04
DDRA05
DDRA06
DDRA07
DDRA08
DDRA09
DDRA10
DDRA11
DDRA12
DDRA13
DDRA14
DDRA15
DDRBA0
DDRBA1
DDRBA2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
A14
B14
F14
F13
A15
C15
B15
D15
F15
E15
E16
D16
E17
C16
D17
C17
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
DSP0_DDR3_EA14
DSP0_DDR3_EA15
OUT
DSP0_DDR3_EA[0..15]
DSP0_DDR3_EODT_0
OUT
(24,25)
(24,25)
DSP0_DDR3_ERAS#
DSP0_DDR3_ECAS#
OUT
OUT
(24,25)
DSP0_DDR3_ECS_0#
OUT
(24,25)
(24,25)
(24,25)
DSP0_DDR3_EWE#
DSP0_DDR3_ECKE_0
DSP0_DDR3_EMRESETN
OUT
OUT
OUT
OUT
OUT
BI
DSP0_DDR3_EDQ[56..63]
B
(24)
VCC1V5
DSP0_DDR3_EDQ[48..55]
BI
DSP0_DDR3_EDQ[32..39]
DDRDQM5
DDRDQM4
DDRD47
DDRD46
DDRD45
DDRD44
DDRD43
DDRD42
DDRD41
DDRD40
DDRD39
DDRD38
DDRD37
DDRD36
DDRD35
DDRD34
DDRD33
DDRD32
DDRDQM1
DDRDQM0
DDRD15
DDRD14
DDRD13
DDRD12
DDRD11
DDRD10
DDRD09
DDRD08
DDRD07
DDRD06
DDRD05
DDRD04
DDRD03
DDRD02
DDRD01
DDRD00
<Characteristic>
TI_TMS320C6670
C27
E29
A26
B26
C26
D26
D25
E25
E24
F24
F25
E26
B28
D27
D28
E27
D29
E28
DSP0_DDR3_EDM_1
DSP0_DDR3_EDM_0
DSP0_DDR3_EDQ15
DSP0_DDR3_EDQ14
DSP0_DDR3_EDQ13
DSP0_DDR3_EDQ12
DSP0_DDR3_EDQ11
DSP0_DDR3_EDQ10
DSP0_DDR3_EDQ9
DSP0_DDR3_EDQ8
DSP0_DDR3_EDQ7
DSP0_DDR3_EDQ6
DSP0_DDR3_EDQ5
DSP0_DDR3_EDQ4
DSP0_DDR3_EDQ3
DSP0_DDR3_EDQ2
DSP0_DDR3_EDQ1
DSP0_DDR3_EDQ0
OUT
OUT
BI
DSP0_DDR3_EDM_1
DSP0_DDR3_EDM_0
DSP0_DDR3_EDQ[8..15]
OUT
(24)
DSP0_DDR3_EDM_2
OUT
DSP0_DDR3_EDM_3
DSP0_DDR3_EDM_2
DSP0_DDR3_EDQ[0..7]
A
BI
BI
(24)
DDRCLKOUTN0
DDRCLKOUTP0
DDRRESETz
B16
A16
B12
A12
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKP_0
OUT
OUT
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKP_0
(24,25)
(24,25)
H24
R469
45.3
1%
R454
10K
DDR3 Slew‐Rate Setting (DDRSLRATE[1:0]):
0 0
1 0
0 1
1 1
U1_DDRSLRATE1
R461
NL/10K
Fastest
Fast
Slow
Slowest
DSP0_DDR3_EDQ[24..31]
(24)
DSP0_DDR3_ECKP_0
R499
39.2
1%
DSP0_DDR3_ECKN_0
R508
39.2
1%
C533
0.1uF
16V
VCC1V5
(24)
(24)
Place these resistors at the
end of the trace.
(24)
B
VCC0V75
BI
A22
A25
C22
B22
C21
D22
F21
E21
F20
D21
E22
C24
B23
A23
E23
D24
F22
F23
DSP0_DDR3_EDM_3
DDRWEz
DDRCKE0
DDRCKE1
DDRSLRATE0
DDRSLRATE1
DDRCLKOUTN1
DDRCLKOUTP1
VCC1V5
R460
10K
DSP0_DDR3_EDQ16
DSP0_DDR3_EDQ17
DSP0_DDR3_EDQ18
DSP0_DDR3_EDQ19
DSP0_DDR3_EDQ20
DSP0_DDR3_EDQ21
DSP0_DDR3_EDQ22
DSP0_DDR3_EDQ23
DSP0_DDR3_EDQ24
DSP0_DDR3_EDQ25
DSP0_DDR3_EDQ26
DSP0_DDR3_EDQ27
DSP0_DDR3_EDQ28
DSP0_DDR3_EDQ29
DSP0_DDR3_EDQ30
DSP0_DDR3_EDQ31
(24)
E11
DSP0_DDR3_EMRESETN
U1_DDRSLRATE0
DDRDQM3
DDRDQM2
DDRD31
DDRD30
DDRD29
DDRD28
DDRD27
DDRD26
DDRD25
DDRD24
DDRD23
DDRD22
DDRD21
DDRD20
DDRD19
DDRD18
DDRD17
DDRD16
(24)
A8
A10
C6
D6
E6
B7
C7
E7
D7
A7
E8
B8
C9
E9
D9
B10
D10
E10
E12
D11
E18
DSP0_DDR3_EWE#
DSP0_DDR3_ECKE_0
DDRCE0z
DDRCE1z
NL/0
NL/0
H27 U1_DDRSLRATE0
H26 U1_DDRSLRATE1
A20
B2
B5
E1
F3
F2
F1
C2
E2
D2
F4
C3
C4
E4
D4
A4
B4
A5
C5
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
DSP0_DDR3_EDM_8
DSP0_DDR3_EDM_5
DSP0_DDR3_EDM_4
DSP0_DDR3_EDQ47
DSP0_DDR3_EDQ46
DSP0_DDR3_EDQ45
DSP0_DDR3_EDQ44
DSP0_DDR3_EDQ43
DSP0_DDR3_EDQ42
DSP0_DDR3_EDQ41
DSP0_DDR3_EDQ40
DSP0_DDR3_EDQ39
DSP0_DDR3_EDQ38
DSP0_DDR3_EDQ37
DSP0_DDR3_EDQ36
DSP0_DDR3_EDQ35
DSP0_DDR3_EDQ34
DSP0_DDR3_EDQ33
DSP0_DDR3_EDQ32
C11
C12
NL/0
J28 R455
H28 R172
C
DDRDQM8
DDRDQM7
DDRDQM6
DDRD62
DDRD61
DDRD60
DDRD63
DDRD59
DDRD58
DDRD57
DDRD56
DDRD55
DDRD54
DDRD53
DDRD52
DDRD51
DDRD50
DDRD49
DDRD48
DSP0_DDR3_EDM_5
DSP0_DDR3_EDM_4
DSP0_DDR3_ECS_0#
RSV06
RSV07
DDRRASz
DDRCASz
NL/0
G27 R466
BI
(24)
(24)
DSP0_DDR3_EDQ[40..47]
C10
D12
G26 R465
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
DSP1L
(24)
DSP0_DDR3_ERAS#
DSP0_DDR3_ECAS#
PTV15
DSP0_DDR3_EDQ48
DSP0_DDR3_EDQ49
DSP0_DDR3_EDQ50
DSP0_DDR3_EDQ51
DSP0_DDR3_EDQ52
DSP0_DDR3_EDQ53
DSP0_DDR3_EDQ54
DSP0_DDR3_EDQ55
DSP0_DDR3_EDQ56
DSP0_DDR3_EDQ57
DSP0_DDR3_EDQ58
DSP0_DDR3_EDQ59
DSP0_DDR3_EDQ63
DSP0_DDR3_EDQ60
DSP0_DDR3_EDQ61
DSP0_DDR3_EDQ62
OUT
OUT
OUT
RSV21
TI_TMS320C6670
<Characteristic>
BI
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
DSP0_DDR3_EDM_8
DDRODT0
DDRODT1
RSV19
R452
NL/10K
(24)
(24)
(25)
D13
E13
DSP0_DDR3_EODT_0
(24,25)
TI_TMS320C6670
<Characteristic>
A13
B13
C13
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_1
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_3
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_5
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_7
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_8
DSP0_DDR3_EDQSP_8
E19
C20
D19
B20
C19
C18
B18
A18
DSP1K
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(25)
(25)
D
DDRCB00
DDRCB01
DDRCB02
DDRCB03
DDRCB04
DDRCB05
DDRCB06
DDRCB07
D
VCC0V75
(24)
DSP0_DDR3_EA0
R512
39.2
1%
C544
0.01uF 16V
DSP0_DDR3_EBA_0
R219
39.2
1%
C545
0.01uF 16V
DSP0_DDR3_EA1
R224
39.2
1%
C177
0.1uF 16V
DSP0_DDR3_EBA_1
R522
39.2
1%
C566
0.1uF 16V
DSP0_DDR3_EA2
R523
39.2
1%
C546
0.01uF 16V
DSP0_DDR3_EBA_2
R507
39.2
1%
C179
0.01uF 16V
DSP0_DDR3_EA3
R222
39.2
1%
C180
0.1uF 16V
DSP0_DDR3_EODT_0
R488
39.2
1%
C540
0.1uF 16V
DSP0_DDR3_EA4
R528
39.2
1%
C174
0.01uF 16V
DSP0_DDR3_EWE#
R500
39.2
1%
C527
0.01uF 16V
DSP0_DDR3_EA5
R225
39.2
1%
C188
0.1uF 16V
DSP0_DDR3_ERAS#
R506
39.2
1%
C184
0.1uF 16V
DSP0_DDR3_EA6
R531
39.2
1%
DSP0_DDR3_ECAS#
R212
39.2
1%
DSP0_DDR3_EA7
R228
39.2
1%
DSP0_DDR3_ECKE_0
R216
39.2
1%
DSP0_DDR3_EA8
R532
39.2
1%
DSP0_DDR3_ECS_0#
R215
39.2
1%
DSP0_DDR3_EA9
R559
39.2
1%
DSP0_DDR3_EA10
R511
39.2
1%
DSP0_DDR3_EA11
R226
39.2
1%
DSP0_DDR3_EMRESETN
R227
4.7K
DSP0_DDR3_EA12
R223
39.2
1%
DSP0_DDR3_EA13
R529
39.2
1%
DSP0_DDR3_EA14
R232
39.2
1%
DSP0_DDR3_EA15
R220
39.2
1%
VCC0V75
A
DSP0_DDR3_EDQ[16..23]
Designed for TI by ADVANTECH
Title
DSP_DDR3
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
13
of
36
5
4
3
2
1
JTAG & EMU
Power Supply for Daughter Board
VCC1V8
DSP_TRST#_R
C47
8.2pF
50V
R402
4.7K
DSP_TDI
R401
4.7K
DSP_TCK
R79
4.7K
C500
0.1uF
16V
(30)
DSP_TDO
R417
4.7K
DSP_TRST#
R389
NL/4.75K
1%
XDS560_IL
560V2_PWR1
1
2
3
4
5
6
7
8
IN
VCC3V3_AUX
C499
10uF
6.3V
R68
49.9
1%
C493
0.1uF
16V
R58
VCC3V3_AUX
VCC3V3_AUX
(26)
4.75K 1%
EMU1
PTH
EXT_EMU_DET0
OUT
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
EXT_EMU_DET0
PH_4x2V_2.54mm
(30)
TRGRSTZ
NL/10K
OUT
VCC1V8
IN
IN
DSP_TMS
DSP_TDI
DSP_TDO
DSP_TCK
IN
IN
OUT
IN
(26)
DSP_TRST#
IN
VCC1V8
AE29
AF29
DSP_TMS
DSP_TDI
DSP_TDO
AC26
AD28
AC27
AD29
DSP_TRST# AD26
R368
AJ25
1K
EMU00
EMU01
TMS
TDI
TDO
TCK
TRSTz
EMU02
EMU03
EMU04
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
AE28
AF28
AE26
AD25
AF25
AE25
AF27
AG29
AF26
AG28
AG27
AG25
AH28
AJ27
AH27
AJ26
AH25
DSP_EMU_02
DSP_EMU_03
DSP_EMU_04
DSP_EMU_05
DSP_EMU_06
DSP_EMU_07
DSP_EMU_08
DSP_EMU_09
DSP_EMU_10
DSP_EMU_11
DSP_EMU_12
DSP_EMU_13
DSP_EMU_14
DSP_EMU_15
DSP_EMU_16
DSP_EMU_17
DSP_EMU_18
(26)
EMU_TMS
(26)
EMU_TDI
(26)
EMU_TDO
(26)
EMU_TCK
(26)
EMU_EMU_00
OUT
OUT
IN
VCC1V8
OUT
IN
EMU_TMS
DSP_EMU_17
EMU_TDI
DSP_EMU_14
DSP_EMU_12
EMU_TDO
4.7K
TRGRSTZ
R65
R74
R84
R89
R95
R115
R118
R132
R138
R149
R155
R158
R166
10
10
10
10
10
10
100
10
10
10
10
10
10
DSP_TMS_R
DSP_EMU_17_R
DSP_TDI_R
DSP_EMU_14_R
DSP_EMU_12_R
DSP_TDO_R
DSP_TVD
DSP_EMU_09_R
DSP_EMU_07_R
DSP_EMU_05_R
EMU_TCK_R
DSP_EMU_02_R
DSP_EMU_00_R
DSP_EMU_09
DSP_EMU_07
DSP_EMU_05
EMU_TCK
DSP_EMU_02
EMU_EMU_00
D1
C1
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
DSP_EMU_18_R
DSP_TRST#_R
DSP_EMU_16_R
DSP_EMU_15_R
DSP_EMU_13_R
DSP_EMU_11_R
DSP_TCK_R
DSP_EMU_10_R
DSP_EMU_08_R
DSP_EMU_06_R
DSP_EMU_04_R
DSP_EMU_03_R
DSP_EMU_01_R
R73
R405
R87
R94
R112
R117
R450
R126
R133
R146
R152
R156
R160
DSP_EMU_18
EMU_TRST#
DSP_EMU_16
DSP_EMU_15
DSP_EMU_13
DSP_EMU_11
EMU_TCK_R
DSP_EMU_10
DSP_EMU_08
DSP_EMU_06
DSP_EMU_04
DSP_EMU_03
EMU_EMU_01
10
10
10
10
10
10
10
10
10
10
10
10
10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DSP
EMU_TCK
R292
RSV01
TI_TMS320C6670
<Characteristic>
DSP AIF
EMU_EMU_00
R168
4.75K
EMU_EMU_01
R170
4.75K
VCC1V8
EMU_TRST#
OUT
IN
EMU_TCK_R
PTH
(26)
EMU_EMU_01
(26)
DSP_TCK_R
H1
DSP_EMU_00
DSP_EMU_01
(26)
(26)
(26)
(26)
DSP_EMU_00
DSP_EMU_01
D
B1
A1
60‐pin Header
R173
DSP1O
C
4.7K
C492
10uF
16V
R125
(26)
(26)
R83
VCC5
H2
D
DSP_TMS
R291
C
BB_30x2V_S1.27mm
NAND FLASH
VCC1V8
R25
4.7K
DSP_GPIO_11
R12
4.7K
NAND_WP#
NAND1
B
(15,29,31)
(15,29,31)
(15,29,31)
(15,29,31)
(15,29,31)
(15,29,31)
(15,29,31)
(15,29,31)
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
IN
IN
IN
IN
IN
IN
IN
IN
(15,29,31)
(30)
DSP_GPIO_10
NAND_WP#
IN
IN
(15,29,31)
(15,29,31)
(15,29,31)
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_11
IN
IN
IN
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
H4
J4
K4
K5
K6
J7
K7
J8
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
DSP1M
R443
R427
NL/0
NL/0
L25
U25
RSV27
RSV26
AIFRXN5
AIFRXP5
AIFRXN4
AIFRXP4
AIFRXN3
AIFRXP3
AIFRXN2
AIFRXP2
AIFRXN1
AIFRXP1
AIFRXN0
AIFRXP0
AIFTXN5
AIFTXP5
AIFTXN4
AIFTXP4
AIFTXN3
AIFTXP3
AIFTXN2
AIFTXP2
AIFTXN1
AIFTXP1
AIFTXN0
AIFTXP0
U28
V28
T29
U29
P29
N29
R28
P28
K29
L29
L28
M28
U26
V26
U27
T27
P27
N27
R26
P26
L27
K27
L26
M26
AIF5_RXN
AIF5_RXP
AIF4_RXN
AIF4_RXP
AIF3_RXN
AIF3_RXP
AIF2_RXN
AIF2_RXP
AIF1_RXN
AIF1_RXP
AIF0_RXN
AIF0_RXP
C74
C71
C81
C76
C86
C95
C80
C84
C112
C100
C97
C91
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
16V
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
AMCC_P18_AIF5_TXN
AMCC_P18_AIF5_TXP
AMCC_P17_AIF4_TXN
AMCC_P17_AIF4_TXP
AMCC_P15_AIF3_TXN
AMCC_P15_AIF3_TXP
AMCC_P14_AIF2_TXN
AMCC_P14_AIF2_TXP
AMCC_P13_AIF1_TXN
AMCC_P13_AIF1_TXP
AMCC_P12_AIF0_TXN
AMCC_P12_AIF0_TXP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AMCC_P18_AIF5_RXN
AMCC_P18_AIF5_RXP
AMCC_P17_AIF4_RXN
AMCC_P17_AIF4_RXP
AMCC_P15_AIF3_RXN
AMCC_P15_AIF3_RXP
AMCC_P14_AIF2_RXN
AMCC_P14_AIF2_RXP
AMCC_P13_AIF1_RXN
AMCC_P13_AIF1_RXP
AMCC_P12_AIF0_RXN
AMCC_P12_AIF0_RXP
AMCC_P18_AIF5_TXN
AMCC_P18_AIF5_TXP
AMCC_P17_AIF4_TXN
AMCC_P17_AIF4_TXP
AMCC_P15_AIF3_TXN
AMCC_P15_AIF3_TXP
AMCC_P14_AIF2_TXN
AMCC_P14_AIF2_TXP
AMCC_P13_AIF1_TXN
AMCC_P13_AIF1_TXP
AMCC_P12_AIF0_TXN
AMCC_P12_AIF0_TXP
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(15,29,31)
(15,29,31)
DSP_GPIO_09
DSP_GPIO_08
IN
IN
DSP_GPIO_10
NAND_WP#
C7
C3
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_11
D4
C6
C8
DSP_GPIO_09
DSP_GPIO_08
C4
D5
A1
A2
A9
A10
B1
B9
B10
L1
L2
L9
L10
M1
M2
M9
M10
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
C5
K3
K8
TI_TMS320C6670
<Characteristic>
W
WP
R
E
RB
AL
CL
DU1
DU2
DU3
DU4
DU5
DU6
DU7
DU8
DU9
DU10
DU11
DU12
DU13
DU14
DU15
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
VDD1
VDD2
D3
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F7
F8
G3
G4
G5
G6
G7
G8
H3
H5
H6
H7
J3
J5
B
H8
J6
VCC1V8
C6
0.1uF
16V
C257
0.1uF
16V
C11
10uF
6.3V
VSS1
VSS2
VSS3
NUMONYX_NAND512R3A2DZA6E
<Characteristic>
(NUMONYX_NAND512R3A2DZA6E, 1410021161)
A
A
Designed for TI by ADVANTECH
Title
DSP_JTAG_EMU_AIF
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
14
of
36
5
4
3
2
I2C, TIMER0,1, SPI, UART
16M SPI NOR Flash
1
1M‐bit I2C EEPROM
0x50h/0x51h
VCC1V8
VCC1V8
C485
0.1uF
16V
VCC1V8
R309
NL/0
SPI1
R424
R445
D
VCC1V8
4.7K
4.7K
DSP1R
DSP_SSPCK
(29,30)
(29,30)
(29,30)
DSP_SSPCS1
OUT
NOR_SSPMOSI
NOR_SSPMISO
OUT
IN
R362
AG21
10
R31
10
AH21
AJ22
NOR_SSPMOSI R32
NOR_SSPMISO
10
AJ21
AH22
NOR_SSPCS
DSP_SSPCS1
SPICLK
SPISCS0
SPISCS1
TIMI0
TIMI1
TIMO0
TIMO1
SPIDOUT UARTTXD
SPIDIN
UARTRXD
UARTRTS
UARTCTS
AJ23
AG23
AH23
AF23
AJ24
AF24
AG24
AH24
R336
R352
10
10
R34
10
R33
R342
10
10
IN
IN
OUT
OUT
DSP_TIMI0 (29,31)
DSP_TIMI1 (29,31)
DSP_TIMO0 (29)
DSP_TIMO1 (29)
2
1
R464
4.7K NOR_HD#
NOR_SSPCS 7
NOR_SSPCK 16
15
NOR_SSPMOSI
8
NOR_SSPMISO R446
10
NOR_WP# 9
R406
4.7K
10
(30)
NOR_WP#
IN
VCC
HOLD/DQ3
S
SCK
DQ0
DQ1
W/Vpp/DQ2
VSS
14
13
12
11
6
5
4
3
DU/NC8
DU/NC7
DU/NC6
DU/NC5
DU/NC4
DU/NC3
DU/NC2
DU/NC1
R297
NL/0
R264
NL/0
C229
0.1uF
16V
EEPROM1
1
2
3
4
R312
NL/0
R296
0
R263
0
DU
E1
E2
VSS
VCC
WC
SCL
SDA
8
7
6
5
EEPROM_WP
DSP_SCL
DSP_SDA
R236
R235
4.7K
4.7K
D
ST_M24M01-HRMN6TP
R237
4.7K
IN
EEPROM_WP
(30)
NUMONYX_N25Q128A21BSF40F
VCC1V8
DSP_UARTTXD_V1P8
DSP_UARTRXD_V1P8
DSP_UARTRTS_V1P8
DSP_UARTCTS_V1P8
VCC1V8
VCC3V3_AUX
TI_TMS320C6670
NOR_SSPMISO
R30
4.7K
C230
0.1uF
16V
VCC1V8
C228
0.1uF
16V
U2
DSP_UARTRTS_V1P8
DSP_UARTTXD_V1P8
DSP_UARTCTS_V1P8
DSP_UARTRXD_V1P8
GPIO
16
15
14
13
12
11
10
9
C
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
R240
R241
R242
R243
R244
R245
R246
R247
R248
R249
R250
R251
R252
R253
R254
R255
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSP_GPIO_R00
DSP_GPIO_R01
DSP_GPIO_R02
DSP_GPIO_R03
DSP_GPIO_R04
DSP_GPIO_R05
DSP_GPIO_R06
DSP_GPIO_R07
DSP_GPIO_R08
DSP_GPIO_R09
DSP_GPIO_R10
DSP_GPIO_R11
DSP_GPIO_R12
DSP_GPIO_R13
DSP_GPIO_R14
DSP_GPIO_R15
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
AJ20
AG18
AD19
AE19
AF18
AE18
AG20
AH19
AJ19
AE21
AG19
AD20
AE20
AF21
AH20
AD21
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
RSV23
RSV22
AD16
R373
NL/0
AE16
R358
NL/0
R359
R372
DSP_SCL
DSP_SDA
R334
C
1
2
3
4
GND
VREF1
SCL1
SDA1
10K
EN
VREF2
SCL2
SDA2
8
7
6
5
C208
0.1uF
16V
OUT
BI
R307
2K
R306
2K
VCC3V3_AUX
10K
R194
4.7K
C145
1uF
6.3V
R195
4.7K
0.1uF 16V
0.1uF 16V
C159
0.1uF 16V
0.1uF 16V
RS232_RX
1
2
3
4
5
6
7
8
EN
C1+
V+
C1C2+
C2VRIN
FORCEOFF
VCC
GND
DOUT
FORCEON
DIN
INVALID
ROUT
16
15
14
13
12
11
10
9
R338
4.7K
RS232_TX
(10)
(10)
IN
IN
PHYSYNC
RADSYNC
1
AH15
AC16
AD15
0.1uF 16V RP1FBN AA29
0.1uF 16V RP1FBP Y29
AB27
AA27
PHYSYNC
RADSYNC
R179
R470
NL/0
NL/0
H23
J23
R335
R350
NL/0
NL/0
AD22
AC22
CORESEL0
CORESEL1
CORESEL2
AC21
DSP_BOOTCOMPLETE
OUT
DSP_BOOTCOMPLETE
700mA
3
VCC1V8
(30)
U29
EXTFRAMEEVENT
RP1FBN
RP1FBP
NMIz
HOUT
PHYSYNC
RADSYNC
RSV10
RSV11
RSV12
RSV13
RSV03
PACLKSEL
RSV08
RSV09
SDA
SCL
AE17 EXTFRAMEEVENT R361
R360
AC25
DSP_NMIZ
AC18
DSP_HOUT
AC23
AD23
R343
PACLKSEL_C R380
J24
J25
AD17
AC17
R463
R449
NL/0
10K
OUT
IN
OUT
NL/0
0
IN
FPGA_EXTFRAMEEVENT
DSP_NMIZ
DSP_HOUT
(30)
DSP_SSPCK
NOR_SSPCK
R61
33
R366
33
(30)
(30)
DSP_PACLKSEL
(29)
OUT
PH_SSPCK
1
2
3
4
5
6
7
1OE
1A
1Y
2OE
2A
2Y
GND
VCC
4OE
4A
4Y
3OE
3A
3Y
14
13
12
11
10
9
8
2
DSP_CORESEL0
DSP_CORESEL1
DSP_CORESEL2
IN
IN
B
UART_MAX_RX
TI_MAX3221ECPWR
BOOTCOMPLETE
AMC_RP1FBN
AMC_RP1FBP
R181
4.7K
UART_MAX_TX
B15
2200pF
(10)
(10)
DSP_UARTRXD
UART_MAX_TX
C170
C164
DSP1N
C248
C241
C136
0.1uF
16V
U16
Core Control
IN
IN
IN
(10)
(10)
VCC3V3_AUX
C150
DSP_CORESEL0
DSP_CORESEL1
DSP_CORESEL2
AMC_EXP_SCL
AMC_EXP_SDA
TI_PCA9306DCUT
VCC1V8
B
(30)
(30)
(30)
(29)
(29)
(29)
(29)
U28
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
DSP_UARTRTS
DSP_UARTTXD
DSP_UARTCTS
DSP_UARTRXD
R310
100K
NL/0
NL/0
R333
R274
R275
R276
R277
R278
R279
R280
R281
R282
R283
R284
R285
R286
R261
R262
OUT
OUT
IN
IN
VCC3V3_AUX
C242
0.1uF
16V
AF17
AG17
VCC1V8
DSP_GPIO_R01
DSP_GPIO_R02
DSP_GPIO_R03
DSP_GPIO_R04
DSP_GPIO_R05
DSP_GPIO_R06
DSP_GPIO_R07
DSP_GPIO_R08
DSP_GPIO_R09
DSP_GPIO_R10
DSP_GPIO_R11
DSP_GPIO_R12
DSP_GPIO_R13
DSP_GPIO_R14
DSP_GPIO_R15
DSP_UARTRTS
DSP_UARTTXD
DSP_UARTCTS
DSP_UARTRXD
SCL/SDA
RSV25
RSV24
R273
1
2
3
4
5
6
7
8
VCC1V8
TI_TMS320C6670
DSP_GPIO_R00
VCCA
1DIR
2DIR
1A1
1A2
2A1
2A2
GND1
TI_SN74AVC4T245PWR
<Characteristic>
DSP1I
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(14,29,31)
(29,31)
(29,31)
VCCB
1OE
2OE
1B1
1B2
2B1
2B2
GND2
DSP_SSPCK
33
R11
COM_SEL1(2-4)
MINIJUMPER_2_2.54mm
OUT
FPGA_SSPCK
(30)
TI_SN74ALVC125PWR
(30)
COM_SEL1(1-3)
MINIJUMPER_2_2.54mm
0
NL/0
DSP_SDA
DSP_SCL
BI
OUT
DSP_SDA
DSP_SCL
(29)
(29)
JP‐UART(1‐3) & (2‐4) : UART over USB Connector (Default)
JP‐UART(3‐5) & (4‐6) : UART over 3‐Pin Header J5
COM1
1
2
3
TI_TMS320C6670
RS232_RX
RS232_TX
(11,26)
A
W_3V_2.54mm
UART_FT_TX
OUT
1
3
5
UART_FT_TX
DSP_UARTTXD
UART_MAX_TX
10K
NL/10K
RP1FBN
RP1FBP
R388
R395
10K
10K
PHYSYNC
RADSYNC
R404
R416
UART_FT_RX
DSP_UARTRXD
UART_MAX_RX
IN
UART_FT_RX
(11,26)
A
PH_3x2V_2.54mm
VCC1V8
R403
R415
COM_SEL1
2
4
6
NL/10K
10K
Designed for TI by ADVANTECH
Title
DSP_MISC
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
15
of
36
5
4
3
2
1
All blocking capacitors should be placed near DSP to keep
connecting routes short and minimize vias
DSP CLOCK / RESET
DSP1H
D
250.00MHz Input
(22)
(22)
SRIOSGMIICLKN
SRIOSGMIICLKP
IN
IN
122.88MHz Input
(23)
(23)
CORECLKN
CORECLKP
IN
IN
66.67MHz Input
(21)
(21)
DDRCLKN
DDRCLKP
IN
IN
250.00MHz Input
(22)
(22)
MCMCLKN
MCMCLKP
IN
IN
122.88MHz Input
(23)
(23)
PASSCLKN
PASSCLKP
IN
IN
30.72MHz Input
(23)
(23)
RP1CLKP
RP1CLKN
IN
IN
122.88MHz Input
(23)
(23)
SYSCLKP
SYSCLKN
IN
IN
(30)
DSP_SYSCLKOUT
SRIOSGMIICLKN
SRIOSGMIICLKP
C31
C32
0.1uF 16V
0.1uF 16V
SRIOSGMIICLKN_C
SRIOSGMIICLKP_C
AH16
AJ16
CORECLKN
CORECLKP
C57
C63
0.1uF 16V
0.1uF 16V
CORECLKN_C
CORECLKP_C
AB28
AB29
DDRCLKN
DDRCLKP
C108
C118
0.1uF 16V
0.1uF 16V
DDRCLKN_C
DDRCLKP_C
H29
G29
MCMCLKN
MCMCLKP
C62
C56
0.1uF 16V
0.1uF 16V
MCMCLKN_C
MCMCLKP_C
W2
W1
PASSCLKN
PASSCLKP
C15
C16
0.1uF 16V
0.1uF 16V
PASSCLKN_C
PASSCLKP_C
AH18
AJ18
RP1CLKP
RP1CLKN
C72
C68
0.1uF 16V
0.1uF 16V
RP1CLKP_C
RP1CLKN_C
Y28
AA28
SYSCLKP
SYSCLKN
C53
C48
0.1uF 16V
0.1uF 16V
SYSCLKP_C
SYSCLKN_C
AC29
AC28
DSP_PCIECLKN
DSP_PCIECLKP
100.00MHz Input
C269
C270
ALTCORECLKN
ALTCORECLKP
RSV20
AA24
AB25
CLKSEL
AB26
R421
NL/0
R397
0
R423
NL/0
IN
DSP_DSPCLKSEL
(30,31)
DDRCLKN
DDRCLKP
MCMCLKN
MCMCLKP
RSV05
RSV04
PASSCLKN
PASSCLKP
PORz
RESETz
RP1CLKP
RP1CLKN
lresetz
SYSCLKP
SYSCLKN
resetfullz
RESETSTATz
SYSCLKOUT
LRESETNMIENz
AJ17
AH17
PCIECLKN_C
PCIECLKP_C
0.1uF 16V
0.1uF 16V
RSV18
CORECLKSEL
AA26
DSP_SYSCLKOUT
OUT
TP12
SRIOSGMIICLKN
SRIOSGMIICLKP
W27
Y27
R414
R413
AC19
DSP_PORZ
NL/0
NL/0
D
AC24
DSP_RESETZ
AE22
DSP_LRESETZ
AE23
DSP_RESETFULLZ
AD18
DSP_RESETSTAT#
AC20
DSP_LRESETNMIENZ
IN
DSP_PORZ
IN
DSP_RESETZ
IN
DSP_LRESETZ
IN
DSP_RESETFULLZ
(30)
DSP_RESETSTAT#
(30)
OUT
IN
(30)
(30)
(30)
DSP_LRESETNMIENZ
(30)
PCIECLKN
PCIECLKP
TI_TMS320C6670
(10)
(10)
AMC_RP1CLKP
AMC_RP1CLKN
C379
C366
IN
IN
NL/0.1uF 16V
NL/0.1uF 16V
RP1CLKP_C
RP1CLKN_C
DSP_PORZ
R379
4.7K
DSP_RESETFULLZ
R398
4.7K
DSP_RESETZ
R420
4.7K
VCC3V3_AUX_ICS557
2200pF
700mA
R313
NL/1K
C200
0.01uF
16V
C193
0.01uF
16V
C5
0.01uF
16V
C192
10uF
6.3V
PCIECLKP_ICS557
C189
10uF
6.3V
R265
(10)
R303
PCIE_REF_CLK_N
(LVDS)
(22)
(22)
100
2
3
R294
R260
5
6
PCIECLKP_ICS557
PCIECLKN_ICS557
0
0
(30)
FPGA_ICS557_SEL
IN
(30)
FPGA_ICS557_PD#
IN
(30)
R257
NL/1K
NL/100
IN
PCIECLKP IN
PCIECLKN IN
PCIECLKN_ICS557
VDD_1
VDD_2
VDD_3
IN
16
4
7
FPGA_ICS557_OE
IN
R233
10K
FPGA_ICS557_PD#
R2
10K
FPGA_ICS557_OE
R5
NL/10K
FPGA_ICS557_SEL
R315
10K
VCC3V3_AUX
IN1
IN1
CLK
CLK
15
14
PCI-E_P
PCI-E_N
R305
R293
33
33
DSP_PCIECLKP
DSP_PCIECLKN
1%
1%
DSP_PCIECLKP
C
R298
R304
R292
IN2
IN2
150
150
1%
1%
Layout From Clock Device
REF_CLK output
SEL
PD
IREF
OE
9
R1
475
100
DSP_PCIECLKN
1%
GND_1
GND_2
GND_3
3
2
1
PCIE_REF_CLK_P
(HCSL)
B11
C
U1
(10)
VCC3V3_AUX_ICS557
8
12
13
VCC3V3_AUX
1
10
11
VCC3V3_AUX_ICS557
IDT_ICS557GI-08LFT
Default: IN2/CDCE62005
VCC1V8
Smart Reflex
IN
B
C435
0.1uF
16V
U30
TI_PCA9306DCUT
1
2
3
4
DSP1Q
VCL
VD
VCNTL0
VCNTL1
VCNTL2
VCNTL3
Y4
W4
DSP_VCL
DSP_VD
AB4
AB3
AA4
AB1
VCC1V8
GND
VREF1
SCL1
SDA1
EN
VREF2
SCL2
SDA2
PCA9306_EN
(30)
R410
100K
8
7
6
5
B
C390
0.1uF
16V
DSP_VCL_1
DSP_VD_1
OUT
BI
R429
10K
R412
10K
R438
10K
R411
10K
DSP_VCL_1
DSP_VD_1
(30)
(30)
VCC3V3_AUX
TI_TMS320C6670
VCC1V8
R164
10K
VCC1V8
R163
10K
R162
10K
VCC3V3_AUX
C122
0.1uF
16V
R161
10K
VID_OE#
R448
33
DSP_VIDA
DSP_VIDB
DSP_VIDC
DSP_VIDS
C61
0.1uF
16V
U7
TI_SN74AVC4T245PWR
16
15
14
13
12
11
10
9
VCCB
1OE
2OE
1B1
1B2
2B1
2B2
GND2
VCCA
1DIR
2DIR
1A1
1A2
2A1
2A2
GND1
VCC3V3_AUX
1
2
3
4
5
6
7
8
R103
10K
UCD9222_VIDA
UCD9222_VIDB
UCD9222_VIDC
UCD9222_VIDS
R102
10K
R101
10K
R100
10K
OUT
OUT
OUT
OUT
UCD9222_VIDA
UCD9222_VIDB
UCD9222_VIDC
UCD9222_VIDS
(33)
(33)
(33)
(33)
A
A
(31)
VID_OE#
IN
VID_OE#
R459
10K
Designed for TI by ADVANTECH
VCC3V3_AUX
Title
DSP_CLOCK_Smart Reflex
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
16
of
36
5
4
3
2
1
1.8V
VCC1V8
Place near to DSP
D
D
VCC1V8
DSP1D
AB5
AC2
AC4
V5
Y5
DVDD18_3
DVDD18_4
DVDD18_5
DVDD18_6
DVDD18_7
DVDD18_8
DVDD18_9
DVDD18_10
DVDD18_11
DVDD18_12
DVDD18_13
AVDDA1
AVDDA2
AVDDA3
W24
VCC1V8_AVDD1
J26
VCC1V8_AVDD2
AB15
3
C44
0.1uF
16V
VCC1V8_AVDD3
C45
0.01uF
16V
C222
10uF
6.3V
C223
10uF
6.3V
C221
4.7uF
6.3V
1
B28
2200pF
700mA
C362
560pF
50V
C239
100uF
6.3V
2
AB17
AB19
AB21
AE24
AE27
AF19
AF22
AH26
AH29
AJ28
Y25
C258
100uF
6.3V
VCC1V8
DVDD18_1
DVDD18_2
C256
4.7uF
6.3V
VCC1V8
Place near to DSP pins
3
DVDD18_14
DVDD18_15
DVDD18_16
DVDD18_16
DVDD18_18
RSV0A
RSV0B
K24
K23
NL/0
NL/0
R447
R453
C437
0.1uF
16V
C433
0.01uF
16V
C226
0.1uF
16V
1
C225
0.1uF
16V
C214
0.1uF
16V
C247
0.01uF
16V
C309
0.01uF
16V
C363
0.01uF
16V
C344
1000pF
50V
C381
1000pF
50V
C331
560pF
50V
C326
560pF
50V
C302
560pF
50V
C350
1000pF
50V
B37
2200pF
700mA
C444
560pF
50V
2
G28
H25
TI_TMS320C6670
<Characteristic>
VCC1V8
3
C267
0.01uF
16V
B20
2200pF
700mA
C359
560pF
50V
C354
560pF
50V
2
C268
0.1uF
16V
C
Place near to DSP pins
1
C334
560pF
50V
C224
560pF
50V
C321
560pF
50V
C455
560pF
50V
C
1.5V
Place near to DSP
VCC1V5
VCC1V5
VCC1V5
VCC1V5
VCC1V5
VCC1V5
Place near to DSP pins
Place near to DSP pins
DSP1C
VDDR3_SGMII
AE6
VDDR4_SRIO
AE11
C522
0.01uF
16V
C520
0.01uF
16V
C563
0.01uF
16V
C557
0.01uF
16V
C153
0.01uF
16V
C558
560pF
50V
C506
560pF
50V
C454
560pF
50V
C461
560pF
50V
C460
560pF
50V
C459
560pF
50V
C458
560pF
50V
C421
560pF
50V
C446
0.1uF
16V
C447
0.01uF
16V
1
VCC1V5
C448
1000pF
50V
3
VDDR2_PCIE
B40
2200pF
700mA
C330
560pF
50V
C266
0.1uF
16V
C265
0.01uF
16V
1
VCC1V5
B19
2200pF
700mA
C254
1000pF
50V
VDDR3
VDDR4
VDDR6
3
VDDR3_SGMII
VDDR5
VREFSSTL
E14
C339
560pF
50V
R218
1K
1%
DSP_VREFSSTL
C261
0.1uF
16V
C260
0.01uF
16V
DSP_VREFSSTL
3
1
C393
560pF
50V
R217
1K
1%
C318
0.1uF
16V
C337
0.01uF
16V
C325
1000pF
50V
3
VDDR4_SRIO
C340
560pF
50V
VCC1V5
B30
2200pF
700mA
(24,25)
A
VCC1V5
B17
2200pF
700mA
C262
1000pF
50V
VDDR5_AIF1
OUT
1
DSP_VREFSSTL
C483
0.1uF
16V
VCC1V5
C172
0.1uF
16V
C152
0.01uF
16V
3
VDDR1_MCM
TI_TMS320C6670
<Characteristic>
C173
0.1uF
16V
C508
0.1uF
16V
VDDR2
N25
VDDR6_AIF2
C480
0.1uF
16V
B
VDDR1
R25
VDDR5_AIF1
C556
0.1uF
16V
C263
0.1uF
16V
C264
0.01uF
16V
1
C253
1000pF
50V
3
VDDR6_AIF2
C389
560pF
50V
C415
0.1uF
16V
C402
0.01uF
16V
VCC1V5
B18
2200pF
700mA
2
AE15
C543
0.1uF
16V
1
VCC1V5
B33
2200pF
700mA
C419
1000pF
50V
A
2
K6
VDDR2_PCIE
C516
4.7uF
6.3V
2
VDDR1_MCM
C491
4.7uF
6.3V
C505
560pF
50V
2
E3
F5
F7
F9
F11
F17
F19
F27
G10
G12
G14
G16
G18
G2
G20
G22
G24
G4
G8
2
B
DVDD15_1 DVDD15_17
DVDD15_2 DVDD15_18
DVDD15_3 DVDD15_19
DVDD15_4 DVDD15_20
DVDD15_5 DVDD15_21
DVDD15_6 DVDD15_22
DVDD15_7 DVDD15_23
DVDD15_8 DVDD15_24
DVDD15_9 DVDD15_25
DVDD15_10DVDD15_26
DVDD15_11DVDD15_27
DVDD15_12DVDD15_28
DVDD15_29
DVDD15_13DVDD15_30
DVDD15_14DVDD15_31
DVDD15_15
DVDD15_16
2
A11
A17
A2
A28
B1
B29
C14
C25
D20
D23
D5
D8
Designed for TI by ADVANTECH
Title
DSP_POWERA
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
17
of
36
5
4
0.6V - 1.1V (CVDD) (Smart Reflex)
3
1
CVDD
Place near to DSP
C119
100uF
6.3V
Fix_1.0V(VCC1P0)
2
C423
100uF
6.3V
C120
100uF
6.3V
C450
100uF
6.3V
C414
47uF
6.3V
C468
47uF
6.3V
C469
47uF
6.3V
C471
10uF
6.3V
C470
10uF
6.3V
D
D
CVDD
Place near to DSP pins
C368
0.1uF
16V
C360
0.1uF
16V
C474
0.1uF
16V
C486
0.1uF
16V
C382
0.1uF
16V
C427
0.1uF
16V
CVDD
Place near to DSP pins
C406
0.01uF
16V
C462
0.01uF
16V
C113
0.01uF
16V
C396
0.01uF
16V
C394
0.01uF
16V
C451
0.01uF
16V
C383
0.01uF
16V
C464
0.01uF
16V
C479
560pF
50V
C478
560pF
50V
C452
560pF
50V
C395
560pF
50V
C408
560pF
50V
C349
560pF
50V
C273
0.1uF
16V
C281
0.01uF
16V
C347
560pF
50V
C355
560pF
50V
CVDD
R12
R14
R16
R18
R20
R22
R8
T11
T13
T15
T17
T19
T21
T9
U10
U12
U14
U16
U18
U20
U22
U8
V11
V13
V15
V17
V19
V21
V23
V9
W10
W18
W20
W22
W8
Y19
Y21
Y23
Y9
AA22
CVDD
Place near to DSP pins
C
C357
560pF
50V
C463
560pF
50V
C126
560pF
50V
C398
560pF
50V
C449
560pF
50V
C407
560pF
50V
C475
560pF
50V
C473
560pF
50V
C453
560pF
50V
C476
560pF
50V
C472
560pF
50V
C358
560pF
50V
C477
560pF
50V
C370
560pF
50V
C125
560pF
50V
Place near to DSP pins
3
VDDT2
C364
0.1uF
16V
C335
0.01uF
16V
C346
560pF
50V
1
VCC1V0
B25
2200pF
700mA
C295
4.7uF
6.3V
2
CVDD_42
CVDD_43
CVDD_44
CVDD_45
CVDD_46
CVDD_47
CVDD_48
CVDD_49
CVDD_50
CVDD_51
CVDD_52
CVDD_53
CVDD_54
CVDD_55
CVDD_56
CVDD_57
CVDD_58
CVDD_59
CVDD_60
CVDD_61
CVDD_62
CVDD_63
CVDD_64
CVDD_65
CVDD_66
CVDD_67
CVDD_68
CVDD_69
CVDD_70
CVDD_71
CVDD_72
CVDD_73
CVDD_74
CVDD_75
CVDD_76
CVDD_77
CVDD_78
CVDD_79
CVDD_80
CVDD_81
B
VDDT3
3
VDDT1
C417
0.1uF
16V
C376
0.01uF
16V
C403
560pF
50V
1
B36
2200pF
700mA
C388
560pF
50V
2
VDDT1
C369
0.01uF
16V
3
VDDT3
C386
560pF
50V
C401
0.1uF
16V
C405
0.01uF
16V
C375
1000pF
50V
1
VCC1V0
C392
4.7uF
6.3V
VCC1V0
B35
2200pF
700mA
2
B
C114
0.01uF
16V
VDDT3_5
VDDT3_6
VDDT3_7
VDDT3_8
VDDT3_9
VDDT3_10
VDDT3_11
VDDT3_12
VDDT3_1
VDDT3_2
VDDT3_3
VDDT3_4
VDDT1_1
VDDT1_2
VDDT1_3
VDDT1_4
VDDT1_5
VDDT1_6
VDDT1_7
VDDT1_8
TI_TMS320C6670
<Characteristic>
M7
N6
P7
R6
T7
V7
W6
Y7
C
CVDD_1
CVDD_2
CVDD_3
CVDD_4
CVDD_5
CVDD_6
CVDD_7
CVDD_8
CVDD_9
CVDD_10
CVDD_11
CVDD_12
CVDD_13
CVDD_14
CVDD_15
CVDD_16
CVDD_17
CVDD_18
CVDD_19
CVDD_20
CVDD_21
CVDD_22
CVDD_23
CVDD_24
CVDD_25
CVDD_26
CVDD_27
CVDD_28
CVDD_29
CVDD_30
CVDD_31
CVDD_32
CVDD_33
CVDD_34
CVDD_35
CVDD_36
CVDD_37
CVDD_38
CVDD_39
CVDD_40
CVDD_41
K25
L24
M23
M25
N24
P23
P25
R24
T23
T25
U24
V25
DSP1A
AA10
AA12
AA14
AA16
AA18
AA20
AA8
AB23
H11
H13
H15
H17
H19
H21
J12
J18
K11
K19
L12
L18
M11
M13
M15
M17
M19
N10
N12
N14
N16
N18
N20
N22
N8
P11
P13
P15
P17
P19
P21
P9
R10
VDDT2_1
VDDT2_2
VDDT2_3
VDDT2_4
VDDT2_5
VDDT2_6
VDDT2_7
VDDT2_8
VDDT2_9
VDDT2_10
VDDT2_11
VDDT2_12
VDDT2_13
CVDD
AC10
AC12
AC14
AC6
AC8
AD11
AD13
AD5
AD7
AD9
AE10
AE12
AE4
VDDT2
A
A
Designed for TI by ADVANTECH
Title
DSP_POWERB
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
18
of
36
5
4
3
2
1
1.0V Serdes
VCC1V0
VCC1V0
DSP1B
D
D
VCC1V0
CVDD1_17
CVDD1_18
CVDD1_19
CVDD1_20
CVDD1_21
CVDD1_22
J14
J16
K13
K15
K17
L14
L16
J20
J22
K21
L20
L22
M21
AD1
AD3
AE2
AF1
AG2
AH1
AJ2
VCC1V0
CVDD1_1
CVDD1_2
CVDD1_3
CVDD1_4
CVDD1_5
CVDD1_6
CVDD1_7 TI_TMS320C6670
CVDD1_8 <Characteristic>
CVDD1_9
CVDD1_10
CVDD1_11
CVDD1_12
CVDD1_13
CVDD1_14
CVDD1_15
CVDD1_16
W12
W14
W16
Y11
Y13
Y15
Y17
CVDD1_23
CVDD1_24
CVDD1_25
CVDD1_26
CVDD1_27
CVDD1_28
CVDD1_29
CVDD1_30
CVDD1_31
CVDD1_32
CVDD1_33
CVDD1_34
CVDD1_35
CVDD1_36
G6
H1
H3
H5
H7
H9
J10
J2
J4
J6
J8
K7
K9
L10
L8
M9
CVDD1_37
CVDD1_38
CVDD1_39
CVDD1_40
CVDD1_41
CVDD1_42
CVDD1_43
C
C
VCC1V0
C353
100uF
6.3V
C352
100uF
6.3V
C40
4.7uF
6.3V
VCC1V0
Place near to DSP pins
C378
0.01uF
16V
C371
0.01uF
16V
C384
0.01uF
16V
C442
0.01uF
16V
C441
0.01uF
16V
C440
0.01uF
16V
B
B
VCC1V0
Place near to DSP pins
C422
0.1uF
16V
C432
0.1uF
16V
C50
0.1uF
16V
C436
0.1uF
16V
VCC1V0
Place near to DSP pins
C439
560pF
50V
C428
560pF
50V
C377
560pF
50V
C418
560pF
50V
C424
560pF
50V
C431
560pF
50V
C434
560pF
50V
C443
560pF
50V
C426
560pF
50V
C367
560pF
50V
A
A
Designed for TI by ADVANTECH
Title
DSP_POWERC
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
19
of
36
5
4
3
2
DSP1T
DSP1E
J9
K1
K10
K12
K14
K16
K18
K2
K20
K22
K26
K28
K3
K4
K5
K8
L11
L13
L15
L17
L19
L2
L21
L23
L3
L5
L6
L7
L9
M10
M12
M14
M16
M18
M20
M22
M24
M27
M29
M3
M6
M8
N1
N11
N13
N15
N17
N19
N21
N23
N26
N28
N3
N4
N7
N9
P10
P12
P14
P16
P18
P2
P20
P22
P24
P3
P5
P6
P8
R11
R13
R15
R17
D
C
B
1
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
R19
R21
R23
AA25
AA5
AA6
AA7
AA9
AB10
AB11
AB12
AB13
AB14
AB16
AB18
AB2
AB20
AB22
AB24
AB6
AB7
AB8
AB9
AC1
AC11
AC13
AC15
AC3
AC5
AC7
AC9
AD10
AD12
AD14
AD2
AD24
AD27
AD4
AD6
AD8
AE1
AE13
AE3
AE7
AE9
AF11
AF14
AF15
V24
V27
V29
V6
V8
W11
W13
W15
W17
W19
W21
W23
W25
W26
W28
W29
W5
W7
W9
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
Y26
Y6
Y8
A1
A29
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AF2
AF20
AF5
AF8
AG1
AG12
AG15
AG22
AG26
AG3
AG6
AG9
AH11
AH14
AH2
AH5
AH8
AJ1
AJ12
AJ15
AJ29
AJ3
AJ6
AJ9
B11
B17
B25
C23
C8
D14
D18
D3
E20
E5
F10
F12
F16
F18
F26
F28
F29
F6
F8
G1
G11
G13
G15
G17
G19
G21
G23
G25
G3
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
G5
G7
G9
H10
H12
H14
H16
H18
H2
H20
H22
H4
H6
H8
J1
J11
J13
J15
J17
J19
J21
J27
J29
J3
J5
J7
R27
R29
R3
R7
R9
T1
T10
T12
T14
T16
T18
T20
T22
T24
T26
T28
T3
T4
T6
T8
U1
U11
U13
U15
U17
U19
U2
U21
U23
U3
U4
U5
U6
U7
U9
V10
V12
V14
V16
V18
V20
V22
D
C
B
TI_TMS320C6670
<Characteristic>
TI_TMS320C6670
<Characteristic>
Designed for TI by ADVANTECH
A
A
Title
DSP_GND
Size
B
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
20
of
36
5
4
3
2
1
CLOCK GEN1 ( DDR3)
D
D
VCC_VCO1
VCC3V3_AUX
VCCPLLD1
C
C
C165
0.1uF
16V
VCCPLLA1
VCC3V3_AUX
29
30
2
R208
10K
REFCLK1_PD#
(31)
REFCLK1_PD#
(31) CLOCK1_SSPCS1
(31) CLOCK1_SSPCK
(31) CLOCK1_SSPSI
(31) CLOCK1_SSPSO
REFCLK1_PD#
IN
IN
IN
IN
OUT
C167
C138
C132
C131
CLOCK1_SSPCS1
CLOCK1_SSPCK
CLOCK1_SSPSI
CLOCK1_SSPSO
10uF
10uF
10uF
10uF
6.3V
6.3V
6.3V
6.3V
6
18
17
8
7
5
27
20
23
19
C157
0.1uF
16V
C149
0.1uF
16V
C496
0.1uF
16V
C495
1uF
6.3V
AUX_IN
PD
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MISO
REG_CAP1
REG_CAP2
REG_CAP3
REG_CAP4
TESTSYNC
31
28
4
22
9
12
13
16
3
1
24
REF+
REF-
U0P
U0N
U1P
U1N
PLL_LOCK
GND_PLLDIV
EPAD
Thermal_VIA1
Thermal_VIA2
Thermal_VIA3
Thermal_VIA4
Thermal_VIA5
Thermal_VIA6
Thermal_VIA7
Thermal_VIA8
Thermal_VIA9
11
10
DDRCLKP
DDRCLKN
VCC3V3_AUX
DDRCLKP
DDRCLKN
OUT
OUT
(16)
(16)
1
15
14
32
3
B44
2200pF
0.7A
66.67MHz Output
2
0.1uF 16V
0.1uF 16V
VCC_IN
VCC_PLLA
VCC_PLLD
VCC_PLLDIV
VCC_OUT0_1
VCC_OUT0_2
VCC_OUT1_1
VCC_OUT1_2
C148
C151
IN
IN
EXT_LFP
EXT_LFN
CLOCK1_PLL_LOCK
OUT
CLOCK1_PLL_LOCK
VCC_VCO1
(31)
21
33
VCC3V3_AUX
34
35
36
37
38
39
40
41
42
1
3
B43
2200pF
0.7A
2
REFCK_P
REFCK_N
VBB
25
26
(22)
(22)
C158
0.1uF
16V
1uF 6.3V
CLK1
VCC_AUX
VCC_VCO
C166
C144
0.1uF
16V
VCCPLLA1
C490
0.1uF
16V
C489
1uF
6.3V
B
B
TI_CDCE62002RHBT
VCC3V3_AUX
1
3
2
B10
2200pF
0.7A
VCCPLLD1
C186
0.1uF
16V
C183
1uF
6.3V
A
A
Designed for TI by ADVANTECH
Title
CLOCK GEN1
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
21
of
36
5
4
3
2
1
CLOCK GEN2
D
D
VCCPLLA2C
VCCPLLA2B
VCC3V3_AUX
VCCPLLA2A
VCC3V3_AUX
C197
0.1uF
16V
VCC_VCO2A
IN
IN
IN
OUT
R327
R325
1uF
1uF
6.3V
6.3V
4
38
C201
0.1uF
16V
C233
0.1uF
16V
C234
1uF
6.3V
C236
0.1uF
16V
C10
1uF
6.3V
C313
0.1uF
16V
C314
1uF
6.3V
C190
0.1uF
16V
C215
0.1uF
16V
C204
0.1uF
16V
C217
0.1uF
16V
C211
0.1uF
16V
C30
0.1uF
16V
C29
1uF
6.3V
C13
0.1uF
16V
C14
1uF
6.3V
C202
0.1uF
16V
C
11
18
21
26
29
32
34
35
5
39
42
U3P
U3N
TI_CDCE62005RGZT
U4P
U4N
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MISO
PCIECLKP
PCIECLKN
19
20
MCMCLKP
MCMCLKN
16
17
SRIOSGMIICLKP
SRIOSGMIICLKN
9
10
REFCK_P
REFCK_N
AUXOUT
AUXIN
REG_CAP1
REG_CAP2
PLL_LOCK
PCIECLKP
PCIECLKN
(16)
(16)
OUT
OUT
MCMCLKP
MCMCLKN
(16)
(16)
OUT
OUT
SRIOSGMIICLKP
SRIOSGMIICLKN
OUT
OUT
REFCK_P
REFCK_N
C280
NL/47pF
50V
100.00MHz Output
13
43
37
VCC3V3_AUX
3
B16
2200pF
0.7A
VCC_VCO2A
VCC3V3_AUX
1
(21)
(21)
Y5
OUT
VCCPLLA2C
25MHz Output
1
3
B23
2200pF
0.7A
25MHz_20pF
CLOCK2_PLL_LOCK
3
B4
2200pF
0.7A
250.00MHz Output
VCC3V3_AUX
REFCLK2_XTALIN
1
250.00MHz Output
(16)
(16)
6
7
TP33
TEST_MODE
TESTOUTA
OUT
OUT
2
27
28
2
VCC_OUT2
VCC_OUT3
VCC_OUT4
VCC_OUT5
VCC_OUT6
VCC_OUT7
VCC_VCO1
VCC_VCO2
VCC1_PLL1
VCC1_PLL2
VCC1_PLL3
47
1
8
U2P
U2N
36
B
VCC_OUT1
EXT_LFP
EXT_LFN
GND_VCO
C315
C12
33
30
10K
1K
C198
0.1uF
16V
VCC_VCO2B
VCC3V3_AUX
1
3
VCCPLLA2B
B3
2200pF
0.7A
2
VCC3V3_AUX
25
24
23
22
U1P
U1N
REF_SEL
Power_Down
SYNC
C205
0.1uF
16V
2
(31) CLOCK2_SSPCS1
(31) CLOCK2_SSPCK
(31) CLOCK2_SSPSI
(31) CLOCK2_SSPSO
31
12
14
10K
C216
0.1uF
16V
(31)
VCC3V3_AUX
1
3
B29
2200pF
0.7A
VCCPLLA2A
B
2
R326
NL/10K
VCC3V3_AUX
(31) REFCLK2_PD#
IN
R49
U0P
U0N
PRIREF+
PRIREF-
EPAD
Thermal_VIA1
Thermal_VIA2
Thermal_VIA3
Thermal_VIA4
Thermal_VIA5
Thermal_VIA6
Thermal_VIA7
Thermal_VIA8
Thermal_VIA9
Thermal_VIA10
Thermal_VIA11
Thermal_VIA12
Thermal_VIA13
Thermal_VIA14
Thermal_VIA15
Thermal_VIA16
Thermal_VIA17
Thermal_VIA18
Thermal_VIA19
Thermal_VIA20
Thermal_VIA21
Thermal_VIA22
Thermal_VIA23
Thermal_VIA24
Thermal_VIA25
40
41
SECREF+
SECREF-
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
3
2
45
46
VCC_IN_PRI
VCC_IN_SEC
48
VBB
CLK2
44
15
1uF
6.3V
VCC_AUXIN
VCC_AUXOUT
C41
C
VCC3V3_AUX
VCC_VCO2B
A
A
Designed for TI by ADVANTECH
Title
CLOCK GEN2
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
22
of
36
5
4
3
2
1
CLOCK GEN3
D
D
VCCPLLA3C
VCCPLLA3B
VCC3V3_AUX
VCC3V3_AUX
VCCPLLA3A
VCC3V3_AUX
VCC_VCO3B
C301
0.1uF
16V
VCC_VCO3A
10K
31
12
14
25
24
23
22
IN
IN
IN
OUT
R15
R13
33
30
10K
1K
1uF
1uF
6.3V
6.3V
4
38
U4P
U4N
C286
0.1uF
16V
C252
0.1uF
16V
C251
0.1uF
16V
C250
0.1uF
16V
PASSCLKP
PASSCLKN
16
17
RP1CLKP
RP1CLKN
9
10
SYSCLKP
SYSCLKN
AUXOUT
AUXIN
REG_CAP1
REG_CAP2
PLL_LOCK
CORECLKP
CORECLKN
(16)
(16)
OUT
OUT
PASSCLKP
PASSCLKN
OUT
OUT
RP1CLKP
RP1CLKN
(16)
(16)
30.72MHz Output
OUT
OUT
SYSCLKP
SYSCLKN
(16)
(16)
122.88MHz Output
(16)
(16)
122.88MHz Output
13
43
37
C3
1
3
B2
2200pF
0.7A
VCC3V3_AUX
NL/47pF
50V
Y1
REFCLK3_XTALIN
VCC3V3_AUX
122.88MHz Output
6
7
TP34
TEST_MODE
TESTOUTA
OUT
OUT
VCC_VCO3A
C8
0.1uF
16V
C9
1uF
6.3V
C7
0.1uF
16V
C232
1uF
6.3V
C195
0.1uF
16V
C194
1uF
6.3V
VCC3V3_AUX
1
3
1
1
3
B1
2200pF
0.7A
30.72MHz_20pF
3
VCCPLLA3C
B13
2200pF
0.7A
C206
0.1uF
16V
C207
1uF
6.3V
C212
0.1uF
16V
C219
1uF
6.3V
2
CORECLKP
CORECLKN
19
20
2
47
1
C300
0.1uF
16V
11
18
21
26
29
32
34
35
5
39
42
VCC_OUT2
VCC_OUT3
VCC_OUT4
VCC_OUT5
VCC_OUT6
VCC_OUT7
VCC_VCO1
VCC_VCO2
VCC1_PLL1
VCC1_PLL2
VCC1_PLL3
U3P
U3N
TI_CDCE62005RGZT
SPI_LE
SPI_CLK
SPI_MOSI
SPI_MISO
36
B
8
U2P
U2N
GND_VCO
C196
C4
EXT_LFP
EXT_LFN
REF_SEL
Power_Down
SYNC
C279
0.1uF
16V
VCC_VCO3B
VCC3V3_AUX
1
3
VCCPLLA3B
B14
2200pF
0.7A
2
VCC3V3_AUX
NL/10K
R234
C299
0.1uF
16V
2
(31) CLOCK3_SSPCS1
(31) CLOCK3_SSPCK
(31) CLOCK3_SSPSI
(31) CLOCK3_SSPSO
R14
C278
0.1uF
16V
OUT
CLOCK3_PLL_LOCK
(31)
VCC3V3_AUX
1
3
B12
2200pF
0.7A
VCCPLLA3A
B
2
IN
U1P
U1N
27
28
4
VCC3V3_AUX
REFCLK3_PD#
C259
0.1uF
16V
2
(31)
U0P
U0N
PRIREF+
PRIREF-
EPAD
Thermal_VIA1
Thermal_VIA2
Thermal_VIA3
Thermal_VIA4
Thermal_VIA5
Thermal_VIA6
Thermal_VIA7
Thermal_VIA8
Thermal_VIA9
Thermal_VIA10
Thermal_VIA11
Thermal_VIA12
Thermal_VIA13
Thermal_VIA14
Thermal_VIA15
Thermal_VIA16
Thermal_VIA17
Thermal_VIA18
Thermal_VIA19
Thermal_VIA20
Thermal_VIA21
Thermal_VIA22
Thermal_VIA23
Thermal_VIA24
Thermal_VIA25
40
41
SECREF+
SECREF-
C288
0.1uF
16V
C
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
3
2
45
46
VCC_OUT1
VBB
CLK3
VCC_IN_PRI
VCC_IN_SEC
48
C
44
15
1uF
6.3V
VCC_AUXIN
VCC_AUXOUT
C1
A
A
Designed for TI by ADVANTECH
Title
CLOCK GEN3
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
23
of
36
5
4
3
2
1
VCC1V5
(13,24,25)
DSP0_DDR3_EA[0..15]
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
D
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
(13,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_1
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_0
DSP0_DDR3_EDM_1
IN
IN
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)
DSP0_DDR3_EODT_0
IN
(13,24,25)
DSP0_DDR3_EMRESETN
IN
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
DSP0_DDR3_EA[0..15]
M2
N8
M3
L3
K3
J3
L2
DSP0_DDR3_EDQSP_0
DSP0_DDR3_EDQSN_0
DSP0_DDR3_EDQSP_1
DSP0_DDR3_EDQSN_1
F3
G3
C7
B7
DSP0_DDR3_EDM_0
DSP0_DDR3_EDM_1
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
240 1% L8
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA13
DSP0_DDR3_EA14
C
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
R503
(13,24,25)
VCC1V5
U18
IN
J1
J9
L1
L9
M7
T3
T7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
(13,24,25)
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
C521
0.1uF
16V
C534
C514
0.1uF
16V
C161
0.1uF
16V
C523
0.1uF
16V
U21
IN
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
C551
22uF
6.3V
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
0.1uF 16V
Trace need 20 mil.
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C531
0.1uF
16V
DSP0_DDR3_EA[0..15]
DSP_VREFSSTL
IN
BI
DSP0_DDR3_EDQ0
DSP0_DDR3_EDQ1
DSP0_DDR3_EDQ2
DSP0_DDR3_EDQ3
DSP0_DDR3_EDQ4
DSP0_DDR3_EDQ5
DSP0_DDR3_EDQ6
DSP0_DDR3_EDQ7
DSP0_DDR3_EDQ8
DSP0_DDR3_EDQ9
DSP0_DDR3_EDQ10
DSP0_DDR3_EDQ11
DSP0_DDR3_EDQ12
DSP0_DDR3_EDQ13
DSP0_DDR3_EDQ14
DSP0_DDR3_EDQ15
BI
DSP_VREFSSTL
DSP0_DDR3_EDQ[0..7]
(13)
DSP0_DDR3_EDQ[8..15]
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
(17,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
(13,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_5
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_4
DSP0_DDR3_EDM_5
IN
IN
(13)
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)
DSP0_DDR3_EODT_0
IN
(13,24,25)
DSP0_DDR3_EMRESETN
IN
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_4
DSP0_DDR3_EDQSN_4
DSP0_DDR3_EDQSP_5
DSP0_DDR3_EDQSN_5
F3
G3
C7
B7
DSP0_DDR3_EDM_4
DSP0_DDR3_EDM_5
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
R510
(13,24,25)
DSP0_DDR3_EA[0..15]
M2
N8
M3
240 1% L8
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA13
DSP0_DDR3_EA14
J1
J9
L1
L9
M7
T3
T7
* Data bits can be swapped within
the byte lane to ease routing.
* Address/Command/Control/Clock
routing must be Fly‐By in byte order
0, 1, 2, 3 ECC, 4, 5, 6, 7.
SAMSUNG_K4B1G1646G-BCH9
<Characteristic>
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C532
0.1uF
16V
C526
0.1uF
16V
C525
0.1uF
16V
C553
0.1uF
16V
C524
0.1uF
16V
D
C541
0.1uF 16V
Trace need 20 mil.
DSP_VREFSSTL
DSP0_DDR3_EDQ32
DSP0_DDR3_EDQ33
DSP0_DDR3_EDQ34
DSP0_DDR3_EDQ35
DSP0_DDR3_EDQ36
DSP0_DDR3_EDQ37
DSP0_DDR3_EDQ38
DSP0_DDR3_EDQ39
DSP0_DDR3_EDQ40
DSP0_DDR3_EDQ41
DSP0_DDR3_EDQ42
DSP0_DDR3_EDQ43
DSP0_DDR3_EDQ44
DSP0_DDR3_EDQ45
DSP0_DDR3_EDQ46
DSP0_DDR3_EDQ47
IN
DSP_VREFSSTL
(17,24,25)
BI
DSP0_DDR3_EDQ[32..39]
(13)
BI
DSP0_DDR3_EDQ[40..47]
(13)
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
C
SAMSUNG_K4B1G1646G-BCH9
<Characteristic>
VCC1V5
(13,24,25)
DSP0_DDR3_EA[0..15]
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
B
(13,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_3
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_2
DSP0_DDR3_EDM_3
IN
IN
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)
DSP0_DDR3_EODT_0
IN
(13,24,25)
DSP0_DDR3_EMRESETN
IN
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
DSP0_DDR3_EA[0..15]
M2
N8
M3
L3
K3
J3
L2
DSP0_DDR3_EDQSP_2
DSP0_DDR3_EDQSN_2
DSP0_DDR3_EDQSP_3
DSP0_DDR3_EDQSN_3
F3
G3
C7
B7
DSP0_DDR3_EDM_2
DSP0_DDR3_EDM_3
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
240 1%
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA13
DSP0_DDR3_EA14
A
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
R505
(13,24,25)
VCC1V5
U19
IN
T2
L8
J1
J9
L1
L9
M7
T3
T7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
(13,24,25)
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
C542
0.1uF
16V
C537
C517
0.1uF
16V
C550
0.1uF
16V
C529
0.1uF
16V
DSP0_DDR3_EA[0..15]
U22
IN
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
C555
22uF
6.3V
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
0.1uF 16V
(13,24,25)
(13,24,25)
(13,24,25)
Trace need 20 mil.
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C549
0.1uF
16V
DSP_VREFSSTL
DSP0_DDR3_EDQ16
DSP0_DDR3_EDQ17
DSP0_DDR3_EDQ18
DSP0_DDR3_EDQ19
DSP0_DDR3_EDQ20
DSP0_DDR3_EDQ21
DSP0_DDR3_EDQ22
DSP0_DDR3_EDQ23
DSP0_DDR3_EDQ24
DSP0_DDR3_EDQ25
DSP0_DDR3_EDQ26
DSP0_DDR3_EDQ27
DSP0_DDR3_EDQ28
DSP0_DDR3_EDQ29
DSP0_DDR3_EDQ30
DSP0_DDR3_EDQ31
BI
BI
DSP0_DDR3_EDQ[16..23]
DSP0_DDR3_EDQ[24..31]
(13,24,25)
(13,24,25)
(13,24,25)
(13,24,25)
(13)
(13)
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
(13)
(13)
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_7
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
IN
IN
(13,24,25)
(13,24,25)
(13,24,25)
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24,25)
DSP0_DDR3_EODT_0
IN
(13,24,25)
DSP0_DDR3_EMRESETN
IN
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_6
DSP0_DDR3_EDQSN_6
DSP0_DDR3_EDQSP_7
DSP0_DDR3_EDQSN_7
F3
G3
C7
B7
DSP0_DDR3_EDM_6
DSP0_DDR3_EDM_7
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN
T2
R501
(13,24,25)
DSP0_DDR3_EA[0..15]
M2
N8
M3
240 1% L8
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA13
DSP0_DDR3_EA14
J1
J9
L1
L9
M7
T3
T7
SAMSUNG_K4B1G1646G-BCH9
<Characteristic>
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
E3
F7
F2
F8
H3
H8
G2
H7
D7
C3
C8
C2
A7
A2
B8
A3
C562
0.1uF
16V
C519
0.1uF
16V
C547
22uF
6.3V
DSP_VREFSSTL
DSP0_DDR3_EDQ48
DSP0_DDR3_EDQ49
DSP0_DDR3_EDQ50
DSP0_DDR3_EDQ51
DSP0_DDR3_EDQ52
DSP0_DDR3_EDQ53
DSP0_DDR3_EDQ54
DSP0_DDR3_EDQ55
DSP0_DDR3_EDQ56
DSP0_DDR3_EDQ57
DSP0_DDR3_EDQ58
DSP0_DDR3_EDQ59
DSP0_DDR3_EDQ60
DSP0_DDR3_EDQ61
DSP0_DDR3_EDQ62
DSP0_DDR3_EDQ63
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
BI
DSP0_DDR3_EDQ[48..55]
(13)
BI
DSP0_DDR3_EDQ[56..63]
(13)
A
Designed for TI by ADVANTECH
Title
DDR3
Date:
2
C561
0.1uF
16V
Trace need 20 mil.
C
3
C564
0.1uF
16V
0.1uF 16V
SAMSUNG_K4B1G1646G-BCH9
<Characteristic>
4
C160
0.1uF
16V
B
C548
Size
5
C560
22uF
6.3V
Document Number
Rev
A102-1
DSPM-8302E
Tuesday, May 24, 2011
Sheet
1
24
of
36
5
4
3
2
1
D
D
CO-LAYOUT
(13,24,25)
U23
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
DSP0_DDR3_EA13
C
K3
L7
L3
K2
L8
L2
M8
M2
N8
M3
H7
M7
K7
N3
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
J2
K8
J3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
H3
G3
F3
H2
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
C3
D3
DSP0_DDR3_EDM_8
ECC_NU
B7
A7
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
F7
G7
G9
DSP0_DDR3_EODT_0
G1
DSP0_DDR3_EMRESETN
N2
ECC_ZQ
H8
DSP0_DDR3_EA15
DSP0_DDR3_EA14
A3
F1
F9
H1
H9
J7
N7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
BA0
BA1
BA2
WE
CAS
RAS
CS
DQS
DQS
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VREFCA
VREFDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
DSP0_DDR3_EA[0..15]
VCC1V5
IN
U20
VCC1V5
J8
E1
DSP_VREFSSTL
B3
C7
C2
C8
E3
E8
D2
E7
DSP0_DDR3_ECC0
DSP0_DDR3_ECC1
DSP0_DDR3_ECC2
DSP0_DDR3_ECC3
DSP0_DDR3_ECC4
DSP0_DDR3_ECC5
DSP0_DDR3_ECC6
DSP0_DDR3_ECC7
(13,24)
(13,24)
(13,24)
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
IN
IN
IN
(13,24)
(13,24)
(13,24)
(13,24)
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
IN
IN
IN
IN
(13)
(13)
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
(13)
DSP0_DDR3_EDM_8
IN
IN
VCC1V5
DM/TDQS
NU/TDOS
CK
CK
CKE
ODT
RESET
ZQ
NC0
NC1
NC2
NC3
NC4
NC5
NC6
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
(13,24)
(13,24)
(13,24)
IN
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
IN
IN
IN
(13,24)
DSP0_DDR3_EODT_0
IN
(13,24)
DSP0_DDR3_EMRESETN
IN
DSP0_DDR3_EA[0..15]
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
DSP0_DDR3_EBA_0
DSP0_DDR3_EBA_1
DSP0_DDR3_EBA_2
M2
N8
M3
DSP0_DDR3_EWE#
DSP0_DDR3_ECAS#
DSP0_DDR3_ERAS#
DSP0_DDR3_ECS_0#
L3
K3
J3
L2
DSP0_DDR3_EDQSP_8
DSP0_DDR3_EDQSN_8
R484
4.7K
R477
4.7K
F3
G3
C7
B7
DSP0_DDR3_EDM_8
R486
4.7K
E7
D3
DSP0_DDR3_ECKP_0
DSP0_DDR3_ECKN_0
DSP0_DDR3_ECKE_0
J7
K7
K9
DSP0_DDR3_EODT_0
K1
DSP0_DDR3_EMRESETN T2
R504
(13,24,25)
DSP0_DDR3_EA0
DSP0_DDR3_EA1
DSP0_DDR3_EA2
DSP0_DDR3_EA3
DSP0_DDR3_EA4
DSP0_DDR3_EA5
DSP0_DDR3_EA6
DSP0_DDR3_EA7
DSP0_DDR3_EA8
DSP0_DDR3_EA9
DSP0_DDR3_EA10
DSP0_DDR3_EA11
DSP0_DDR3_EA12
240 1%
ECC_ZQ
IN
DSP0_DDR3_EA15
DSP0_DDR3_EA13
DSP0_DDR3_EA14
L8
J1
J9
L1
L9
M7
T3
T7
SAMSUNG_K4B1G0846E-HCH9
<Characteristic>
B
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
BA0
BA1
BA2
WE
CAS
RAS
CS
DQSL
DQSL
DQSU
DQSU
DML
DMU
CK
CK
CKE
ODT
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
RESET
ZQ
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
VSSQ_6
VSSQ_7
VSSQ_8
VSSQ_9
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
M8
H1
C162
0.1uF
16V
C538
C528
0.1uF
16V
C515
0.1uF
16V
C163
0.1uF
16V
C539
0.1uF
16V
C559
22uF
6.3V
0.1uF
16V
Trace need 10 mil.
DSP_VREFSSTL
IN
DSP_VREFSSTL
(17,24)
C
E3
DSP0_DDR3_ECC0
F7
DSP0_DDR3_ECC1
F2
DSP0_DDR3_ECC2
F8
DSP0_DDR3_ECC3
H3
DSP0_DDR3_ECC4
H8
DSP0_DDR3_ECC5
G2
DSP0_DDR3_ECC6
H7
DSP0_DDR3_ECC7
D7 ECC_NU R485
4.7K
C3
R487
4.7K
C8
R482
4.7K
C2
R483
4.7K
A7
R478
4.7K
A2
R480
4.7K
B8
R481
4.7K
A3
R479
4.7K
BI
DSP0_DDR3_ECC[0..7]
(13)
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
B
SAMSUNG_K4B1G1646G-BCH9
<Characteristic>
There are two combinations of DDR3
3.a. 512MB: 1410021410 (1Gb, X16)_DDR3‐1333
A
A
Designed for TI by ADVANTECH
Title
DDR3_ECC
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
25
of
36
5
4
3
2
1
B42
0.5A
120_100MHz
VPLL
VCC3V3_AUX
C481
0.01uF
16V
D
VCC1V8_AUX
C482
0.1uF
16V
C129
0.1uF
16V
B41
0.5A
120_100MHz
VCC3V3_AUX
C420
0.1uF
16V
C128
0.1uF
16V
Mini-AB
DATA-
NPH_1
NPH_2
90 OHM DIFF. IMPEDANCE CONTROL
3
4
GND_1
R458
5
GND_2
D4
PGB1010603
D5
PGB1010603
VCC5_VBUS
R187
R180
USB_DM
7
USB_DP
8
12.1K 1%
4.7K
6
FT2232HL_RESET# 14
62
VCC3V3_AUX
VREGOUT
DM
DP
ACBUS0
ACBUS1
ACBUS2
ACBUS3
ACBUS4
ACBUS5
ACBUS6
ACBUS7
REF
RESET
GND_USB
61
EECS
EECLK
BCBUS0
BCBUS1
BCBUS2
BCBUS3
BCBUS4
BCBUS5
BCBUS6
BCBUS7
EEDATA
C
C99
0.1uF
16V
R140
4.7K
U6
8
7
6
5
VCC
NC
ORG
GND
CS
SK
DI
DO
1
2
3
4
C107
33pF 50V
C123
33pF 50V
2
OSCI
Y3
12MHz_20pF
R93
3
2.2K
13
R92
ATMEL_AT93C46DN-SH-T
10K
BDBUS0
BDBUS1
BDBUS2
BDBUS3
BDBUS4
BDBUS5
BDBUS6
BDBUS7
OSCO
TEST
VCC3V3_AUX
B
B9
0.5A
120_100MHz
(26)
(10) AMC_JTAG_TCK IN
(10) AMC_JTAG_TDI IN
(10) AMC_JTAG_TDO IN
(10) AMC_JTAG_TMS IN
(10) AMC_JTAG_RST# OUT
VCC3V3_AUX
24
AMC_JTAG_TCK 48
47
AMC_JTAG_TDI
AMC_JTAG_TDO 42
AMC_JTAG_TMS 41
AMC_JTAG_RST# 35
R535
4.75K 1% 34
R534
4.75K 1% 29
28
3.3V signal
GND_USB
FT_TDK
FT_TDI
FT_TDO
FT_TMS
FT_TRST#
FT_EMU0
FT_EMU1
3V3_TCK
3V3_TDI
3V3_TDO
3V3_TMS
3V3_TRST#
3V3_EMU_00
3V3_EMU_01
R188
VCC3V3_AUX
1K
45
44
39
38
32
31
26
25
R201
4.7K
R206
4.7K
3.3V signal
46
43
40
37
33
30
2
19
R211
OE
A1
A2
A3
A4
A5
A6
A7
A8
10
1
3
4
5
6
7
8
9
4.7K
VCC1V8
1V8_TCK
1V8_TDI
1V8_TDO
1V8_TMS
1V8_TRST#
1V8_EMU_00
1V8_EMU_01
TI_TXS0108EPWR
U17B
TI_SN74LVC00APWR
11
13
4
48
52
53
54
55
57
58
59
6
R209
22
FT_EMU0
8
R210
22
FT_EMU1
5
9
10
C
U17C
TI_SN74LVC00APWR
38
39
40
41
43
44
45
46
UART_FT_RX
UART_FT_TX
OUT
IN
R174
UART_FT_RX (11,15)
UART_FT_TX (11,15)
4.7K
VCC3V3_AUX
60
36
TP10
TP11
C156
0.1uF
16V
U17A
TI_SN74LVC00APWR
1
3
R203
FTDI_FT2232HL
4.7K
2
U31
3.3V control
NC
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
A0
A1
A2
A3
A4
A5
A6
A7
GND17
GND16
GND15
GND14
GND13
GND12
B1
B2
B3
B4
B5
B6
B7
B8
R207
4.7K
U17D
TI_SN74LVC00APWR
12
SEL
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
20
18
17
16
15
14
13
12
VCCA
FT_TDK
FT_TDI
FT_TDO
FT_TMS
FT_TRST#
VCC3V3_AUX
26
27
28
29
30
32
33
34
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
AGND
1
5
11
15
25
35
47
51
10
FT2232HL_RESET#
22
22
22
22
22
U32
3.3V control
FOR EMI
R196
R199
R200
R202
R198
14
PWREN
SUSPEND
FT_TDK_R
FT_TDI_R
FT_TDO_R
FT_TMS_R
FT_TRST#_R
GPIOL1
GPIOL2
GPIOL3
VCCB
20
31
42
56
ADBUS0
ADBUS1
ADBUS2
ADBUS3
ADBUS4
ADBUS5
ADBUS6
ADBUS7
10K
63
(26)
U15
16
17
18
19
21
22
23
24
GND
2
DATA+
VCC1V8_AUX
C169
0.1uF
16V
7
6
7
8
9
PTH_1
PTH_2
PTH_3
PTH_4
49
VREGIN
0.1uF 16V
10
11
MINIUSB_5H
50
R186
0
C133
D
11
VCORE_1
VCORE_2
VCORE_3
VPHY
VPLL
GND_USB
1
C430
0.1uF
16V
C141
0.1uF
16V
VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_4
4
9
U12
+5V
C467
0.1uF
16V
VPLL
VPHY
VCC5_VBUS
USB1
C503
0.1uF
16V
VCC3V3_AUX
C457
0.1uF
16V
12
37
64
C456
0.01uF
16V
(26)
C502
0.1uF
16V
VPHY
VCC3V3_AUX
VDD1
VDD2
VDD3
VDD4
VDD5
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
14
2
4
8
10
15
17
21
23
Level shift
(14)
3V3_TCK
3V3_TDI
3V3_TDO
3V3_TMS
3V3_TRST#
3V3_EMU_00
3V3_EMU_01
24
EXT_EMU_DET0 IN
(14) EMU_TCK
(14) EMU_TDI
(14) EMU_TDO
(14) EMU_TMS
(14) EMU_TRST#
(14) EMU_EMU_00
(14) EMU_EMU_01
48
47
42
41
35
34
29
28
IN
IN
OUT
IN
IN
BI
BI
1.8V signal
1
6
12
19
36
VCC3V3_AUX
C518
0.1uF
16V
3
5
7
9
11
13
16
18
20
22
27
C565
0.1uF
16V
C530
10uF
6.3V
1V8_TCK
1V8_TDI
1V8_TDO
1V8_TMS
1V8_TRST#
1V8_EMU_00
1V8_EMU_01
45
44
39
38
32
31
26
25
1.8V signal
46
43
40
37
33
30
TI_TS3L301DGG
SEL
NC
0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
A0
A1
A2
A3
A4
A5
A6
A7
0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
GND17
GND16
GND15
GND14
GND13
GND12
VDD1
VDD2
VDD3
VDD4
VDD5
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
14
1.8V to DSP
2
4
8
10
15
17
21
23
OUT
OUT
IN
OUT
OUT
BI
BI
1
6
12
19
36
3
5
7
9
11
13
16
18
20
22
27
DSP_TCK (14)
DSP_TDI (14)
DSP_TDO (14)
DSP_TMS (14)
DSP_TRST# (14)
DSP_EMU_00 (14)
DSP_EMU_01 (14)
B
VCC3V3_AUX
C488
0.1uF
16V
C168
0.1uF
16V
C130
10uF
6.3V
TI_TS3L301DGG
Switch for JTAG emulation
FT2232HL_RESET# = 0 ‐‐> AMC
FT2232HL_RESET# = 1 ‐‐> Mini USB
Switch for JTAG emulation
EXT_EMU_DET = 0 ‐‐> External / Mezzanine Emulator
EXT_EMU_DET = 1 ‐‐> On board emulation
A
A
Designed for TI by ADVANTECH
Title
USB-JTAG
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
26
of
36
4
3
R75
(12)
(12)
(30)
DSP_MDC_1
DSP_MDIO_1
PHY_INT#
VCC2V5
IN
BI
IN
4.7K
GTX_CLK
TX_CLK
TX_EN
TX_ER
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
P1_COL_PD
E2
D1
E1
F2
F1
G2
G3
H2
H1
H3
J1
J2
C1
B1
D2
B2
D3
C3
B3
C4
A1
A2
C5
B5
B6
L3
M1
L1
R341
10K
TP4
C
P1_CONFIG0
P1_CONFIG1
P1_CONFIG2
P1_CONFIG3
P1_CONFIG4
P1_CONFIG5
P1_CONFIG6
P1_CLKSEL
K2
D8
E9
F8
G7
F9
G9
G8
H8
C6
C7
D7
E3
E7
F3
J3
J7
M3
M4
M7
M8
N5
B7
AVDD_1
AVDD_2
AVDD_3
AVDD_4
AVDD_5
AVDD_6
K9
L2
B4
C2
K1
R109
GTX_CLK
TX_CLK
TX_EN
TX_ER
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
RX_CLK
RX_DV
RX_ER
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
COL
MDI3+
MDI3MDI2+
MDI2MDI1+
MDI1MDI0+
MDI0S_IN+
S_INS_OUT+
S_OUTS_CLK+
S_CLK-
88E1111-BAB
N8
N9
N6
N7
N3
N4
N1
N2
MDI3_P
MDI3_N
MDI2_P
MDI2_N
MDI1_P
MDI1_N
MDI0_P
MDI0_N
A3
A4
A7
A8
A5
A6
DSP_SGMII_TXP_C
C39
DSP_SGMII_TXN_C
C42
DSP_SGMII_RXP
DSP_SGMII_RXN
R60
4.99K 1%
R72
4.99K 1%
MDI3_P
MDI3_N
MDI2_P
MDI2_N
MDI1_P
MDI1_N
MDI0_P
MDI0_N
BI
BI
BI
BI
BI
BI
BI
BI
(28)
(28)
(28)
(28)
(28)
(28)
(28)
(28)
P1_CLKSEL
NL/10K
P1_CONFIG2
R110
R383
0
R393
0
LED_LINK10
R82
0
LED_LINK1000
R86
0
R391
0
LED_DUPLEX
R390
0
LED_TX
R392
0
VCC2V5
VCC2V5
111
P1_CONFIG5
D
10K
110
P1_CONFIG1
100
DSP_SGMII_TXP
DSP_SGMII_TXN
0.1uF 16V
0.1uF 16V
IN
IN
OUT
OUT
DSP_SGMII_TXP
DSP_SGMII_TXN
DSP_SGMII_RXP
DSP_SGMII_RXN
P1_CONFIG4
(12)
(12)
(12)
(12)
100
P1_CONFIG3
011
P1_CONFIG0
001
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX
MARVELL_88E1111-B2-BAB1C000
TDI
TMS
TCK
TRST
TDO
MDC
MDIO
INT
125CLK
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
SEL_FREQ
HSDAC+
HSDACRSET
RESET
COMA
XTAL1
XTAL2
NC_1
NC_2
D4
G6
J5
J6
K4
K5
K6
L5
L6
D5
D6
E4
E5
E6
F4
F5
F6
G4
G5
H4
H5
H6
J4
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
G1
K7
VCC1V2
C8
B8
A9
E8
C9
D9
L7
L8
L9
M9
K8
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX
R106
NL/0
R107
NL/22
OUT
OUT
LED_LINK100 (28)
LED_LINK1000 (28)
OUT
LED_RX
IN
IN
IN
IN
OUT
P1_CONFIG6
000
(28)
FPGA_JTAG_TDO (32)
BSC_JTAG_TMS (32)
BSC_PHY_TCK
(32)
BSC_JTAG_RST# (31,32)
BSC_JTAG_TDI (32)
R119
FPGA_JTAG_TDO
0
BSC_JTAG_TDI
M5
M6
C
M2
P1_RSET
R18
4.99K 1%
K3
L4
R_P1_LAN_RST#
R19
0
H9
J9
PHY_P1_XTAL1
PHY_P1_XTAL2
PHY_RST#
IN
PHY_RST#
(30)
R332
4.99K
1%
VSSC
4.7K
NL/4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
1
H7
R41
R50
R51
R29
R39
R22
R17
R27
R20
R28
R10
R26
VDDO_1
VDDO_2
VDDO_3
D
AVCC2V5
VDDOX_1
VDDOX_2
VDDOH_1
VDDOH_2
VDDOH_3
PHY1
B9
F7
J8
VCC2V5
2
DVDD_1
DVDD_2
DVDD_3
DVDD_4
DVDD_5
DVDD_6
DVDD_7
DVDD_8
5
PHY_P1_XTAL1_R
R108
0
Y2
25MHz_20pF
PHY_P1_XTAL1
5%
PHY_P1_XTAL2
C67
27pF
50V
88E1111 Device Pin to Configuration Bit Mapping
B
Pin
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
Bit[2]
Bit[1]
PHYADR[2]
ENA_PAUSE
ANEG[3]
ANEG[0]
HWCFG_MODE[2]
DIS_FC
SEL_TWSI
PHYADR[1]
PHYADR[4]
ANEG[2]
ENA_XC
HWCFG_MODE[1]
DIS_SLEEP
INT_POL
Bit[0]
PHYADR[0]
PHYADR[3]
ANEG[1]
DIS_125
HWCFG_MODE[0]
HWCFG_MODE[3]
75/50 OHM
Pin
A
001
100
111
011
100
110
000
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
1
Pin to Constant Mapping
Pin
Bit[2:0]
B
VDDO
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
LED_TX
VSS
111
110
101
100
011
010
001
000
AVCC2V5
VCC2V5
B26
0.5A
120_100MHz
C320
0.01uF
16V
C294
0.1uF
16V
C336
4.7uF
6.3V
C298
0.1uF
16V
C285
4.7uF
6.3V
C329
0.01uF
16V
C328
0.1uF
16V
C343
0.1uF
16V
C271
4.7uF
6.3V
C282
4.7uF
6.3V
VCC1V2
CONFIG Pin Connection
LED Pin
Connection
C66
27pF
50V
PHY Address = 0x01
Hardware
Configuration
Bit Setting
LED_TX
LED_LINK1000
VDDO
LED_DUPLEX
LED_LINK1000
LED_LINK10
VSS
PHY Configuration
C296
0.01uF
16V
C319
0.01uF
16V
C297
0.1uF
16V
C316
4.7uF
6.3V
PHY Address bit[2:0] 001
Enable Pause ,PHY Address bit[4:3] = 00
A
Auto-Neg advertise all capabilities ,prefer Master
Enable MDI crossover, disable 125CLK
SGMII without Clock with SGMII Auto-Neg to copper
Designed for TI by ADVANTECH
Disable fiber /copper Auto-detect, Disable sleep
Select MDIO interface, INT signal active high, 50 ohm SERDES
Title
Gigabit Ethernet PHY
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
27
of
36
5
4
3
2
RJ-45
1
P1_TCT
B22
0.5A
120_100MHz
VCC2V5
C238
0.1uF
16V
C243
0.1uF
16V
C244
0.1uF
16V
C246
0.1uF
16V
C245
0.1uF
16V
D
D
C209
0.1uF
16V
C220
0.1uF
16V
P1_RC_P00
R3
49.9
1%
P1_RC_P01
R4
49.9
1%
R7
49.9
1%
C249
(27)
R9
49.9
1%
LED_RX
LED_RX
IN
R340
100
470pF
50V
LAN_ACT
LAN1
13
G
14
VCC2V5
11
(27)
MDI0_P
BI
(27)
MDI0_N
BI
MDI0_P
P1_TCT
MDI0_N
12
1
TX1+
10
TX12
4
(27)
MDI1_P
BI
(27)
MDI1_N
BI
MDI1_P
P1_TCT
MDI1_N
6
3
TX2+
5
TX26
3
(27)
MDI2_P
BI
(27)
MDI2_N
BI
MDI2_P
P1_TCT
MDI2_N
1
4
TX3+
2
TX35
8
C
(27)
MDI3_P
BI
(27)
MDI3_N
BI
MDI3_P
P1_TCT
MDI3_N
P1_RC_P03
C317
0.1uF
16V
R57
49.9
1%
R21
49.9
1%
R16
49.9
1%
(27)
(27)
LED_LINK100
LED_LINK1000
IN
IN
LED_LINK100
LED_LINK1000
7
TX4+
9
TX48
16
VCC2V5
R64
49.9
1%
7
G
R330
R329
100
100
17
15
H1
H2
H3
H4
75R
O
C
1000pF 2kV
SHIELD GND
P1_RC_P02
GND_LAN
C237
0.1uF
16V
RJ45_W/XFMR&LED
FOR EMI
B5
0.5A
120_100MHz
GND_LAN
B
B
Heatsink Holes
AMC Hole
H5
BRK1
SOCKET841_CSBGA841
1
H1
H2
1
1
H35-NPTH
H35-NPTH
3
6
On board
4
H27P35-MTH
FM1
FM2
NL/Fiducial
NL/Fiducial
5
2
1
FM3
H3
FM4
H4
1
1
H35-NPTH
H35-NPTH
NL/Fiducial
NL/Fiducial
(Bottom Side 3mm) Placed Capacitors
A
A
Designed for TI by ADVANTECH
Title
RJ45
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
28
of
36
5
4
3
2
1
IPASS+HD for HyperLink Bus connection
D
D
Hyperlink1
iPass Plus HD 1x1 Assy
HyperLink_RXPMCLK OUT
HyperLink_RXFLDAT IN
(12)
(12)
HyperLink_TXP0
HyperLink_TXN0
IN
IN
(12)
(12)
HyperLink_TXP2
HyperLink_TXN2
IN
IN
(12)
(12)
HyperLink_RXPMDAT
HyperLink_TXFLDAT
OUT
OUT
HyperLink_RXP0
HyperLink_RXN0
OUT
OUT
(12)
(12)
HyperLink_RXP2
HyperLink_RXN2
OUT
OUT
HyperLink_TXP0
HyperLink_TXN0
HyperLink_TXP2
HyperLink_TXN2
HyperLink_RXPMDAT
HyperLink_TXFLDAT
HyperLink_RXP0
HyperLink_RXN0
HyperLink_RXP2
HyperLink_RXN2
D1
D2
D3
D4
D5
D6
D7
D8
D9
B1
B2
B3
B4
B5
B6
B7
B8
B9
sideband5
sideband6
GND_D3
Txp0
Txn0
GND_D6
Txp2
Txn2
GND_D9
sideband4
sideband2
GND_C3
Txp1
Txn1
GND_C6
Txp3
Txn3
GND_C9
sideband3
sideband1
GND_B3
Rxp0
Rxn0
GND_B6
Rxp2
Rxn2
GND_B9
sideband7
sideband0
GND_A3
Rxp1
Rxn1
GND_A6
Rxp3
Rxn3
GND_A9
H1
H2
(12)
(12)
HyperLink_RXPMCLK
HyperLink_RXFLDAT
NPTH1
NPTH2
(12)
(12)
C1
C2
C3
C4
C5
C6
C7
C8
C9
HyperLink_TXPMDAT
HyperLink_TXPMCLK
A1
A2
A3
A4
A5
A6
A7
A8
A9
HyperLink_TXFLCLK
HyperLink_RXFLCLK
IN
IN
HyperLink_TXP1
HyperLink_TXN1
HyperLink_TXP3
HyperLink_TXN3
HyperLink_TXP1
HyperLink_TXN1
(12)
(12)
IN
IN
HyperLink_TXP3
HyperLink_TXN3
(12)
(12)
OUT
IN
HyperLink_RXP1
HyperLink_RXN1
HyperLink_RXP3
HyperLink_RXN3
HyperLink_TXPMDAT
HyperLink_TXPMCLK
IN
IN
(12)
(12)
HyperLink_TXFLCLK
(12)
HyperLink_RXFLCLK
(12)
OUT
OUT
HyperLink_RXP1
HyperLink_RXN1
(12)
(12)
OUT
OUT
HyperLink_RXP3
HyperLink_RXN3
(12)
(12)
IPASS+HD_36H
C
C
80‐pin Expansion Header
the interfaces on the 80‐pin header are all
1.8V LVCMOS except for the UART which
is 3.3V LVCMOS
H2
TEST_PH1
B
GPIO
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(14,15,31)
(15,31)
(15,31)
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
DSP_SDA
DSP_SCL
BI
IN
DSP_SDA
DSP_SCL
(15)
(15)
I2C
B
DSP_TIMI0
DSP_TIMO0
DSP_TIMI1
DSP_TIMO1
NOR_SSPMISO
R345
10
NOR_SSPMOSI
DSP_SSPCS1
PH_SSPCK
DSP_UARTTXD
DSP_UARTRXD
DSP_UARTRTS
DSP_UARTCTS
H1
A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
OUT
IN
OUT
IN
OUT
IN
IN
IN
IN
OUT
IN
OUT
DSP_TIMI0 (15,31)
DSP_TIMO0 (15)
DSP_TIMI1 (15,31)
DSP_TIMO1 (15)
NOR_SSPMISO (15,30)
NOR_SSPMOSI (15,30)
DSP_SSPCS1 (15,30)
PH_SSPCK (15)
DSP_UARTTXD (15)
DSP_UARTRXD (15)
DSP_UARTRTS (15)
DSP_UARTCTS (15)
TIMI
SPI
UART
DSP_UART(3.3V)
A
PH(F)_40x2V_S1.27mm
<Characteristic>
Designed for TI by ADVANTECH
Title
Connectors for HyperLink & Debug
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Friday, May 20, 2011
Sheet
1
29
of
36
5
4
3
2
1
D
D
TCLKA_P
TCLKB_P
TCLKC_P
TCLKD_P
R396
R387
R377
R370
TCLKA_N
TCLKB_N
TCLKC_N
TCLKD_N
100
100
100
100
Place near to FPGA
R435
VCC3V3_FPGA
(11) MMC_DETECT#
(11) MMC_RESETSTAT#
(11) MMC_POR_IN_AMC#
(11) MMC_WR_AMC#
(11) MMC_BOOTCOMPLETE
(16) PCA9306_EN
(27) PHY_RST#
(35) VCC5_PGOOD
(34) VCC2P5_PGOOD
(35) VCC3_AUX_PGOOD
(34) VCC0P75_PGOOD
(36) VCC1P5_PGOOD
(16) FPGA_ICS557_OE
(36) VCC1P5_EN
(16) FPGA_ICS557_PD#
(34) VCC1P8_EN1
(34) VCC0P75_EN
(34) VCC2P5_EN
(35) VCC_5V_EN
(33) UCD9222_PG2
(33) UCD9222_ENA2
(33) UCD9222_PG1
(33) UCD9222_ENA1
(33) PGUCD9222
(33) UCD9222_RST#
(33) PMBUS_CLK
(33) PMBUS_DAT
(33) PMBUS_ALT
(33) PMBUS_CTL
MMC
PHY 88E1111
POWER SEQUENCE
PCIE CLOCK CONTROL
PCIE CLOCK CONTROL
POWER SEQUENCE
C
POWER UCD9222
PCIE CLOCK CONTROL
Switches RESET
(16)
FPGA_ICS557_SEL
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
OUT
BI
IN
OUT
OUT
MMC_DETECT#
R434
MMC_RESETSTAT#
R436
MMC_POR_IN_AMC# R127
MMC_WR_AMC#
R135
MMC_BOOTCOMPLETE
PCA9306_EN
VCC5_PGOOD
VCC2P5_PGOOD
VCC3_AUX_PGOOD
VCC0P75_PGOOD
VCC1P5_PGOOD
R384
0
R169
R231
R63
R130
UCD9222_PG2
R37
UCD9222_PG1
R35
PGUCD9222
UCD9222_RST#
PMBUS_CLK R69
PMBUS_DAT R53
PMBUS_ALT R62
PMBUS_CTL R356
DSP_VCL_FPGA
DSP_VD_FPGA
SYS_PGOOD
0
0
0
0
(10)
(10)
AMC TCLOCK
(10)
(10)
(10)
(10)
TCLKB_N
TCLKB_P
(10)
(10)
TCLKD_N
TCLKD_P
B27
VCC3V3_FPGA
TCLKA_N
TCLKA_P
IN
IN
TCLKC_N
TCLKC_P
IN
IN
0
0
0
0
0
FULL_RESET
WARM_RESET
Cold_RESET
OUT
OUT
IN
OUT
(11) MMC_SPI_SCK
(11) MMC_SPI_STE
(11) MMC_SPI_MISO
(11) MMC_SPI_MOSI
(27) PHY_INT#
IN
MMC
PHY 88E1111
0
IN
IN
IN
IN
120_100MHz 2A
C322
0.1uF
16V
B
C356
0.1uF
16V
10K
N14
N13
P15
R15
N16
P16
M14
M13
K13
L13
M16
M15
L16
L14
VCC1V5_EN_R
J13
J12
VCC1V8_EN1_R
K14
VCC0V75_EN_R
K15
VCC2V5_EN_R
J16
VCC_5V_EN_R
K16
UCD9222_ENA2_R H14
J14
UCD9222_ENA1_R H16
H15
F16
G16
PMBUS_CLK_R
G14
PMBUS_DAT_R
H13
PMBUS_ALT_R
F15
PMBUS_CTL_R
E16
F14
G13
F13
E14
D15
D16
D14
MMC_SPI_SCK
E13
MMC_SPI_STE
C15
MMC_SPI_MISO
C16
MMC_SPI_MOSI
K12
PHY_INT#
K11
J11
J10
H11
H10
G11
G12
F11
F12
R128
R16
0
E15
H12
J15
N15
C304
C292
0.1uF
0.1uF
16V
16V
1K
1K
1K
1K
FPGA1A
IO_L01N_1/LDC2
IO_L01P_1/HDC
IO_L02N_1/LDC0
IO_L02P_1/LDC1
IO_L03N_1/A1
IO_L03P_1/A0
IO_L05N_1/VREF_1_1
IO_L05P_1
IO_L06N_1/A3
IO_L06P_1/A2
IO_L07N_1/A5
IO_L07P_1/A4
IO_L08N_1/A7
IO_L08P_1/A6
IO_L10N_1/A9
IO_L10P_1/A8
IO_L11N_1/RHCLK1
IO_L11P_1/RHCLK0
IO_L12N_1/TRDY1/RHCLK3
IO_L12P_1/RHCLK2
IO_L14N_1/RHCLK5
IO_L14P_1/RHCLK4
IO_L15N_1/RHCLK7
IO_L15P_1/IRDY1/RHCLK6
IO_L16N_1/A11
IO_L16P_1/A10
IO_L17N_1/A13
IO_L17P_1/A12
IO_L18N_1/A15
IO_L18P_1/A14
IO_L19N_1/A17
IO_L19P_1/A16
IO_L20N_1/A19
IO_L20P_1/A18
IO_L22N_1/A21
IO_L22P_1/A20
IO_L23N_1/A23
IO_L23P_1/A22
IO_L24N_1/A25
IO_L24P_1/A24
IP_L04N_1/VREF_1_2
IP_L04P_1
IP_L09N_1
IP_L09P_1/VREF_1_3
IP_L13N_1
IP_L13P_1
IP_L21N_1
IP_L21P_1/VREF_1_4
IP_L25N_1
IP_L25P_1/VREF_1_5
SUSPEND
VCCO_1_1
VCCO_1_2
VCCO_1_3
VCCO_1_4
Bank1
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0/VREF_0_1
IO_L03N_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0
IO_L05P_0
IO_L06N_0/VREF_0_2
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L08N_0
IO_L08P_0
IO_L09N_0/GCLK5
IO_L09P_0/GCLK4
IO_L10N_0/GCLK7
IO_L10P_0/GCLK6
IO_L11N_0/GCLK9
IO_L11P_0/GCLK8
IO_L12N_0/GCLK11
IO_L12P_0/GCLK10
IO_L13N_0
IO_L13P_0
IO_L14N_0/VREF_0_3
IO_L14P_0
IO_L15N_0
IO_L15P_0
IO_L16N_0
IO_L16P_0
IO_L17N_0
IO_L17P_0
IO_L18N_0
IO_L18P_0
IO_L19N_0
IO_L19P_0
IO_L20N_0/PUDC
IO_L20P_0/VREF_0_4
IP_0_1
IP_0_2
IP_0_3
IP_0_4
IP_0_5
IP_0_6
IP_0_7/VREF_0_5
VCCO_0_1
VCCO_0_2
VCCO_0_3
VCCO_0_4
Bank0
C13
D13
B14
B15
D11
C12
A13
A14
A12
B12
E10
D10
A11
C11
A10
B10
D9
C10
A9
C9
D8
C8
B8
A8
C7
A7
E7
F8
B6
A6
C6
D7
C5
A5
B4
A4
B3
A3
D5
C4
D6
D12
E6
F7
F9
F10
E9
B5
B9
B13
E8
DSP_RESETSTAT#
TRGRSTZ
EEPROM_WP
NOR_WP#
DSP
60 PIN Header
EEPROM
NOR FLASH
IN
IN
OUT
OUT
DSP_RESETSTAT# (16)
TRGRSTZ (14)
EEPROM_WP (15)
NOR_WP# (15)
IN
IN
OUT
IN
DSP_SSPCS1 (15,29)
FPGA_SSPCK (15)
NOR_SSPMISO (15,29)
NOR_SSPMOSI (15,29)
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DSP_PACLKSEL (15)
DSP_LRESETNMIENZ
(16)
DSP_CORESEL0
(15)
DSP_CORESEL1
(15)
DSP_CORESEL2
(15)
DSP_DSPCLKSEL
(16,31)
DSP_NMIZ (15)
DSP_LRESETZ (16)
IN
DSP_HOUT (15)
IN
DSP_BOOTCOMPLETE (15)
IN
DSP_SYSCLKOUT
(16)
VCC1V8
DSP_PORZ (16)
DSP_RESETFULLZ
(16)
DSP_RESETZ (16)
OUT
NAND_WP#
(14)
IN FPGA_EXTFRAMEEVENT (15)
TP13
TP14
DSP_SSPCS1
R349
10
PACLKSEL
R24
10
DSP_LRESETNMIENZ
DSP_CORESEL0
DSP_CORESEL1
DSP_CORESEL2
FPGA_DSPCLKSEL R355
10
DSP_NMIZ
DSP_LRESETZ
DSP_HOUT
DSP_BOOTCOMPLETE
DSP_SYSCLKOUT
VCC1P8_PGOOD
R346
DSP_PORZ
DSP_RESETFULLZ
DSP_RESETZ
1K
OUT
OUT
OUT
FPGA_EXTFRAMEEVENT
DSP SPI
DSP
C
DSP RESETS
FPGA_PUDC
XDS560_IL
XDS560_IL
OUT
B24
C274
0.1uF
16V
C283
0.1uF
16V
C275
0.1uF
16V
(14)
120_100MHz 2A
VCC1V8_AUX
C276
0.1uF
16V
VCC1V8_AUX
B
XILINX_XC3S200AN-4FTG256C
R348
10K
FPGA_PUDC
DSP_VCL_1
DSP_VD_1
IN
BI
VCC3V3_FPGA
Cold_RESET
C135
0.01uF
16V
SW7-P1 R134
1
1
HDK632AR-ST
100
RST_WARM1
HDK632AR-ST
3
4
A
R153
8.2K
VCC3V3_FPGA
FULL_RESET
WARM_RESET
100
C90
0.01uF
16V
3
4
SW8-P1 R78
RST_FULL1
HDK632AR-ST
3
4
100
SYS_PGOOD
R90
8.2K
FULL_RESET
C52
0.01uF
16V
R56
330
High active
PUDC:
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank VCCO input.
0: Pull-ups during configuration
1: No pull-ups
SYSPG_D1
B
RST_COLD1
2
SW1-P1 R177
R193
8.2K
VCC3V3_FPGA
WARM_RESET
2
Cold_RESET
R347
NL/10K
DSP_VCL_1 (16)
DSP_VD_1 (16)
1
NL/0
NL/0
2
R70
R52
DSP_VCL_FPGA
DSP_VD_FPGA
1
PMBUS_CLK
PMBUS_DAT
NL/0
NL/0
2
R375
R48
19-215SUBC/S280/TR8
A
Designed for TI by ADVANTECH
Title
FPGA_XC3S200AN_A
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Tuesday, May 24, 2011
Sheet
1
30
of
36
5
4
3
2
1
VCC3V3_FPGA
VCC3V3_FPGA
VCC3V3_FPGA
R287
330
R288
330
R289
330
R290
330
FPGA_D2
19-215SUBC/S280/TR8
FPGA_D3
19-215SUBC/S280/TR8
19-215SUBC/S280/TR8
2
FPGA_D1
2
FPGA_SPI_HD#
FPGA_SPI_SCK
FPGA_SPI_SI
2
8
7
6
5
VCC3V3_FPGA
DEBUG_LED_1
DEBUG_LED_2
R143
1K
R444
330
R442
330
R426
NL/330
FPGA_INIT#
FPGA_M0
FPGA_M1
FPGA_M2
DEBUG_LED_3
R142
NL/0
R433
NL/0
R431
NL/0
R430
0
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(14,15,29)
(15,29)
(15,29)
DSP
GPIO TO
FPGA
(15,29)
(15,29)
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
DSP_TIMI0
DSP_TIMI1
OUT
OUT
B32
2A
120_100MHz
VCC1V8_AUX
C293
0.1uF
16V
C1
C2
D3
D4
E1
D1
E2
E3
G4
F3
G1
F1
H4
G3
H5
H6
H1
IN
G2
IN
J3
IN
H3
IN
J1
IN
J2
IN
K1
IN
K3
IN
L2
IN
L1
IN
J6
IN
J4
IN
L3
IN
K4
IN
L4
IN
M3
IN
N1
M1
PCIESSEN
P1
User define
N2
FPGA_PACLKSEL
FPGA_TIMI0 P2
R337
10
FPGA_TIMI1 R1
R351
10
M4
N3
F4
E4
G5
G6
J7
H7
K6
K5
L6
L5
D2
H2
J5
M2
C284
C342
C308
0.1uF
0.1uF
0.1uF
16V
16V
16V
BM_GPIO_00
BM_GPIO_01
BM_GPIO_02
BM_GPIO_03
BM_GPIO_04
BM_GPIO_05
BM_GPIO_06
BM_GPIO_07
BM_GPIO_08
BM_GPIO_09
BM_GPIO_10
BM_GPIO_11
BM_GPIO_12
BM_GPIO_13
BM_GPIO_14
BM_GPIO_15
DSP_GPIO_00
DSP_GPIO_01
DSP_GPIO_02
DSP_GPIO_03
DSP_GPIO_04
DSP_GPIO_05
DSP_GPIO_06
DSP_GPIO_07
DSP_GPIO_08
DSP_GPIO_09
DSP_GPIO_10
DSP_GPIO_11
DSP_GPIO_12
DSP_GPIO_13
DSP_GPIO_14
DSP_GPIO_15
IO_L01N_3
IO_L01P_3
IO_L02N_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L05N_3
IO_L05P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3/VREF_3_1
IO_L08P_3
IO_L09N_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L11N_3/LHCLK1
IO_L11P_3/LHCLK0
IO_L12N_3/IRDY2/LHCLK3
IO_L12P_3/LHCLK2
IO_L14N_3/LHCLK5
IO_L14P_3/LHCLK4
IO_L15N_3/LHCLK7
IO_L15P_3/TRDY2/LHCLK6
IO_L16N_3
IO_L16P_3/VREF_3_2
IO_L17N_3
IO_L17P_3
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L20N_3
IO_L20P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
IO_L24P_3
IP_L04N_3/VREF_3_3
IP_L04P_3
IP_L06N_3/VREF_3_4
IP_L06P_3
IP_L13N_3
IP_L13P_3
IP_L21N_3
IP_L21P_3
IP_L25N_3/VREF_3_5
IP_L25P_3
VCCO_3_1
VCCO_3_2
VCCO_3_3
VCCO_3_4
Bank3
Bank2
IO_L01N_2/M0
IO_L01P_2/M1
IO_L02N_2/CSO
IO_L02P_2/M2
IO_L03N_2/VS2
IO_L03P_2/RDWR
IO_L04N_2/VS0
IO_L04P_2/VS1
IO_L05N_2
IO_L05P_2
IO_L06N_2/D6
IO_L06P_2/D7
IO_L07N_2
IO_L07P_2
IO_L08N_2/D4
IO_L08P_2/D5
IO_L09N_2/GCLK13
IO_L09P_2/GCLK12
IO_L10N_2/GCLK15
IO_L10P_2/GCLK14
IO_L11N_2/GCLK1
IO_L11P_2/GCLK0
IO_L12N_2/GCLK3
IO_L12P_2/GCLK2
IO_L13N_2
IO_L13P_2
IO_L14N_2/MOSI/CSI
IO_L14P_2
IO_L15N_2/DOUT
IO_L15P_2/AWAKE
IO_L16N_2
IO_L16P_2
IO_L17N_2/D3
IO_L17P_2/INIT
IO_L18N_2/D1
IO_L18P_2/D2
IO_L19N_2
IO_L19P_2
IO_L20N_2/CCLK
IO_L20P_2/D0/DIN/MISO
IP_2_1
IP_2_2
IP_2_3/VREF_2_1
IP_2_4/VREF_2_2
IP_2_5/VREF_2_3
IP_2_6/VREF_2_4
IP_2_7/VREF_2_5
IP_2_8/VREF_2_6
VCCO_2_1
VCCO_2_2
VCCO_2_3
VCCO_2_4
P4
FPGA_M0
N4
FPGA_M1
T2
OUT
VID_OE# (16)
R2
FPGA_M2
T3
R425
10K
R3
P5
R440
10K
N6
R439
10K
R5
CLOCK2_SSPCS1
CLOCK2_SSPCS1
(22)
OUT
T4 CLOCK2CK R407
10
OUT
CLOCK2_SSPCK (22)
T6
CLOCK2_SSPSI
CLOCK2_SSPSI
(22)
OUT
T5
CLOCK2_SSPSO
IN
CLOCK2_SSPSO (22)
P6
REFCLK2_PD#
REFCLK2_PD#
(22)
OUT
N7
CLOCK3_SSPCS1
OUT
CLOCK3_SSPCS1
(23)
N8 CLOCK3CK R428
10
OUT
CLOCK3_SSPCK (23)
P7
CLOCK3_SSPSI
CLOCK3_SSPSI
(23)
OUT
T7
CLOCK3_SSPSO
IN
CLOCK3_SSPSO (23)
R7
REFCLK3_PD#
REFCLK3_PD#
(23)
OUT
T8
CLOCK1_SSPCS1
OUT
CLOCK1_SSPCS1
(21)
P8 CLOCK1CK R221
10
CLOCK1_SSPCK (21)
OUT
P9
CLOCK1_SSPSI
CLOCK1_SSPSI
(21)
OUT
N9
CLOCK1_SSPSO
IN
CLOCK1_SSPSO (21)
T9
REFCLK1_PD#
REFCLK1_PD#
(21)
OUT
R9
MAIN_48MHZ_CLK_R
M10
CLOCK1_PLL_LOCK
CLOCK1_PLL_LOCK
(21)
IN
N10
CLOCK2_PLL_LOCK
CLOCK2_PLL_LOCK
(22)
IN
P10
CLOCK3_PLL_LOCK
CLOCK3_PLL_LOCK
(23)
IN
T10
TP16
R11
TP17
T11
TP18
N11
BSC_JTAG_RST#
BSC_JTAG_RST# (27,32)
IN
P11
DEBUG_LED_0
P12
DEBUG_LED_1
T12
FPGA_INIT#
R13
DEBUG_LED_2
T13
DEBUG_LED_3
P13
FPGA_SPI_CS#
N12
FPGA_SPI_SI
R14
R451
10 FPGA_SPI_SCK
T14
FPGA_SPI_SO
L7
R437
10
IN
FPGA_DONE (32)
L8
L9
L10
M7
M8
M11
N5
M9
R4
R8
R12
CDCE62005
BM_GPIO
[10:4]
FPGA EEPROM
VCC3V3_FPGA
C361
0.1uF
16V
C399
0.1uF
16V
VCC3V3_AUX
PCIESSEN
B6
120_100MHz
0.5A
Y6
4
2
BOOT STRAP CONFIGURATION
C65
0.1uF
16V
VCC1V8_AUX
R527
R513
R509
R502
10K
10K
10K
10K
BM_GPIO_00
BM_GPIO_01
BM_GPIO_02
BM_GPIO_03
SW3
ESD104EZ
ON
1
2
3
4
8
7
6
5
R536
R537
R538
R539
100
100
100
100
R514
R515
R516
R517
10K
10K
10K
10K
BM_GPIO_04
BM_GPIO_05
BM_GPIO_06
BM_GPIO_07
SW4
ESD104EZ
ON
1
2
3
4
8
7
6
5
R540
R541
R542
R543
100
100
100
100
R518
R519
R520
R521
10K
10K
10K
10K
BM_GPIO_08
BM_GPIO_09
BM_GPIO_10
BM_GPIO_11
SW5
ESD104EZ
ON
1
2
3
4
8
7
6
5
R544
R545
R546
R547
100
100
100
100
R489
R490
R491
R492
10K
10K
10K
10K
BM_GPIO_12
BM_GPIO_13
BM_GPIO_14
BM_GPIO_15
SW6
ESD104EZ
ON
1
2
3
4
8
7
6
5
R548
R549
R550
R551
100
100
100
100
10K
10K
10K
10K
SW9
ESD104EZ
ON
1
PCIESSEN
2
User define
3
FPGA_PACLKSEL 4
VCC1V8
VCC1V8
R493
R494
R495
R496
VCC
GND
OUT
OE
3
1
MAIN_48MHZ_CLK
R88
Input
33 MAIN_48MHZ_CLK_R
48MHz_15pF
3.3V
0
Initial state of the power domain and the clock
domain for PCIE subsystem is disabled
1
Initial state of the power domain and the clock domain for PCIE subsystem is enabled
PCIe Mode
selection(PCIESSMODE[1:0])
00b
01b
10b
Description
PCIe in End‐point mode
PCIe in Legacy End‐point mode(no support for MSI)
PCIe in Legacy Root complex mode
CLK Mode
8
7
6
5
R552
R553
R554
R555
100
100
100
1K
Clock
Default_Down SYSCLK /
ALTCORECLK
DSP_DSPCLKSELL = 0
SYSCLK used to clock the core PLL. DSP_DSPCLKSEL = 1
ALTCORECLK is used to clock the core PLL
Default_Down
FPGA_PACLKSEL = 0
PASSCLK is not used and should be tied to a static state.
FPGA_PACLKSEL = 1
PASSCLK is used as a source for the PA_SS PLL. It must be present before the PA_SS PLL is removed from reset and programmed
PASSCLK
Input
PA driven from core clk
PA driver from PA clk
C
Device
Configuration
Field
The device configuration fields
GPIO[10:4] are used to configure the
boot peripheral and, therefore, the bit
definitions depend on the boot mode.
INPUT
CLK (MHz)
50.00
66.67
80.00
100.00
156.25
250.00
312.50
122.88
CorePac System PLL Configuration
PA driven from core clk
PA driver from PA clk
B
Boot Configuration
Description
BM_GPIO[15:14] INPUT
NOTE
PLL Settings
BM_GPIO
13 12 11
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
B34
2A
120_100MHz
C397
0.1uF
16V
BOOT
Device
EMIF16
sRIO
SMGII
SGMII
PCIe
I2C
SPI
HyperLink
Device Configuration
For FPGA internal reset.
C400
0.1uF
16V
BM_GPIO
3 2 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CDCE62002
XILINX_XC3S200AN-4FTG256C
B
A
D
Boot Device
FPGA1B
C
VCC3V3_FPGA
DEBUG_LED
SPI_EEPROM
For BOOT
MODE
SWITCH
VCC3V3_FPGA
19-215SUBC/S280/TR8
ATMEL_AT25128B-SSHL-B
DEBUG_LED_0
VCC3V3_FPGA
FPGA_D4
B
VCC
HOLD
SCK
SI
B
CS
SO
WP
GND
B
1
2
3
4
B
D
FPGA_SPI_CS#
FPGA_SPI_SO
FPGA_SPI_WP#
4.7K
4.7K
4.7K
1
U10
R189
R190
R191
1
VCC3V3_FPGA
1
VCC3V3_FPGA
R154
4.7K
2
VCC3V3_FPGA
R157
4.7K
1
C87
0.1uF
16V
Description
DIP Switch
DSP
Boot Mode
BM_GPIO0
BM_GPIO1
BM_GPIO2
BM_GPIO3
BM_GPIO4
BM_GPIO5
BM_GPIO6
BM_GPIO7
BM_GPIO8
BM_GPIO9
BM_GPIO10
BM_GPIO11
BM_GPIO12
BM_GPIO13
BM_GPIO14
BM_GPIO15
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
LENDIAN
BOOTMODE00
BOOTMODE01
BOOTMODE02
BOOTMODE03
BOOTMODE04
BOOTMODE05
BOOTMODE06
BOOTMODE07
BOOTMODE08
BOOTMODE09
BOOTMODE10
BOOTMODE11
BOOTMODE12
PCIESSMODE0
PCIESSMODE1
Primary Function
Pull Up
Pull Down
Little Endian Big Endian
Boot Device
Boot Device
Boot Device
Device Cfg
Device Cfg
Device Cfg
Device Cfg
Device Cfg
Device Cfg
Device Cfg
PLL Multiplier/I2C
PLL Multiplier/I2C
PLL Multiplier/I2C
Endpt/RootComplex
Endpt/RootComplex
Designed for TI by ADVANTECH
Title
FPGA_XC3S200AN_B
OUT
DSP_DSPCLKSEL
Size
(16,30)
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
31
of
36
A
5
4
3
2
1
VCC3V3_AUX
TAP_FPGA1
PH_8x1V_2.54mm
1
2
3
4
5
6
7
8
D
VCC3V3_FPGA
R324
R272
22
22
BSC_JTAG_TCK
IN
BSC_JTAG_TDO
BSC_JTAG_TMS
BSC_JTAG_RST#
BSC_JTAG_P8
BSC_JTAG_TDI
(27)
BSC_JTAG_TMS (27)
BSC_JTAG_RST# (27,31)
OUT
OUT
BSC_JTAG_P8
R267
4.7K
BSC_JTAG_TCK
R331
4.7K
BSC_JTAG_TMS
R270
4.7K
BSC_JTAG_TDO
R271
4.7K
BSC_JTAG_TDI
R323
4.7K
BSC_JTAG_RST#
R268
NL/1K
R269
4.7K
C203
0.1uF
16V
D
VCC3V3_AUX
8
C27
0.1uF
16V
2
6
4
1
BSC_JTAG_TCK
5
3
7
BSC_JTAG_TCK
R322
22
R314
22
BSC_FPGA_TCK
U27A
TI_SN74LVC2G125DCUR
BSC_PHY_TCK
OUT
BSC_PHY_TCK
(27)
U26B
TI_SN74LVC2G125DCUR
C
C
FPGA1C
(31)
FPGA_DONE
FPGA_DONE
FPGA_PROG
OUT
BSC_FPGA_TCK
BSC_JTAG_TDO
(27)
FPGA_JTAG_TDO
OUT
R54
R23
0
22
BSC_JTAG_TMS
C445
0.1uF
16V
C372
0.1uF
16V
C303
0.1uF
16V
B
G7
G9
H8
J9
K8
K10
VCC1V2_FPGA
C306
0.1uF
16V
VCC3V3_FPGA
C341
0.1uF
16V
C323
0.1uF
16V
C305
0.1uF
16V
C307
0.1uF
16V
C311
0.1uF
16V
VCC3V3_FPGA
R144
1K
A15
B1
B16
B2
E11
F5
L12
M6
VCC3V3_FPGA
C380
0.1uF
16V
T15
A2
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
DONE
PROG
TCK
TDI
TDO
TMS
VCCAUX_1
VCCAUX_2
VCCAUX_3
VCCAUX_4
VCCINT_1
VCCINT_2
VCCINT_3
VCCINT_4
VCCINT_5
VCCINT_6
A1
A16
B7
B11
C3
C14
E5
E12
F2
F6
G8
G10
G15
H9
J8
K2
K7
K9
L11
L15
M5
M12
P3
P14
R6
R10
T1
T16
B
XILINX_XC3S200AN-4FTG256C
R40
4.7K
FPGA_DONE
FPGA_PROG
VCC3V3_AUX
R145
NL/330
VCC3V3_FPGA
1
B39
G
2
VCC1V2
VCC1V2_FPGA
R38
NL/100K
120_100MHz
2A
D10
NL/KP-1608SGD
B31
C287
10uF
6.3V
<Characteristic>
C351
0.1uF
16V
120_100MHz
2A
C327
10uF
6.3V
C310
0.1uF
16V
During Configuration :
Must be High to allow
configuration to start.
A
A
Designed for TI by ADVANTECH
Title
FPGA_XC3S200AN_C
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
32
of
36
5
4
3
2
1
PMBus Address Bins
CVDD
PMBus Address PMBus RESISTANCE ( K ohm )
C272
4.7uF
6.3V
VCC3V3_AUX
VCC12
9222_TCK
9222_TMS
9222_TDI
9222_TDO
R46
R43
R44
R45
10K
10K
10K
10K
9222_TRST#
R42
10K
41
C277
0.1uF
16V
V33FB
34
R400
48.7K
1%
V33DIO
1uF 6.3V 35
C28
BPCAP
4
1
linMon
45
0.01uF 16V
9222_TEMP1 46
0.01uF 16V 9222_TEMP2 2
UCD9222_GND
R409
C324
10K
C373
1%
C51
1K
EAN1
EAP2 R67
1K
FLT2A
DPWM2A
PG2
ENA2
CS2A
UCD9222_GND
UCD_VIN
EAP1 R365
FLT1A
DPWM1A
PG1
ENA1
CS1A
V33A
33
C59
0.1uF
16V
48
0.1uF 16V
C291
R364
470pF 50V
NL/2K
C43
R55
470pF 50V
NL/2K
VinMon
IinMon
Vtrack
Temp1/AuxADC1
Temp2/AuxADC2
VID1A
VID1B
VID1C
VID1S
VID2A
VID2B
VID2C
VID2S
ADC_REF
37
38
EAp1
EAn1
39
40
EAp2
EAn2
AGND2
AGND3
DGND3
PowerPad
Thermal_VIA1
Thermal_VIA2
Thermal_VIA3
Thermal_VIA4
Thermal_VIA5
Thermal_VIA6
Thermal_VIA7
Thermal_VIA8
Thermal_VIA9
Thermal_VIA10
Thermal_VIA11
Thermal_VIA12
Thermal_VIA13
Thermal_VIA14
Thermal_VIA15
Thermal_VIA16
Thermal_VIA17
Thermal_VIA18
Thermal_VIA19
Thermal_VIA20
Thermal_VIA21
Thermal_VIA22
Thermal_VIA23
Thermal_VIA24
Thermal_VIA25
EAN2
C
(30)
PMBUS_CTL
(30)
(30)
(30)
10K
PMBUS_CTL
IN
PGUCD9222
PMBUS_CLK
PMBUS_DAT
PMBUS_ALT
UCD9222_RST#
44
43
PMBus_ADDR0
PMBus_ADDR1
17
100K
1M
IN
PowerGood
10
11
19
20
PMBUS_CLK
PMBUS_DAT
PMBUS_ALT
IN
BI
OUT
VCC3V3_AUX
(30)
JTAG_TCK
JTAG_TDI/SYNC_IN
JTAG_TDO/SYNC_OUT
JTAG_TMS
JTAG_TRST
PGUCD9222
2K
2K
R385
R354
VCC3V3_AUX
PMBUS1
PH_5x1V_2.54mm
1
PMBUS_CLK
2
PMBUS_DAT
3
PMBUS_ALT
4
PMBUS_CTL
5
OUT
R98
R99
VCC3V3_AUX
R367
VCC3V3_AUX
(30)
R76
R66
R399
VCC3V3_AUX
27
29
28
30
31
9222_TCK
9222_TDI
9222_TDO
9222_TMS
9222_TRST#
100K
100K
10K
Remove other JTAG pins from the
boundary scan chain.
PMBUS Address
=> 6*12+6 = 78
=> 0x4Eh
R560
10K
PMBUS_CLK
PMBUS_DATA
PMBUS_ALERT
PMBUS_CNTRL
5
R96
10K
R97
NL/0
RESET
RST#
6
12
13
25
42
UCD9222_PG2
R561
10K
CS1A
8
14
15
26
3
CS2A
FF-1A1
PWM-1A
UCD9222_PG1
UCD9222_PG1
OUT
UCD9222_ENA1
R378
2.49K 1% lsenes-1A
C312
0.01uF
UCD9222_GND
16V
FF-1A2
PWM-2A
UCD9222_PG2
UCD9222_PG2
OUT
UCD9222_ENA2
R104
lsenes-2A
0
C60
0.01uF 16V
UCD9222_GND
R116
39.2K 1%
16
18
21
7
22
23
24
9
IN
IN
IN
IN
36
47
32
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
R47
10K
(30)
R36
IN
UCD9222_ENA1
(30)
IN
UCD9222_ENA2
(30)
10K
(30)
UCD9222_VIDA
UCD9222_VIDB
UCD9222_VIDC
UCD9222_VIDS
‐‐
205
178
154
133
115
100
86.6
75
64.9
56.2
48.7
42.2
‐‐
OPEN
11
10
9
8
7
6
5
4
3
2
1
0
SHORT
VCC3V3_AUX
U3
VCC3V3_AUX
D
UCD9222_PG1
(16)
(16)
(16)
(16)
DSP
UCD9222_GND
UCD9222
10 ohm
10 ohm
GND
R374
R363
EAP2
EAN2
R77
R59
10
10
10 ohm
CVDD
10
10
10 ohm
GND
EAp1
470 pF
EAn1
1K ohm
EAP2
EAN2
VCC1V0
VCC1V0
1K ohm
EAP1
EAN1
CVDD
EAP1
EAN1
D
C
EAp2
470 pF
EAn2
Series resistors on EA nets to be placed at the load for proper voltage feedback.
TI_UCD9222RGZR
<Characteristic>
R408
NL/10K
VCC12
Q8
2
31
FF-1A1
29
lsenes-1A
1uF
16V
3.92K
1%
10K
BOOT
SRE_MD
R432
VCC3V3_AUX
R129
37
ILIM
R122
8.06K
1%
RDLY 39
C75
0.1uF
16V
2
AVGG 40
VGG R131
A
ILIM
SW_1
SW_2
SW_3
SW_4
SW_5
SW_6
28 R150
5
R441
C429
0.1uF
16V
UCD9222_GND
2K
0
UCD9222_GND
C438
0.22uF
25V
SW_Shape
7
8
9
10
11
12
R462
2 C465
CSP
CSN
36 CSP
R123
2.49K 1%
35 CSN
R124
2.49K 1%
0.01uF 16V
VGG
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
PGND_6
PGND_7
PGND_8
3
VGG C416
R85
SRE_B
10K
0.2uH 24A
R456
267
1%
C365
CVDD
C105
470uF
4V
C104
470uF
4V
C409
47uF
6.3V
C410
47uF
6.3V
R457
1K
1%
FF-1A2
2
FLTRST
12
2.2uF 6.3V
R121
267
1%
C412
47uF
6.3V
C411
47uF
6.3V
C82
47uF
6.3V
C413
47uF
6.3V
R91
10K
UCD9222_GND
lsenes-2A 11
Current sense
monitor output
C70
1000pF
50V
UCD9222_GND
5
C46
4.7uF
16V
TP31
2
21
PWM
UCD74106
SRE
VIN
TMON
13
10
FLT
BST
FLTRST
SW
IMON
PGND
C385
22uF
16V
9222_TEMP2
Temperature
sense pin
C338
0.1uF
16V
1
6
7
VCC1V0
C348
0.22uF UCD9222_GND
25V
L1
0.47uH
C54
17.5A
470uF
4V
TP30
VCC1V0
C345
470uF
4V
C332
47uF
6.3V
C333
47uF
6.3V
R386
1K
1%
VGG
TI_UCD74106RGMT
<Characteristic>
1
C78
1uF
16V
TP-S50X2-SHORT
AGND
B
TP21
L2
4.7uF 16V
13
14
15
16
17
18
19
20
4
3
VCC3V3_AUX
AVGG
Thermal_PAD
Thermal_via1
Thermal_via2
Thermal_via3
Thermal_via4
Thermal_via5
Thermal_via6
Thermal_via7
Thermal_via8
Thermal_via9
Thermal_via10
Thermal_via11
Thermal_via12
Thermal_via13
Thermal_via14
Thermal_via15
Thermal_via16
Thermal_via17
Thermal_via18
Thermal_via19
Thermal_via20
Thermal_via21
PWM-2A
DSP Vcore @9.75A
1
TP35
2
21
1
A
TP-S50X2-SHORT
VGG_DIS
2
UCD9222_GND
UCD9222_GND
UCD9222_GND
Designed for TI by ADVANTECH
Title
TI_TROY(UCD74110)
<Characteristic>
Power ucd9222
UCD9222_GND
Size
C
Date:
5
MICROCHIP_MCP9700AT-E/LT
VCC12
RDLY
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
linMon
27
BP3
32
3
1
5
26
25
24
23
22
21
34
6
4
HS_SNS
FLT
UCD9222_GND
C387
VOUT
NC1
NC2
U4
SRE
IMON
30
MICROCHIP_MCP9700AT-E/LT
UCD9222_GND
VDD
TROY (UCD74110)
33
VDD
C134
0.1uF
16V
AGND
SRE_A
4
VCC3V3_AUX
BP3
10K
9222_TEMP1
8
R137
PWM
3
1
5
9
VCC3V3_AUX
38
VIN_6
VIN_5
VIN_4
VIN_3
VIN_2
VIN_1
PWM-1A
NC_3
NC_2
NC_1
B
VOUT
NC1
NC2
GND
GND
C484
0.1uF
16V
VCC12
U8
Q5
VDD
2
4
VCC3V3_AUX
C124
22uF
16V
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
33
of
36
5
4
3
2
1
VCC1V8_AUX
VCC1V2
1.2V @0.38A
3
R120
0
5%
R113
VCC3V3_AUX
C374
10uF
6.3V
8
VCC3V3_AUX
C404
0.1uF
16V
C106
10uF
6.3V
C94
0.1uF
16V
R139
10K
5
VIN
FB
VCC3V3_AUX
R147
28K
1%
R1
R148
56.2K
1%
R2
C116
10uF
6.3V
C117
0.1uF
16V
D
Vout=(R1+R2)/R2*1.204
1.805V =(28k+56.2k)/56.2k*1.205
8
VCC3V3_AUX
5
C49
0.1uF
16V
VIN
EN
VOUT
FB
1
R80
39.2K
1%
C64
0.1uF
16V
R1
0 VCC2P5_EN_C
R71
10K
VCC3V3_AUX
C146
0.1uF
16V
5
(30)
U5
4
FB
EN
VCC1V8
3
R183
28K
1%
R1
R184
56.2K
1%
R2
C497
10uF
6.3V
C498
0.1uF
16V
VCC1P8_EN1
R175
10K
R114
10K
5
VOUT
IN
VCC3V3_AUX
VCC
VIN
1
4
9
Vout=(R1+R2)/R2*1.204
2.50V =(39.2k+36.5k)/36.5k*1.204
1
2
3
TP25
2
6
7
R2
8
C140
10uF
6.3V
1K
[email protected]
Q4
TI_TPS73701DRBT
R81
36.5K
1%
NC1
NC2
NC3
R563
IN
C58
10uF
6.3V
GND
EPAD
VCC2P5_EN
C
VCC2V5
3
4
9
C55
10uF
6.3V
NC1
NC2
NC3
2
6
7
TP24
GND
EPAD
C
VCC1V8
2.5V @0.21A
R562 Q1
NL/1K TI_TPS73701DRBT
R111
VCC1V8_AUX
3
VCC3V3_AUX
VCC2V5
VCC2V5
1
R2
Vout=(R1+R2)/R2*1.204
1.204V = (0+10k)/10k*1.204
(30)
TP23
VOUT
EN
R1
10K
R105
10K
1%
1.8V_AUX @0.3A
2
6
7
VCC1V2
4
9
FB
EN
1
NC1
NC2
NC3
2
6
7
VOUT
4
9
D
5
C391
0.1uF
16V
NC1
NC2
NC3
C77
10uF
6.3V
VIN
GND
EPAD
8
VCC3V3_AUX
Q3
TI_TPS73701DRBT
TP22
GND
EPAD
Q2
TI_TPS73701DRBT
VCC2P5_PGOOD
GND
OUT
VCC2P5_PGOOD
Vout=(R1+R2)/R2*1.204
1.805V =(28k+56.2k)/56.2k*1.205
(30)
TI_SN74LVC1G07DBVR
B
B
VCC0V75
R213
VCC1V5
C171
10uF
6.3V
1K
VCC3V3_AUX
1%
C175
0.1uF
16V
R214
1K
1%
R230
10K
C176
0.01uF
16V
U24
TI_TPS51200DRCT
1
2
3
VCC0V75
C535
10uF
6.3V
C536
10uF
6.3V
C178
10uF
6.3V
4
5
VIN
PGOOD
VO
GND
PGND
VOSNS
EN
REFOUT
10
9
VCC0P75_PGOOD
OUT
VCC0P75_PGOOD
(30)
8
7
VCC0P75_EN
IN
VCC0P75_EN
(30)
6
A
EPAD
VIA1
VIA2
VIA3
VIA4
VIA5
TP26
VLDOIN
C185
0.1uF
16V
11
12
13
14
15
16
A
REFIN
C187
0.1uF
16V
R229
10K
Designed for TI by ADVANTECH
0.75V @0.25A
Title
Power_1.2V/1.8V/2.5V/0.75V
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
34
of
36
5
4
3
2
1
VCC3V3_AUX
Assume 90% Pe,
Iin = ( 3.3V * 2.58A ) / 90% / 12V = 788mA
VCC3V3_AUX
[email protected]
U13
TI_TPS54620RGY
56.2K 1%
D
1
2
3
4
5
6
7
B38
2A
120_100MHz
VCC12
C425
10uF
16V
C93
10uF
16V
VCC12
C110
0.1uF
16V
PWRGD
BOOT
PH2
PH1
EN
SS/TR
COMP
14
VCC3_AUX_PGOOD
VCC3_AUX_PGOOD
OUT
13
C137
0.1uF 16V
12
L5
3.3uH 6A
11
10 VCC3V3_AUX_EN_R R192
VCC3V3_AUX_EN
0
C512
9
100uF
8
6.3V
R182
1.69K
1%
15
C111
0.1uF
16V
RT/CLK
GND1
GND2
PVIN1
PVIN2
VIN
VSENSE
EPAD
R171
3.3V_AUX @2.57A
R178
10K
TP27
VCC3V3_AUX
R167
31.6K
1%
R1
VCC12
C142
0.01uF
16V
C127
8200pF
50V
Rrt=48000xFsw(kHz)^(‐0.997‐2)
=48000x840^(‐0.997‐2)
=~56.2 (k ohms)
D
(30)
R159
10K
1%
R2
R473
31.6K
1%
VCC3V3_AUX_EN
Vout=0.8 V*(R1/R2+1)
3.3=0.8 V*(10k/3.1k+1)
(Over all tolerance is 5% ,DC tolerance is 2.5% )
+++output capacitor Calculation+++
Cout=(2*delta(Iout))/(Fsw*delta(Vout))
Cout=(2*3/(840kHz*0.0825)
Cout=~87uF
C
Reference Capacitor=100uF
R197
10K
1%
(KIND=0.3)
+++Inductor Calculation+++
L = (Vin ‐ Vout)/(Iout * Kind) * (Vout/(Vin * Fsw)
L = ((12 ‐ 3.3)/(3A * 0.3) * (3.3 / (12 * 840kHz))
L = 9.67 * 0.33u
L = ~3.2 uH
Reference Inductor 3.3uH
C
VCC5
Assume 80% Pe,
Iin = ( 5V * 1A ) / 80% / 12V = 520mA
5V @1A
[email protected]
TP28
2
L4
C121
0.1uF
16V
C88
10uF
16V
B
C102
0.01uF
16V
(30)
VCC_5V_EN
IN
U11
1
2
3
4
120_100MHz
2A
R151
NL/33K
R136
EN Pin:2.79V
8
7
6
5
BOOT
PH
VIN
GND
EN
COMP
SS
VSENSE
C466
1200pF
50V
TI_TPS54231D
R141
10K
C101
0.01uF
16V
R165
VCC5
1K
VCC
5
Cout=1/( 2 * 3.14 * 5 * 25K)
Cout=1.3 uf
Reference Capacitor=100uF
R176
10K
4
GND
VCC5_PGOOD
OUT
VCC5_PGOOD
R475
10K
1%
R1
C487
56pF
50V
B
R472
1.87K
1%
VCC3V3_AUX
U9
VCC5
C513
100uF
6.3V
R468
22.6K
1%
+++output capacitor Calculation+++
1
2
3
2.8A
0
Vout=0.8 V*(R1/R2+1)
5=0.8 V*(10k/1.87k+1)
A
D3
B340A
3A
1
B7
VCC12
22uH
R2
(KIND=0.3)
+++Inductor Calculation+++
L = ((Vin(max) - Vout)/Iout * Kind)) * (Vout/(Vin(max) * Fsw))
L = ((12.6 - 5)/1 * Kind) * (5 / (12.7 * 570K))
L = ((7.6/ 0.3) * (5 / (7239K))
L = (25.3) * (0.69M)
L = 17.5uH
Reference Inductor 22uH
A
(30)
TI_SN74LVC1G07DBVR
Designed for TI by ADVANTECH
Title
Power_VCC5 / VCC3V3_AUX
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
35
of
36
5
4
3
2
1
VCC1V5
D
D
VCC3V3_AUX
Assume 90% Pe,
Iin = ( 1.5V * 2.12A ) / 90% / 12V = 295mA
R204
10K
1
2
3
4
5
6
7
120_100MHz
2A
C147
0.1uF
16V
C
C155
10uF
16V
C154
10uF
16V
U14
TI_TPS54620RGY
VCC12
C143
0.1uF
16V
RT/CLK
GND1
GND2
PVIN1
PVIN2
VIN
VSENSE
EPAD
B8
VCC12
56.2K 1%
PWRGD
BOOT
PH2
PH1
EN
SS/TR
COMP
14
13
12
11
10
9
8
C507
VCC1P5_PGOOD
0.1uF 16V
L3
3.3uH
VCC1P5_EN
R474
1.69K
1%
15
[email protected]
R205
1.5V @1.67A
OUT
VCC1P5_PGOOD
(30)
TP29
6A
VCC1V5
C504
100uF
6.3V
C494
100uF
6.3V
R471
9.09K
1%
C
R1
C139
0.01uF
16V
C501
8200pF
50V
IN
R185
10K
1%
R2
VCC1P5_EN
(30)
R476
10K
Vout=0.8 V*(R1/R2+1)
1.52=0.8 V*(9.09k/10k+1)
(Over all tolerance is 5% ,DC tolerance is 2.5%)
+++output capacitor Calculation+++
Cout=(2*delta(Iout))/(Fsw*delta(Vout))
Cout=(2*2A)/(840kHz*0.0375)
Cout= 4/31.5k
Cout=~127uF
Reference Capacitor=200uF
B
(KIND=0.3)
+++Inductor Calculation+++
L = (Vin ‐ Vout)/(Iout * Kind) * Vout/(Vin * Fsw)
L = (12 ‐ 1.5)/(2A * 0.3) * 1.5 / (12 * 840kHz)
L = (17.5) * (0.15u)
L = ~2.63uH
Reference Inductor 3.3uH
B
A
A
Designed for TI by ADVANTECH
Title
Power VCC1V5
Size
C
Date:
5
4
3
2
Document Number
Rev
A102-1
DSPM-8302E
Wednesday, June 01, 2011
Sheet
1
36
of
36