The following document contains information on Cypress products. FUJITSU MICROELECTRONICS DATA SHEET DS07-16801-3E 32-bit Microcontroller CMOS FR60Lite MB91270 Series MB91F273(S)/MB91V280 ■ DESCRIPTION The MB91270 series is single chip microcontroller that builds various I/O resources and the bus control mechanisms into by using 32-bit efficient RISC CPU for the built-in control being demanded for CPU processing high performance/high-speed. RAM (for reading data) is included in order to support CPU to access to the vast address space and to speed up the execution of CPU instructions. This series is optimized to the embedded applications; automotive applications such as car audio or car air-conditioning equipment that require high-performance CPU processing power. It is designed based on the FR-family* CPU. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited. ■ FEATURES • FR CPU characteristics • 32-bit RISC, load/store architecture with a five-stage pipeline • Maximum operating frequency: 32 MHz (using the PLL at an oscillation frequency of 4 MHz) • 16-bit fixed length instructions (basic instructions), 1 instruction per cycle • Function entry/exit instructions, multiple - register load/store instructions : Instructions adapted for high - level languages • Memory-to-memory transfer, bit manipulation, barrel shift instruction etc.: Instruction optimized for embedded applications (Continued) For the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ Copyright©2005-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2009.3 MB91270 Series • Register interlock functions: Easier assembler coding enabled • Built-in multiplier supported at the instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles • Interrupt (PC, PS save): 6 cycles, 16 priority levels • Harvard architecture allowing program access and data access to be executed simultaneously • Instruction compatible with FR family • External bus interface • Maximum operating frequency: 16 MHz • Can output full 24-bit address range (16 Mbyte space) • 8,16-bit data output • Unused data/address pin can be used as general-purpose I/O ports. • Capable of chip select output for completely independent four areas settable in 64 Kbytes minimum. • Supports the following memory interfaces SRAM, ROM/Flash • Basic bus cycle: 2 cycles • Programmable automatic wait cycle generation function capable of inserting wait cycles for each area • RDY input for external wait cycles • Built-in memory MB91V280 MB91F273 (S) ROM/Flash External SRAM Flash 512 Kbytes F-bus RAM 48 Kbytes 24 Kbytes The peripheral circuits are described below. Refer to “■PRODUCT LINEUP” for the number of available channels on each model. • DMAC (DMA Controller) • Capable of simultaneous operation of up to five channels • Two forwarding factors (internal peripheral/software) • Bit search module (for REALOS) Search for the first position of the bit “1”/ “0” changed in one word from the MSB • LIN UARTs (LIN-UART) : Up to 7 channels • Asynchronous (start-stop synchronous) communications, clock synchronous communications • Synch-Break detection • Built-in baud rate generator on each channel • Supports SPI (mode 2: Clock synchronous communication mode) • CAN CONTROLLERS : 3 channels (Max) • High-speed transfer : 1 Mbps • 32 message buffer (128 message buffer on the MB91V280) (Continued) 2 DS07-16801-3E MB91270 Series • Various timers • 16-bit reload timer : 3 channels (including one channel for REALOS) The internal clock can be divided by 2, 8, or 32 • 16-bit free-running timer: 4 channels Output compare module: 8 channels Input capture module: 8 channels • 8/16-bit PPG timer: 8-bit x 16 channels or 16-bit x 8 channels • Interrupt controller • Interrupt from internal peripheral • Software-selectable priority level (16 levels) • D/A converter : 2 channels 8-bit or 10-bit resolution, R-2R type • A/D converter: 24 channels (MB91V280 has an additional module with eight more channels) • 10-bit resolution • Successive approximation conversion type Conversion time : 3 μs • Conversion mode (single conversion mode, continuous conversion mode) • Activation source (software, external trigger, peripheral interrupt) • Other interval timer/counter • 8/16-bit up down counter : 8 bits × 4 channels or 16 bits × 2 channels • 16-bit timebase timer / watchdog timer • I2C bus interface (400 kbps): 3 channels • Master/slave sending and receiving • Arbitration and clock synchronization • Hardware watchdog Interval time: 569 ms (Min), 771 ms (Max) (Use of self-oscillation circuit with timing (100 kHz) ) • I/O port • Pull-up/pull-down can be controlled independently for each pin. • The input level for each pin can be set to either CMOS Schmitt trigger levels or CMOS automotive Schmitt trigger levels. • The pin level can be read directly. • Max 82 ports • Other features • Internal oscillator circuit as clock source, allowing PLL multiplication to be selected • INIT is prepared as a reset pin. • Watchdog timer reset, software reset • Available low-power consumption modes are stop mode, sleep mode, and real time clock mode. Supports low-power consumption operation with CPU operating at 32 kHz (“s” without only product). • Gear function • Built-in timebase timer • Wild register (Continued) DS07-16801-3E 3 MB91270 Series (Continued) • Output clock (clock monitor) • Clock Modulator • Package PGA-401, LQFP-100 • CMOS technology (0.35 μm) • Power supply voltage: 3.5 V to 5.5 V The 3.3 V supply to internal circuits is generated by an internal step-down circuit. 4 DS07-16801-3E MB91270 Series ■ PRODUCT LINEUP Kind Parameter Package Built-in ROM/ Flash RAM External bus External interrupt MB91F273 (S) MB91V280 LQFP-100 PGA-401 Flash 512 Kbytes External SRAM 24 Kbytes 48 Kbytes Address : 24 bits Data : 16 bits (Multiplex only) Address : 24 bits Data : 16 bits 16 channels 40 channels DMAC (DMA Controller) 5 channels Clock modulator Yes Clock supervisor No Yes Clock monitor 32 kHz sub-clock Yes Option (Models without S-suffix part number only) Real time clock CAN controllers Yes Yes 1 channel (32 message buffer) 3 channels (128 message buffer) LIN UARTs (LIN-UART) 7 channels I2C interface 3 channels 16-bit reload timer 3 channels 8/16-bit up down counter 2 channels 16-bit free-run timer 4 channels Input capture 8 channels Output compare 8 channels 16-bit × 8 channels 8-bit × 16 channels 8/16-bit PPG 24 channels 24 channels + 8 channels No 2 channels Pin pull-up/down Refer to “■ PIN FUNCTION” All pins Input level selector Refer to “■ PIN FUNCTION” All pins Debugging support Wild register DSU4 10-bit A/D converter 8/10-bit D/A converter DS07-16801-3E 5 MB91270 Series ■ PIN ASSIGNMENT 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P25/A21/IN1 P24/A20/IN0 P23/A19/PPGF P22/A18/PPGD P21/A17/PPGB P20/A16/PPG9 P17/AD15/SCK4 P16/AD14/SOT4 P15/AD13/SIN4 X0 X1 VSS VCC P14/AD12/SCK3 P13/AD11/SOT3 P12/AD10/SIN3/INT11R P11/AD09/TOT1 P10/AD08/TIN1 P07/AD07/INT15 P06/AD06/INT14 P05/AD05/SCK6/INT13 P04/AD04/SOT6/INT12 P03/AD03/SIN6/INT11 P02/AD02/SCK5/INT10 P01/AD01/SOT5/INT9 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP-100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P00/AD00/SIN5/INT8 PA1/TX0 PA0/RX0/INT8R P97/OUT3 P96/OUT2/ZIN0 P95/OUT1/BIN0 P94/OUT0/AIN0 P93/PPG7/ZIN3/CS3 P92/PPG5/BIN3/CS2 P91/PPG3/AIN3/CS1 P90/PPG1/CS0 VSS VCC P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/TOT2/SOT0 P82/TIN2/SIN0/INT14R P81/TOT0/INT13R/CKOT P80/TIN0/INT12R/ADTG P77/AN23/INT7/SCL2 P76/AN22/INT6/SDA2 INIT MD0 P54/AN12/AIN1 P55/AN13/ZIN1 P56/AN14/DAO0 P57/AN15/DAO1 AVCC AVRH AVRL AVSS P60/AN0/PPG0 P61/AN1/PPG2 P62/AN2/PPG4 P63/AN3/PPG6 P64/AN4/PPG8 P65/AN5/PPGA P66/AN6/PPGC P67/AN7/PPGE VSS P70/AN16/INT0 P71/AN17/INT1 P72/AN18/INT2 P73/AN19/INT3 P74/AN20/INT4 P75/AN21/INT5 MD2 MD1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P26/A22/IN2 P27/A23/IN3 P30/AS/IN4 P31/RD/IN5 P32/WR0/RX2/INT10R P33/WR1/TX2 P34/BRQ/OUT4 P35/BGRNT/OUT5 P36/RDY/OUT6 P37/SYSCLK/OUT7 P40/(X0A) P41/(X1A) VCC VSS C P42/IN6/RX1/INT9R P43/IN7/TX1 P44/SDA0/FRCK0 P45/AIN2/SCL0/FRCK1 P46/BIN2/SDA1 P47/ZIN2/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/BIN1 (FPT-100P-M05) 6 DS07-16801-3E MB91270 Series ■ PIN FUNCTION Pin No. Pin name Function name I/O circuit type* 90 X1 X1 OB Oscillator output pin 91 X0 X0 OA Oscillator input pin 52 INIT INIT N Reset input pin (“L” active) J Operation mode select input pins. Connect to VCC or VSS directly. 49 to 51 MD2 to MD0 MD2 to MD0 Function Port 0 General-purpose I/O port. This function is enabled in single-chip mode. P00 75 76 P00/AD00/ SIN5/INT8 P01/AD01/ SOT5/INT9 AD00 T INT8 External interrupt request 8 input pin SIN5 Serial data input pin for LIN-UART5 P01 General-purpose I/O port. This function is enabled in single-chip mode. AD01 T P02/AD02/ SCK5/INT10 External interrupt request 9 input pin SOT5 Serial data output pin for LIN-UART5 General-purpose I/O port. This function is enabled in single-chip mode. AD02 T 79 P03/AD03/ SIN6/INT11 P04/AD04/ SOT6/INT12 External address/data bus I/O pin bit 2 This function is enabled when the external bus is enabled. INT10 External interrupt request 10 input pin SCK5 Clock I/O pin for LIN-UART5 General-purpose I/O port. This function is enabled in single-chip mode. P03 78 External address/data bus I/O pin bit 1 This function is enabled when the external bus is enabled. INT9 P02 77 External address/data bus I/O pin bit 0 This function is enabled when the external bus is enabled. AD03 T External address/data bus I/O pin bit 3 This function is enabled when the external bus is enabled. INT11 External interrupt request 11 input pin SIN6 Serial data input pin for LIN-UART6 P04 General-purpose I/O port. This function is enabled in single-chip mode. AD04 T External address/data bus I/O pin bit 4 This function is enabled when the external bus is enabled. INT12 External interrupt request 12 input pin SOT6 Serial data output pin for LIN-UART6 * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) DS07-16801-3E 7 MB91270 Series Pin No. Pin name Function name I/O circuit type* General-purpose I/O port. This function is enabled in single-chip mode. P05 80 P05/AD05/ SCK6/INT13 AD05 T P06/AD06/ INT14 External interrupt request 13 input pin SCK6 Clock I/O pin for LIN-UART6 General-purpose I/O port. This function is enabled in single-chip mode. AD06 T INT14 P07/AD07/ INT15 AD07 External address/data bus I/O pin bit 6 This function is enabled when the external bus is enabled. External interrupt request 14 input pin General-purpose I/O port. This function is enabled in single-chip mode. P07 82 External address/data bus I/O pin bit 5 This function is enabled when the external bus is enabled. INT13 P06 81 Function T INT15 External address/data bus I/O pin bit 7 This function is enabled when the external bus is enabled. External interrupt request 15 input pin Port 1 General-purpose I/O port. This function is enabled in single-chip mode. P10 83 84 P10/AD08/ TIN1 P11/AD09/ TOT1 AD08 T TIN1 Event input pin for reload timer 1 P11 General-purpose I/O port. This function is enabled in single-chip mode. AD09 T TOT1 P12/AD10/ SIN3/ INT11R AD10 General-purpose I/O port. This function is enabled in single-chip mode. T SIN3 External interrupt request 11 input pin (Set by EISSR) General-purpose I/O port. This function is enabled in single-chip mode. P13 P13/AD11/ SOT3 AD11 SOT3 External address/data bus I/O pin bit 10 This function is enabled when the external bus is enabled. Serial data input pin for LIN-UART3 INT11R 86 External address/data bus I/O pin bit 9 This function is enabled when the external bus is enabled. Output pin for reload timer 1 P12 85 External address/data bus I/O pin bit 8 This function is enabled when the external bus is enabled. T External address/data bus I/O pin bit 11 This function is enabled when the external bus is enabled. Serial data output pin for LIN-UART3 * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) 8 DS07-16801-3E MB91270 Series Pin No. Pin name Function name I/O circuit type* General-purpose I/O port. This function is enabled in single-chip mode. P14 87 P14/AD12/ SCK3 AD12 T SCK3 93 P15/AD13/ SIN4 P16/AD14/ SOT4 AD13 General-purpose I/O port. This function is enabled in single-chip mode. T Serial data input pin for LIN-UART4 P16 General-purpose I/O port. This function is enabled in single-chip mode. AD14 T AD15 External address/data bus I/O pin bit 14 This function is enabled when the external bus is enabled. Serial data output pin for LIN-UART4 General-purpose I/O port. This function is enabled in single-chip mode. P17 P17/AD15/ SCK4 External address/data bus I/O pin bit 13 This function is enabled when the external bus is enabled. SIN4 SOT4 94 External address/data bus I/O pin bit 12 This function is enabled when the external bus is enabled. Clock I/O pin for LIN-UART3 P15 92 Function T SCK4 External address/data bus I/O pin bit 15 This function is enabled when the external bus is enabled. Clock I/O pin for LIN-UART4 Port 2 General-purpose I/O port. This function is enabled in single-chip mode. P20 95 P20/A16/ PPG9 A16 A PPG9 Output pin for PPG9 General-purpose I/O port. This function is enabled in single-chip mode. P21 96 P21/A17/ PPGB A17 A PPGB P22/A18/ PPGD A18 PPGD External address bus output pin bit 17 This function is enabled when the external bus is enabled. Output pin for PPGB General-purpose I/O port. This function is enabled in single-chip mode. P22 97 External address bus output pin bit 16 This function is enabled when the external bus is enabled. A External address bus output pin bit 18 This function is enabled when the external bus is enabled. Output pin for PPGD * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) DS07-16801-3E 9 MB91270 Series Pin No. Pin name Function name I/O circuit type* General-purpose I/O port. This function is enabled in single-chip mode. P23 98 P23/A19/ PPGF A19 A PPGF P24/A20/IN0 to A20 to A23 P27/A23/IN3 External address bus output pin bit 19 This function is enabled when the external bus is enabled. Output pin for PPGF General-purpose I/O port. This function is enabled in single-chip mode. P24 to P27 99, 100, 1, 2 Function A IN0 to IN3 External address bus output pins bits 20 to 23 This function is enabled when the external bus is enabled. Data sample input pins for input capture ICU0 to ICU3 Port 3 General-purpose I/O port. This function is enabled in single-chip mode. P30 3 4 5 P30/AS/IN4 P31/RD/IN5 P32/WR0/ RX2/ INT10R AS A IN4 Data sample input pin for input capture ICU4 P31 General-purpose I/O port. This function is enabled in single-chip mode. RD A Data sample input pin for input capture ICU5 P32 General-purpose I/O port. This function is enabled in single-chip mode. WR0 External data bus write strobe output pin. Enabled when the external bus is enabled. WR0 is used as the data write strobe for 8-bit access and as the upper 8 bits of the data in 16-bit access. A CAN2 RX input pin (MB91V280 only) INT10R External interrupt request 10 input pin (Set by EISSR) General-purpose I/O port. This function is enabled in single-chip mode. P33 P33/WR1/ TX2 External read strobe output pin This function is enabled when the external bus is enabled. IN5 RX2 6 External address strobe output pin This function is enabled when the external bus is enabled. WR1 TX2 A Write strobe output pin for lower 8 bits in external data bus Enabled when the external bus is enabled and external bus 16-bit mode is selected. CAN2 TX output pin (MB91V280 only) * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) 10 DS07-16801-3E MB91270 Series Pin No. Pin name Function name I/O circuit type* General-purpose I/O port. This function is enabled in single-chip mode. P34 7 P34/BRQ/ OUT4 BRQ T (A) OUT4 P35/ BGRNT/ OUT5 BGRNT General-purpose I/O port. This function is enabled in single-chip mode. A OUT5 P36/RDY/ OUT6 RDY General-purpose I/O port. This function is enabled in single-chip mode. T OUT6 P37/ SYSCLK/ OUT7 SYSCLK External ready input pin Enabled when the external bus and the bus request functions are enabled. Waveform output pin for output compare OCU6. General-purpose I/O port. This function is enabled in single-chip mode. P37 10 External bus acknowledge output pin Enabled when the external bus and the bus request functions are enabled. (MB91V280 only) Waveform output pin for output compare OCU5. P36 9 External bus request input pin Enabled when the external bus and the bus request functions are enabled. (MB91V280 only) Waveform output pin for output compare OCU4. P35 8 Function A OUT7 External clock output pin This function is enabled when the external bus is enabled. Waveform output pin for output compare OCU7. Port 4 11, 12 P40/ (X0A) , P41/ (X1A) P40, P41 A X0A, X1A WA WB P42 16 P42/IN6/ RX1/INT9R IN6 RX1 A 18 P44/SDA0/ FRCK0 IN7 Data sample input pin for input capture ICU6 CAN1 RX input pin (MB91V280 only) External interrupt request 9 input pin (Set by EISSR) P43 17 sub-clock oscillator input pin (without S-suffix models) General-purpose I/O port INT9R P43/IN7/ TX1 General-purpose I/O port (S-suffix models) General-purpose I/O port A Data sample input pin for input capture ICU7 TX1 CAN1 TX output pin (MB91V280 only) P44 General-purpose I/O port SDA0 FRCK0 C Serial data I/O pin for I2C0 16-bit input/output timer 0 input pin * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) DS07-16801-3E 11 MB91270 Series Pin No. Pin name 19 P45/AIN2/ SCL0/ FRCK1 Function name I/O circuit type* P45 20 21 P46/BIN2/ SDA1 P47/ZIN2/ SCL1 SCL0 FRCK1 Function General-purpose I/O port C Serial clock I/O pin for I2C0 16-bit input/output timer 1 input pin AIN2 8/16-bit up-count input pin for up down counter 2/3 P46 General-purpose I/O port SDA1 C Serial clock I/O pin for I2C1 BIN2 8/16-bit down-count input pin for up down counter 2/3 P47 General-purpose I/O port SCL1 C ZIN2 Serial clock I/O pin for I2C1 8/16-bit reset input pin for up down counter 2/3 Port 5 P50 22 23 P50/AN8/ SIN2 P51/AN9/ SOT2 AN8 General-purpose I/O port D SIN2 Serial data input pin for LIN-UART2 P51 General-purpose I/O port AN9 D SOT2 24 AN10 General-purpose I/O port D SCK2 25 26 27 28 P54/AN12/ AIN1 P55/AN13/ ZIN1 P56/AN14/ DAO0 AN11 General-purpose I/O port D 8-bit down-count input pin for 16-bit up down counter 1 P54 General-purpose I/O port AN12 D Analog input pin of A/D converter AIN1 8-bit up-count input pin for 16-bit up down counter 1 P55 General-purpose I/O port AN13 D Analog input pin of A/D converter ZIN1 8-bit reset input pin for 16-bit up down counter 1 P56 General-purpose I/O port AN14 E AN15 DAO1 Analog input pin of A/D converter Analog output pin 0 for D/A converter (MB91V280 only) P57 29 Analog input pin of A/D converter BIN1 DAO0 P57/AN15/ DAO1 Analog input pin of A/D converter Clock I/O pin for LIN-UART2 P53 P53/AN11/ BIN1 Analog input pin of A/D converter Serial data output pin for LIN-UART2 P52 P52/AN10/ SCK2 Analog input pin of A/D converter General-purpose I/O port E Analog input pin of A/D converter Analog output pin 1 for D/A converter (MB91V280 only) * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) 12 DS07-16801-3E MB91270 Series Pin No. Pin name Function name I/O circuit type* Function Port 6 34 to 41 P60/AN0/ PPG0 to P67/AN7/ PPGE P60 to P67 General-purpose I/O port AN0 to AN7 Analog input pins of A/D converter PPG0 PPG2 PPG4 PPG6 PPG8 PPGA PPGC PPGE D Output pins for PPG Port 7 43 to 48 P70/AN16/ INT0 to P75/AN21/ INT5 P70 to P75 AN16 to AN21 General-purpose I/O port D INT0 to INT5 External interrupt request 0 to 5 input pin P76 53 P76/AN22/ INT6/SDA2 AN22 INT6 General-purpose I/O port CA P77 P77/AN23/ INT7/SCL2 AN23 INT7 Analog input pin of A/D converter External interrupt request 6 input pin Serial clock I/O pin for I2C2 SDA2 54 Analog input pins of A/D converter General-purpose I/O port CA Analog input pin of A/D converter External interrupt request 7 input pin Serial clock I/O pin for I2C2 SCL2 Port 8 P80 55 P80/TIN0/ INT12R/ ADTG TIN0 ADTG General-purpose I/O port A INT12R 56 TOT0 CKOT General-purpose I/O port A INT13R P82/TIN2/ SIN0/INT14R SIN0 TIN2 INT14R Output pin for reload timer 0 Output pin for clock monitor External interrupt request 13 input pin (Set by EISSR) P82 57 Trigger input pin for A/D converter External interrupt request 12 input pin (Set by EISSR) P81 P81/TOT0/ INT13R/ CKOT Event input pin for reload timer 0 General-purpose I/O port A Serial data input pin for LIN-UART0 Event input pin for reload timer 2 External interrupt request 14 input pin (Set by EISSR) * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) DS07-16801-3E 13 MB91270 Series Pin No. Pin name 58 P83/TOT2/ SOT0 Function name I/O circuit type* P83 SOT0 General-purpose I/O port A TOT2 59 SCK0 General-purpose I/O port A INT15R 60 P85/SIN1 61 P86/SOT1 62 P87/SCK1 P85 SIN1 P86 SOT1 P87 SCK1 Serial data output pin for LIN-UART0 Output pin for reload timer 2 P84 P84/SCK0/ INT15R Function Clock I/O pin for LIN-UART0 External interrupt request 15 input pin (Set by EISSR) A A A General-purpose I/O port Serial data input pin for LIN-UART1 General-purpose I/O port Serial data output pin for LIN-UART1 General-purpose I/O port Clock I/O pin for LIN-UART1 Port 9 P90 65 P90/PPG1/ CS0 CS0 General-purpose I/O port A PPG1 Output pin for PPG1 P91 66 67 68 69 P91/PPG3/ AIN3/CS1 P92/PPG5/ BIN3/CS2 P93/PPG7/ ZIN3/CS3 P94/OUT0/ AIN0 CS1 External chip select 0 This function is enabled when the external bus is enabled. General-purpose I/O port A External chip select 1 This function is enabled when the external bus is enabled. PPG3 Output pin for PPG3 AIN3 8-bit up-count input pin for up down counter 3 P92 General-purpose I/O port CS2 External chip select 2 This function is enabled when the external bus is enabled. A PPG5 Output pin for PPG5 BIN3 8-bit down-count input pin for up down counter 3 P93 General-purpose I/O port CS3 A External chip select 3 This function is enabled when the external bus is enabled. PPG7 Output pin for PPG7 ZIN3 8-bit reset input pin for up down counter 3 P94 General-purpose I/O port OUT0 AIN0 A Waveform output pin for output compare OCU0 16/8-bit up-count input pin for up down counter 0/1 * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) 14 DS07-16801-3E MB91270 Series Pin No. Pin name 70 P95/OUT1/ BIN0 Function name I/O circuit type* P95 71 P96/OUT2/ ZIN0 OUT1 General-purpose I/O port A P97/OUT3 Waveform output pin for output compare OCU1 BIN0 8/16-bit down-count input pin for up down counter 0/1 P96 General-purpose I/O port OUT2 A ZIN0 72 Function P97 OUT3 Waveform output pin for output compare OCU2 8/16-bit reset input pin for up down counter 0/1 A General-purpose I/O port Waveform output pin for output compare OCU3 Port A PA0 73 PA0/RX0/ INT8R RX0 General-purpose I/O port A INT8R 74 PA1/TX0 PA1 TX0 RX input pin for CAN0 External interrupt request 8 input pin (Set by EISSR) A General-purpose I/O port TX output pin for CAN0 Port B (MB91V280 only) PB0 ⎯ PB0 INT8-2 General-purpose I/O port A SIN5-2 Serial data input pin for LIN-UART5 (Set by PFRB) PB1 ⎯ PB1 INT9-2 General-purpose I/O port A SOT5-2 PB2 INT10-2 General-purpose I/O port A SCK5-2 PB3 INT11-2 General-purpose I/O port A SIN6-2 PB4 INT12-2 General-purpose I/O port A SOT6-2 PB5 INT13-2 SCK6-2 External interrupt request 12 input pin (Set by EPFRB) Serial data output pin for LIN-UART6 PB5 ⎯ External interrupt request 11 input pin (Set by EPFEB) Serial data input pin for LIN-UART6 (Set by PFRB) PB4 ⎯ External interrupt request 10 input pin (Set by EPFRB) Clock I/O pin for LIN-UART5 (set by PFRB) PB3 ⎯ External interrupt request 9 input pin (Set by EPFRB) Serial data output pin for LIN-UART5 PB2 ⎯ External interrupt request 8 input pin (Set by EPFRB) General-purpose I/O port A External interrupt request 13 input pin (Set by EPFRB) Clock I/O pin for LIN-UART6 (set by PFRB) Port C (MB91V280 only) * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) DS07-16801-3E 15 MB91270 Series Pin No. Pin name Function name I/O circuit type* PC0 ⎯ PC0 OUT4-2 General-purpose I/O port A INT0R PC1 OUT5-2 General-purpose I/O port A INT1R PC2 SIN3-2 General-purpose I/O port A INT2R PC3 SOT3-2 General-purpose I/O port A INT3R PC4 SCK3-2 General-purpose I/O port A INT4R PC5 SIN4-2 General-purpose I/O port A INT5R PC6 SOT4-2 General-purpose I/O port A INT6R PC7 SCK4-2 Serial data output pin for LIN-UART4 External interrupt request 6 input pin (Set by EISSR) PC7 ⎯ Serial data input pin for LIN-UART4 (Set by PFRC) External interrupt request 5 input pin (Set by EISSR) PC6 ⎯ Clock I/O pin for LIN-UART3 (set by PFRC) External interrupt request 4 input pin (Set by EISSR) PC5 ⎯ Serial data output pin for LIN-UART3 External interrupt request 3 input pin (Set by EISSR) PC4 ⎯ Serial data input pin for LIN-UART3 (Set by PFRC) External interrupt request 2 input pin (Set by EISSR) PC3 ⎯ Output pin for output compare 5 External interrupt request 1 input pin (Set by EISSR) PC2 ⎯ Output pin for output compare 4 External interrupt request 0 input pin (Set by EISSR) PC1 ⎯ Function General-purpose I/O port A INT7R Clock I/O pin for LIN-UART4 (set by PFRC) External interrupt request 7 input pin (Set by EISSR) Port D (MB91V280 only) PD0 ⎯ PD0 INT16 General-purpose I/O port A PPG9-2 Output pin for PPG9 (8) PD1 ⎯ ⎯ PD1 PD2 INT17 External interrupt request 16 input pin General-purpose I/O port A External interrupt request 17 input pin PPGB-2 Output pin for PPGB (A) PD2 General-purpose I/O port INT18 PPGD-2 A External interrupt request 18 input pin Output pin for PPGD (C) * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) 16 DS07-16801-3E MB91270 Series Pin No. Pin name Function name I/O circuit type* PD3 ⎯ ⎯ ⎯ ⎯ ⎯ PD3 PD4 PD5 PD6 PD7 INT19 Function General-purpose I/O port A External interrupt request 19 input pin PPGF-2 Output pin for PPGF (E) PD4 General-purpose I/O port INT20 A External interrupt request 20 input pin IN0-2 Input pin for input capture ICU0 (set by PFRD) PD5 General-purpose I/O port INT21 A External interrupt request 21 input pin IN1-2 Input pin for input capture ICU1 (set by PFRD) PD6 General-purpose I/O port INT22 A External interrupt request 22 input pin IN2-2 Input pin for input capture ICU2 (set by PFRD) PD7 General-purpose I/O port INT23 A IN3-2 External interrupt request 23 input pin Input pin for input capture ICU3 (set by PFRD) Port E (MB91V280 only) PE0 ⎯ PE0 A00 General-purpose I/O port A INT24 External interrupt request 24 input pin PE1 ⎯ PE1 A01 General-purpose I/O port A INT25 PE2 A02 General-purpose I/O port A INT26 PE3 A03 General-purpose I/O port A INT27 PE4 A04 INT28 External address bus output pin bit 3 This function is enabled when the external bus is enabled. External interrupt request 27 input pin PE4 ⎯ External address bus output pin bit 2 This function is enabled when the external bus is enabled. External interrupt request 26 input pin PE3 ⎯ External address bus output pin bit 1 This function is enabled when the external bus is enabled. External interrupt request 25 input pin PE2 ⎯ External address bus output pin bit 0 This function is enabled when the external bus is enabled. General-purpose I/O port A External address bus output pin bit 4 This function is enabled when the external bus is enabled. External interrupt request 28 input pin * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) DS07-16801-3E 17 MB91270 Series Pin No. Pin name Function name I/O circuit type* PE5 ⎯ PE5 A05 General-purpose I/O port A INT29 PE6 A06 General-purpose I/O port A INT30 PE7 A07 External address bus output pin bit 6 This function is enabled when the external bus is enabled. External interrupt request 30 input pin PE7 ⎯ External address bus output pin bit 5 This function is enabled when the external bus is enabled. External interrupt request 29 input pin PE6 ⎯ Function General-purpose I/O port A INT31 External address bus output pin bit 7 This function is enabled when the external bus is enabled. External interrupt request 31 input pin Port F (MB91V280 only) PF0 ⎯ PF0 A08 General-purpose I/O port A INT32 External interrupt request 32 input pin PF1 ⎯ PF1 A09 General-purpose I/O port A INT33 PF2 A10 General-purpose I/O port A INT34 PF3 A11 General-purpose I/O port A INT35 PF4 A12 General-purpose I/O port A INT36 PF5 A13 INT37 External address bus output pin bit 12 This function is enabled when the external bus is enabled. External interrupt request 36 input pin PF5 ⎯ External address bus output pin bit 11 This function is enabled when the external bus is enabled. External interrupt request 35 input pin PF4 ⎯ External address bus output pin bit 10 This function is enabled when the external bus is enabled. External interrupt request 34 input pin PF3 ⎯ External address bus output pin bit 9 This function is enabled when the external bus is enabled. External interrupt request 33 input pin PF2 ⎯ External address bus output pin bit 8 This function is enabled when the external bus is enabled. General-purpose I/O port A External address bus output pin bit 13 This function is enabled when the external bus is enabled. External interrupt request 37 input pin * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. (Continued) 18 DS07-16801-3E MB91270 Series (Continued) Pin No. Pin name Function name I/O circuit type* PF6 ⎯ PF6 A14 General-purpose I/O port A INT38 PF7 A15 External address bus output pin bit 14 This function is enabled when the external bus is enabled. External interrupt request 38 input pin PF7 ⎯ Function General-purpose I/O port A INT39 External address bus output pin bit 15 This function is enabled when the external bus is enabled. External interrupt request 39 input pin Port G (MB91V280 only) ⎯ PG0 ⎯ PG1 ⎯ PG2 ⎯ PG3 ⎯ PG4 ⎯ PG5 ⎯ PG6 ⎯ PG7 PG0 AN24 PG1 AN25 PG2 AN26 PG3 AN27 PG4 AN28 PG5 AN29 PG6 AN30 PG7 AN31 D D D D D D D D General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter General-purpose I/O port Analog input pin of A/D converter Power supply pin 13, 63, 88 VCC ⎯ ⎯ Power supply (5 V) input pin 14, 42, 64, 89 VSS ⎯ ⎯ Power supply (0 V) input pin 15 C ⎯ ⎯ Power stabilization capacitance pin 30 AVCC ⎯ ⎯ Analog power supply input pin 31 AVRH ⎯ ⎯ Reference voltage input pin for the A/D converter Ensure that a voltage greater than AVRH is applied to AVCC when turning this power supply on or off. 32 AVRL ⎯ ⎯ Low reference voltage input pin for the A/D converter 33 AVSS ⎯ ⎯ Analog VSS input pin * : Refer to “■ I/O CIRCUIT TYPE” for the I/O circuit type. DS07-16801-3E 19 MB91270 Series ■ I/O CIRCUIT TYPE Type Circuit A Pull-up control P-ch P-ch Pout N-ch N-ch Nout Pull-down control Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis input (With function to disconnect input during standby mode. ) • Automotive input (With function to disconnect input during standby mode. ) • Resistor that can be set pull-up resistor : Approx. 50 Ω CMOS hysteresis input Automotive input Standby control for disconnect input B P-ch Pout N-ch Nout CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis input (With function to disconnect input during standby mode. ) • Automotive input (With function to disconnect input during standby mode. ) Automotive input Standby control for disconnect input C P-ch Pout N-ch Nout CMOS hysteresis input • CMOS level output (IOL = 3 mA, IOH = −3 mA) • CMOS hysteresis input (With function to disconnect input during standby mode. ) • Automotive input (With function to disconnect input during standby mode. ) Automotive input Standby control for disconnect input (Continued) 20 DS07-16801-3E MB91270 Series Type Circuit CA P-ch Pout N-ch Nout CMOS hysteresis input Remarks • CMOS level output (IOL = 3 mA, IOH = −3 mA) • CMOS hysteresis input (With function to disconnect input during standby mode. ) • Automotive input (With function to disconnect input during standby mode. ) • A/D analog input Automotive input Standby control for disconnect input Analog input D Pull-up control P-ch P-ch Pout N-ch N-ch Nout Pull-down control • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis input (With function to disconnect input during standby mode. ) • Automotive input (With function to disconnect input during standby mode. ) • Resistor that can be set pull-up resistor : Approx. 50 Ω • A/D analog input CMOS hysteresis input Automotive input Standby control for disconnect input Analog input (Continued) DS07-16801-3E 21 MB91270 Series Type Circuit E P-ch Pout N-ch Nout CMOS hysteresis input Automotive input Remarks • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis input (With function to disconnect input during standby mode. ) • Automotive input (With function to disconnect input during standby mode. ) • A/D analog input • D/A analog output Standby control for disconnect input Analog input Analog output J CMOS hysteresis input CMOS hysteresis input N • CMOS hysteresis input • Pull-up resistor value : Approx. 50 kΩ Pull-up resistor CMOS hysteresis input T Pull-up control P-ch P-ch Pout N-ch N-ch Nout Pull-down control CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH = −4 mA) • CMOS hysteresis input (With function to disconnect input during standby mode. ) • Automotive input (With function to disconnect input during standby mode. ) • TTL (With function to disconnect input during standby mode. ) • Resistor that can be set pull-up resistor : Approx. 50 kΩ Automotive input TTL input Standby control for disconnect input (Continued) 22 DS07-16801-3E MB91270 Series (Continued) Type OA OB X1 Circuit Remarks Xout Oscillation circuit High speed oscillation feedback resistance = Approx. 1 MΩ X0 Standby control signal WA WB X1A Xout Oscillation circuit Low speed oscillation feedback resistance = Approx. 10 MΩ X0A Standby control signal DS07-16801-3E 23 MB91270 Series ■ I/O CELL LIST Input Type Pull Up/Down (50 kΩ) CMOS (C) CMOS Schmitt (CS) Automotive (A) Input Stop A Up/Down switch CS/A switch Stop ⎯ 4 mA B ⎯ CS/A switch Stop ⎯ 4 mA C* ⎯ CS/A switch Stop ⎯ 3 mA I2C CA* ⎯ CS/A switch Stop Input 3 mA I2C + A/DC D Up/Down switch CS/A switch Stop Input 4 mA A/DC E ⎯ CS/A switch Stop I/O 4 mA A/DC + D/AC J ⎯ C ⎯ ⎯ ⎯ MD[2 : 0] N Up CS (initx) ⎯ ⎯ ⎯ INIT T Up/Down switch CS/A/TTL switch Stop ⎯ 4 mA Has TTL input OA OB ⎯ ⎯ Stop ⎯ ⎯ 4 MHz Oscillator WA WB ⎯ ⎯ Stop ⎯ ⎯ 32 kHz Oscillator Analog Line Output Driver Remarks * : When the C and CA ports are set for the use of an I2C interface, the outputs are Nch open drain outputs. Otherwise, functions as a CMOS output. ■ PIN INPUT VOLTAGE Form VIL VIH VSS + 0.3 V VCC − 0.3 V CMOS Schmitt trigger input (for INIT pin) 0.2 × VCC 0.8 × VCC CMOS Schmitt trigger input 0.3 × VCC 0.7 × VCC A CMOS automotive Schmitt trigger input 0.5 × VCC 0.8 × VCC T TTL input 0.8 V 2.1 V C CS (initx) CS 24 Type CMOS input DS07-16801-3E MB91270 Series ■ HANDLING DEVICES • Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC pin and VSS pin. A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, do not exceed the maximum rating. • Treatment of Unused Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. • Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations such as latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS near this device. • Crystal Oscillator Circuit Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, X0A and X1A pins the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. • Notes on Using External Clock When external clock is selected, supply it to X0 pin generally, and simultaneously the opposite phase clock to X0 must be supplied to X1 pin. However, in this case the stop mode (oscillation stop mode) must not be used. (This is because the X1 pin stops at High level output in STOP mode.) Using an external clock (normal) X0 X1 Note : The STOP mode (oscillation stop mode) cannot be used. DS07-16801-3E 25 MB91270 Series • Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Retransmit the data if an error occurs because of applying the checksum to the last data in consideration of receiving wrong data due to the noise. • Notes when using no sub-clock Use a single-clock model if not using the sub-clock. Always connect a resonator of 100 kHz or less on dual clock models. • Treatment of NC or OPEN pins Pins marked as NC and OPEN must be left open - circuit. • Mode pins (MD0 to MD2) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance is low. • Operation at start-up The INIT pin must be held at the “L”level when turning on the power. • Source oscillation input at power on When turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state. • Caution on operations during PLL Clock Mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. • External bus setting This device is guaranteed for use with a 16 MHz external bus. If the base clock is set to 32 MHz with DIVR1 (external bus base clock division setting register) set to its initial value, the external bus also operates at 32 MHz. When changing the base clock, set the external bus so that it will not exceed 16 MHz. • Pull-up control The AC characteristics cannot be guaranteed if pull-up resistors are used for the pins used as external bus pins. 26 DS07-16801-3E MB91270 Series ■ BLOCK DIAGRAM Watchdog timer FR 60 Lite CPU CORE Clock generator Voltage regulator 32 32 I-bus Bit search module Flash/ MASK ROM D-bus Debug support 32 DMA controller Harvard bus converter F-bus 32 F-busRAM 32 External bus 24-bit address 16-bit data CAN controller R-bus adapter External bus I/F 8/10-bit D/AC 16 Clock supervisor 10-bit A/DC Hardware watchdog R-bus LINUART0 sub-clock 16-bit reload timer LINUART ICU 16 bits Clock monitor 16-bit free-run timer Real time clock Output Compare 16 bits I2C 400 kHz External interrupt DS07-16801-3E Up down counter 8/16 bits PPG 8/16 bits 27 MB91270 Series ■ MEMORY MAP MB91V280 MB91F273 (S) I/O I/O I/O I/O Access prohibited Access prohibited CAN CAN 0000 0000H 0000 0400H Direct addressing area Refer to “■I/O MAP” 0001 0000H 0002 0000H 0002 0500H Access prohibited 0003 4000H 0003 A000H 0003 D800H Access prohibited Built-in RAM 48 Kbytes Built-in RAM 24 Kbytes 0004 0000H Access prohibited Access prohibited Emulation SRAM area Flash 512 Kbytes 0008 0000H 0010 0000H External area External area FFFF FFFFH Note : The initial value for the emulation SRAM area on the MB91V280 is 512 Kbytes (0000080000H to 0000100000H) . An SRAM area is supported up to 1024 Kbytes (0000050000H to 0000150000H) 28 DS07-16801-3E MB91270 Series ■ I/O MAP How to read I/O map Address 000000H Register +0 +1 +2 +3 PDR0 [R/W] B XXXXXXXX PDR1 [R/W] B XXXXXXXX PDR2 [R/W] B XXXXXXXX PDR3 [R/W] B XXXXXXXX Block T-unit Port data register Read/Write attribute, Access unit (B : byte, H : halfword, W : word) Initial value after reset Register name (First-column register at address 4n; second-column register at 4n + 1, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Note : Initial values of register bits are represented as follows : “ 1 ” : Initial value “1” “ 0 ” : Initial value “0” “ X ” : Initial value “undefined” “-” : No physical register present at this location Access by any undescribed data access attribute is prohibited. DS07-16801-3E 29 MB91270 Series Address Register +0 +1 +2 +3 000000H PDR0 [R/W] B, H XXXXXXXX PDR1 [R/W] B, H XXXXXXXX PDR2 [R/W] B, H XXXXXXXX PDR3 [R/W] B, H XXXXXXXX 000004H PDR4 [R/W] B, H XXXXXXXX PDR5 [R/W] B, H XXXXXXXX PDR6 [R/W] B, H XXXXXXXX PDR7 [R/W] B, H XXXXXXXX 000008H PDR8 [R/W] B, H XXXXXXXX PDR9 [R/W] B, H XXXXXXXX PDRA [R/W] B, H ------XX PDRB [R/W] B, H --XXXXXX 00000CH PDRC [R/W] B, H PDRD [R/W] B, H PDRE [R/W] B, H XXXXXXXX XXXXXXXX XXXXXXXX 000010H PDRG [R/W] B, H XXXXXXXX Block Port Data Registers (PDRB to PDRG are only available PDRF [R/W] B, H on the MB91V280.) XXXXXXXX ⎯ 000014H to 00003CH ⎯ System Reserved 000040H EIRR0 [R/W] 00000000 ENIR [R/W] 00000000 ELVR0 [R/W] 00000000 00000000 Ext. INT 0-7 000044H DICR [R/W] -------0 HRCL [R, R/W] 0--11111 ⎯ DLY / I-Unit TMRLR0 [W] XXXXXXXX XXXXXXXX TMR0 [R] XXXXXXXX XXXXXXXX 00004CH ⎯ TMCSR0 [R, RW] 00000000 00000000 000050H TMRLR1 [W] XXXXXXXX XXXXXXXX TMR1 [R] XXXXXXXX XXXXXXXX 000054H ⎯ TMCSR1 [R, RW] 00000000 00000000 000058H TMRLR2 [W] XXXXXXXX XXXXXXXX TMR2 [R] XXXXXXXX XXXXXXXX 000048H TMCSR2 [R, RW] 00000000 00000000 00005CH ⎯ ⎯ 000060H SCR0 [R, R/W] 00000000 SMR0 [W, R/W] 00000000 000064H ESCR0 [R/W] 00000100 ECCR0 [R, W, R/W] 000000XX BGR10 [R/W] 00000000 BGR00 [R/W] 00000000 000068H SCR5 [R, R/W] 00000000 SMR5 [W, R/W] 00000000 SSR5 [R, R/W] 00001000 RDR5/TRD5 [R/W] 00000000 ESCR5 [R/W] 00000100 ECCR5 [R, W, R/W] 000000XX 00006CH SSR0 [R, R/W] 00001000 BGR15 [R/W] 00000000 RDR0/TRD0 [R/W] 00000000 Reload Timer 0 Reload Timer 1 Reload Timer 2 LIN-UART 0 LIN-UART 5 BGR05 [R/W] 00000000 (Continued) 30 DS07-16801-3E MB91270 Series Register Address 000070H 000074H +0 +1 +2 +3 SCR6 [R, R/W] 00000000 SMR6 [W, R/W] 00000000 SSR6 [R, R/W] 00001000 RDR6/TRD6 [R/W] 00000000 ESCR6 [R/W] 00000100 ECCR6 [R, W, R/W] 000000XX 000078H to 0000ACH BGR16 [R/W] 00000000 LIN-UART 6 BGR06 [R/W] 00000000 ⎯ System Reserved SSR1 [R, R/W] 00001000 RDR1/TRD1 [R/W] 00000000 SCR1 [R, R/W] 00000000 SMR1 [W, R/W] 00000000 0000B4H ESCR1 [R/W] 00000100 ECCR1 [R, W, R/W] 000000XX BGR11 [R/W] 00000000 BGR01 [R/W] 00000000 0000B8H SCR2 [R, R/W] 00000000 SMR2 [W, R/W] 00000000 SSR2 [R, R/W] 00001000 RDR2/TRD2 [R/W] 00000000 0000BCH ESCR2 [R/W] 00000100 ECCR2 [R, W, R/W] 000000XX BGR12 [R/W] 00000000 BGR02 [R/W] 00000000 0000C0H SCR3 [R, R/W] 00000000 SMR3 [W, R/W] 00000000 SSR3 [R, R/W] 00001000 RDR3/TRD3 [R/W] 00000000 0000C4H ESCR3 [R/W] 00000100 ECCR3 [R, W, R/W] 000000XX BGR13 [R/W] 00000000 BGR03 [R/W] 00000000 0000C8H SCR4 [R, R/W] 00000000 SMR4 [W, R/W] 00000000 SSR4 [R, R/W] 00001000 RDR4/TRD4 [R/W] 00000000 0000CCH ESCR4 [R/W] 00000100 ECCR4 [R, W, R/W] 000000XX 0000D0H EIRR1 [R/W] 00000000 ENIR1 [R/W] 00000000 0000B0H Block BGR14 [R/W] 00000000 LIN-UART 1 LIN-UART 2 LIN-UART 3 LIN-UART 4 BGR04 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 Ext. INT 8 to 15 0000D4H TCTDT0 [R/W] H 00000000 00000000 ⎯ TCCS0 [R/W] B 00000000 Free-run Timer 0 0000D8H TCTDT1 [R/W] H 00000000 00000000 ⎯ TCCS1 [R/W] B 00000000 Free-run Timer 1 0000DCH TCTDT2 [R/W] H 00000000 00000000 ⎯ TCCS2 [R/W] B 00000000 Free-run Timer 2 0000E0H TCTDT3 [R/W] H 00000000 00000000 ⎯ TCCS3 [R/W] B 00000000 Free Run Timer 3 (Continued) DS07-16801-3E 31 MB91270 Series Address 0000E4H Register +0 0000FCH ICS01 [R/W] 00000000 IPCP3 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX ICS23 [R/W] 00000000 ⎯ IPCP5 [R] XXXXXXXX XXXXXXXX IPCP4 [R] XXXXXXXX XXXXXXXX ICS45 [R/W] 00000000 ⎯ 0000F8H IPCP7 [R] XXXXXXXX XXXXXXXX IPCP6 [R] XXXXXXXX XXXXXXXX ICS67 [R/W] 00000000 ⎯ 000100H +3 IPCP0 [R] XXXXXXXX XXXXXXXX ⎯ 0000F0H 0000F4H +2 IPCP1 [R] XXXXXXXX XXXXXXXX 0000E8H 0000ECH +1 ⎯ 000104H Block Input Capture Unit 0, 1 Input Capture Unit 2, 3 Input Capture Unit 4, 5 Input Capture Unit 6, 7 System Reserved 000108H OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP0 [R/W] XXXXXXXX XXXXXXXX Output Compare 1/0 00010CH OCCP3 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX Output Compare 3/2 000110H OCS23 [R/W] 11101100 00001100 OCS01 [R/W] 11101100 00001100 Output Compare 3 to 0 Ctrl. 000114H OCCP5 [R/W] XXXXXXXX XXXXXXXX OCCP4 [R/W] XXXXXXXX XXXXXXXX Output Compare 5/4 000118H OCCP7 [R/W] XXXXXXXX XXXXXXXX OCCP6 [R/W] XXXXXXXX XXXXXXXX Output Compare 7/6 00011CH OCS67 [R/W] 11101100 00001100 OCS45 [R/W] 11101100 00001100 Output Compare 7 to 4 Ctrl. 000120H to 00012CH ⎯ System Reserved 000130H EIRR2 [R/W] 00000000 ENIR2 [R/W] 00000000 ELVR2 [R/W] 00000000 00000000 Ext. INT 16 to 23 000134H EIRR3 [R/W] 00000000 ENIR3 [R/W] 00000000 ELVR3 [R/W] 00000000 00000000 Ext. INT 24 to 31 (MB91V280 only) 000138H EIRR4 [R/W] 00000000 ENIR4 [R/W] 00000000 ELVR4 [R/W] 00000000 00000000 Ext. INT 32 to 39 (MB91V280 only) 00013CH ⎯ DACR [R/W] -----000 DADR0 [R/W] ------00 00000000 000140H DADR1 [R/W] ------00 00000000 ⎯ DADBL [R/W] -------0 D/A Converter (MB91V280 only) (Continued) 32 DS07-16801-3E MB91270 Series Register Address +0 +1 +2 000144H ⎯ WTDBL [R/W] B ------00 000148H ⎯ +3 WTCR [R/W] B, H 00000000 000-00-X WTBR [R/W] B ---XXXXX XXXXXXXX XXXXXXXX 00014CH WTHR [R/W] B, H WTMR [R/W] B, H XXXXXXXX XXXXXXXX 000150H ADERH [R/W] 00000000 00000000 WTSR [R/W] B --XXXXXX Real Time Clock ⎯ ADERL [R/W] 00000000 00000000 000154H ADCS1 [R/W] 00000000 ADCS0 [R, R/W] 00000000 ADCR1 [R] ------XX ADCR0 [R] XXXXXXXX 000158H ADCT1 [R/W] 00010000 ADCT0 [R/W] 00101100 ADSCH [R/W] ---00000 ADECH [R/W] ---00000 00015CH CUCR [R/W] B, H, W -------- ---00000 CUTD [R/W] B, H, W 10000000 00000000 000160H CUTR1 [R] B, H, W -------- 00000000 CUTR2 [R] B, H, W 00000000 00000000 000164H to 00016CH ⎯ UDRC1 [W] B, H 00000000 UDRC0 [W] B, H 00000000 UDCR1 [R] B, H 00000000 UDCR0 [R] B, H 00000000 000174H UDCCH0 [R/W] B, H 00000000 UDCCL0 [R/W] B, H -0000000 ⎯ UDCS0 [R/W] B 00000000 000178H UDCCH1 [R/W] B, H -0000000 UDCCL1 [R/W] B, H -0000000 ⎯ UDCS1 [R/W] B 00000000 ⎯ UDRC3 [W] B, H 00000000 UDRC2 [W] B, H 00000000 UDCR3 [R] B, H 00000000 UDCR2 [R] B, H 00000000 000184H UDCCH2 [R/W] B, H 00000000 UDCCL2 [R/W] B, H -0000000 ⎯ UDCS2 [R/W] B 00000000 000188H UDCCH3 [R/W] B, H -0000000 UDCCL3 [R/W] B, H -0000000 ⎯ UDCS2 [R/W] B 00000000 ⎯ AD2ERH [R/W] 00000000 00000000 000190H Clock Calibration (MB91V280 and without S-suffix models only) Up Down Counter 0/1 System Reserved 000180H 00018CH A/D Converter System Reserved 000170H 00017CH Block Up Down Counter 2/3 System Reserved AD2ERL [R/W] 00000000 00000000 000194H AD2CS1 [R/W] 00000000 AD2CS0 [R, R/W] 00000000 AD2CR1 [R] ------XX AD2CR0 [R] XXXXXXXX 000198H AD2CT1 [R/W] 00010000 AD2CT0 [R/W] 00101100 AD2SCH [R/W] ---00000 AD2ECH [R/W] ---00000 A/D Converter 2 (MB91V280 only) (Continued) DS07-16801-3E 33 MB91270 Series Address Register +0 +1 +2 +3 ⎯ 00019CH System Reserved CMCR [R/W] B, H -0010000 0001A0H CMPR [R/W] B, H --000010 11111101 ⎯ 0001A4H CMT1 [R/W] B, H, W 00000000 10000000 CMT2 [R/W] B, H, W 00000000 00000000 0001A8H CANPRE [R, R/W] 00000000 EISSR [R/W] B, H 00000000 00000000 ⎯ ⎯ 0001ACH PRLH0 [R/W] B, H, W XXXXXXXX PRLL0 [R/W] B, H, W XXXXXXXX PRLH1 [R/W] B, H, W XXXXXXXX PRLL1 [R/W] B, H, W XXXXXXXX 0001B4H PRLH2 [R/W] B, H, W XXXXXXXX PRLL2 [R/W] B, H, W XXXXXXXX PRLH3 [R/W] B, H, W XXXXXXXX PRLL3 [R/W] B, H, W XXXXXXXX 0001B8H PPGC0 [R/W] B, H, W 0000000X PPGC1 [R/W] B, H, W 0000000X PPGC2 [R/W] B, H, W 0000000X PPGC3 [R/W] B, H, W 0000000X ⎯ PRLH4 [R/W] B, H, W XXXXXXXX PRLL4 [R/W] B, H, W XXXXXXXX PRLH5 [R/W] B, H, W XXXXXXXX PRLL5 [R/W] B, H, W XXXXXXXX 0001C4H PRLH6 [R/W] B, H, W XXXXXXXX PRLL6 [R/W] B, H, W XXXXXXXX PRLH7 [R/W] B, H, W XXXXXXXX PRLL7 [R/W] B, H, W XXXXXXXX 0001C8H PPGC4 [R/W] B, H, W 0000000X PPGC5 [R/W] B, H, W 0000000X PPGC6 [R/W] B, H, W 0000000X PPGC7 [R/W] B, H, W 0000000X ⎯ PRLH8 [R/W] B, H, W XXXXXXXX PRLL8 [R/W] B, H, W XXXXXXXX PRLH9 [R/W] B, H, W XXXXXXXX PRLL9 [R/W] B, H, W XXXXXXXX 0001D4H PRLHA [R/W] B, H, W XXXXXXXX PRLLA [R/W] B, H, W XXXXXXXX PRLHB [R/W] B, H, W XXXXXXXX PRLLB [R/W] B, H, W XXXXXXXX 0001D8H PPGC8 [R/W] B, H, W 0000000X PPGC9 [R/W] B, H, W 0000000X PPGCA [R/W] B, H, W 0000000X PPGCB [R/W] B, H, W 0000000X ⎯ PPG0 to PPG3 PPG4 to PPG7 System Reserved 0001D0H 0001DCH CAN Clock Presc / Ext. Int. Source Sel. System Reserved 0001C0H 0001CCH Clock Modulator System Reserved 0001B0H 0001BCH Block PPG8 to PPGB System Reserved (Continued) 34 DS07-16801-3E MB91270 Series Register Address +0 +1 +2 +3 0001E0H PRLHC [R/W] B, H, W XXXXXXXX PRLLC [R/W] B, H, W XXXXXXXX PRLHD [R/W] B, H, W XXXXXXXX PRLLD [R/W] B, H, W XXXXXXXX 0001E4H PRLHE [R/W] B, H, W XXXXXXXX PRLLE [R/W] B, H, W XXXXXXXX PRLHF [R/W] B, H, W XXXXXXXX PRLLF [R/W] B, H, W XXXXXXXX 0001E8H PPGCC [R/W] B, H, W 0000000X PPGCD [R/W] B, H, W 0000000X PPGCE [R/W] B, H, W 0000000X PPGCF [R/W] B, H, W 0000000X ⎯ 0001ECH PPGTRG [R/W] B, H, W 00000000 00000000 0001F0H Block PPGC to PPGF System Reserved PPGREVC [R/W] B, H, W 00000000 00000000 PPG0 to PPGF Enable / Reverse 0001F4H PPGSWAP [R/W] B 00000000 ⎯ PPG0 to PPGF Output Swap 0001F8H CMCLKR [R/W] B ----0000 ⎯ Clock Monitor 0001FCH ⎯ 000200H DMACA0 [R/W] 00000000 00000000 00000000 00000000 000204H DMACB0 [R/W] 00000000 00000000 00000000 00000000 000208H DMACA1 [R/W] 00000000 00000000 00000000 00000000 00020CH DMACB1 [R/W] 00000000 00000000 00000000 00000000 000210H DMACA2 [R/W] 00000000 00000000 00000000 00000000 000214H DMACB2 [R/W] 00000000 00000000 00000000 00000000 000218H DMACA3 [R/W] 00000000 00000000 00000000 00000000 00021CH DMACB3 [R/W] 00000000 00000000 00000000 00000000 000220H DMACA4 [R/W] 00000000 00000000 00000000 00000000 000224H DMACB4 [R/W] 00000000 00000000 00000000 00000000 000228H to 00023CH ⎯ System Reserved DMAC DMAC System Reserved (Continued) DS07-16801-3E 35 MB91270 Series Address Register +0 +1 +2 +3 Block 000240H DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX DMAC 000244H to 0003ECH ⎯ System Reserved 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000400H DDR0 [R/W] B, H 00000000 DDR1 [R/W] B, H 00000000 DDR2 [R/W] B, H 00000000 DDR3 [R/W] B, H 00000000 000404H DDR4 [R/W] B, H 00000000 DDR5 [R/W] B, H 00000000 DDR6 [R/W] B, H 00000000 DDR7 [R/W] B, H 00000000 000408H DDR8 [R/W] B, H 00000000 DDR9 [R/W] B, H 00000000 DDRA [R/W] B, H DDRB [R/W] B, H ------00 --000000 00040CH DDRC [R/W] B, H DDRD [R/W] B, H DDRE [R/W] B, H 00000000 00000000 00000000 000410H DDRG [R/W] B, H 00000000 DDRF [R/W] B, H 00000000 Bit Search Data Direction Registers (DDRB to DDRG are only available on the MB91V280) ⎯ 000414H to 00041CH ⎯ System Reserved 000420H PFR0 [R/W] B, H 00000000 PFR1 [R/W] B, H 00000000 PFR2 [R/W] B, H 00000000 PFR3 [R/W] B, H 00000000 000424H PFR4 [R/W] B, H 00000000 PFR5 [R/W] B, H 00000000 PFR6 [R/W] B, H 00000000 PFR7 [R/W] B, H 00000000 000428H PFR8 [R/W] B, H 00000000 PFR9 [R/W] B, H 00000000 PFRA [R/W] B, H ------00 PFRB [R/W] B, H --000000 00042CH PFRC [R/W] B, H 00000000 PFRD [R/W] B, H 00000000 PFRE [R/W] B, H 00000000 PFRF [R/W] B, H 00000000 000430H PFRG [R/W] B, H 00000000 Port Function Registers (PFRB to PFRG are only available on the MB91V280) ⎯ (Continued) 36 DS07-16801-3E MB91270 Series Register Address +0 +1 000434H to 00043CH +2 +3 ⎯ System Reserved 000440H ICR00 [R, R/W] ---11111 ICR01 [R, R/W] ---11111 ICR02 [R, R/W] ---11111 ICR03 [R, R/W] ---11111 000444H ICR04 [R, R/W] ---11111 ICR05 [R, R/W] ---11111 ICR06 [R, R/W] ---11111 ICR07 [R, R/W] ---11111 000448H ICR08 [R, R/W] ---11111 ICR09 [R, R/W] ---11111 ICR10 [R, R/W] ---11111 ICR11 [R, R/W] ---11111 00044CH ICR12 [R, R/W] ---11111 ICR13 [R, R/W] ---11111 ICR14 [R, R/W] ---11111 ICR15 [R, R/W] ---11111 000450H ICR16 [R, R/W] ---11111 ICR17 [R, R/W] ---11111 ICR18 [R, R/W] ---11111 ICR19 [R, R/W] ---11111 000454H ICR20 [R, R/W] ---11111 ICR21 [R, R/W] ---11111 ICR22 [R, R/W] ---11111 ICR23 [R, R/W] ---11111 000458H ICR24 [R, R/W] ---11111 ICR25 [R, R/W] ---11111 ICR26 [R, R/W] ---11111 ICR27 [R, R/W] ---11111 00045CH ICR28 [R, R/W] ---11111 ICR29 [R, R/W] ---11111 ICR30 [R, R/W] ---11111 ICR31 [R, R/W] ---11111 000460H ICR32 [R, R/W] ---11111 ICR33 [R, R/W] ---11111 ICR34 [R, R/W] ---11111 ICR35 [R, R/W] ---11111 000464H ICR36 [R, R/W] ---11111 ICR37 [R, R/W] ---11111 ICR38 [R, R/W] ---11111 ICR39 [R, R/W] ---11111 000468H ICR40 [R, R/W] ---11111 ICR41 [R, R/W] ---11111 ICR42 [R, R/W] ---11111 ICR43 [R, R/W] ---11111 00046CH ICR44 [R, R/W] ---11111 ICR45 [R, R/W] ---11111 ICR46 [R, R/W] ---11111 ICR47 [R, R/W] ---11111 000470H to 00047CH ⎯ RSRR [R, R/W] 10000000 STCR [R/W] 00110011 TBCR [R/W] 00XXXX00 CTBR [W] XXXXXXXX 000484H CLKR [R/W] 00000000 WPR [W] XXXXXXXX DIVR0 [R/W] 00000011 DIVR1 [R/W] 00000000 OSCCR [R/W] XXXXXXX0 ⎯ ⎯ ⎯ 00048CH 000490H OSCR [W, R/W] 00000000 Interrupt Control Unit System Reserved 000480H 000488H Block Clock Control Unit System Reserved ⎯ Stb. Wait Timer (Continued) DS07-16801-3E 37 MB91270 Series Address Register +0 +1 000494H to 0004A8H 0004ACH +2 +3 ⎯ ⎯ System Reserved CSVCR [R/W] 0001XX00 0004B0H to 0004FCH ⎯ Clock Supervisor ⎯ System Reserved 000500H PPER0 [R/W] B, H 00000000 PPER1 [R/W] B, H 00000000 PPER2 [R/W] B, H 00000000 PPER3 [R/W] B, H 00000000 000504H PPER4 [R/W] B, H 00000000 PPER5 [R/W] B, H 00000000 PPER6 [R/W] B, H 00000000 PPER7 [R/W] B, H 00000000 000508H PPER8 [R/W] B, H 00000000 PPER9 [R/W] B, H 00000000 PPERA [R/W] B, H ------00 PPERB [R/W] B, H --000000 00050CH PPERC [R/W] B, H 00000000 PPERD [R/W] B, H 00000000 PPERE [R/W] B, H 00000000 PPERF [R/W] B, H 00000000 000510H PPERG [R/W] B, H 00000000 Port Pull-up/down Enable Registers (PPERB to PPERG are only available on the MB91V280) ⎯ 000514H to 00051CH ⎯ System Reserved 000520H PPCR0 [R/W] B, H 00000000 PPCR1 [R/W] B, H 00000000 PPCR2 [R/W] B, H 00000000 PPCR3 [R/W] B, H 00000000 000524H PPCR4 [R/W] B, H 00000000 PPCR5 [R/W] B, H 00000000 PPCR6 [R/W] B, H 00000000 PPCR7 [R/W] B, H 00000000 000528H PPCR8 [R/W] B, H 00000000 PPCR9 [R/W] B, H 00000000 PPCRA [R/W] B, H ------00 PPCRB [R/W] B, H --000000 00052CH PPCRC [R/W] B, H 00000000 PPCRD [R/W] B, H 00000000 PPCRE [R/W] B, H 00000000 PPCRF [R/W] B, H 00000000 000530H PPCRG [R/W] B, H 00000000 000534H to 00053CH Block Port Pull-up/down Control Registers (PPCRB to PPCRG are only available on the MB91V280) ⎯ ⎯ System Reserved (Continued) 38 DS07-16801-3E MB91270 Series Register Address +0 +1 +2 +3 000540H PILR0 [R/W] B, H 00000000 PILR1 [R/W] B, H 00000000 PILR2 [R/W] B, H 00000000 PILR3 [R/W] B, H 00000000 000544H PILR4 [R/W] B, H 00000000 PILR5 [R/W] B, H 00000000 PILR6 [R/W] B, H 00000000 PILR7 [R/W] B, H 00000000 000548H PILR8 [R/W] B, H 00000000 PILR9 [R/W] B, H PILRA [R/W] B, H PILRB [R/W] B, H 00000000 ------00 --000000 00054CH PILRC [R/W] B, H PILRD [R/W] B, H PILRE [R/W] B, H PILRF [R/W] B, H 00000000 00000000 00000000 00000000 000550H PILRG [R/W] 00000000 Block Port Input Level select Registers (PILRB to PILRG are only available on the MB91V280) ⎯ 000554H to 00055CH ⎯ System Reserved 000560H IBCR0 [R/W] 00000000 IBSR0 [R] 00000000 ITBAH0 [R/W] ------00 ITBAL0 [R/W] 00000000 000564H ITMKH0 [R/W, R] 00----11 ITMKL0 [R/W] 11111111 ISMK0 [R/W] 01111111 ISBA0 [R/W] -0000000 000568H ⎯ IDAR0 [R/W] 00000000 ICCR0 [R/W] -0011111 ⎯ ⎯ 00056CH System Reserved 000570H IBCR1 [R/W] 00000000 IBSR1 [R] 00000000 ITBAH1 [R/W] ------00 ITBAL1 [R/W] 00000000 000574H ITMKH1 [R/W, R] 00----11 ITMKL1 [R/W] 11111111 ISMK1 [R/W] 01111111 ISBA1 [R/W] -0000000 000578H ⎯ IDAR1 [R/W] 00000000 ICCR1 [R/W] -0011111 ⎯ ⎯ 00057CH I2C 0 I2C 1 System Reserved 000580H IBCR2 [R/W] 00000000 IBSR2 [R] 00000000 ITBAH2 [R/W] ------00 ITBAL2 [R/W] 00000000 000584H ITMKH2 [R/W, R] 00----11 ITMKL2 [R/W] 11111111 ISMK2 [R/W] 01111111 ISBA2 [R/W] -0000000 000588H ⎯ IDAR2 [R/W] 00000000 ICCR2 [R/W] -0011111 ⎯ I2C 2 00058CH ⎯ System Reserved 000590H to 0005F8H ⎯ System Reserved 0005FCH ⎯ HWDCS [R/W] B, H 00011000 ⎯ Hardware Watchdog (Continued) DS07-16801-3E 39 MB91270 Series Address Register +0 +1 +2 +3 000600H EPFR0 [R/W] B, H 00000000 EPFR1 [R/W] B, H 00000000 EPFR2 [R/W] B, H 00000000 EPFR3 [R/W] B, H 00000000 000604H EPFR4 [R/W] B, H 00000000 EPFR5 [R/W] B, H 00000000 EPFR6 [R/W] B, H 00000000 EPFR7 [R/W] B, H 00000000 000608H EPFR8 [R/W] B, H 00000000 EPFR9 [R/W] B, H 00000000 EPFRA [R/W] B, H ------00 EPFRB [R/W] B, H --000000 00060CH EPFRC [R/W] B, H 00000000 EPFRD [R/W] B, H 00000000 EPFRE [R/W] B, H 00000000 EPFRF [R/W] B, H 00000000 000610H EPFRG [R/W] B, H 00000000 Block Extra Port Function Register (EPFRB to EPFRG are only available on the MB91V280) ⎯ 000614H to 00061CH ⎯ System Reserved 000620H PIDR0 [R] B, H XXXXXXXX PIDR1 [R] B, H XXXXXXXX PIDR2 [R] B, H XXXXXXXX PIDR3 [R] B, H XXXXXXXX 000624H PIDR4 [R] B, H XXXXXXXX PIDR5 [R] B, H XXXXXXXX PIDR6 [R] B, H XXXXXXXX PIDR7 [R] B, H XXXXXXXX 000628H PIDR8 [R] B, H XXXXXXXX PIDR9 [R] B, H XXXXXXXX PIDRA [R] B, H ------XX PIDRB [R] B, H --XXXXXX 00062CH PIDRC [R] B, H XXXXXXXX PIDRD [R] B, H XXXXXXXX PIDRE [R] B, H XXXXXXXX PIDRF [R] B, H XXXXXXXX 000630H PIDRG [R] B, H XXXXXXXX 000634H to 00063CH Input Data Direct Read Data Register (PIDRB to PDIRG are only available on the MB91V280) ⎯ ⎯ System Reserved 000640H ASR0 [R/W] 00000000 00000000 ACR0 [R/W] 00110*00 00000000 000644H ASR1 [R/W] XXXXXXXX XXXXXXXX ACR1 [R/W] XXXX0X00 00X0XXXX 000648H ASR2 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXX0X00 00X0XXXX 00064CH ASR3 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] 01XX0X00 00X0XXXX T-Unit (Continued) 40 DS07-16801-3E MB91270 Series Register Address +0 +1 +2 000650H to 00065CH +3 ⎯ 000660H AWR0 [R/W] 01110000 01011011 AWR1 [R/W] XXXX0000 XX0X1XXX 000664H AWR2 [R/W] 0XXX0000 XX0X1XXX AWR3 [R/W] 0XXX0000 0X0X1XXX 000668H to 00067CH 000680H Block T-Unit ⎯ CSER [R/W] ----0001 ⎯ 000684H to 0007F8H 0007FCH ⎯ ⎯ 000800H to 000FFCH MODR [W] XXXXXXXX System Reserved ⎯ ⎯ 001000H ⎯ DMASA0 [R/W] ----0000 00000000 00000000 001004H ⎯ DMADA0 [R/W] ----0000 00000000 00000000 001008H ⎯ DMASA1 [R/W] ----0000 00000000 00000000 00100CH ⎯ DMADA1 [R/W] ----0000 00000000 00000000 001010H ⎯ DMASA2 [R/W] ----0000 00000000 00000000 001014H ⎯ DMADA2 [R/W] ----0000 00000000 00000000 001018H ⎯ DMASA3 [R/W] ----0000 00000000 00000000 00101CH ⎯ DMADA30 [R/W] ----0000 00000000 00000000 001020H ⎯ DMASA4 [R/W] 00000000 00000000 00000000 001024H ⎯ DMADA4 [R/W] 00000000 00000000 00000000 00102BH to 006FFCH ⎯ Mode Register System Reserved DMAC System Reserved (Continued) DS07-16801-3E 41 MB91270 Series Address Register +0 +1 +2 007000H FLCR [R/W] 0110X000 ⎯ 007004H FLWC [R/W] 00000011 ⎯ 007008H to 01FFFCH +3 Block Flash I/F ⎯ System Reserved 020000H CTRLR0 [R, R/W] 00000000 00000001 STATR0 [R, R/W] 00000000 00000000 020004H ERRCNT0 [R] 00000000 00000000 BTR0 [R, R/W] 00100011 00000001 020008H INTR0 [R] 00000000 00000000 TESTR0 [R, R/W] 00000000 00000000 02000CH BRPER0 [R, R/W] 00000000 00000000 ⎯ 020010H IF1CREQ0 [R, R/W] 00000000 00000001 IF1CMSK0 [R, R/W] 00000000 00000000 020014H IF1MSK20 [R, R/W] 11111111 11111111 IF1MSK10 [R, R/W] 11111111 11111111 020018H IF1ARB20 [R/W] 00000000 00000000 IF1ARB10 [R/W] 00000000 00000000 02001CH IF1MCTR0 [R, R/W] 00000000 00000000 ⎯ 020020H IF1DTA10 [R/W] XXXXXXXX XXXXXXXX IF1DTA20 [R/W] XXXXXXXX XXXXXXXX 020024H IF1DTB10 [R/W] XXXXXXXX XXXXXXXX IF1DTB20 [R/W] XXXXXXXX XXXXXXXX 020030H to 02003CH System Reserved (IF1 data mirror, little endian byte ordering) 020040H IF2CREQ0 [R, R/W] 00000000 00000001 IF2CMSK0 [R, R/W] 00000000 00000000 020044H IF2MSK20 [R, R/W] 11111111 11111111 IF2MSK10 [R, R/W] 11111111 11111111 020048H IF2ARB20 [R/W] 00000000 00000000 IF2ARB10 [R/W] 00000000 00000000 02004CH IF2MCTR0 [R, R/W] 00000000 00000000 ⎯ 020050H IF2DTA10 [R/W] XXXXXXXX XXXXXXXX IF2DTA20 [R/W] XXXXXXXX XXXXXXXX 020054H IF2DTB10 [R/W] XXXXXXXX XXXXXXXX IF2DTB20 [R/W] XXXXXXXX XXXXXXXX CAN 0 CAN 0 (Continued) 42 DS07-16801-3E MB91270 Series Address 020060H to 02007CH Register +0 +1 +2 +3 Block System Reserved (IF2 data mirror, little endian byte ordering) 020080H TREQR20 [R] 00000000 00000000 TREQR10 [R] 00000000 00000000 020090H NEWDT20 [R] 00000000 00000000 NEWDT10 [R] 00000000 00000000 0200A0H INTPND20 [R] 00000000 00000000 INTPND10 [R] 00000000 00000000 0200B0H MSGVAL20 [R] 00000000 00000000 MSGVAL10 [R] 00000000 00000000 0200B4H to 0200FCH ⎯ CAN 0 System Reserved 020100H CTRLR1 [R, R/W] 00000000 00000001 STATR1 [R, R/W] 00000000 00000000 020104H ERRCNT1 [R] 00000000 00000000 BTR1 [R, R/W] 00100011 00000001 020108H INTR1 [R] 00000000 00000000 TESTR1 [R, R/W] 00000000 00000000 02010CH BRPER1 [R, R/W] 00000000 00000000 ⎯ 020110H IF1CREQ1 [R, R/W] 00000000 00000001 IF1CMSK1 [R, R/W] 00000000 00000000 020114H IF1MSK21 [R, R/W] 11111111 11111111 IF1MSK11 [R, R/W] 11111111 11111111 020118H IF1ARB21 [R/W] 00000000 00000000 IF1ARB11 [R/W] 00000000 00000000 CAN 1 02011CH IF1MCTR1 [R, R/W] 00000000 00000000 ⎯ (MB91V280 only) 020120H IF1DTA11 [R/W] XXXXXXXX XXXXXXXX IF1DTA21 [R/W] XXXXXXXX XXXXXXXX 020124H IF1DTB11 [R/W] XXXXXXXX XXXXXXXX IF1DTB21 [R/W] XXXXXXXX XXXXXXXX 020130H to 02013CH System Reserved (IF1 data mirror, little endian byte ordering) 020140H IF2CREQ1 [R, R/W] 00000000 00000001 IF2CMSK1 [R, R/W] 00000000 00000000 020144H IF2MSK21 [R, R/W] 11111111 11111111 IF2MSK11 [R, R/W] 11111111 11111111 020148H IF2ARB21 [R/W] 00000000 00000000 IF2ARB11 [R/W] 00000000 00000000 (Continued) DS07-16801-3E 43 MB91270 Series Address Register +0 +1 +2 +3 02014CH IF2MCTR1 [R, R/W] 00000000 00000000 ⎯ 020150H IF2DTA11 [R/W] XXXXXXXX XXXXXXXX IF2DTA21 [R/W] XXXXXXXX XXXXXXXX 020154H IF2DTB11 [R/W] XXXXXXXX XXXXXXXX IF2DTB21 [R/W] XXXXXXXX XXXXXXXX 020160H to 02017CH System Reserved (IF2 data mirror, little endian byte ordering) Block CAN 1 (MB91V280 only) 020180H TREQR21 [R] 00000000 00000000 TREQR11 [R] 00000000 00000000 020190H NEWDT21 [R] 00000000 00000000 NEWDT11 [R] 00000000 00000000 0201A0H INTPND21 [R] 00000000 00000000 INTPND11 [R] 00000000 00000000 0201B0H MSGVAL21 [R] 00000000 00000000 MSGVAL11 [R] 00000000 00000000 020200H CTRLR2 [R, R/W] 00000000 00000001 STATR2 [R, R/W] 00000000 00000000 020204H ERRCNT2 [R] 00000000 00000000 BTR2 [R, R/W] 00100011 00000001 020208H INTR2 [R] 00000000 00000000 TESTR2 [R, R/W] 00000000 00000000 02020CH BRPER2 [R, R/W] 00000000 00000000 ⎯ 020210H IF1CREQ2 [R, R/W] 00000000 00000001 IF1CMSK2 [R, R/W] 00000000 00000000 020214H IF1MSK22 [R, R/W] 11111111 11111111 IF1MSK12 [R, R/W] 11111111 11111111 CAN 2 020218H IF1ARB22 [R/W] 00000000 00000000 IF1ARB12 [R/W] 00000000 00000000 (MB91V280 only) 02021CH IF1MCTR2 [R, R/W] 00000000 00000000 ⎯ 020220H IF1DTA12 [R/W] XXXXXXXX XXXXXXXX IF1DTA22 [R/W] XXXXXXXX XXXXXXXX 020224H IF1DTB12 [R/W] XXXXXXXX XXXXXXXX IF1DTB22 [R/W] XXXXXXXX XXXXXXXX 020230H to 02023CH 020240H System Reserved (IF1 data mirror, little endian byte ordering) IF2CREQ2 [R, R/W] 00000000 00000001 IF2CMSK2 [R, R/W] 00000000 00000000 (Continued) 44 DS07-16801-3E MB91270 Series (Continued) Address Register +0 +1 +2 +3 020244H IF2MSK22 [R, R/W] 11111111 11111111 IF2MSK12 [R, R/W] 11111111 11111111 020248H IF2ARB22 [R/W] 00000000 00000000 IF2ARB12 [R/W] 00000000 00000000 02024CH IF2MCTR2 [R, R/W] 00000000 00000000 ⎯ 020250H IF2DTA12 [R/W] XXXXXXXX XXXXXXXX IF2DTA22 [R/W] XXXXXXXX XXXXXXXX 020254H IF2DTB12 [R/W] XXXXXXXX XXXXXXXX IF2DTB22 [R/W] XXXXXXXX XXXXXXXX 020260H to 02027CH System Reserved (IF2 data mirror, little endian byte ordering) 020280H TREQR22 [R] 00000000 00000000 TREQR12 [R] 00000000 00000000 020290H NEWDT22 [R] 00000000 00000000 NEWDT12 [R] 00000000 00000000 0202A0H INTPND22 [R] 00000000 00000000 INTPND12 [R] 00000000 00000000 0202B0H MSGVAL22 [R] 00000000 00000000 MSGVAL12 [R] 00000000 00000000 Block CAN 2 (MB91V280 only) 034000H to 03FFFCH ⎯ F-bus RAM (MB91V280) 03A000H to 03FFFCH ⎯ F-bus RAM (MB91F273 (S) ) 080000H to 0FFFFCH ⎯ Flash memory (MB91F273 (S) ) DS07-16801-3E 45 MB91270 Series ■ INTERRUPT VECTOR Interrupt number Interrupt level Interrupt vector DMA Decimal Hexadecimal Register Address Offset TBR default address RN Stop Reset 0 00 ⎯ ⎯ 3FCH 000FFFFCH ⎯ ⎯ Mode vector 1 01 ⎯ ⎯ 3F8H 000FFFF8H ⎯ ⎯ System reserved 2 02 ⎯ ⎯ 3F4H 000FFFF4H ⎯ ⎯ System reserved 3 03 ⎯ ⎯ 3F0H 000FFFF0H ⎯ ⎯ System reserved 4 04 ⎯ ⎯ 3ECH 000FFFECH ⎯ ⎯ System reserved 5 05 ⎯ ⎯ 3E8H 000FFFE8H ⎯ ⎯ System reserved 6 06 ⎯ ⎯ 3E4H 000FFFE4H ⎯ ⎯ Coprocessor absent trap 7 07 ⎯ ⎯ 3E0H 000FFFE0H ⎯ ⎯ Coprocessor error trap 8 08 ⎯ ⎯ 3DCH 000FFFDCH ⎯ ⎯ INTE instruction 9 09 ⎯ ⎯ 3D8H 000FFFD8H ⎯ ⎯ System reserved 10 0A ⎯ ⎯ 3D4H 00FFFD4CH ⎯ ⎯ System reserved 11 0B ⎯ ⎯ 3D0H 000FFFD0H ⎯ ⎯ Step trace trap 12 0C ⎯ ⎯ 3CCH 000FFFCCH ⎯ ⎯ NMI request (tool) 13 0D ⎯ ⎯ 3C8H 000FFFC8H ⎯ ⎯ Undefined instruction exception 14 0E ⎯ ⎯ 3C4H 000FFFC4H ⎯ ⎯ NMI request 15 0F 15 (FH) fixed ⎯ 3C0H 000FFFC0H ⎯ ⎯ External interrupt 0 16 10 ICR00 0x440 3BCH 000FFFBCH 6 ⎯ External interrupt 1 17 11 ICR01 0x441 3B8H 000FFFB8H 7 ⎯ External interrupt 2 18 12 ICR02 0x442 3B4H 000FFFB4H ⎯ ⎯ External interrupt 3 19 13 ICR03 0x443 3B0H 000FFFB0H ⎯ ⎯ External interrupt 4 20 14 ICR04 0x444 3ACH 000FFFACH ⎯ ⎯ External interrupt 5 21 15 ICR05 0x445 3A8H 000FFFA8H ⎯ ⎯ External interrupt 6 22 16 ICR06 0x446 3A4H 000FFFA4H ⎯ ⎯ External interrupt 7 23 17 ICR07 0x447 3A0H 000FFFA0H ⎯ ⎯ Reload timer 0 24 18 ICR08 0x448 39CH 000FFF9CH 8 ⎯ Reload timer 1 25 19 ICR09 0x449 398H 000FFF98H 9 ⎯ Reload timer 2 26 1A ICR10 0x44A 394H 000FFF94H 10 ⎯ LIN-UART 0 reception 27 1B ICR11 0x44B 390H 000FFF90H 0 Stop LIN-UART 0 transmission 28 1C ICR12 0x44C 38CH 000FFF8CH 3 ⎯ LIN-UART 1 reception 29 1D ICR13 0x44D 388H 000FFF88H 1 Stop LIN-UART 1 transmission 30 1E ICR14 0x44E 384H 000FFF84H 4 ⎯ Interrupt source (Continued) 46 DS07-16801-3E MB91270 Series Interrupt number Interrupt source Decimal Interrupt level HexaRegister decimal Interrupt vector DMA Address Offset TBR default address RN Stop LIN-UART 2 reception 31 1F ICR15 0x44F 380H 000FFF80H 2 Stop LIN-UART 2 transmission 32 20 ICR16 0x450 37CH 000FFF7CH 5 ⎯ CAN 0 33 21 ICR17 0x451 378H 000FFF78H ⎯ ⎯ CAN 1/ICU 6/7* 34 22 ICR18 0x452 374H 000FFF74H ⎯ ⎯ CAN 2* 35 23 ICR19 0x453 370H 000FFF70H ⎯ ⎯ LIN-UART 3/5 reception 36 24 ICR20 0x454 36CH 000FFF6CH ⎯ ⎯ LIN-UART 3/5 transmission 37 25 ICR21 0x455 368H 000FFF68H ⎯ ⎯ LIN-UART 4/6 reception 38 26 ICR22 0x456 364H 000FFF64H ⎯ ⎯ LIN-UART 4/6 transmission 39 27 ICR23 0x457 360H 000FFF60H ⎯ ⎯ 2 40 28 ICR24 0x458 35CH 000FFF5CH ⎯ ⎯ 2 41 29 ICR25 0x459 358H 000FFF58H ⎯ ⎯ 2 IC2 42 2A ICR26 0x45A 354H 000FFF54H ⎯ ⎯ A/D converter 43 2B ICR27 0x45B 350H 000FFF50H 14 ⎯ RTC 44 2C ICR28 0x45C 34CH 000FFF4CH ⎯ ⎯ UDC 1 45 2D ICR29 0x45D 348H 000FFF48H ⎯ ⎯ Main oscillation stabilization wait timer 46 2E ICR30 0x45E 344H 000FFF44H ⎯ ⎯ TBT overflow 47 2F ICR31 0x45F 340H 000FFF40H ⎯ ⎯ PPG 0/1/4/5 48 30 ICR32 0x460 33CH 000FFF3CH ⎯ ⎯ PPG 2/3/6/7 49 31 ICR33 0x461 338H 000FFF38H ⎯ ⎯ PPG 8/9/C/D 50 32 ICR34 0x462 334H 000FFF34H ⎯ ⎯ PPG A/B/E/F 51 33 ICR35 0x463 330H 000FFF30H ⎯ ⎯ FRT 0/1 52 34 ICR36 0x464 32CH 000FFF2CH ⎯ ⎯ FRT 2/3 53 35 ICR37 0x465 328H 000FFF28H ⎯ ⎯ ICU 0/1/2/3 54 36 ICR38 0x466 324H 000FFF24H ⎯ ⎯ ICU 4/5 55 37 ICR39 0x467 320H 000FFF20H ⎯ ⎯ OCU 0/1/2/3 UDC 3 56 38 ICR40 0x468 31CH 000FFF1CH ⎯ ⎯ OCU 4/5/6/7 57 39 ICR41 0x469 318H 000FFF18H ⎯ ⎯ UDC 0 58 3A ICR42 0x46A 314H 000FFF14H ⎯ ⎯ External interrupt 8/9/10/11 59 3B ICR43 0x46B 310H 000FFF10H ⎯ ⎯ External interrupt 12 to 39* 60 3C ICR44 0x46C 30CH 000FFF0CH ⎯ ⎯ ROM correction interrupt 61 3D ICR45 0x46D 308H 000FFF08H ⎯ ⎯ DMA 62 3E ICR46 0x46E 304H 000FFF04H ⎯ ⎯ Delay interrupt 63 3F ICR47 0x46F 300H 000FFF00H IC0 I C 1/UDC 2 DS07-16801-3E ⎯ ⎯ (Continued) 47 MB91270 Series (Continued) Interrupt number Interrupt level Interrupt vector DMA Offset TBR default address RN Stop ⎯ 2FCH 000FFEFCH ⎯ ⎯ ⎯ ⎯ 2F8H 000FFEF8H ⎯ ⎯ 42 ⎯ ⎯ 2F4H 000FFEF4H ⎯ ⎯ 67 43 ⎯ ⎯ 2F0H 000FFEF0H ⎯ ⎯ System reserved 68 44 ⎯ ⎯ 2ECH 000FFEECH ⎯ ⎯ System reserved 69 45 ⎯ ⎯ 2E8H 000FFEE8H ⎯ ⎯ System reserved 70 46 ⎯ ⎯ 2E4H 000FFEE4H ⎯ ⎯ System reserved 71 47 ⎯ ⎯ 2E0H 000FFEE0H ⎯ ⎯ System reserved 72 48 ⎯ ⎯ 2DCH 000FFEDCH ⎯ ⎯ System reserved 73 49 ⎯ ⎯ 2D8H 000FFED8H ⎯ ⎯ System reserved 74 4A ⎯ ⎯ 2D4H 000FFED4H ⎯ ⎯ System reserved 75 4B ⎯ ⎯ 2D0H 000FFED0H ⎯ ⎯ System reserved 76 4C ⎯ ⎯ 2CCH 000FFECCH ⎯ ⎯ System reserved 77 4D ⎯ ⎯ 2C8H 000FFEC8H ⎯ ⎯ System reserved 78 4E ⎯ ⎯ 2C4H 000FFEC4H ⎯ ⎯ System reserved 79 4F ⎯ ⎯ 2C0H 000FFEC0H ⎯ ⎯ 50 to FF ⎯ ⎯ 2BCH to 000H 000FFEBCH to 000FFC00H ⎯ ⎯ Interrupt source Decimal Hexadecimal System reserved (REALOS) 64 40 ⎯ System reserved (REALOS) 65 41 System reserved 66 System reserved Used by INT instruction 80 to 255 Register Address * : CAN1, CAN2, and external interrupts 16 to 39 are only available on the MB91V280. 48 DS07-16801-3E MB91270 Series ■ PIN STATES IN EACH CPU STATE • Pin states in single-chip mode At initialization Port name Specified function Function name name P00 INT8 SIN5 P00 P01 INT9 SOT5 P01 P02 INT10 SCK5 P02 P03 INT11 SIN6 P03 P04 INT12 SOT6 P04 P05 INT13 SCK6 P05 P06 INT14 P06 P07 INT15 P07 P10 TIN1 P10 P11 TOT1 P11 P12 SIN3 INT11R P12 P13 SOT3 P13 P14 SCK3 P14 P15 SIN4 P15 P16 SOT4 P16 P17 SCK4 P17 P20 PPG9 P20 P21 PPGB P21 P22 PPGD P22 P23 PPGF P23 P24 IN0 P24 P25 IN1 P25 P26 IN2 P26 P27 IN3 P27 Sleep Internal ROM mode vector (MD2-0 = 000) INIT In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 RST Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled (Continued) DS07-16801-3E 49 MB91270 Series At initialization Port name Specified function Function name name P30 IN4 P30 P31 IN5 P31 P32 RX2 INT10R P32 P33 TX2 P33 P34 OUT4 P34 P35 OUT5 P35 P36 OUT6 P36 P37 OUT7 P37 P40 ⎯ P40 P41 ⎯ P41 P42 IN6 INT9R P42 P43 IN7 P43 P44 SDA0 FRCK0 P44 P45 SCL0 FRCK1 AIN2 P45 P46 SDA1 BIN2 P46 P47 SCL1 ZIN2 P47 P50 AN8 SIN2 P50 P51 AN9 SOT2 P51 P52 AN10 SCK2 P52 P53 AN11 BIN1 P53 P54 AN12 AIN1 P54 Sleep Internal ROM mode vector (MD2-0 = 000) INIT In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 RST *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled (Continued) 50 DS07-16801-3E MB91270 Series At initialization Port name Specified function Function name name P55 AN13 ZIN1 P55 P56 AN14 DAO0 P56 P57 AN15 DAO1 P57 P60 AN0 PPG0 P60 P61 AN1 PPG2 P61 P62 AN2 PPG4 P62 P63 AN3 PPG6 P63 P64 AN4 PPG8 P64 P65 AN5 PPGA P65 P66 AN6 PPGC P66 P67 AN7 PPGE P67 P70 AN16 INT0 P70 P71 AN17 INT1 P71 P72 AN18 INT2 P72 P73 AN19 INT3 P73 P74 AN20 INT4 P74 P75 AN21 INT5 P75 P76 AN22 INT6 SDA2 P76 P77 AN23 INT7 SCL2 P77 Sleep Internal ROM mode vector (MD2-0 = 000) INIT In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 RST Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled (Continued) DS07-16801-3E 51 MB91270 Series At initialization Port name Specified function Function name name P80 TIN0 ADTG INT12R P80 P81 TOT0 CKOT INT13R P81 P82 SIN0 TIN2 INT14R P82 P83 SOT0 TOT2 P83 P84 SCK0 INT15R P84 P85 SIN1 P85 P86 SOT1 P86 P87 SCK1 P87 P90 PPG1 P90 P91 PPG3 AIN3 P91 P92 PPG5 BIN3 P92 P93 PPG7 ZIN3 P93 P94 OUT0 AIN0 P94 P95 OUT1 BIN0 P95 P96 OUT2 ZIN0 P96 P97 OUT3 P97 PA0 RX0 INT8R PA0 PA1 TX0 PA1 PB0 INT8-2 SIN5-2 PB0 Sleep Internal ROM mode vector (MD2-0 = 000) INIT In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 RST *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 *2 (Continued) 52 DS07-16801-3E MB91270 Series At initialization Port name Specified function Function name name PB1 INT9-2 SOT5-2 PB1 PB2 INT10-2 SCK5-2 PB2 PB3 INT11-2 SIN6-2 PB3 PB4 INT12-2 SOT6-2 PB4 PB5 INT13-2 SCK6-2 PB5 PC0 OUT4-2 INT0R PC0 PC1 OUT5-2 INT1R PC1 PC2 SIN3-2 INT2R PC2 PC3 SOT3-2 INT3R PC3 PC4 SCK3-2 INT4R PC4 PC5 SIN4-2 INT5R PC5 PC6 SOT4-2 INT6R PC6 PC7 SCK4-2 INT7R PC7 Sleep Internal ROM mode vector (MD2-0 = 000) INIT In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 RST Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *2 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled (Continued) DS07-16801-3E 53 MB91270 Series At initialization Specified Port function name Function name name PD0 PPG9-2 INT16 PD0 PD1 PPGB-2 INT17 PD1 PD2 PPGD-2 INT18 PD2 PD3 PPGF-2 INT19 PD3 PD4 IN0-2 INT20 PD4 PD5 IN1-2 INT21 PD5 PD6 IN2-2 INT22 PD6 PD7 IN3-2 INT23 PD7 PE0 INT24 PE0 PE1 INT25 PE1 PE2 INT26 PE2 PE3 INT27 PE3 PE4 INT28 PE4 PE5 INT29 PE5 PE6 INT30 PE6 PE7 INT31 PE7 PF0 INT32 PF0 PF1 INT33 PF1 PF2 INT34 PF2 PF3 INT35 PF3 PF4 INT36 PF4 PF5 INT37 PF5 PF6 INT38 PF6 PF7 INT39 PF7 Sleep Internal ROM mode vector (MD2-0 = 000) INIT In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 RST Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled (Continued) 54 DS07-16801-3E MB91270 Series (Continued) At initialization Port name Specified function Function name name PG0 AN24 PG0 PG1 AN25 PG1 PG2 AN26 PG2 PG3 AN27 PG3 PG4 AN28 PG4 PG5 AN29 PG5 PG6 AN30 PG6 PG7 AN31 PG7 Sleep Internal ROM mode vector (MD2-0 = 000) INIT In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 RST Output Hi-Z Output Hi-Z Output Hi-Z Maintain Maintain Input Input Input previous state previous state disconnect enabled enabled *1 *1 : Pins become inputs and can be used to wakeup from STOP mode when the corresponding external interrupt is enabled in ENIR and the pin is selected as an external interrupt input pin in EISSR. *2 : Pins will be available to input and can be used to restore from the STOP mode when the corresponding external interrupt is enabled in ENIR and the pin is selected as an external interrupt input pin in EPFR. Input enabled Input disconnect : This indicates that the input function is available in this state. : Disconnects the external input at the input gate immediately adjacent to the pin . An "L" level is passed to internal circuits. Output Hi-Z : Turns the pin to high-impedance by preventing the pin drive transistor from driving. Output maintained : Indicates that pins maintain the output level they had prior to changing to this mode. In other words, the pin outputs the value in accordance with the peripheral operation if the internal peripheral that uses the output is operating, and the pin maintains its output level if the pin is set as a port. Maintain previous state : Indicates that output pins maintain the output level they had prior to this mode, or input pins continue to operate. DS07-16801-3E 55 MB91270 Series • Pin states in external bus mode • The external bus interface pins will be in an output mode while the device is in the settings initialization (INIT) state. The pins is in the Hi-Z state while the INIT pin is at the “L” level. The value listed in the table is output when the INIT pin goes to the “H” level. • The external bus interface output functions for ports 2, 3, 9, E, and F can be disabled by setting EPFR. The symbols in the table indicate : B : External bus interface function mode (EPFR = 0) P : General-purpose port or peripheral function mode (EPFR = 1) In stop mode In RTC mode At a initial/reset Port name Specified function Function name name P00 AD00 INT8 SIN5 AD00 P01 AD01 INT9 SOT5 AD01 P02 AD02 INT10 SCK5 AD02 P03 AD03 INT11 SIN6 AD03 P04 AD04 INT12 SOT6 AD04 P05 AD05 INT13 SCK6 AD05 P06 AD06 INT14 AD06 P07 AD07 INT15 AD07 Initial Value External ROM mode vector (MD2-0 = 001) Output Hi-Z Input enabled Internal ROM mode vector (MD2-0 = 000) Output Hi-Z Input enabled Sleep Remarks Sub sleep HIZ = 0 Address output (MPX) Output Hi-Z Input enabled (Data) HIZ = 1 Output Hi-Z Input disconnect *1 (Continued) 56 DS07-16801-3E MB91270 Series In stop mode In RTC mode At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) P10 AD08 TIN1 AD08 P11 AD09 TOT1 AD09 P12 AD10 SIN3 INT11R AD10 P13 AD11 SOT3 AD11 P14 AD12 SCK3 AD12 P15 AD13 SIN4 AD13 P16 AD14 SOT4 AD14 P17 AD15 SCK4 AD15 P20 A16 PPG9 A16 P21 A17 PPGB A17 P22 A18 PPGD A18 P23 A19 PPGF A19 P24 A20 IN0 A20 P25 A21 IN1 A21 P26 A22 IN2 A22 P27 A23 IN3 A23 Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 Output Hi-Z Input enabled Output Hi-Z Input enabled Address output (MPX) Output Hi-Z Input Output Hi-Z Input disconnect enabled (Data) Output Hi-Z Input enabled Output Hi-Z Input enabled Address output (MPX) Output Hi-Z Input Output Hi-Z Input disconnect enabled (Data) Output 0xFF Output Hi-Z Input enabled B : Address output P : Maintain previous state Output Hi-Z Input disconnect *1 *2 (Continued) DS07-16801-3E 57 MB91270 Series In stop mode In RTC mode At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) P30 AS IN4 AS P31 RD IN5 RD P32 WR0 RX2 INT10R WR0 P33 WR1 TX2 WR1 P34 OUT4 P34 P35 OUT5 P35 P36 RDY OUT6 RDY Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 *2 B : “H” level output “H” level output P : Maintain previous state *1 *2 *2 Output Hi-Z Input enabled Output Maintain previous state Hi-Z Output Hi-Z Input Input enabled B : Output Hi-Z disconnect P : Maintain previous state B: B: “H” level Clock output output P37 SYSCLK OUT7 P37 P40 ⎯ P40 P41 ⎯ P41 P42 IN6 INT9R P42 P43 IN7 P43 P44 SDA0 FRCK0 P44 Clock output P: Maintain previous state P: Maintain previous state *2 Same as single-chip mode (Continued) 58 DS07-16801-3E MB91270 Series In stop mode In RTC mode At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) P45 SCL0 AIN2 FRCK1 P45 P46 SDA1 BIN2 P46 P47 SCL1 ZIN2 P47 P50 AN8 SIN2 P50 P51 AN9 SOT2 P51 P52 AN10 SCK2 P52 P53 AN11 BIN1 P53 P54 AN12 AIN1 P54 P55 AN13 ZIN1 P55 P56 AN14 DAO0 P56 P57 AN15 DAO1 P57 P60 AN0 PPG0 P60 P61 AN1 PPG2 P61 P62 AN2 PPG4 P62 P63 AN3 PPG6 P63 P64 AN4 PPG8 P64 P65 AN5 PPGA P65 P66 AN6 PPGC P66 P67 AN7 PPGE P67 Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 Same as single-chip mode Same as single-chip mode Same as single-chip mode (Continued) DS07-16801-3E 59 MB91270 Series At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) P70 AN16 INT0 P70 P71 AN17 INT1 P71 P72 AN18 INT2 P72 P73 AN19 INT3 P73 P74 AN20 INT4 P74 P75 AN21 INT5 P75 P76 AN22 INT6 SDA2 P76 P77 AN23 INT7 SCL2 P77 P80 TIN0 ADTG INT12R P80 P81 TOT0 CKOT INT13R P81 P82 SIN0 TIN2 INT14R P82 P83 SOT0 TOT2 P83 P84 SCK0 INT15R P84 P85 SIN1 P85 P86 SOT1 P86 P87 SCK1 P87 Sleep In stop mode In RTC mode Remarks Sub sleep HIZ = 0 HIZ = 1 Same as single-chip mode Same as single-chip mode (Continued) 60 DS07-16801-3E MB91270 Series In stop mode In RTC mode At a initial/reset Port name Specified Initial Value function Function External ROM Internal ROM name name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) P90 CS0 PPG1 CS0 P91 CS1 PPG3 AIN3 CS1 P92 CS2 PPG5 BIN3 CS2 P93 CS3 PPG7 ZIN3 CS3 P94 OUT0 AIN0 P94 P95 OUT1 BIN0 P95 P96 OUT2 ZIN0 P96 P97 OUT3 P97 PA0 RX0 INT8R PA0 PA1 TX0 PA1 PB0 INT8-2 SIN5-2 PB0 PB1 INT9-2 SOT5-2 PB1 PB2 INT10-2 SCK5-2 PB2 PB3 INT11-2 SIN6-2 PB3 PB4 INT12-2 SOT6-2 PB4 PB5 INT13-2 SCK6-2 PB5 Sleep Remarks Sub sleep HIZ = 0 B : “H” level output Output Hi-Z “H” level output Input enabled P : Maintain previous state HIZ = 1 Output Hi-Z Input disconnect *2 Same as single-chip mode Same as single-chip mode Same as single-chip mode (Continued) DS07-16801-3E 61 MB91270 Series In stop mode In RTC mode At a initial/reset Port name Specified function Function name name PC0 OUT4-2 INT0R PC0 PC1 OUT5-2 INT1R PC1 PC2 SIN3-2 INT2R PC2 PC3 SOT3-2 INT3R PC3 PC4 SCK3-2 INT4R PC4 PC5 SIN4-2 INT5R PC5 PC6 SOT4-2 INT6R PC6 PC7 SCK4-2 INT7R PC7 PD0 PPG9-2 INT16 PD0 PD1 PPGB-2 INT17 PD1 PD2 PPGD-2 INT18 PD2 PD3 PPGF-2 INT19 PD3 PD4 IN0-2 INT20 PD4 PD5 IN1-2 INT21 PD5 PD6 IN2-2 INT22 PD6 PD7 IN3-2 INT23 PD7 Initial Value External ROM mode vector (MD2-0 = 001) Internal ROM mode vector (MD2-0 = 000) Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 Same as single-chip mode Same as single-chip mode Same as single-chip mode (Continued) 62 DS07-16801-3E MB91270 Series In stop mode In RTC mode At a initial/reset Port name Specified Initial Value function Function name External ROM Internal ROM name mode vector mode vector (MD2-0 = 001) (MD2-0 = 000) PE0 A00 INT24 A00 PE1 A01 INT25 A01 PE2 A02 INT26 A02 PE3 A03 INT27 A03 PE4 A04 INT28 A04 PE5 A05 INT29 A05 PE6 A06 INT30 A06 PE7 A07 INT31 A07 PF0 A08 INT32 A08 PF1 A09 INT33 A09 PF2 A10 INT34 A10 PF3 A11 INT35 A11 PF4 A12 INT36 A12 PF5 A13 INT37 A13 PF6 A14 INT38 A14 PF7 A15 INT39 A15 PG0 AN24 PG0 PG1 AN25 PG1 PG2 AN26 PG2 PG3 AN27 PG3 Sleep Remarks Sub sleep HIZ = 0 B : Address output “H” level output Output Hi-Z Input enabled “H” level output Output Hi-Z Input enabled P : Maintain previous state B : Address output P : Maintain previous state HIZ = 1 Output Hi-Z Input disconnect *1 *2 Output Hi-Z Input disconnect *1 *2 Same as single-chip mode (Continued) DS07-16801-3E 63 MB91270 Series (Continued) In stop mode In RTC mode At a initial/reset Port name Specified function Function name name PG4 AN28 PG4 PG5 AN29 PG5 PG6 AN30 PG6 PG7 AN31 PG7 Initial Value External ROM mode vector (MD2-0 = 001) Internal ROM mode vector (MD2-0 = 000) Sleep Remarks Sub sleep HIZ = 0 HIZ = 1 Same as single-chip mode *1 : Pins become inputs and can be used to wakeup from STOP mode when the corresponding external interrupt is enabled in ENIR and the pin is selected as an external interrupt input pin in EISSR. *2 : Outputs go to Hi-Z at power on or while the INIT pin is at the “L” level starting from the falling edge on the INIT pin. Input enabled Input disconnect : This indicates that the input function is available in this state. : Disconnects the external input at the input gate immediately adjacent to the pin . An "L" level is passed to internal circuits. Output Hi-Z : Turns the pin to high-impedance by preventing the pin drive transistor from driving. Output maintained : Indicates that pins maintain the output level they had prior to changing to this mode. In other words, the pin outputs the value in accordance with the peripheral operation if the internal peripheral that uses the output is operating, and the pin maintains its output level if the pin is set as a port. Maintain previous state : Indicates that output pins maintain the output level they had prior to this mode, or input pins continue to operate. 64 DS07-16801-3E MB91270 Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol Rating Unit Remarks Min Max VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*1 AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH VI VSS − 0.3 VCC + 0.3 V VO VSS − 0.3 VCC + 0.3 V “L” level maximum output current* IOL1 ⎯ 15 mA “L” level average output current*3 IOLAV1 ⎯ 4 mA “L” level total maximum output current ΣIOL1 ⎯ 120 mA “L” level total average output current*4 ΣIOLAV1 ⎯ 50 mA IOH1 ⎯ − 15 mA IOHAV1 ⎯ −4 mA ΣIOH1 ⎯ − 120 mA ΣIOHAV1 ⎯ − 50 mA Power consumption PD ⎯ 500 mW Operating temperature TA − 40 + 105 °C Single-chip mode − 40 + 85 °C External bus mode Tstg − 55 + 150 °C IIHH ⎯ 2 mA Power supply voltage Input voltage Output voltage 2 “H” level maximum output current* “H” level average output current* 2 3 “H” level total maximum output current 4 “H” level total average output current* Storage temperature +B Input rating (Maximum clamp current) *5 *1 : Ensure that AVCC does not exceed VCC when the power is turned on. *2 : The maximum output current specifies the peak current for an individual pin. *3 : The average output current specifies the average current that flows through an individual pin over a period of 100 ms. The average value is the operating current × operation ratio. *4 : The total average output current specifies the average current that flows through all of the pins over a period of 100 ms. The average value is the operating current × operation ratio. *5 : The +B input rating specifies the current for an individual pin. [Pins applicable] P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0, PA1, PB0 to PB5, PC0 to PC7, PD0 to PD7, PE0 to PE7, PF0 to PF7, PG0 to PG7 (+B input to P56 and P57 not allowed on the MB91V280.) WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. DS07-16801-3E 65 MB91270 Series [ For +B input (12V to 16V) ] 1. Do not connect the +B potential directly to a microcontroller pin. 2. Always place a current-limiting resistor between the +B signal and microcontroller pins. IIHH = 2mA per pin (Max) [during normal operation and during transients such as when turning the power on or off] 3. Although the internal protection diode in the microcontroller causes the potential between the +B input-limiting resistor and microcontroller pin to be equal to the VCC + on voltage of the protection diode, do not use a circuit structure that obstructs this operation or that causes this potential to be exceeded. Sample recommended circuits: Protection diode IIHH Current-limiting resistor + B input (0 V to 16 V) 66 DS07-16801-3E MB91270 Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage Symbol Value Unit Remarks Min Max VCC AVCC 4.5 5.5 V Normal operation VCC AVCC 3.5 5.5 V Excluding A/D converter operation VCC 3.0 5.5 V Maintain RAM data during STOP mode μF Use a ceramic capacitor or a capacitor of similar frequency characteristics. On the Vcc pin, use a bypass capacitor with a larger capacity than that of Cs. Smoothing capacitor* CS Operating temperature TA 1 ( ± 50 % tolerance) − 40 + 105 °C Single-chip mode − 40 + 85 °C External bus mode * : Refer to the following figure for connection of smoothing capacitor Cs. • C Pin Connection Diagram C CS VSS AVSS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. DS07-16801-3E 67 MB91270 Series 3. DC Characteristics (TA : Recommended Operating Conditions, VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V) Parameter SymCondiPin name bol tions Value Min Typ Max Unit Remarks VIHS ⎯ ⎯ 0.8 × VCC ⎯ VCC + 0.3 V CMOS automotive input VIHC ⎯ ⎯ 0.7 × VCC ⎯ VCC + 0.3 V CMOS Schmitt input VIHT ⎯ ⎯ 2.1 ⎯ VCC + 0.3 V TTL input*1 VIHM MD0 MD1 MD2 ⎯ VCC − 0.3 ⎯ VCC + 0.3 V VIHI INIT ⎯ 0.8 × VCC ⎯ VCC + 0.3 V VILS ⎯ ⎯ VSS − 0.3 ⎯ 0.5 × VCC V CMOS automotive input VILC ⎯ ⎯ VSS − 0.3 ⎯ 0.3 × VCC V CMOS Schmitt input VILT ⎯ ⎯ VSS − 0.3 ⎯ 0.8 V TTL input*1 VILM MD0 MD1 MD2 ⎯ VSS − 0.3 ⎯ VSS + 0.3 V VILI INIT ⎯ VSS − 0.3 ⎯ 0.2 × VCC V ICC VCC *2 ⎯ 100 120 mA Normal operation*11 *3 ⎯ 70 90 mA Normal operation*11 ICCS VCC *4 ⎯ 40 55 mA SLEEP operation*11 *5 ⎯ 20 30 mA SLEEP operation*11 ICCL VCC *6 ⎯ 400 700 μA Sub operation ICCSL VCC *7 ⎯ 300 600 μA Sub-SLEEP operation ICCR32 VCC *8 ⎯ 200 300 μA 32 kHz clock operation *12 ICCR4 VCC *9 ⎯ 700 1000 μA 4 MHz clock operation*12 ICCH VCC *10 ⎯ 20 100 μA STOP Input leak current IIL ⎯ ⎯ −5 ⎯ 5 μA All input pins Input capacitance CIN ⎯ ⎯ ⎯ 5 15 pF Pull-up resistor RUP ⎯ ⎯ 25 50 100 kΩ Selectable except for P44 to P47, P56, P57, P76, and P77 RDOWN ⎯ ⎯ 25 50 100 kΩ Selectable except for P44 to P47, P56, P57, P76, and P77 “H” level input voltage “L” level input voltage Power supply current Pull-down resistor (Continued) 68 DS07-16801-3E MB91270 Series (Continued) Parameter Symbol Pin name “H” level Output voltage “L” level Output voltage Remarks IOH = − 4 mA VCC − 0.5 ⎯ ⎯ V Other than P44 to P47, P76 and P77 P44 to P47 IOH = − 3 mA VCC − 0.5 P76, P77 ⎯ ⎯ V Pins also used for I2C ⎯ Min Unit Max IOL = 4 mA ⎯ ⎯ 0.4 V Other than P44 to P47, P76 and P77 P44 to P47 IOL = 3 mA P76, P77 ⎯ ⎯ 0.4 V Pins also used for I2C ⎯ VOL VOLI Value Typ VOH VOHI Conditions *1 : In external bus mode, only P00 to P07, P10 to P17, and P36 can be selected. *2 : CLKB = 32 MHz, CLKP = 32 MHz, CLKT = 16 MHz, CANCLK = 16 MHz *3 : CLKB = 32 MHz, CLKP = 8 MHz, CLKT = 4 MHz, CANCLK = 8 MHz *4 : CPU halted for case *2. *5 : CPU halted for case *3. *6 : CLKB = CLKP = CLKT = CANCLK = 32 kHz, TA = + 25 °C *7 : CPU halted for case *6 *8 : CPU and peripheral circuits halted, main oscillation halted, 32 kHz clock operation, TA= + 25 °C *9 : CPU and peripheral circuits halted, sub-oscillation halted, 4 MHz clock operation, TA= + 25 °C *10 : CPU and peripheral circuits halted, all oscillation circuits halted, TA = + 25 °C *11 : The current consumption values for normal operation mode and SLEEP mode assume that the peripheral circuits are operating at maximum capacity. *12 : The current consumption value for clock mode operation does not include the consumption of the external oscillator. DS07-16801-3E 69 MB91270 Series 4. Flash Memory Program and Erase Characteristics Parameter Conditions Value Min Typ Max Unit Remarks Sector erase time TA = + 25 °C VCC = 5.0 V ⎯ 1 5 s Excludes time for internal write prior to erase. Chip erase time TA = + 25 °C VCC = 5.0 V ⎯ 14 ⎯ s Excludes time for internal write prior to erase. Half-word write time TA = + 25 °C VCC = 5.0 V ⎯ 16 3600 μs Excludes system-level overhead time. Chip write time TA = + 25 °C VCC = 5.0 V ⎯ 2.1 ⎯ s Excludes system-level overhead time. ⎯ 10000 ⎯ ⎯ cycle Average TA = + 85 °C 20* ⎯ ⎯ year Erase/Write cycle Data retention time * : Calculated value based on technology reliability test data. (Value calculated using the Arrhenius equation for the burn-in test results with an average temperature of + 85 °C.) 70 DS07-16801-3E MB91270 Series 5. AC Characteristics (TA : Recommended Operating Conditions, VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V) Parameter Source oscillation clock frequency Symbol Pin name FC Conditions Value Unit Min Typ Max X0, X1 ⎯ 4 12 MHz FCA X0A, X1A ⎯ 32.768 100 kHz Remarks Source oscillation clock cycle time tCYL X0, X1 83.3 250 ⎯ ns tCYLL X0A, X1A 10 30.5 ⎯ μs Input clock pulse width PWH PWL X0 30 ⎯ ⎯ ns Use a duty ratio in the range 40 % to 60 %. tcr, tcf X0 ⎯ ⎯ 5 ns When external clock is used Internal operation clock frequency FCP ⎯ ⎯ ⎯ 32 MHz When main clock, PLL clock are used. Internal operation clock cycle time tCP ⎯ 31.25 ⎯ ⎯ ns When main clock, PLL clock are used. Input clock rise time and fall time ⎯ X0, X1 Clock Timing tCYL 0.8 VCC X0 0.2 VCC PWH DS07-16801-3E tcf PWL tcr 71 MB91270 Series • Operation Assurance Range Relation between internal operation clock frequency and power supply voltage Recommended operation range (A/D converter accuracy guarantee range) Operation Assurance Range Power supply voltage VCC (V) 5.5 4.5 3.5 PLL operation guarantee range 2 8 32 Internal operation clock frequency FCP (MHz) Note : Use a PLL operation stabilization wait time of 500 μs or more. Relation between oscillation clock frequency and internal operation clock Internal operation clock frequency PLL clock Main clock PLL multi- PLL multi- PLL multi- PLL multi- PLL multiplication plication plication plication plication rate = 6 rate = 8 rate = 4 rate = 2 rate = 3 Oscillation clock frequency 4 MHz 2 MHz 8 MHz 12 MHz 16 MHz 24 MHz 32 MHz 8 MHz 4 MHz 16 MHz 24 MHz 32 MHz ⎯ ⎯ 12 MHz 6 MHz 24 MHz ⎯ ⎯ ⎯ ⎯ Sample oscillation circuit X0 X1 R C1 72 C2 DS07-16801-3E MB91270 Series The AC standards assume the following measurement reference voltages. Input signal waveform Output signal waveform Hysteresis input pin Output pin 0.7 VCC 4.6 V 0.3 VCC 0.4 V Hysteresis input pin (Automotive) 0.8 VCC 0.5 VCC ⎯ TTL input pin ⎯ 2.1 V 0.8 V DS07-16801-3E 73 MB91270 Series • Reset input (TA : Recommended Operating Conditions, VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin name INIT input time tINTL Conditions ⎯ INIT Value Unit Remarks Min Max 10 ⎯ μs 300 ⎯ μs At STOP 8 ⎯ ms At power-on tINTL INIT 0.2 VCC 0.2 VCC The following reset input standard should be satisfied as RAM data protection standard. Voltage drop time VCC (V) External reset input standard (INIT) Min Max Min Max 256 tCP* ⎯ 300 μs ⎯ 3.5 V 3.5 V At drop of 4.0 ≥ 3.5 V * : tCP : Period of the internal base clock. VCC 4V INIT 300 μs or more 256 tCP To protect RAM data, input INIT of 256 tCP or more before voltage drop at VCC = 3.5 V or less. 74 DS07-16801-3E MB91270 Series • UART Timing (TA : Recommended Operating Conditions, VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V) Parameter Symbol Serial clock cycle time tSCYC SCK↓→SOT delay time tSLOV Valid SIN→SCK↑ tIVSH SCK↑→ valid SIN hold time tSHIX Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH Pin name Conditions Value Unit Min Max SCKx 8 tCP ⎯ ns SCKx SOTx − 80 + 80 ns 100 ⎯ ns 60 ⎯ ns 4 tCP ⎯ ns 4 tCP ⎯ ns ⎯ 150 ns 60 ⎯ ns 60 ⎯ ns ⎯ SCKx SINx Remarks Internal shift clock mode Output pin capacitance is CL = 80 pF + 1 × TTL SCKx SCK↓→SOT delay time tSLOV Valid SIN→SCK↑ tIVSH SCK↑→ valid SIN hold time tSHIX SCKx SOTx SCKx SINx ⎯ External shift clock mode Output pin capacitance is CL = 80 pF + 1 × TTL Note : These are AC Characteristics in the clock synchronous mode. CL is the load capacitance connected to the pin for testing. DS07-16801-3E 75 MB91270 Series • Internal shift clock mode tSCYC 2.4 V SCKx 0.8 V 0.8 V tSLOV 2.4 V SOTx 0.8 V tIVSH SINx tSHIX 0.8 VCC 0.8 VCC 0.5 VCC 0.5 VCC • External shift clock mode tSLSH tSHSL 0.8 VCC SCKx 0.8 VCC 0.6 VCC 0.6 VCC tSLOV 2.4 V SOTx 0.8 V tIVSH SINx 76 tSHIX 0.8 VCC 0.8 VCC 0.5 VCC 0.5 VCC DS07-16801-3E MB91270 Series • Timer input timing (TA : Recommended Operating Conditions, VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V) Parameter Symbol Pin name Conditions Input pulse width tTIWH tTIWL TINx INx ⎯ tTIWH TINx INx DS07-16801-3E 0.8 VCC Value Min Max 4 tCP ⎯ Unit Remarks ns ⎯ tTIWL 0.8 VCC 0.5 VCC 0.5 VCC 77 MB91270 Series 6. Electrical Characteristics for the A/D Converter • Electrical characteristics (TA : Recommended Operating Conditions, VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V) Symbol Pin name Resolution ⎯ Total error Parameter Value Unit Remarks Min Typ Max ⎯ ⎯ ⎯ 10 bit ⎯ ⎯ ⎯ ⎯ ± 3.0 LSB Nonlinear error ⎯ ⎯ ⎯ ⎯ ± 2.5 LSB Differential linear error ⎯ ⎯ ⎯ ⎯ ± 1.9 LSB Zero transition voltage VOT AN0 to AN23 AVSS AVSS AVSS − 1.5 LSB + 0.5 LSB + 2.5 LSB V Full-scale transition voltage VFST AN0 to AN23 AVRH AVRH AVRH − 3.5 LSB − 1.5 LSB + 0.5 LSB V Sampling time tSMP ⎯ 1.375 ⎯ ⎯ μs *1 Compare time tCMP ⎯ 1.375 ⎯ ⎯ μs *2 A/D conversion time tCNV ⎯ 2.750 ⎯ ⎯ μs *3 Analog port input current IAIN AN0 to AN23 ⎯ ⎯ 10 μA VAVSS ≤ VAIN ≤ VAVCC Analog input voltage VAIN AN0 to AN23 0 ⎯ AVRH V AVRH AVRH 4.0 ⎯ AVCC V ⎯ 2.4 4.7 mA ⎯ ⎯ 5 μA *4 ⎯ 600 900 μA VAVRH = 5.0 V ⎯ ⎯ 5 μA *4 ⎯ ⎯ 4 LSB Reference voltage Power supply current IA IAH IR Reference voltage supplying current IRH Interchannel disparity ⎯ AVCC AVRH AN0 to AN31 1 LSB = (AVRH − AVSS) / 1024 *1 : For FCP = 32 MHz, tSMP = (Rext + Rin) × Cin × 7 = ST × CLKP period = 2 ch × 31.25 ns = 1.375 μs *2 : For FCP = 32 MHz, tCMP = CKIN × 11 = CT × CLKP period × 11 = 4 h × 31.25 ns × 11 = 1.375 μs *3 : For FCP = 32 MHz, this is equivalent to the conversion time per channel when tSMP and tCMP are selected. *4 : Specifies the power supply current when the A/D converter is not operating and the CPU is in stop mode (Vcc = AVcc = AVRH = 5.0 V) Notes : •The error becomes proportionately larger as the AVRH voltages go lower. • Use the device with external circuits of the following output impedance rS for analog inputs : External circuit output impedance rS = 5 kΩ (Max) • If the output impedance of the external circuit is too high, the analog voltage sampling time may be insufficient. • If inserting a capacitor between the external circuit and an input pin to prevent direct current flow, select a capacitance several thousand times larger than CSH to minimize the capacitive voltage divider effect due to the CSH sampling capacitor in the chip. 78 DS07-16801-3E MB91270 Series • Analog input equivalent circuit Microcontroller internal circuit External circuit Input pin AN0 RSH rS CSH Comparator Input pin AN7 S/H circuit VS Analog channel selector < Recommended parameter values for each component > rS : under 5 kΩ RSH = Approx. 2.5 kΩ CSH = Approx. 10 pF Note : Parameter values for each component are indicative design values. DS07-16801-3E 79 MB91270 Series • Definition of terminology Resolution Represents the change in analog signal enabled to be detected by the A/D converter. For 10-bit conversion, the analog voltage can be resolved into 210 = 1024 increments. Total error This error indicates the difference between actual and theoretical values, and is the total value of errors that results from offset error, gain error, nonlinear error, and noise. Linearity error Represents the difference between the actual conversion characteristic and the line between the zero transition point (“00 0000 0000” ←→ “00 0000 0001”) and full scale transition point (“11 1111 1110”←→ “11 1111 1111”). Differential linear error Deviation of input voltage, which is required for changing output code by 1 LSB, from a desired value. 80 DS07-16801-3E MB91270 Series • Conversion characteristics for 10-bit A/D converter 11 1111 1111 11 1111 1110 11 1111 1101 11 1111 1100 Digital output 1 LSB × N + VOT Linearity error 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N+1)T VFST Analog input VOT = AVSS + 0.5 LSB [V] (theoretical value) VFST = AVRH − 1.5 LSB [V] (theoretical value) VFST = Digital output voltage at which transition from (N − 1) to N occurs. 1 LSB = Linearity error = Differential linear error = DS07-16801-3E VFST − VOT 1022 VNT − (1 LSB × N + VOT) 1 LSB [LSB] V (N + 1) T − VNT 1 LSB [LSB] −1 81 MB91270 Series ■ ORDERING INFORMATION Part number Package Remarks MB91V280CR 401-pin ceramic PGA (PGA-401C-A02) Evaluation model MB91F273SPMC 100-pin plastic LQFP (FPT-100P-M05) Single clock model MB91F273PMC 100-pin plastic LQFP (FPT-100P-M05) Dual clock model 82 DS07-16801-3E MB91270 Series ■ PACKAGE DIMENSIONS 401-pin ceramic PGA Lead pitch 2.54 interstitial Pin matrix 37 Sealing method Metal seal (PGA-401C-A02) 401-pin ceramic PGA (PGA-401C-A02) 48.26 ± 0.55 SQ (1.900 ± .022) 2.54 (.100) TYP 0.40 ± 0.10 DIA (.016 ± .004) 1.00 (.039) DIA TYP (4 PLCS) 45.72 (1.800) REF INDEX AREA 1.02 (.040) C TYP (4 PLCS) 1.20 ± 0.25 (.047 ± .010) EXTRA INDEX PIN 3.40 ± 0.40 (.134 ± .016) 5.27 (.207) MAX C 1994-2008 FUJITSU MICROELECTRONICS LIMITED R401002SC-2-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. (Continued) DS07-16801-3E 83 MB91270 Series (Continued) 100-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 14.0 × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.65g Code (Reference) P-LFQFP100-14×14-0.50 (FPT-100P-M05) 100-pin plastic LQFP (FPT-100P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 100 26 1 25 C 84 0.20±0.05 (.008±.002) 0.08(.003) 2003-2008 FUJITSU MICROELECTRONICS LIMITED F100007S-c-4-7 M 0.10±0.10 (.004±.004) (Stand off) 0°~8° "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. DS07-16801-3E MB91270 Series ■ MAIN CHANGES IN THIS EDITION Page Section ⎯ ⎯ Change Results Deleted the part number MB91F278(S). 4 ■ FEATURES Deleted “• Clock supervisor”. 26 ■ HANDLING DEVICES Added “• Serial Communication”. The vertical lines marked in the left side of the page show the changes. DS07-16801-3E 85 MB91270 Series MEMO 86 DS07-16801-3E MB91270 Series MEMO DS07-16801-3E 87 MB91270 Series FUJITSU MICROELECTRONICS LIMITED Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department