Datasheet - Spansion

S29AL004D
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
Data Sheet
S29AL004D Cover Sheet
This product has been retired and is not recommended for designs. For new and current designs,
S29AL008J supercedes S29AL004D. This is the factory-recommended migration path. Please refer to the
S29AL008J data sheet for specifications and ordering information.
Availability of this document is retained for reference and historical purposes only.
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S29AL004D_00
Revision A
Amendment 6
Issue Date February 27, 2009
D at a
S hee t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
ii
S29AL004D
S29AL004D_00_A6 February 27, 2009
S29AL004D
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
Data Sheet
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
„ Single Power Supply Operation
„ High Performance
– 2.7 to 3.6 volt read and write operations for battery-powered
applications
„ Manufactured on 200 nm Process Technology
– Access times as fast as 55 ns
– Extended temperature range (-40°C to +125°C)
„ Ultra-low Power Consumption (typical values at 5 MHz)
– Compatible with 0.32 µm Am29LV400B and MBM29LV400T/BC
„ Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte
sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword
sectors (word mode)
– Supports full chip erase
„ Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
„ Top or Bottom Boot Block Configurations Available
–
–
–
–
200 nA Automatic Sleep mode current
200 nA standby mode current
9 mA read current
20 mA program/erase current
„ Cycling Endurance: 1,000,000 cycles per sector typical
„ Data Retention: 20 years typical
Package Options
„ 48-ball FBGA
„ 48-pin TSOP
„ 44-pin SO
„ Embedded Algorithms
– Embedded Erase algorithm automatically preprograms and erases
the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically writes and verifies data
at specified addresses
„ Compatibility with JEDEC Standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
„ Sector Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Software Features
„ Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase operation
completion
„ Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data to,
a sector that is not being erased, then resumes the erase operation
Hardware Features
„ Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
„ Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
Publication Number S29AL004D_00
Revision A
Amendment 6
Issue Date February 27, 2009
D at a
S hee t
General Description
The S29AL004D is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The
device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears
on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt
VCC supply to perform read, program, and erase operations. A standard EPROM programmer can also be
used to program and erase the device.
This device is manufactured using Spansion’s 200 nm process technology, and offers all the features and
benefits of the Am29LV400B and MBM29LV400T/BC, which were manufactured using 320 nm process
technology.
The standard device offers access times of 70 and 90 ns, allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally
generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using standard microprocessor write timings. Register
contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading
data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write
cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,
or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle is
completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. The hardware sector protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the
device enters the automatic sleep mode. The system can also place the device into the standby mode.
Power consumption is greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
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S29AL004D
S29AL004D_00_A6 February 27, 2009
Data
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Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.
Ordering Information (Standard Products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2
Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3
Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6
Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7
RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
11
11
11
11
12
12
13
14
14
16
8.
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4
Word/Byte Program Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
17
19
19
20
9.
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.5
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.6
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.7
DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
23
23
24
24
25
25
10.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12.
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
12.1 Zero Power Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13.
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14.
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
15.
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.2 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
16.
Erase And Programming Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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17.
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.1 TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm . . . . . . . . . . . . . . . . .
17.3 SO 044—44-Pin Small Outline Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
42
43
18.
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.1 Revision A0 (November 12, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.2 Revision A1 (February 18, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.3 Revision A2 (June 1, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.4 Revision A3 (June 21, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.5 Revision A4 (May 22, 2006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.6 Revision A5 (June 22, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.7 Revision A6 (February 27, 2009) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
44
44
44
45
45
45
45
S29AL004D
S29AL004D_00_A6 February 27, 2009
Data
1.
She et
Product Selector Guide
Family Part Number
S29AL004D
55
70
90
Max access time, ns (tACC)
55
70
90
Max CE# access time, ns (tCE)
55
70
90
Max OE# access time, ns (tOE)
25
30
35
Speed Options
Full Voltage Range: VCC = 2.7–3.6 V
Note
See AC Characteristics on page 31 for full specifications.
2. Block Diagram
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A17
February 27, 2009 S29AL004D_00_A6
S29AL004D
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3. Connection Diagrams
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard TSOP
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO
S29AL004D
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
S29AL004D_00_A6 February 27, 2009
Data
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FBGA
Top View, Balls Facing Down
3.1
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
F6
G6
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
BYTE# DQ15/A-1
H6
VSS
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
NC
NC
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA
packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity
may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of
time.
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S29AL004D
7
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4.
S hee t
Pin Configuration
A0–A17
DQ0–DQ14
DQ15/A-1
BYTE#
18 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
CE#
Chip enable
OE#
Output enable
WE#
Write enable
RESET#
Hardware reset pin, active low
RY/BY#
Ready/Busy# output
VCC
3.0 volt-only single power supply
(see Product Selector Guide on page 5 for speed options and voltage supply tolerances)
VSS
Device ground
NC
Pin not connected internally
5. Logic Symbol
18
A0–A17
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
8
S29AL004D
RY/BY#
S29AL004D_00_A6 February 27, 2009
Data
6.
She et
Ordering Information (Standard Products)
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J
supercedes S29AL004D. This is the factory-recommended migration path. Please refer to the S29AL008J
data sheet for specifications and ordering information.
Spansion standard products are available in several packages and operating ranges. The order number
(Valid Combination) is formed by a combination of the elements below.
S29AL004D
55
T
A
I
01
0
Packing Type
0 = Tray
1 = Tube
2 = 7” Tape and Reel
3 = 13” Tape and Reel
Model Number
01 = VCC = 2.7 - 3.6V, top boot sector device
R1 = VCC = 3.0 - 3.6V, top boot sector device
02 = VCC = 2.7 - 3.6V, bottom boot sector device
R2 = VCC = 3.0 - 3.6V, bottom boot sector device
Temperature Range
I = Industrial (-40°C to +85°C)
N = Extended (-40°C to +125°C)
Package Material Set
A = Standard
F = Pb-Free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
B = Fine-pitch Ball-Grid Array Package
M = Small Outline Package (SOP) Standard Pinout
Speed Option
55 = 55 ns Access Speed
70 = 70 ns Access Speed
90 = 90 ns Access Speed
Device Number/Description
S29AL004D
4 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase
S29AL004D Valid Combinations
Device Number
Speed
Option
Package Type,
Material, and
Temperature Range
Model
Number
TAI, TFI
01, 02
TAN, TFN
R1, R2
TAI, TFI, TAN, TFN
01, 02
BAI, BFI
01, 02
BAN, BFN
R1, R2
Packing Type
Package Description
55
70, 90
0, 3 (Note 1)
TS048 (Note 3)
TSOP
0, 2, 3 (Note 1)
VBK048 (Note 4)
Fine-Pitch
BGA
0, 1, 3 (Note 2)
SO044 (Note 3)
SOP
55
S29AL004D
70, 90
BAI, BFI, BAN, BFN
01, 02
MAI, MFI
01, 02
MAN, MFN
R1, R2
MAI, MFI, MAN, MFN
01, 02
55
70, 90
Notes
1. Type 0 is standard. Specify other options as required.
2. Type 1 is standard. Specify other options as required.
3. TSOP and SOP package markings omit packing type designator from ordering part number.
4. BGA package marking omits leading S29 and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
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7.
S hee t
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 7.1 S29AL004D Device Bus Operations
DQ8–DQ15
CE#
OE#
WE#
RESET#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
Read
L
L
H
H
AIN
DOUT
DOUT
Write
L
H
L
H
AIN
DIN
DIN
Operation
BYTE# = VIL
DQ8–DQ14 = High-Z,
DQ15 = A-1
VCC ± 0.3V
X
X
VCC ± 0.3V
X
High-Z
High-Z
Output Disable
L
H
H
H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
VID
Sector Address,
A6 = L, A1 = H,
A0 = L
DIN
X
X
Sector Unprotect (Note 2)
L
H
L
VID
Sector Address,
A6 = H, A1 = H,
A0 = L
DIN
X
X
Temporary Sector Unprotect
X
X
X
VID
AIN
DIN
DIN
High-Z
Standby
High-Z
Legend
L = Logic Low = VIL
H = Logic High = VIH
VID = 12.0 ± 0.5 V
X = Don’t Care
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/
Unprotection on page 14.
7.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
7.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
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S29AL004D
S29AL004D_00_A6 February 27, 2009
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See Reading Array Data on page 16 for more information. Refer to the AC Read Operations on page 31 for
timing specifications and to Figure 15.1 on page 31 for the timing diagram. ICC1 in DC Characteristics
on page 28 represents the active current specification for reading array data.
7.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or
words. Refer to Word/Byte Configuration on page 10 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The Word/
Byte Program Command Sequence on page 17 has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 7.2 on page 12 and
Table 7.3 on page 13 indicate the address space that each sector occupies. A sector address consists of the
address bits required to uniquely select a sector. The Command Definitions on page 16 has details on
erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 13 and
Autoselect Command Sequence on page 17 for more information.
ICC2 in DC Characteristics on page 28 represents the active current specification for the write mode. The AC
Characteristics on page 31 contains timing specification tables and timing diagrams for write operations.
7.4
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write
Operation Status on page 22 for more information, and to AC Characteristics on page 31 for timing
diagrams.
7.5
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
standard access time (tCE) for read access when the device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
In the DC Characteristics on page 28 table, ICC3 and ICC4 represents the standby current specification.
7.6
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. ICC4 in DC
Characteristics on page 28 represents the automatic sleep mode current specification.
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S29AL004D
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7.7
S hee t
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to the tables in AC Characteristics on page 31 for RESET# parameters and to Figure 15.2 on page 32
for the timing diagram.
7.8
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high
impedance state.
Table 7.2 S29AL004D Top Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/Kwords)
(x8) Address Range
(x16) Address Range
SA0
0
0
0
X
X
X
64/32
00000h–0FFFFh
00000h–07FFFh
SA1
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA2
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA3
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA4
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA5
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA6
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA7
1
1
1
0
X
X
32/16
70000h–7FFFFh
38000h–38FFFh
SA8
1
1
1
1
0
0
8/4
78000h–79FFFh
3C000h–3CFFFh
SA9
1
1
1
1
0
1
8/4
7A000h–7BFFFh
3D000h–3DFFFh
SA10
1
1
1
1
1
X
16/8
7C000h–7FFFFh
3E000h–3FFFFh
Note
The address range is A17:A-1 in byte mode and A17:A0 in word mode. See Word/Byte Configuration on page 10.
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S29AL004D
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Table 7.3 S29AL004D Bottom Boot Block Sector Addresses
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x8)
Address Range
(x16)
Address Range
SA0
0
0
0
0
0
X
16/8
00000h–03FFFh
00000h–01FFFh
SA1
0
0
0
0
1
0
8/4
04000h–05FFFh
02000h–02FFFh
SA2
0
0
0
0
1
1
8/4
06000h–07FFFh
03000h–03FFFh
SA3
0
0
0
1
X
X
32/16
08000h–0FFFFh
04000h–07FFFh
SA4
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA5
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA6
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA7
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA8
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA9
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA10
1
1
1
X
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
Note
The address range is A17:A-1 in byte mode and A17:A0 in word mode. See Word/Byte Configuration on page 10.
7.9
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in Table 7.4. In addition, when verifying sector protection, the
sector address must appear on the appropriate highest order address bits (see Table 7.2 on page 12 and
Table 7.3 on page 13). Table 7.4 on page 13 shows the remaining address bits that are don’t care. When all
necessary bits are set as required, the programming equipment may then read the corresponding identifier
code on DQ7–DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in Table 8.2 on page 20. This method does not require VID. See Command
Definitions on page 16 for details on using the autoselect mode.
Table 7.4 S29AL004D Autoselect Codes (High Voltage Method)
Description
Mode
Manufacturer ID: Spansion
Device ID:
S29AL004D
(Top Boot Block)
Device ID:
S29AL004D
(Bottom Boot
Block)
CE#
OE#
WE#
A17
to
A12
X
L
L
H
Word
L
L
H
Byte
L
L
H
Word
L
L
H
Byte
L
L
H
X
X
Sector Protection
Verification
L
L
H
SA
A11
to
A10
X
X
X
X
A9
A8
to
A7
VID
X
VID
VID
VID
X
X
X
A6
A4
to
A5
A3
to
A2
A1
A0
L
X
L
L
L
L
L
L
X
X
X
L
L
L
L
L
H
DQ8
to
DQ15
DQ7
to
DQ0
X
01h
22h
B9h
H
X
B9h
22h
BAh
X
BAh
X
01h
(protected)
X
00h
(unprotected)
H
L
Legend
L = Logic Low = VIL
H = Logic High = VIH
SA = Sector Address
X = Don’t care.
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7.10
S hee t
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting
sectors at its factory prior to shipping the device through Spansion’s ExpressFlash™ Service. Contact an
Spansion representative for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 13 for
details.
Sector Protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via
programming equipment. Figure 7.2 on page 15 shows the algorithms and Figure 15.12 on page 38 shows
the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all
unprotected sectors must first be protected prior to the first sector unprotect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices.
7.11
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the
RESET# pin, all the previously protected sectors are protected again.
Figure 7.1 shows the algorithm and Figure 15.11 on page 38 shows the timing diagrams, for this feature.
Figure 7.1 Temporary Sector Unprotect Operation
START
RESET# = VID (Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
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S29AL004D
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Figure 7.2 In-System Sector Protect/Sector Unprotect Algorithms
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 μs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 μs
First Write No
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 μs
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Wait 15 ms
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Yes
Device failed
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
Protect another
sector?
No
Yes
PLSCNT
= 1000?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
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S29AL004D
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7.12
S hee t
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 8.2 on page 20 for command definitions). In addition, the following
hardware data protection measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during VCC power-up and power-down transitions, or from system
noise.
7.12.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
7.12.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
7.12.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
7.12.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
8. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Figure 8.2 on page 20 defines the valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in AC
Characteristics on page 31.
8.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/
Erase Resume Commands on page 20 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See Reset Command on page 17.
See also Requirements for Reading Array Data on page 10 for more information. The Read Operations
on page 31 provides the read parameters, and Figure 15.1 on page 31 shows the timing diagram.
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8.2
She et
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the device to reading array data (also applies to programming in Erase
Suspend mode). Once programming begins, however, the device ignores reset commands until the operation
is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
8.3
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes,
and determine whether or not a sector is protected. Table 8.2 on page 20 shows the address and data
requirements. This method is an alternative to that shown in Table 7.4 on page 13, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode, and the system may read at any address any
number of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to Table 7.2 on page 12 and Table 7.3 on page 13 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
8.4
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming
is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles,
followed by the program set-up command. The program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not required to provide further controls or timings.
The device automatically provides internally generated program pulses and verifies the programmed cell
margin. Table 8.2 on page 20 shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and
addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See Write Operation Status on page 22 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The program command sequence
should be reinitiated once the device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from
a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling
algorithm to indicate the operation was successful. However, a succeeding read shows that the data is still 0.
Only erase operations can convert a 0 to a 1.
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8.4.1
S hee t
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the
standard program command sequence. The unlock bypass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 8.2 on page 20 shows the
requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle must contain the data 90h; the second cycle the data 00h (F0h). Addresses are
don’t care for both cycles. The device then returns to reading array data.
Figure 8.1 illustrates the algorithm for the program operation. See Table 15.3 on page 33 for parameters, and
Figure 15.5 on page 35 for timing diagrams.
Figure 8.1 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note
See Table 8.1 on page 21 for program command sequence.
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Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations. Table 8.2 on page 20 shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command
sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write
Operation Status on page 22 for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.
Figure 8.2 on page 20 illustrates the algorithm for the erase operation. See Table 15.3 on page 33 for
parameters and Figure 15.6 on page 35 for timing diagrams.
8.6
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase command. Table 8.2 on page 20 shows the address
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 µs, otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase
Timer on page 25). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the sector erase operation immediately terminates the
operation. The Sector Erase command sequence should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to Write Operation Status on page 22 for information on these status bits.
Figure 8.2 on page 20 illustrates the algorithm for the erase operation. Refer to Table 15.3 on page 33 for
parameters, and to Figure 15.6 on page 35 for timing diagrams.
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8.7
S hee t
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm.
Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation is suspended, the system can read array data from or program data to any sector
not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read and write
timings and command definitions apply. Reading at any address within erase-suspended sectors produces
status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is
actively erasing or is erase-suspended. See Write Operation Status on page 22 for information on these
status bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 22 for more
information.
The system may also write the autoselect command sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes
are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the
Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence
on page 17 for more information.
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend
mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device has resumed erasing.
Figure 8.2 Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes
1. See Sector Erase Command Sequence on page 19 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 25 for more information.
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Cycles
Table 8.1 S29AL004D Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2-5)
First
Second
Addr
Data
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Word
Manufacturer ID
555
4
Autoselect (Note 8)
Byte
Device ID,
Top Boot Block
Word
Device ID,
Bottom Boot Block
Word
Data
90
X00
01
555
55
Addr
Sixth
Data
Addr
Data
555
55
555
X01
22B9
X02
B9
X01
22BA
90
AAA
2AA
AA
AAA
Fifth
Addr
555
555
555
4
Byte
Fourth
Data
AAA
2AA
AA
AAA
Third
Addr
55
555
555
4
Data
2AA
AA
AAA
Byte
Addr
90
AAA
X02
BA
XX00
Word
555
2AA
555
(SA)X02
XX01
Sector Protect Verify
(Note 9)
4
AA
55
90
00
Byte
AAA
555
AAA
Word
555
2AA
555
(SA)X04
01
Program
4
Byte
Word
Unlock Bypass
AA
AAA
555
3
Byte
55
555
2AA
AA
AAA
XXX
A0
PA
PD
Unlock Bypass Reset (Note 11)
2
XXX
90
XXX
00
(F0h)
555
6
Byte
Word
Sector Erase
2AA
AA
AAA
Byte
555
1
XXX
B0
Erase Resume (Note 13)
1
XXX
30
555
55
555
555
80
AAA
2AA
AA
AAA
555
55
555
Erase Suspend (Note 12)
555
80
AAA
2AA
AA
AAA
20
55
555
555
6
PD
AAA
2
Word
PA
555
55
555
Unlock Bypass Program (Note 10)
Chip Erase
A0
AAA
10
AAA
2AA
AA
AAA
55
SA
30
555
Legend
X = Don’t care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation, and
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17–A12 uniquely select any sector.
Notes
1. See Table 7.1 on page 10 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A17–A11 are don’t cares for unlock and command cycles, unless PA or SA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status
data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence on page 17 for more information.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation.
13. The Erase Resume command is valid only during the Erase Suspend mode.
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9. Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 9.1 on page 26 and the following subsections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
9.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.
This is analogous to the complement/true datum output described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The
system must provide an address within any of the sectors selected for erasure to read valid status information
on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 15.8 on page 36 illustrates this.
Table 9.1 on page 26 shows the outputs for Data# Polling on DQ7. Figure 9.1 on page 23 shows the Data#
Polling algorithm.
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Figure 9.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for
erasure. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
9.2
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 9.1 on page 26 shows the outputs for RY/BY#. Figure 15.1 on page 31, Figure 15.2 on page 32,
Figure 15.5 on page 35, and Figure 15.6 on page 35 shows RY/BY# for read, reset, program, and erase
operations, respectively.
9.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the
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Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see DQ7: Data# Polling on page 22).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 9.1 on page 26 shows the outputs for Toggle Bit I on DQ6. Figure 9.2 on page 25 shows the toggle bit
algorithm. Figure 15.9 on page 37 shows the toggle bit timing diagrams. Figure 15.10 on page 37 shows the
differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page 24.
9.4
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that are selected for erasure. (The
system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 9.1 on page 26 to compare
outputs for DQ2 and DQ6.
Figure 9.2 on page 25 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II
on page 24 explains the algorithm. See also the DQ6: Toggle Bit I on page 23 subsection. Figure 15.9
on page 37 shows the toggle bit timing diagram. Figure 15.10 on page 37 shows the differences between
DQ2 and DQ6 in graphical form.
9.5
Reading Toggle Bits DQ6/DQ2
Refer to Figure 9.2 on page 25 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 25). If
it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not completed the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 9.2 on page 25)
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DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device
halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the reset command to return the device to reading array
data.
9.7
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can
guarantee that the time between additional sector erase commands is always less than 50 µs. See also the
Sector Erase Command Sequence on page 19.
Figure 9.2 Toggle Bit Algorithm
START
Read DQ7–DQ0
(Note 1)
Read DQ7–DQ0
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes 1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
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After the sector erase command sequence is written, the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read
DQ3. If DQ3 is 1, the internally controlled erase cycle has begun; all further commands (other than Erase
Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector
erase commands. To ensure the command is accepted, the system software should check the status of DQ3
prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted. Table 9.1 shows the outputs for DQ3.
Table 9.1 Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5:
Exceeded Timing Limits on page 25 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
10. Absolute Maximum Ratings
Storage Temperature Plastic Packages
–65°C to +150°C
Ambient Temperature with Power Applied
–65°C to +125°C
Voltage with Respect to Ground VCC (Note 1)–0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2)
–0.5 V to +12.5 V
All other pins (Note 1)
–0.5 V to VCC+0.5 V
Output Short Circuit Current (Note 3)
200 mA
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods
of up to 20 ns. See Figure 11.1 on page 27. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or
I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 11.2 on page 27.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot
VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1 on page 27. Maximum DC input voltage on pin A9 is +12.5 V which may
overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under Absolute Maximum Ratings on page 26 may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
11. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA)
-40°C to +85°C
Extended (N) Devices
Ambient Temperature (TA)
-40°C to +125°C
VCC Supply Voltages
VCC for full voltage range
+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
26
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Figure 11.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 11.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
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12. DC Characteristics
Parameter
Description
Test Conditions
ILI
Input Load Current
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ILO
Min
10 MHz
CE# = VIL, OE# = VIH,
Byte Mode
ICC1
Typ
VIN = VSS to VCC,
VCC = VCC max
VCC Active Read Current
(Notes 1, 2)
Max
Unit
±1.0
µA
35
µA
±1.0
µA
18
35
5 MHz
9
16
1 MHz
2
4
10 MHz
15
30
5 MHz
9
16
1 MHz
2
4
mA
CE# = VIL, OE# = VIH,
Word Mode
ICC2
VCC Active Write Current
(Notes 2, 3, 6)
CE# = VIL, OE# = VIH
20
35
mA
ICC3
VCC Standby Current (Notes 2, 4)
CE#, RESET# = VCC±0.3 V
0.2
5
µA
ICC4
VCC Reset Current (Notes 2, 4)
RESET# = VSS ± 0.3 V
0.2
5
µA
ICC5
Automatic Sleep Mode
(Notes 2, 4, 5)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
0.2
5
µA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.3 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
IOH = –2.0 mA, VCC = VCC min
2.4
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage
2.3
V
2.5
V
Notes
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85°C), typical current is 5µA and maximum current is 10µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
6. Not 100% tested.
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Zero Power Flash
Figure 12.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
Supply Current in mA
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note
Addresses are switching at 1 MHz.
Figure 12.2 Typical ICC1 vs. Frequency
Supply Current in mA
10
8
3.6 V
6
2.7 V
4
2
0
1
2
3
4
5
Frequency in MHz
Note
T = 25 °C
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13. Test Conditions
Figure 13.1 Test Setup
3.3 V
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Note
Nodes are IN3064 or equivalent.
Table 13.1 Test Specifications
Test Condition
55
70
Output Load
90
Unit
100
pF
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
30
Input Rise and Fall Times
5
Input Pulse Levels
ns
0.0 or VCC
Input timing measurement reference levels
0.5VCC
Output timing measurement reference levels
0.5VCC
V
14. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Figure 14.1 Input Waveforms and Measurement Levels
VCC
0.0 V
30
Input
0.5VCC
Measurement Level
S29AL004D
0.5VCC
Output
S29AL004D_00_A6 February 27, 2009
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15. AC Characteristics
15.1
Read Operations
Table 15.1 Read Operations
Parameter
Speed Options
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
Description
Test Setup
tAVQV
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
OE# = VIL
55
70
90
Min
55
70
90
Max
55
70
90
tELQV
tCE
Chip Enable to Output Delay
Max
55
70
90
tGLQV
tOE
Output Enable to Output Delay
Max
25
30
35
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
Min
20
tAXQX
Unit
ns
tSR/W
Latency Between Read and Write Operations
tOEH
Output Enable
Hold Time (Note 1)
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Read
Min
0
Toggle and Data# Polling
Min
10
Min
0
Notes
1. Not 100% tested.
2. See Figure 13.1 on page 30 and Table 13.1 on page 30 for test specifications.
Figure 15.1 Read Operations Timings
tRC
Addresses Stable
Addresses
tACC
CE#
OE#
tDF
tOE
tSR/W
tOEH
WE#
tCE
HIGH Z
Outputs
tOH
Output Valid
HIGH Z
RESET#
RY/BY#
0V
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Table 15.2 Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
tREADY
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
Test Setup
All Speed Options
Unit
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
500
ns
Max
tREADY
tRP
RESET# Pulse Width
500
ns
tRH
RESET# High Time Before Read (See Note)
50
ns
tRPD
RESET# Low to Standby Mode
20
µs
tRB
RY/BY# Recovery Time
0
ns
Min
Note
Not 100% tested.
Figure 15.2 RESET# Timings
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
tRH
RESET#
tRP
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Table 15.3 Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Speed Options
Std
Description
tELFL/tELFH
55
CE# to BYTE# Switching Low or High
Max
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
tFHQV
BYTE# Switching High to Output Active
Min
70
90
Unit
5
16
55
70
ns
90
Figure 15.3 BYTE# Timings for Read Operations
CE#
OE#
BYTE#
tELFL
BYTE#
Switching
from word
to byte
mode
Data Output
(DQ0–DQ14)
DQ0–DQ14
Data Output
(DQ0–DQ7)
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 15.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note
Refer to Erase/Program Operations on page 34 for tAS and tAH specifications.
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15.2
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Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
Description
55
tAVAV
tWC
Write Cycle Time (Note 1)
70
90
55
70
90
tAVWL
tAS
Address Setup Time
0
tWLAX
tAH
Address Hold Time
45
tDVWH
tDS
Data Setup Time
tWHDX
tDH
Data Hold Time
tOES
Output Enable Setup Time
35
35
Min
0
Read Recovery Time Before Write
(OE# High to WE# Low)
0
0
tGHWL
tELWL
tCS
CE# Setup Time
tWHEH
tCH
CE# Hold Time
0
tWLWH
tWP
Write Pulse Width
35
tWPH
Write Pulse Width High
tSR/W
Latency Between Read and Write Operations
ns
30
Min
20
Typ
7
Byte
tWHWH1
tWHWH1
Programming Operation (Note 2)
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
ns
5
µs
Word
Min
0.7
sec
50
µs
tVCS
VCC Setup Time (Note 1)
tRB
Recovery Time from RY/BY#
Min
0
Program/Erase Valid to RY/BY# Delay
Max
90
tBUSY
45
0
tGHWL
tWHWL
Unit
ns
Notes
1. Not 100% tested.
2. See the Sector Erase Command Sequence on page 19 section for more information.
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Figure 15.5 Program Operation Timings
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 15.6 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 22).
2. Illustration shows device in word mode.
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Figure 15.7 Back to Back Read/Write Cycle Timing
tWC
tRC
PA
Addresses
PA
PA
PA
tACC
tAH
tCPH
tCE
CE#
tCP
tOE
OE#
tGHWL
t
SR/W
tWP
WE#
tWDH
Data
tDF
tDS
tOH
tDH
Valid In
Valid Out
Valid
In
Valid
Out
Figure 15.8 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
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Figure 15.9 Toggle Bit Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 15.10 DQ2 vs. DQ6
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Erase Suspend
Suspend
Read
Program
Erase
Erase
Complete
DQ6
DQ2
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Table 15.4 Temporary Sector Unprotect
Parameter
JEDEC
All Speed Options
Unit
tVIDR
Std
VID Rise and Fall Time (See Note)
Description
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector Unprotect
Min
4
µs
Note
Not 100% tested.
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Figure 15.11 Temporary Sector Unprotect Timing Diagram
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 15.12 Sector Protect/Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
Valid*
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
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Table 15.5 Alternate CE# Controlled Erase/Program Operation
Parameter
Speed Options
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
tAVEL
tAS
Address Setup Time
0
tELAX
tAH
Address Hold Time
45
tDVEH
tDS
Data Setup Time
tEHDX
tDH
Data Hold Time
tOES
Output Enable Setup Time
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
0
0
tGHEL
Description
55
70
90
55
70
90
35
35
45
0
0
Min
tWLEL
tWS
WE# Setup Time
tEHWH
tWH
WE# Hold Time
0
tELEH
tCP
CE# Pulse Width
35
tCPH
CE# Pulse Width High
tSR/W
Latency Between Read and Write Operations
tEHEL
Unit
ns
30
Min
20
Byte
tWHWH1
tWHWH1
Programming Operation
(Note 2)
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
ns
5
µs
Word
Typ
7
0.7
sec
Note
1. Not 100% tested.
2. See Erase And Programming Performance on page 40 for more information.
Figure 15.13 Alternate CE# Controlled Write Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
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16. Erase And Programming Performance
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
Parameter
0.7
10
s
Chip Erase Time
11
Byte Programming Time
7
210
µs
Word Programming Time
7
210
µs
Chip Programming Time
Byte Mode
4.2
12.5
s
(Note 3)
Word Mode
2.9
8.5
s
s
Comments
Excludes 00h programming
prior to erasure
Excludes system level
overhead (Note 5)
Notes
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 8.1
on page 21 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector
Table 16.1 TSOP, SO, And BGA Pin Capacitance
Parameter Symbol
CIN
Parameter Description
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
VIN = 0
VOUT = 0
VIN = 0
Package
Typ
Max
TSOP, SO
6
7.5
5.0
BGA
4.2
TSOP, SO
8.5
12
BGA
5.4
6.5
TSOP, SO
7.5
9
BGA
3.9
4.7
Unit
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
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17. Physical Dimensions
17.1
TS 048—48-Pin Standard TSOP
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
2
0.10
0.10
1
A2
N
SEE DETAIL B
A
REVERSE PIN OUT (TOP VIEW)
3
B
1
N
E 5
N
+1
2
N
2
D1
0.25
9
A1
4
D
2X (N/2 TIPS)
e
5
C
SEATING
PLANE
B
A
B
N
+1
2
N
2
SEE DETAIL A
0.08MM
(0.0031")
b
M
C A-B S
6
7
WITH PLATING
7
(c)
c1
b1
SECTION B-B
BASE METAL
R
(c)
e/2
GAUGE PLANE
θ°
PARALLEL TO
SEATING PLANE
0.25MM (0.0098") BSC
X
C
L
X = A OR B
DETAIL A
DETAIL B
NOTES:
Jedec
MO-142 (D) DD
Symbol
A
A1
A2
b1
b
c1
c
D
D1
E
e
L
0
R
N
MAX
1.20
0.15
0.05
1.05
1.00
0.95
0.20
0.23
0.17
0.27
0.22
0.17
0.16
0.10
0.21
0.10
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
0.50 BASIC
0.70
0.50
0.60
8˚
0˚
0.20
0.08
48
MIN
NOM
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
2
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
3
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
6
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
8
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3355 \ 16-038.10c
Note
For reference only. BSC is an ANSI standard for Basic Space Centering.
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VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm
0.10 (4X)
D
D1
A
6
5
e
7
4
E
SE
E1
3
2
1
H
PIN A1
CORNER
INDEX MARK
10
6
B
G
F
fb
E
D
C
SD
B
A
A1 CORNER
7
f 0.08 M C
TOP VIEW
f 0.15 M C A B
BOTTOM VIEW
A
0.10 C
A2
SEATING PLANE
A1
C
0.08 C
SIDE VIEW
NOTES:
PACKAGE
VBK 048
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
8.15 mm x 6.15 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
NOTE
OVERALL THICKNESS
BALL HEIGHT
8.15 BSC.
BODY SIZE
6.15 BSC.
BODY SIZE
5.60 BSC.
BALL FOOTPRINT
E1
4.00 BSC.
MD
8
ROW MATRIX SIZE D DIRECTION
ME
6
ROW MATRIX SIZE E DIRECTION
N
48
---
BALL FOOTPRINT
TOTAL BALL COUNT
0.43
BALL DIAMETER
e
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
---
REPRESENTS THE SOLDER BALL GRID PITCH.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
E
D1
0.35
e
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
BODY THICKNESS
D
fb
4.
DEPOPULATED SOLDER BALLS
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25b
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S29AL004D
S29AL004D_00_A6 February 27, 2009
Data
17.3
She et
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
February 27, 2009 S29AL004D_00_A6
S29AL004D
43
D at a
S hee t
18. Revision Summary
18.1
Revision A0 (November 12, 2004)
Initial release
18.2
Revision A1 (February 18, 2005)
Added Cover Page
Ordering Information
Change package type from S to M.
Valid Combination Table
Package Type, Material, and Temperature Range from SAL and SFI to MAL and MFI.
Changed Package Description from SSOP to SOP
Erase and Programming Performance Table
Changed chip erase time in table.
18.3
Revision A2 (June 1, 2005)
Global
Updated status from Advance Information to Preliminary data sheet.
Distinctive Characteristics
Updated High Performance access time to 55 ns.
Product Selector Guide
Added 55 ns speed column.
Ordering Information
Added tube packing type.
Added Extended Temperature range.
Added 55 ns speed option.
Valid Combinations Table
Added two designators to packing types.
Added speed option along with speed option package type nomenclature.
Added Note for this table.
Operating Range
Added extended temperature range information.
Moved Figures 7 and 8 under Operating Range area.
Erase and Programming Performance
Changed Byte Programing Time values for Typical and Maximum.
44
S29AL004D
S29AL004D_00_A6 February 27, 2009
Data
18.4
She et
Revision A3 (June 21, 2005)
Global
Update from Preliminary status to full Data Sheet.
Ordering Information
Added two Model Numbers.
Valid Combinations Table
Updated table with new Model Numbers and Package Types.
18.5
Revision A4 (May 22, 2006)
AC Characteristics
Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/write cycle
timing diagram. Changed maximum value for tDF and tFLQZ.
18.6
Revision A5 (June 22, 2006)
Connection Diagrams
Changed inputs on pins 1 and 2 of SO package.
Read Operations Timings figure
Connected end of tRC period to start of tOH period.
Erase/Program Operations table
Changed tBUSY to a maximum specification.
18.7
Revision A6 (February 27, 2009)
Global
Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information
sections of data sheet.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2004-2009 Spansion Inc. All rights reserved. Spansion®, the Spansion Logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
ORNAND2™, HD-SIM™, EcoRAM™ and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names
used are for informational purposes only and may be trademarks of their respective owners.
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