CX20745 Low-Power I2S CODEC Data Sheet General Description Features The CX20745 is an Integrated Interchip Sound (I2S) audio Coder-Decoder (CODEC), with integrated stereo class-D speaker amplifiers and capless headphones with performance that exceeds 100dB Signal-to-Noise Ratio (SNR). Innovative Digital Signal Processing (DSP) maximizes speaker loudness without distortion, performs loudness compensation, and normalizes microphone pick-up levels. Combined with Conexant’s software and design support services, the CX20745 is an ideal turnkey solution for tablets, ultrabooks, portable media players, SMART phones, and digital docking stations. • The integrated filterless class-D stereo amplifier with spread spectrum Electro-Magnetic Interference (EMI) dispersion technology is capable of driving up to 2W RMS per channel into 4 speakers. Built-in, fully configurable hardware Equalizer (EQ) and Dynamic Range Compression (DRC) improve frequency response, maximize the output volume, and get best audio performance from integrated speakers independent of the driver and Operating System (OS). A stereo pair of capless headphone drivers includes integrated short circuit protection and auto-recovery. These high performance headphone drivers save cost by eliminating external headphone amplifiers and Direct Current (DC) blocking capacitors. The capless architecture outputs a full-range frequency response that exceeds 100dB SNR. Conexant supports both Applestyle and Nokia-style headsets, as well in-line command sensing for headset button controls. One single-ended line output can be used to drive power speakers or external devices. One differential microphone/line-in port is available, which is re-taskable to be single-ended. A programmable microphone boost and bias is provided. Local analog loopback with EQ/DRC from line or microphone inputs to the outputs can be configured. A Digital Microphone Interface (DMIC) allows interfacing to two digital microphones, and includes a hardware DC-level filter that eliminates problems caused by digital microphones with DC offset. Programmable microphone clock outputs of 3.072MHz and 1.536MHz are available. Hardware Automatic Gain Control (AGC) is available for all microphone paths to normalize the capture levels in real-time. 07/31/14 • Depending on the master clock, the CX20745 has a stereo 8-bit/16-bit/24-bit: – Digital-to-Analog Converter (DAC) that supports sample rates capable of 8kHz, 8.018kHz,11.025kHz, 12kHz, 16kHz, 16.0364kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz ■ 98dB dynamic range, 101dB SNR ■ –85dB Total Harmonic Distortion (THD) – Analog-to-Digital Converter (ADC) that supports sample rates capable of 8kHz, 8.018kHz, 11.025kHz, 12kHz, 16kHz, 16.0364kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz Provides independent gain and mute control for both DAC and ADC • Data interface—I2S that can be converted to Pulse Code Modulation (PCM) • • Control Interface—I2C slave only Supports master clocks of 24.576MHz and 22.5792MHz Line-in Loopback mode, where the input signal loops back to the DAC for playback with the EQ/DRC PopShield active anti-pop ensures no pops or clicks All digital interfaces operate at 3.3V Integrated LDO converts 5V to 3.3V, and 3.3V to 1.8V Pulse Density Modulated (PDM) digital microphone interface supports a clock frequency of 3.072MHz and 1.536MHz Jack sense supports up to four jacks with selectable de-bounce • • • • • • Applications • • • • • • Mobile Internet devices Tablets Digital dock stations Portable Navigation Devices (PNDs) Portable Media Players (PMPs) Portable gaming systems Conexant Confidential • www.conexant.com 008DSR00 CX20745 Data Sheet Revision History Revision History Document/ Revision No. Release Date Change Description 008DSR00 07/31/14 Template and minor text updates. F 03/30/12 Minor updates. E 11/30/11 Updated the "Transmitter and Receiver Configuration” figure to include the CX20745 part number on the receiver and transmitter blocks. D 05/19/11 Updated: • • "Power Consumption" table. "Package Dimensions" to "Package Dimensions and Thermal Specifications." Added: • "Thermal Specifications" table. Complete document update. Added "Appendix A." C 05/03/11 • • B 01/26/11 Complete document update. A 10/14/10 Initial release. Conexant Confidential 07/31/14 008DSR00 ii CX20745 Data Sheet Table of Contents Table of Contents General Description.......................................................................................................................................................i Features..........................................................................................................................................................................i Applications ...................................................................................................................................................................i Revision History ...........................................................................................................................................................ii Introduction...................................................................................................................................................................1 Overview............................................................................................................................................................................... 1 Features................................................................................................................................................................................ 2 Packaging............................................................................................................................................................................. 2 Applications ..................................................................................................................................................................3 Block Diagram...................................................................................................................................................................... 3 Hardware Interface .......................................................................................................................................................4 Pin Information .................................................................................................................................................................... 5 Pin Configuration ........................................................................................................................................................ 5 Pin Assignments ......................................................................................................................................................... 6 Pin Signal Definitions.................................................................................................................................................. 7 Electrical Characteristics.............................................................................................................................................9 Package Dimensions and Thermal Specifications ..................................................................................................12 Device Description .....................................................................................................................................................13 Analog Audio Input Paths................................................................................................................................................. 13 Analog-to-Digital Converter (ADC) ........................................................................................................................... 13 Microphone/Line Input .............................................................................................................................................. 13 Microphone Bias (Micbias) Generator ...................................................................................................................... 13 Jack Sense ............................................................................................................................................................... 14 Analog Audio Output Paths.............................................................................................................................................. 14 Digital-to-Analog Converter (DAC) ........................................................................................................................... 14 Line-Out .................................................................................................................................................................... 14 Class-D/Pulse-Width Modulation (PWM).................................................................................................................. 14 Capless Headphone Driver....................................................................................................................................... 15 Digital Audio....................................................................................................................................................................... 15 Pulse Code Modulation (PCM)/Integrated Interchip Sound (I2S) Interface .............................................................. 15 I2S............................................................................................................................................................................. 16 PCM.......................................................................................................................................................................... 20 Conexant Confidential 07/31/14 008DSR00 iii CX20745 Data Sheet Table of Contents Control Interface ....................................................................................................................................................... 21 Digital Signal Processing (DSP)....................................................................................................................................... 23 Equalizer (EQ)/Dynamic Range Compressor (DRC)................................................................................................ 24 Digital Microphone Interface (DMIC) ........................................................................................................................ 25 Automatic Gain Control (AGC) Record Path ............................................................................................................ 26 General Purpose Input/Output (GPIO) Functions..................................................................................................... 28 GPIO 3...................................................................................................................................................................... 32 GPIO 4...................................................................................................................................................................... 32 Clocking.............................................................................................................................................................................. 32 Clock Inputs .............................................................................................................................................................. 32 Registers .....................................................................................................................................................................33 Register Summary ............................................................................................................................................................. 33 Register Details.................................................................................................................................................................. 38 Coder-Decoder (CODEC) Control Registers ............................................................................................................ 38 Data I/F Registers..................................................................................................................................................... 46 AGC Registers.......................................................................................................................................................... 49 Test Registers........................................................................................................................................................... 59 Read Only Registers................................................................................................................................................. 62 GPIO Registers......................................................................................................................................................... 64 Ordering Information..................................................................................................................................................66 Conexant Confidential 07/31/14 008DSR00 iv CX20745 Data Sheet List of Figures List of Figures Figure 1: CX20745 Block Diagram ................................................................................................................................................... 3 Figure 2: Hardware Interface Signals ............................................................................................................................................... 4 Figure 3: CX20745 48-QFN Pin Configuration ................................................................................................................................. 5 Figure 4: Package Diagram ............................................................................................................................................................ 12 Figure 5: Transmitter and Receiver Configuration .......................................................................................................................... 16 Figure 6: I2S Timing........................................................................................................................................................................ 17 Figure 7: One-Clock Data Shift ....................................................................................................................................................... 17 Figure 8: Left-Justified Timing......................................................................................................................................................... 18 Figure 9: Right-Justified Timing ...................................................................................................................................................... 18 Figure 10: I2S Transmitter Timing................................................................................................................................................... 19 Figure 11: Short Frame Sync (Shown with 16-Bit Sample) ............................................................................................................ 20 Figure 12: Long Frame Sync (Shown with 8-Bit Companded Sample) .......................................................................................... 20 Figure 13: Transferring Data on I2C................................................................................................................................................ 21 Figure 14: Data Transfer Format .................................................................................................................................................... 22 Figure 15: Definition of Timing for F/S-Mode Devices on the I2C Bus............................................................................................ 23 Figure 16: DAC Digital Section ....................................................................................................................................................... 23 Figure 17: DRC Threshold .............................................................................................................................................................. 24 Figure 18: DMIC.............................................................................................................................................................................. 25 Figure 19: DMIC Timing.................................................................................................................................................................. 26 Figure 20: AGC Record Path .......................................................................................................................................................... 26 Figure 21: Rotary Encoder.............................................................................................................................................................. 28 Figure 22: Rotary Encoder Block Diagram ..................................................................................................................................... 28 Figure 23: Chattering Prevention Circuit Block Diagram ................................................................................................................ 29 Figure 24: Up/Down Detection Circuit............................................................................................................................................. 31 Conexant Confidential 07/31/14 008DSR00 V CX20745 Data Sheet List of Tables List of Tables Table 1: Pin Assignments ................................................................................................................................................................. 6 Table 2: Pin Signal Definitions.......................................................................................................................................................... 7 Table 3: General ............................................................................................................................................................................... 9 Table 4: Mic/Line Input...................................................................................................................................................................... 9 Table 5: Class-D/Speaker Output ..................................................................................................................................................... 9 Table 6: Line Output ......................................................................................................................................................................... 9 Table 7: Headphone Output............................................................................................................................................................ 10 Table 8: Charge Pump.................................................................................................................................................................... 10 Table 9: Micbias.............................................................................................................................................................................. 10 Table 10: Jack Sensing................................................................................................................................................................... 10 Table 11: Voltage Regulator ........................................................................................................................................................... 11 Table 12: Power Consumption........................................................................................................................................................ 11 Table 13: Thermal Specifications.................................................................................................................................................... 13 Table 14: Jack Sense Impedance Values....................................................................................................................................... 14 Table 15: DAC ................................................................................................................................................................................ 15 Table 16: ADC ................................................................................................................................................................................ 16 Table 17: Master Transmitter with a Data Rate of 2.5MHz (±10%) (All Values in ns).................................................................... 19 Table 18: Slave Receiver with a Data Rate of 2.5MHz (±10%) (All Values in ns).......................................................................... 19 Table 19: Slave Addressing Format for I2C .................................................................................................................................... 22 Table 20: I2C Conditions ................................................................................................................................................................ 23 Table 21: Pins Used........................................................................................................................................................................ 25 Table 22: EC16B Standard Data .................................................................................................................................................... 29 Table 23: Clock Inputs .................................................................................................................................................................... 32 Table 24: Register Summary .......................................................................................................................................................... 33 Table 25: Equalizer Crossover Enable Bypass (0x00) ................................................................................................................... 38 Table 26: Equalizer Coefficient B0 High (0x01) .............................................................................................................................. 38 Table 27: Equalizer Coefficient B0 Low (0x02)............................................................................................................................... 38 Table 28: Equalizer Coefficient B1 High (0x03) .............................................................................................................................. 38 Table 29: Equalizer Coefficient B1 Low (0x04)............................................................................................................................... 39 Table 30: Equalizer Coefficient B2 High (0x05) .............................................................................................................................. 39 Table 31: Equalizer Coefficient B2 Low (0x06)............................................................................................................................... 39 Table 32: Equalizer Coefficient A0 High (0x07) .............................................................................................................................. 39 Table 33: Equalizer Coefficient A0 Low (0x08)............................................................................................................................... 39 Conexant Confidential 07/31/14 008DSR00 VI CX20745 Data Sheet List of Tables Table 34: Equalizer Coefficient A1 High (0x09) .............................................................................................................................. 39 Table 35: Equalizer Coefficient A1 Low (0x0A) .............................................................................................................................. 39 Table 36: Gain (0x0B)..................................................................................................................................................................... 39 Table 37: Coeff Load Control (0x0C) .............................................................................................................................................. 40 Table 38: DRC_Gain High (0x0D) .................................................................................................................................................. 40 Table 39: DRC_Gain Low (0x0E) ................................................................................................................................................... 40 Table 40: DAC 1:2 Sample Size/Rate (0x0F) ................................................................................................................................. 41 Table 41: DAC 1 (Left Channel) Volume/Mute Control (0x10)........................................................................................................ 41 Table 42: DAC 2 (Right Channel) Volume/Mute Control (0x11) ..................................................................................................... 42 Table 43: Digital Microphone Control (0x12) .................................................................................................................................. 42 Table 44: ADC Sample Rate/Enable Register (0x13)..................................................................................................................... 43 Table 45: ADC Left Channel Volume/Mute Control (0x14) ............................................................................................................. 43 Table 46: ADC Right Channel Volume/Mute Control (0x15)........................................................................................................... 44 Table 47: HP Control Register (0x16)............................................................................................................................................. 44 Table 48: Line-Out Control Register (0x17) .................................................................................................................................... 45 Table 49: SPKR Control Registers (0x18) ...................................................................................................................................... 45 Table 50: ADC Analog Left Channel Control Register (0x19)......................................................................................................... 45 Table 51: ADC Analog Right Channels Control Register (0x1A) .................................................................................................... 46 Table 52: Micbias Control Register (0x1B) ..................................................................................................................................... 46 Table 53: I2S Transmitter Control-1 (0x1C).................................................................................................................................... 46 Table 54: I2S Transmitter Control-2 (0x1D).................................................................................................................................... 46 Table 55: I2S Receiver Control-1 (0x1E) ........................................................................................................................................ 47 Table 56: I2S Receiver Control-2 (0x1F) ........................................................................................................................................ 47 Table 57: I2S/PCM Control-1 (0x20)............................................................................................................................................... 47 Table 58: I2S/PCM Control-2 (0x21)............................................................................................................................................... 47 Table 59: PCM Transmitter Control-1 (0x22).................................................................................................................................. 48 Table 60: PCM Transmitter Control-2 (0x23).................................................................................................................................. 48 Table 61: PCM Transmitter Control-3 (0x24).................................................................................................................................. 48 Table 62: PCM Receiver Control-1 (0x25)...................................................................................................................................... 48 Table 63: PCM Receiver Control-2 (0x26)...................................................................................................................................... 48 Table 64: PCM Receiver Control-3 (0x27)...................................................................................................................................... 49 Table 65: AD_DC_REJECT_POLE (0x28) ..................................................................................................................................... 49 Table 66: AD_BETA_VOICE SHFT (0x29)..................................................................................................................................... 49 Table 67: AD_BETA_NOISE_SHFT (0x2A) ................................................................................................................................... 49 Table 68: AD_TEST_GAIN (0x2B) ................................................................................................................................................. 49 Conexant Confidential 07/31/14 008DSR00 VII CX20745 Data Sheet List of Tables Table 69: AD_RELEASE_DELAY MSB (0x2C) .............................................................................................................................. 50 Table 70: AD_RELEASE_DELAY LSB (0x2D) ............................................................................................................................... 50 Table 71: AD_POWERIN_INITVAL MSB (0x2E)............................................................................................................................ 50 Table 72: AD_POWERIN_INITVAL LSB (0x2F) ............................................................................................................................. 50 Table 73: AD_MIN_SNR MSB (0x30)............................................................................................................................................. 50 Table 74: AD_MIN_SNR LSB (0x31).............................................................................................................................................. 50 Table 75: AGC_VOLUME_RAMP_STEP (0x32) ............................................................................................................................ 50 Table 76: AD_POWERNOISE_INITVAL MSB (0x33)..................................................................................................................... 51 Table 77: AD_POWERNOISE_INITVAL LSB (0x34)...................................................................................................................... 51 Table 78: AD_MIN_THRESH MSB (0x35)...................................................................................................................................... 51 Table 79: AD_MIN_THRESH LSB (0x36)....................................................................................................................................... 51 Table 80: AD_ON2OFF_DELAY_BLOCKS (0x37)......................................................................................................................... 51 Table 81: AGC_UPDATE_BKS (0x38) ........................................................................................................................................... 51 Table 82: AGC_ENERGY_THRESH_LO MSB (0x39) ................................................................................................................... 51 Table 83: AGC_ENERGY_THRESH_HI MSB (0x3A) .................................................................................................................... 52 Table 84: AGC_STABILITY_BLOCKS (0x3B) ................................................................................................................................ 52 Table 85: AGC_STEP_UP (0x3C) .................................................................................................................................................. 52 Table 86: AGC_STEP_DOW MSB (0x3D) ..................................................................................................................................... 52 Table 87: AGC_STAB_CNT_POS_INC (0x3E) .............................................................................................................................. 52 Table 88: AGC_STAB_CNT_NEG_INC (0x3F) .............................................................................................................................. 52 Table 89: DRC_RELEASE_DELAY MSB (0x40)............................................................................................................................ 52 Table 90: DRC_GAIN_STEP_SLOW (0x41) .................................................................................................................................. 53 Table 91: DRC_GAIN_STEP_FAST (0x42).................................................................................................................................... 53 Table 92: DRC_MAX_LIN_OUT (0x43) .......................................................................................................................................... 53 Table 93: DRC_GAIN_SHIFT (0x44).............................................................................................................................................. 53 Table 94: DRC_MAXABS_INITVAL (0x45) .................................................................................................................................... 53 Table 95: AGC_GAIN_INITVAL (0x46)........................................................................................................................................... 54 Table 96: DRC_OUTPUT_LIMIT (0x47) ......................................................................................................................................... 54 Table 97: AGC_CLIPPING_THRESH (0x48) ................................................................................................................................. 54 Table 98: DAC_HP_CNTRL (0x59) ................................................................................................................................................ 54 Table 99: Line In Loop (I2S Input) Gain Control (0x5A).................................................................................................................. 55 Table 100: Volume GPIO Control (0x5B)........................................................................................................................................ 55 Table 101: Volume Control (0x5C) ................................................................................................................................................. 55 Table 102: Interrupt Enable (0x5D)................................................................................................................................................. 56 Table 103: Interrupt Status (0x5E).................................................................................................................................................. 56 Conexant Confidential 07/31/14 008DSR00 VIII CX20745 Data Sheet List of Tables Table 104: SPKR_DRC_ATTACK_UPDATE_STEP (0x64) ........................................................................................................... 56 Table 105: SPKR_DRC_RELEASE_UPDATE_STEP (0x65)......................................................................................................... 56 Table 106: SPKR_DRC_RELEASE_DELAY (0x66)....................................................................................................................... 56 Table 107: SPKR_DRC_TRANSIENT_UPDATE_STEP (0x67)..................................................................................................... 57 Table 108: SPKR_DRC_TRANSIENT_RELEASE_DELAY (0x68) ................................................................................................ 57 Table 109: SPKR_DRC_BOOST_DB MSB (0x69)......................................................................................................................... 57 Table 110: SPKR_DRC_BOOST_DB LSB (0x6A) ......................................................................................................................... 57 Table 111: SPKR_DRC_MAX_LIN_OUT_DBFS MSB (0x6B) ....................................................................................................... 57 Table 112: SPKR_DRC_MAX_LIN_OUT_DBFS LSB (0x6C) ........................................................................................................ 57 Table 113: SPKR_DRC_OUT_LIMIT_DBFS MSB (0x6D) ............................................................................................................. 57 Table 114: SPKR_DRC_OUT_LIMIT_DBFS LSB (0x6E)............................................................................................................... 57 Table 115: SPKR_DRC_IN_LIMIT_DB MSB (0x6F) ...................................................................................................................... 58 Table 116: SPKR_DRC_IN_LIMIT_DB LSB (0x70)........................................................................................................................ 58 Table 117: SPKR_DRC_BALANCE_RAMP_STEP MSB (0x71).................................................................................................... 58 Table 118: SPKR_DRC_COMP_RATIO LSB (0x72)...................................................................................................................... 58 Table 119: SPKR_DRC_GAIN_SHIFT (0x73) ................................................................................................................................ 58 Table 120: SPKR_DRC_MAXABS_INITVAL (0x74)....................................................................................................................... 58 Table 121: SPKR_DRC_VOLUME_RAMP_STEP (0x75) .............................................................................................................. 58 Table 122: SPKR_DRC_MAX_RAMP_STEP_SHIFT (0x76) ......................................................................................................... 58 Table 123: SPKR_DRC_RELEASE_RATE_TH (0x77) .................................................................................................................. 59 Table 124: CODEC Test 0 (0x88)................................................................................................................................................... 59 Table 125: CODEC Test 21 (0x9D) ................................................................................................................................................ 59 Table 126: CODEC Test 22 (0x9E) ................................................................................................................................................ 59 Table 127: CODEC Test 23 (0x9F)................................................................................................................................................. 60 Table 128: Analog Test 4 (0xA8) .................................................................................................................................................... 60 Table 129: Analog Test 5 (0xA9) .................................................................................................................................................... 61 Table 130: Analog Test 6 (0xAA).................................................................................................................................................... 61 Table 131: Analog Test 8 (0xAC).................................................................................................................................................... 61 Table 132: Analog Test 13 (0xB1) .................................................................................................................................................. 62 Table 133: Analog Test 14 (0xB2) .................................................................................................................................................. 62 Table 134: Monitor ADC LSB (0xE1) .............................................................................................................................................. 62 Table 135: Monitor ADC MSB (0xE2) ............................................................................................................................................. 62 Table 136: Jack Sense Status and Bond Option (0xE3)................................................................................................................. 62 Table 137: Class-D Protection Status (0xE4) ................................................................................................................................. 63 Table 138: Class-D Calibration Observe (0xE5)............................................................................................................................. 63 Conexant Confidential 07/31/14 008DSR00 IX CX20745 Data Sheet List of Tables Table 139: HP A Offset Calibration Observe (0xE6)....................................................................................................................... 63 Table 140: HP B Offset Calibration Observe (0xE7)....................................................................................................................... 63 Table 141: Memory BIST Status (0xE8) ......................................................................................................................................... 63 Table 142: AGC Gain LSB Read Register (0xE9) .......................................................................................................................... 63 Table 143: AGC Gain MSB Read Register (0xEA)......................................................................................................................... 64 Table 144: SPKR DRC Gain LSB Read Register (0xEB) ............................................................................................................... 64 Table 145: SPKR DRC Gain MSB Read Register (0xEC).............................................................................................................. 64 Table 146: Micbias Detect Read Register (0xED) .......................................................................................................................... 64 Table 147: GPIO In Registers (0xF1) ............................................................................................................................................. 64 Table 148: GPIO Out Registers (0xF2)........................................................................................................................................... 65 Table 149: GPIO Direction Registers (0xF3) .................................................................................................................................. 65 Table 150: GPIO Control Registers (0xF4)..................................................................................................................................... 65 Table 151: I2S DATA Control (0xF5) .............................................................................................................................................. 65 Table 152: DMIC Drive Control (0xF6) ........................................................................................................................................... 65 Table 153: Device ID LSB (0xFD)................................................................................................................................................... 65 Table 154: Device ID MSB (0xFE).................................................................................................................................................. 66 Table 155: Bond Option Read (0xFF)............................................................................................................................................. 66 Table 156: Ordering Information..................................................................................................................................................... 66 Conexant Confidential 07/31/14 008DSR00 X CX20745 Data Sheet Introduction Introduction Overview The CX20745 is an I2S audio CODEC, with integrated stereo class-D speaker amplifiers and capless headphones with performance that exceeds 100dB SNR. Innovative DSP maximizes speaker loudness without distortion, performs loudness compensation, and normalizes microphone pick-up levels. Combined with Conexant’s software and design support services, the CX20745 is an ideal turnkey solution for tablets, ultrabooks, portable media players, SMART phones, and digital docking stations. The integrated filterless class-D stereo amplifier with spread spectrum EMI dispersion technology is capable of driving up to 2W RMS per channel into 4 speakers. Built-in, fully configurable hardware EQ and DRC improve frequency response, maximize the output volume, and get best audio performance from integrated speakers independent of the driver and OS. A stereo pair of capless headphone drivers includes integrated short circuit protection and auto-recovery. These high performance headphone drivers save cost by eliminating external headphone amplifiers and DC blocking capacitors. The capless architecture outputs a full-range frequency response that exceeds 100dB SNR. Conexant supports both Apple-style and Nokia-style headsets, as well in-line command sensing for headset button controls. One single-ended line output can be used to drive power speakers or external devices. One differential microphone/line-in port is available, which is re-taskable to be single-ended. A programmable microphone boost and bias is provided. Local analog loopback with EQ/DRC from line or microphone inputs to the outputs can be configured. A DMIC allows interfacing to two digital microphones, and includes a hardware DC-level filter that eliminates problems caused by digital microphones with DC offset. Programmable microphone clock outputs of 3.072MHz and 1.536MHz are available. Hardware AGC is available for all microphone paths to normalize the capture levels in real-time. Two integrated Low Dropout Regulators (LDOs) generate the internal clean power rails for analog and digital. All output ports feature PopShield circuitry that eliminates pops and clicks. Jack sensing is available that can detect up to four jacks with programmable switch de-bounce. The digital Input/Output (I/O), Inter-Integrated Circuit (I2C), and I2S interfaces support a wide range of topologies for connections to application processors and docking stations, and run at 3.3V. The hardware digital volume control supports Up and Down buttons, as well as an “infinity” volume control knob commonly found in high-end Audio and Video (AV) equipment. Host processor interrupts can be generated based on various events such as class-D errors, jack sense activity, and hardware volume control changes to avoid driver and system polling overheads and ensure immediate event detection. The CODEC drivers for all major OSs are available. • • • • • In-house developed super wideband Voice Processing Algorithms (VPAs) enhance the clarity of Voice-over-Internet Protocol (VoIP) calls and improve the accuracy of voice commands and dictation Far Field Pickup enables long-range speakerphone applications for chat and multi-participant conference calls Multi-band dynamic EQ further improves the sound quality of low-cost speakers and prevents speaker rattle and distortion Phantom bass creates virtual bass content on mainstream speakers 3D headphone recreates a surround, speaker-like environment in headphones so users can enjoy a richer and fuller music listening experience Conexant Confidential 07/31/14 008DSR00 1 CX20745 Data Sheet Features Features • • Depending on the master clock, the CX20745 has a stereo 8-bit/16-bit/24-bit: – DAC that supports sample rates capable of 8kHz, 8.018kHz,11.025kHz, 12kHz, 16kHz, 16.0364kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz ■ 98dB dynamic range, 101dB SNR ■ –85dB THD – ADC that supports sample rates capable of 8kHz, 8.018kHz, 11.025kHz, 12kHz, 16kHz, 16.0364kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz Provides independent gain and mute control for both DAC and ADC • Data interface—I2S that can be converted to PCM • Control Interface—I2C slave only • • Supports master clocks of 24.576MHz and 22.5792MHz Audio ports: – Stereo analog input port supports up to two single-ended mono microphones, one differential mono microphone, one single-ended stereo line input, or one differential mono line input. – Open Mobile Terminal Platform (OMTP) headset jack is compliant with integrated in-line command sensing. Microphone Bias (micbias) sensing capability for external headset control. Supports autosense and switching between the MIC and GND pins. – Stereo class-D amplifier – Stereo capless headphone port – Single-ended analog line output (stereo) – Digital microphone input (stereo) Class-D amplifier with the following modes of operation: – Up to 2W per channel into 4, with 5V supply – Up to 1W per channel into 4, with 3.3V supply – Spread spectrum for EMI protection on the class-D amplifier Integrated hardware DSP features a: – Five-band EQ – DRC that provides a compressor and limiter – Microphone AGC Line-in Loopback mode, where the input signal loops back to the DAC for playback with the EQ/DRC PopShield active anti-pop ensures no pops or clicks All digital interfaces operate at 3.3V Integrated LDO converts 5V to 3.3V, and 3.3V to 1.8V PDM digital microphone interface supports a clock frequency of 3.072MHz and 1.536MHz Jack sense supports up to four jacks with selectable de-bounce Four General Purpose Input/Outputs (GPIOs)—Multi-function pins support GPIO, hardware volume controls, and system interrupt generation Power management • • • • • • • • • • Packaging • • CX20745-11Z is packaged in a 48-pin QFN Operating Range: –40°C to 85°C Conexant Confidential 07/31/14 008DSR00 2 CX20745 Data Sheet Applications Applications • • • • • • Mobile Internet devices Tablets Digital dock stations PNDs PMPs Portable gaming systems Block Diagram The following figure shows the CX20745 block diagram. SENSE_A Jack Sense Capless HP Out 32Ω Micbias Bias Generator Capless HP Out 32Ω 2W Class-D 4Ω Line/Mic In M ADC AGC Σ M + - Five Band EQ DRC Five Band EQ DRC PWM Out DAC Fault 2W Class-D 4Ω Line/Mic In M ADC Σ M AGC DAC 10K Line M 3.3V_FILT 3.3V LDO 5.0V_IN 3.3V_IN TX_WS/SYNC TX_DAT 1.8V_FILT 1.8V LDO PCM/I2S BIT_CLK PCM/I2S RX_WS/SYNC I2C Slave RX_DAT Clock Circuitry SCL Master Clock 10K Line BIT_CLK Mic Clock M Digital Mic SDA Mic Data PWM Out Figure 1: CX20745 Block Diagram Conexant Confidential 07/31/14 008DSR00 3 CX20745 Data Sheet Hardware Interface Hardware Interface The following figure provides the hardware interface signals. Analog Power Digital Power 21/29 30 33 3/45 4 44 14 16 C lass-D Power 19 39 13 37 Charge Pump Flying Cap GPIOs Reset 38 36 AVDD_3.3 AVDD_5V AVDD_HP VDD VDDO2 DIG_MIC_DATA DIG_MIC_CLK VDDO1 LEFT+ LEFTRIGHTRIGHT+ DVDD_3.3_CD LEFT PWR RIGHT PWR DVDD_3.3_CP CLASSD_REF CX20745 48-Pin QFN FLY_N FLY_P LINE_IN_R LINE_IN_L GPIO2 GPIO3 12 RSTN 1 2 5 6 7 8 9 10 11 47 32 34 HP_L 35 GPIO4 Class-D Amp 27 LINE_OUT_L SENSE Digital Mic 15 17 18 20 LINE_OUT_R HP_R GPIO1 I2S/I2C Signals 46 28 31 AVEE 40 41 42 43 49 Pin 49 r efer s to the exposed ground paddle MCLK SCL SDA DSCLK DSDATA DLRCLK ASCLK ASDATA ALRCK 24 IREF VREF_1p65 22 23 MICBIAS 26 Analog Signals J ac k Sens e Reference Voltage EP/GND Microphone Bias Figure 2: Hardware Interface Signals Conexant Confidential 07/31/14 008DSR00 4 CX20745 Data Sheet Pin Information Pin Information Pin Configuration T E ST D IG _M IC _C LK D IG _M IC _D AT A V DD V DD O 1 G PIO 4 G PIO 3 G PIO 2 G P IO 1 D VD D _3 .3_ C P F L Y_P F L Y_ N 45 44 43 42 41 40 39 38 37 1 2 36 AVE E 35 34 33 32 31 HP _L HP _R AVD D _H P LIN E_ O U T _R LIN E_ O U T _L 30 29 28 AVD D _5 V A VD D _3 .3 LINE_IN_L 11 27 26 12 25 LINE_IN_R M IC BIAS NC 24 C X2 0 7 4 5 SEN S E 10 V R EF _1 P65 AS DA T A AL RC L K RSTN 18 19 20 21 22 23 6 7 8 9 16 17 D SC L K DS DA T A D L RC L K ASC L K L EF T PW R LE FT R IG HT R IG H T PW R R IG HT + AV DD _ 3.3 IR EF 3 4 5 13 14 15 SCL VD D V D DO 2 SD A CLASSD_REF D VD D _3. 3_ CD LE F T+ MC L K 48 47 46 The following figure shows the CX20745 pin configuration. Figure 3: CX20745 48-QFN Pin Configuration Note: Pin 49 (paddle) is ground. Conexant Confidential 07/31/14 008DSR00 5 CX20745 Data Sheet Pin Information Pin Assignments The following table lists the CX20745 pin assignments. Table 1: Pin Assignments Pad Number Signal Name Pad Number Signal Name 1 MCLK 26 MICBIAS 2 SCL 27 LINE_IN_R 3 VDD 28 LINE_IN_L 4 VDDO2 29 AVDD_3.3 5 SDA 30 AVDD_5V 6 DSCLK 31 LINE_OUT_L 7 DSDATA 32 LINE_OUT_R 8 DLRCK 33 AVDD_HP 9 ASCLK 34 HP_R 10 ASDATA 35 HP_L 11 ALRCK 36 AVEE 12 RSTN 37 FLY_N 13 CLASSD_REF 38 FLY_P 14 DVDD_3.3_CD 39 DVDD_3.3_CP 15 LEFT+ 40 GPIO1 16 LEFTPWR 41 GPIO2 17 LEFT- 42 GPIO3 18 RIGHT- 43 GPIO4 19 RIGHTPWR 44 VDDO1 20 RIGHT+ 45 VDD 21 AVDD_3.3 46 DIG_MIC_DATA 22 IREF 47 DIG_MIC_CLK 23 VREF_1p65 48 TEST 24 SENSE 49 EP/PADDLE 25 NC Conexant Confidential 07/31/14 008DSR00 6 CX20745 Data Sheet Pin Information Pin Signal Definitions Table 2 provides the CX20745 pin description. The following lists the acronyms used in this table: • • • • AI = Analog In AO = Analog Out DI = Digital In DIO = Digital Input/Output • • • • DO = Digital Out PD = Pull-Down PU = Pull-Up PWR = Power Table 2: Pin Signal Definitions Pin Number I/O Type Signal Name/Description VDD 3/45 PWR Output Voltage from LDO. 1.8V—Connect to an external decoupling capacitor. VDDO2 4 PWR Digital Supply Voltage. 3.3V (+5%). DVDD_3.3_CD 14 PWR Class-D 3.3V Supply. 3.3V (+5%). LEFTPWR 16 PWR Class-D Left Supply Voltage. Connect to 3.3V to 5V (+5%). RIGHTPWR 19 PWR Class-D Right Supply Voltage. Connect to 3.3V to 5V (+5%). AVDD_3.3 21/29 PWR 3.3V LDO Output (can be used as an input if by-passing the LDO). 3.3V (5%). AVDD_5V 30 PWR 5V LDO Input Supply Voltage. Connect to +5V (+5%). For 3.3V-only operation, the LDO may be bypassed by connecting AVDD_5V to AVDD_3.3 (pins 21/29) and to the 3.3V (+ 5%) supply. AVDD_HP 33 PWR Headphone 3.3V Supply (+ 5%). AVEE 36 PWR Internally Generated Analog Negative Supply. Connect to an external decoupling capacitor. FLY_N 37 PWR Charge Pump Fly Capacitor. Connect to FLY_P through a 1μF capacitor. FLY_P 38 PWR Charge Pump Fly Capacitor. Connect to FLY_N through a 1μF capacitor. DVDD_3.3_CP 39 PWR Headphone Negative Charge Pump. 3.3V (+5%). VDDO1 44 PWR Digital Supply Voltage. 3.3V (+5%). EP/GROUND 49 PWR Ground (Paddle). Label Power Digital Audio and Interface MCLK 1 Digital In 24.576MHz/22.5792MHz Input Clock. MCLK must be a derivative of the I2S bit clocks for proper operation. SCL 2 Digital Out I2C Clock. SDA 5 Digital In I2C Data-in from the Host. DSCLK 6 Digital In I2S Bit Clock for the Receiver (Rx). DSDATA 7 Digital In I2S Data for Rx. DLRCK 8 Digital In I2S Word Clock for Rx. ASCLK 9 Digital In I2S Bit Clock for the Transceiver (Tx). ASDATA 10 Digital In I2S Data for Tx. Conexant Confidential 07/31/14 008DSR00 7 CX20745 Data Sheet Pin Information Table 2: Pin Signal Definitions (Continued) Label Pin Number I/O Type Signal Name/Description ALRCK 11 Digital In I2S Word Clock for Tx. DIG_MIC_DATA 46 Digital In Digital Microphone Data. DIG_MIC_CLK 47 Digital Out Digital Microphone Clock. Analog Audio and Signals LEFT+ 15 Analog Out Class-D Left (+) Output. LEFT- 17 Analog Out Class-D Left (–) Output. RIGHT- 18 Analog Out Class-D Right (–) Output. RIGHT+ 20 Analog Out Class-D Right (+) Output. SENSE 24 Analog In Jack Sense Input. LINE_IN_R 27 Analog In Mic/Line-in Right/Line-in Mono (-). LINE_IN_L 28 Analog In Mic/Line-in Left/Line-in Mono (+). LINE_OUT_L 31 Analog Out Line-out Left. LINE_OUT_R 32 Analog Out Line-out Right. HP_R 34 Analog Out Headphone Right Output. HP_L 35 Analog Out Headphone Left Output. CLASSD_REF 13 REF Class-D Reference. Connect through a 0.1μF capacitor to the LEFTPWR/RIGHTPWR supply. IREF 22 REF Current Reference. Connect to the analog ground through a 54.9k (1%) resistor. VREF_1p65 23 REF Internal Analog Reference (Filter Pin). MICBIAS 26 REF Micbias Output. RSTN 12 Digital In Active-low CODEC Reset. GPIO1 40 Digital I/O GPIO1. GPIO2 41 Digital I/O GPIO2. GPIO3 42 Digital I/O GPIO3. GPIO4 43 Digital I/O GPIO4. Reference GPIO/Test/Other Conexant Confidential 07/31/14 008DSR00 8 CX20745 Data Sheet Electrical Characteristics Electrical Characteristics Table 3: General Parameter Minimum Nominal Maximum Unit Comments Temperature -40 27 125 °C Junction temperature. Table 4: Mic/Line Input Parameter Minimum Nominal Maximum Unit Comments Gain 0 - 40 dB In steps of 10dB. Full Scale Input Signal - 1 - VRMS AC-coupled. Dynamic Range1 - 87 - dBFS A-weighted, 20kHz to 20kHz. THD plus Noise (THD+N) at –3dBFS - –80 - dBFS 20kHz to 20kHz. Input Resistance - 15 kΩ 15kΩ with 0dB gain, otherwise 5kΩ. 5 1 = The dynamic range is the ratio of the full scale signal level to the RMS noise floor in the presence of the signal, expressed in dBFS. This ratio should be measured by performing a THD+N measurement with a –60dBFS signal. Table 5: Class-D/Speaker Output Parameter Minimum Nominal Maximum Unit Comments Power - • - 2W - • Output Load Dynamic Range1 THD+N at –3dBFS 5V mode: – Up to 2 with channel 4Ω when a headphone is not in use – Up to 1.5 with channel 4Ω when a headphone is in use 3V mode: Up to 1 with channel 4Ω - 4 - Ω 752 - 85 90 dBFS A-weighted, 20kHz to 20kHz. - –65 - dBFS 20kHz to 20kHz into 4Ω. 1 = The dynamic range is the ratio of the full scale signal level to the RMS noise floor in the presence of the signal, expressed in dBFS. This ratio should be measured by performing a THD+N measurement with a –60dBFS signal. 2 = Although the CX20745 System-on-a-Chip (SoC) audio CODEC is designed to provide nominal class-D dynamic range performance of 85 dBFS, testing has found that some production parts have an actual performance value as low at 75dBFS. Table 6: Line Output Parameter Minimum Nominal Maximum Unit Comments Full Scale Output Signal - 1 - VRMS AC-coupled. Output Load 10 - - kΩ - 98 - dBFS A-weighted, 20kHz to 20kHz. THD+N at –3dBFS - –85 - dBFS 20kHz to 20kHz into a 10kΩ load. Crosstalk - –70 - dB Dynamic Range1 - - 1 = The dynamic range is the ratio of the full scale signal level to the RMS noise floor in the presence of the signal, expressed in dBFS. This ratio should be measured by performing a THD+N measurement with a –60dBFS signal. Conexant Confidential 07/31/14 008DSR00 9 CX20745 Data Sheet Electrical Characteristics Table 7: Headphone Output Parameter Minimum Nominal Maximum Unit Comments Full Scale Output Signal - 1 - VRMS - Output Offset –8 0 8 mV Reduces to + 250μV with offset cancellation. Output Load 16 32 - Ω Can drive –3dBFS into 16Ω without clipping. Dynamic Range1 95 - - dBFS A-weighted, 20kHz to 20kHz. THD+N at –3dBFS - - –85 dBFS 20kHz to 20kHz into a 10kΩ load. Crosstalk - - –70 dB - 1 = The dynamic range is the ratio of the full scale signal level to the RMS noise floor in the presence of the signal, expressed in dBFS. This ratio should be measured by performing a THD+N measurement with a –60dBFS signal. Table 8: Charge Pump Parameter Minimum Nominal Maximum Unit Comments Input Voltage 3 3.3 3.6 V dvddh_cpump. Output Voltage –2 - –2.6 V avee_cpump, programmable. Current Load avee = –2 avee = –2.6 - - 250 150 mA mA - Clock Frequency - 500 - kHz - Table 9: Micbias Parameter Minimum Nominal Maximum Unit Comments Output Voltage - Pad Voltage when Bias Disabled –3.3 1.65 2.65 V Programmable to be 50%—60% or 80% of supply. - 3.3 V When disabled, the micbias is high-Z with an option to ground the micbias pad. Table 10: Jack Sensing Parameter Minimum Nominal Maximum Unit Comments Input Voltage 0 - 3.3 V Off-chip resistor network should be connected to the AVDDH chip supply. Pad Sampling Interval - 10 - ms Sampling on sense is interleaved. The ADC outputs on the sense are de-bounced over 12 samples. SAR Clock Rate - 500 - kHz Using a Resistor–Capacitor (RC) oscillator. Conexant Confidential 07/31/14 008DSR00 10 CX20745 Data Sheet Electrical Characteristics Table 11: Voltage Regulator Parameter Minimum Nominal Maximum Unit Comments LDO Supply Voltage 3.5 5 5.5 V avdd5v. Output Voltage 3.3 3.55 V • • 3.15 avddh avddh_sc, avddh_port Table 12: Power Consumption Voltage Power (V) (mW) State Description Standby DAC/ADC Off, Output VDDO1, VDDO2 Ports Muted in D3, External Clock Removed AVDD_3.3, AVDD_5V1 3.3 13.93 3.3 3.34 Silent VDDO1, VDDO2, AVDD_3.32 3.3 48.84 Full Scale VDDO1, VDDO2, AVDD_3.32 3.3 50.16 VDDO1, VDDO2 3.3 42.90 AVDD_3.3, AVDD_HP, DVDD_3.3_CP3 3.3 45.54 VDDO1, VDDO2 3.3 44.06 AVDD_3.3, AVDD_HP, DVDD_3.3_CP3 3.3 61.71 VDDO1, VDDO2 3.3 44.06 3.3 211.20 VDDO1, VDDO2, AVDD_3.3, DVDD_3.3_CD1 3.3 78.87 LEFTPWR, RIGHTPWR 3.3 28.71 3.3 78.21 LEFTPWR, RIGHTPWR 3.3 2455.20 VDDO1, VDDO2, AVDD_3.3, DVDD_3.3_CD1 3.3 78.87 LEFTPWR, RIGHTPWR 5 65 VDDO1, VDDO2, AVDD_3.3, DVDD_3.3_CD1 3.3 78.21 LEFTPWR, RIGHTPWR 5 4635 Line Level Stereo Playback (10kΩ) Play Silence Headphone Stereo Playback (32Ω) Play 1mW output Play Full Scale Supply AVDD_3.3, AVDD_HP, Class-D Stereo Playback (4Ω Speaker, 3.3V Supply, 1W) Class-D Stereo Playback (4Ω Speaker, 5V Supply, 2W) Play Silence Play Full Scale Play Silence Play Full Scale DVDD_3.3_CP3 VDDO1, VDDO2, AVDD_3.3, DVDD_3.3_CD1 Stereo Recording Line Level VDDO1, VDDO2, AVDD_3.34 3.3 53.10 Full-duplex—Line In and Headphone Silence VDDO1, VDDO2, AVDD_3.3, DVDD_3.3_CP, AVDD_HP5 3.3 129.69 Line Input to Silence Headphone Digital Loop VDDO1, VDDO2, AVDD_3.3, DVDD_3.3_CP, AVDD_HP5 3.3 127.05 1 = The DVDD_3.3_CP and AVDD_HP supplies are grounded. The AVDD_5V supply is connected to AVDD_3.3 (LDO bypassed). 2 = The AVDD_HP, DVDD_3.3_CP, DVDD_3.3_CD, LEFTPWR, and RIGHTPWR supplies are all grounded. The AVDD_5V supply is connected to AVDD_3.3 (LDO bypassed). 3 = The DVDD_3.3_CD, LEFTPWR, RIGHTPWR supplies are all grounded. The AVDD_5V supply is connected to AVDD_3.3 (LDO bypassed). 4 = The AVDD_HP, DVDD_3.3_CP, DVDD_3.3_CD, LEFTPWR, RIGHTPWR supplies are all grounded. The AVDD_5V supply is connected to AVDD_3.3 (LDO bypassed). 5 = The LEFTPWR, RIGHTPWR, DVDD_3.3_CD supplies are all grounded. The AVDD_5V supply is connected to AVDD_3.3 (LDO bypassed). Conexant Confidential 07/31/14 008DSR00 11 CX20745 Data Sheet Package Dimensions and Thermal Specifications Package Dimensions and Thermal Specifications The following figure provides the CX20745 package diagram. S Y M B O L A A1 A2 A3 D D1 E E1 Θ P Q R COMMON DIMENSIONS MIN. NOM. MAX 0.80 0.00 0.60 0.85 0.01 0.65 0.20 REF. 6.00 BSC 5.75 BSC 6.00 BSC 5.75 BSC -0.42 0.40 0.17 0.90 0.05 0.70 0 0.24 0.30 0.13 12o 0.60 0.65 0.23 10 8, 11 8, 11 GENERAL: NOMINAL EXPOSED PAD D2/E2 DIMENSION = NOMINAL DIE ATTACH PAD DIMENSION - 0.20 NOMINAL DIE ATTACH PAD DIMENSION 0.10 NOMINAL EXPOSED PAD D2/E2 DIMENSION 0.10 <DIE ATTACH PAD X - SECTION VIEW> 4.30 4.30 4.40 4.40 4.50 4.50 Figure 4: Package Diagram Conexant Confidential 07/31/14 008DSR00 12 CX20745 Data Sheet Device Description The following table defines the thermal specifications. Table 13: Thermal Specifications Parameter Symbol Minimum Typical Maximum Units Notes Theta-JA (Junction-to-Ambient JA Thermal Resistance) - 31.91 - o Psi-JT (Junction-to-Package JT Top Thermal Characterization Parameter) - 0.09 - o C/W Four-layer Printed Circuit Board (PCB) with a solid ground plane and thermal vias (still air). C/W Four-layer PCB with a solid ground plane and thermal vias (still air). Note: Measurements are per the JEDEC EIA/JESD 51 standard. The JA of application boards with more than four layers stay the same or improve if the PCB construction is similar to the JEDEC EIA/ JESD 51 defined four-layer PCB (2S2P plus vias). Device Description Analog Audio Input Paths Analog-to-Digital Converter (ADC) One stereo ADC is connected to the mic/line input. Conexant supports sample widths of 8-bit, 16-bit, and 24-bit at sample rates of either: • • 8kHz, 12kHz, 24kHz, 32kHz, and 48kHz at the 24.576MHz master clock 8.0182kHz, 11.025kHz, 16.0364kHz, 22.05kHz, or 44.1kHz at the 22.5792MHz master clock Microphone/Line Input Two analog input buffers with adjustable gain settings. With the gain set at 0dB, the input buffer can accept a 1VRMS signal. Microphone Bias (Micbias) Generator The bias generator is capable of generating a controllable 2.64V (8% of 3.3V) bias voltage to support an analog microphone. The bias voltage can be disabled, which puts the bias buffer in a low-power and highimpedance mode. The buffer output pads allow for a full 1VRMS swing below ground without and impedance change. Conexant Confidential 07/31/14 008DSR00 13 CX20745 Data Sheet Analog Audio Output Paths Jack Sense Jack sense is provided that can sense up to four jacks using an external resistor divider network. Grounding a resistor indicates that an audio device is connected to the corresponding port. It is possible to map the four jack sense bits to any input or output port. The de-bounce time is adjustable with a default of 250ms. Table 14: Jack Sense Impedance Values Jack Impedance Line-out 5.11kΩ Line/MIc-R 10kΩ Line/Mic-L 20kΩ Headphone 39.2kΩ Analog Audio Output Paths Digital-to-Analog Converter (DAC) One stereo DAC is available with sample widths of 8-bit, 16-bit, and 24-bit at sample rates of either: • • 8kHz, 12kHz, 24kHz, 32kHz, 48kHz, and 96kHz at the 24.576MHz master clock 8.0182kHz, 11.025kHz, 16.0364kHz, 22.05kHz, 44.1kHz, or 88.2kHz at the 22.5792MHz master clock Line-Out The line output can drive 1VRMS into a 10k load, and meets the DAC path performance specifications. The line-outs have the following configuration options: • • • Power on/off Differential or single-ended operating mode 1VRMS or 2VRMS output level (differential mode) • Mute on/off Class-D/Pulse-Width Modulation (PWM) The output drivers can be configured for either Pulse-Width Modulation (PWM) or class-D speaker output. The drivers can either provide differential PWM output signals to drive external class-D amplifiers or can drive up to 2W RMS into 4 speakers, and meet the specified speaker path performance requirements. The class-D/PWM outputs have the following configuration options: • • • • • Power on/off PWM or class-D mode Spread spectrum clocking and low EMI clocking Single-channel operation Over current protection, under voltage protection, and over temperature protection Conexant Confidential 07/31/14 008DSR00 14 CX20745 Data Sheet Digital Audio Capless Headphone Driver Two output drivers can be configured for either line-out (10k load) or headphone-out (32 load). The drivers can drive 50mW into a 32 load or 1VRMS into a 10k load, and meet the specified DAC path performance requirements. The capless headphone outputs have the following configuration options: • • Power on/off Mute on/off Digital Audio Pulse Code Modulation (PCM)/Integrated Interchip Sound (I2S) Interface The CX20745 CODEC contains a single digital data audio interface either through I2S Tx/Rx or through the PCM. A six-wire I2S T/Rx can be converted to a six-wire PCM interface through the I2C control. The following lists the six wires for the interface: • • • • • • DSCLK DSATA DLRCK ASCLK ASDATA ALRCK The I2S Tx and Rx support different sampling frequencies of either 48K or 44.1K multiples. Both PCM and I2S only support the slave configuration. Table 15 and Table 16 provide the supporting sampling frequency with the associated bit clock. Table 15: DAC DAC Sample Rate DAC Bit Clock Master Clock 8kHz (BCLK/64) 0.512MHz (MCLK/48) 24.576MHz 12kHz (BCLK/64) 0.768MHz (MCLK/32) 24.576MHz 16kHz (BCLK/64) 1.024MHz (MCLK/24) 24.576MHz 24kHz (BCLK/64) 1.536MHz (MCLK/16) 24.576MHz 32kHz (BCLK/64) 2.048MHz (MCLK/12) 24.576MHz 48kHz (BCLK/64) 3.072MHz (MCLK/8) 24.576MHz 96kHz (BCLK/64) 6.144MHz (MCLK/4) 24.576MHz 8.0182kHz (BCLK/64) 0.513MHz (MCLK/44) 22.5792MHz 11.025kHz (BCLK/64) 0.7056MHz (MCLK/32) 22.5792MHz 16.0364kHz (BCLK/64) 1.026MHz (MCLK/22) 22.5792MHz 22.05kHz (BCLK/64) 1.44112MHz (MCLK/16) 22.5792MHz 44.1kHz (BCLK/64) 2.8224MHz (MCLK/8) 22.5792MHz 88.2kHz (BCLK/64) 5.6448MHz (MCLK/4) 22.5792MHz Conexant Confidential 07/31/14 008DSR00 15 CX20745 Data Sheet Digital Audio Table 16: ADC ADC Sample Rate ADC Bit Clock Master Clock 8kHz (BCLK/64) 0.512MHz (MCLK/48) 24.576MHz 12kHz (BCLK/64) 0.768MHz (MCLK/32) 24.576MHz 16kHz (BCLK/64) 1.024MHz (MCLK/24) 24.576MHz 24kHz (BCLK/64) 1.536MHz (MCLK/16) 24.576MHz 32kHz (BCLK/64) 2.048MHz (MCLK/12) 24.576MHz 48kHz (BCLK/64) 3.072MHz (MCLK/8) 24.576MHz 8.0182kHz (BCLK/64) 0.513MHz (MCLK/44) 22.5792MHz 11.025kHz (BCLK/64) 0.7056MHz (MCLK/32) 22.5792MHz 16.036kHz (BCLK/64) 1.026MHz (MCLK/22) 22.5792MHz 22.05kHz (BCLK/64) 1.44112MHz (MCLK/16) 22.5792MHz 44.1kHz (BCLK/64) 2.8224MHz (MCLK/8) 22.5792MHz I2S Figure 5 shows the transmitter and receiver configuration in relationship with master and slave terminology. The CX20745 operates in slave mode only. Clock SCK Transmitter Clock SCK Word Select WS Data SD CX20745 (Receiver) CX20745 (Transmitter) Transmitter = Master Word Select WS Data SD Receiver Receiver = Master Figure 5: Transmitter and Receiver Configuration The CX20745 I2S interface supports three different modes of the data transfer operation. Conexant Confidential 07/31/14 008DSR00 16 CX20745 Data Sheet Digital Audio I2S Justified The I2S timing uses LRCK to define when the data being transmitted is for the left and right channels. The WS is low for the left channel, and high for the right channel. A WS polarity control bit is provided to allow either high or low to represent the left channel. The default setting of the polarity control is 0, which means low WS = left channel. The WS does not need to be symmetrical. A system clock (clk_au) running at a minimum of 2 x (sample width +1) x sample frequency is used to clock in the data. There is a delay of one clock bit from the time the LRCK signal changes state to the first data bit on the data line. The data is written Most Significant Bit (MSB) first, and is valid on the rising edge of the bit clock. When the programmed sample width is taken, any remaining bits are ignored. 1/fs L-Channel 1 2 3 R-Channel N-2 N-1 N MSB 1 LSB 2 3 N-2 N-1 N MSB 1 2 LSB Figure 6: I2S Timing Important! One case to be careful of in dealing with I2S is when the number of bits in the sample word matches the number of clocks per frame. Because true I2S requires a one-clock shift of the data, the Least Significant Bit (LSB) of each word arrives after the WS signal changes state (illustrated in Figure 7). To handle this correctly, the internal channel indicator should only change state after the bit count is reached and the state of LRCK does not match the expected value for the current channel. LRCLK 16 Clks 16 Clks Left Channel Right Channel SCLK SCLK MSB LSB LSB MSB 16-bit Mode 15 14 13 12 11 10 9 8 5 4 3 2 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1 Figure 7: One-Clock Data Shift Conexant Confidential 07/31/14 008DSR00 17 CX20745 Data Sheet Digital Audio Left-Justified Left-justified timing uses the LRCK clock to define when the data being transmitted is for the left and right channels. The WS is high for the left channel, and low for the right channel (requires the WS polarity control bit to be set to 1). A bit clock running at a minimum of 2 x sample width x sample frequency is used to clock the data. The first data bit appears on the data lines at the same time that LRCK toggles. The data is written MSB first and is valid on the rising edge of bit clock. When the programmed sample width is taken, any remaining bits are ignored. If the LRCK toggles before the full word length is read, the remaining bits are zeroed. 1/fs L-Channel R-Channel 1 2 3 N-2 N-1 N 1 LSB MSB 2 3 N-2 N-1 N MSB 1 2 LSB Figure 8: Left-Justified Timing Right-Justified Right-justified timing uses the LRCK clock to define when the data being transmitted is for the left and right channels. The WS is high for the left channel, and low for the right channel (requires the LRCK polarity control bit to be set to 1). A bit clock running at a minimum of 2 x sample width x sample frequency is used to clock the data. Data is captured in a 24-bit shift register until LRCK toggles. When LRCK toggles, the last 24/16/8 bits are transferred to the channel indicated by the previous state of LRCK. In right-justified mode, the LSB of data is always clocked by the last bit clock before the LRCK transitions. The data is written MSB first and is valid on the rising edge of bit clock. All leading bits are ignored. 1/fs L-Channel 14 15 16 1 MSB 2 R-Channel 3 14 15 16 LSB 1 MSB 2 3 14 15 16 LSB Figure 9: Right-Justified Timing Conexant Confidential 07/31/14 008DSR00 18 CX20745 Data Sheet Digital Audio I2S Timing Transmitter • • • SCK -> ASCLK (CX20745) SD - > ASDATA (CX20745) WS - > ALRCK (CX20745) T tRC tLC > 0.35T tHC > 0.35T SCK thtr > 0 tdtr < 0.8T SD and WS VH = 2.0V VL = 0.8V Figure 10: I2S Transmitter Timing Note: • • T = Clock period ttr = Minimum allowed clock period for transmitter T > ttr • tRC = Only relevant for transmitter in slave mode Table 17: Master Transmitter with a Data Rate of 2.5MHz (±10%) (All Values in ns) Name Minimum Typical Maximum Condition Clock Period T 360 400 440 Ttr = 360 Clock HIGH tHC 160 - - Minimum > 0.35T = 140 (at the typical data rate) Clock LOW tLC 160 - - Minimum > 0.35T = 140 (at the typical data rate) Delay tdtr - - 300 Maximum > 0.80T = 320 (at the typical data rate) Hold Time thtr 100 - - Minimum > 0 - 60 Maximum > 0.15Ttr = 54 (only relevant in the slave mode) Clock Rise Time tRC - I2S Receiver • • • SCK - > DSCLK (CX20745) SD - > DSDATA (CX20745) WS - > DLRCK (CX20745) Table 18: Slave Receiver with a Data Rate of 2.5MHz (±10%) (All Values in ns) Name Minimum Typical Maximum Condition Clock Period T 360 400 440 Ttr = 360 Clock HIGH tHC 110 - - Minimum > 0.35T = 126 Clock LOW tLC 110 - - Minimum > 0.35T = 126 Setup Time tsr 60 - - Minimum > 0.20T = 72 Hold Time thtr 0 - - Minimum > 0 Conexant Confidential 07/31/14 008DSR00 19 CX20745 Data Sheet Digital Audio PCM There are three modes of operation for PCM: • • • Short frame mode Long frame mode Multi-slot mode In short frame mode, the falling edge of PCM_SYNC indicates the start of the PCM word. The PCM_SYNC is one clock long. Data is driven out on the rising edge of PCM_CLK after the PCM_SYNC pulse. PCM_SYNC PCM_CLK PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCM_IN Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Undefined Figure 11: Short Frame Sync (Shown with 16-Bit Sample) In long frame mode, the rising edge of PCM_SYNC indicates the start of the PCM word. The PCM_SYNC is at least two clocks long. Data is driven out on the rising edge of PCM_CLK coincident with the rising edge of PCM_SYNC. PCM_SYNC PCM_CLK PCM_OUT PCM_IN Undefined 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 8 Undefined Figure 12: Long Frame Sync (Shown with 8-Bit Companded Sample) In multi-slot mode, PCM_SYNC can be either long or short. Three words of data can be sent or received. The position of the start of the PCM word is determined by the length of the sync pulse. Slots are determined by counting data width clocks (8, 16, or 24) from the first PCM word. Conexant Confidential 07/31/14 008DSR00 20 CX20745 Data Sheet Digital Audio Control Interface The control interface is through a two-wire I2C. The device address is 0x14. Register Read/Write Operation Write to a Slave Device 1. Send a start sequence. 2. Send the I2C address of the slave. 3. Send the internal register number you want to write to. 4. Send the data byte. 5. Optional: Send any further data bytes. 6. Perform the burst operation. 7. Send the stop sequence. Read from a Slave Device 1. Send a start sequence. 2. Send I2C address of the slave. 3. Send the internal address of the bearing register. 4. Send a start sequence again (repeated start). 5. Read the data byte. 6. Send the stop sequence. Register Address: Transferring Data on the Inter-Integrated Circuit (I2C) Bus Every byte put on the Serial Data Automation (SDA) line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first, as shown in the following figure. P SDA Acknowledgement Signal from Slave MSB Acknowledgement Signal from Receiver Sr Byte Complete Interrupt within the Slave Clock Line Held Low While Interrupts are Serviced SCL S or Sr 1 2 7 8 9 1 2 ACK START or Repeated START Condition 3-8 9 ACK Sr or P STOP or Repeated START Condition Figure 13: Transferring Data on I2C Conexant Confidential 07/31/14 008DSR00 21 CX20745 Data Sheet Digital Audio A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. The START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The following figure shows a possible data transfer format. S SLAVE ADDRESS A R/W 0 (Write) from Master to Slave DATA A DATA A/A P Data Transferred (n Bytes + Acknowledge) A = Acknowledge (SDA LOW) A = Not Acknowledge (SDA HIGH) S = START Condition from Slave to Master P = STOP Condition Figure 14: Data Transfer Format Slave Address Format The following table shows the slave addressing format for I2C. Table 19: Slave Addressing Format for I2C Slave Address R/W Bit Description 0000 000 0 General call address. 0000 000 1 START byte. 0000 001 X CBUS address. 0000 010 X Reserved for a different bus format. 0000 011 X Reserved for future purposes. 0000 1XX X Hs-mode master code. 1111 1XX X Reserved for future purposes. 1111 0XX X 10-bit slave addressing. Conexant Confidential 07/31/14 008DSR00 22 CX20745 Data Sheet Digital Signal Processing (DSP) I2C Interface 400kHz Timing The following figure defines the timing of the F/S-mode devices on the I2C bus. SDA tLOW tf tSU:DAT tr tf tHD:STA tSP tBUF tr SCL S tHD:STA tHD:DAT tSU:STA tHIGH tSU:STO P Sr S MSCS10 Figure 15: Definition of Timing for F/S-Mode Devices on the I2C Bus Table 20: I2C Conditions I2C (400kHz) Symbol Minimum Maximum Setup Time Start Condition tSU.STA 0.6μs - Hold Time Start Condition tHD.STA 0.6μs - SCL Clock LOW Period tLOW 1.3μs - SCL Clock HIGH Period tHIGH 0.6μs - Data Setup Time tSU.DAT 100ns - Data Hold Time tHD.DAT 0 0.9μs Setup Time for STOP Condition tSU.STO 0.6μs - Digital Signal Processing (DSP) A DSP system with a digital audio input signal in the range of 0kHz to 20kHz uses oversampling techniques, and a third order delta-sigma modulator to convert the 8-bit/16-bit/24-bit digital signal at the following sampling frequencies: • • 48kHz/ 96kHz/8kHz/12kHz/16kHz/24kHz/32kHz/ into a multi-bit stream at a rate of 12.288MHz 88.2kHz/44.1kHz/22.05kHz/11.025kHz/8.0182kHz/16.0364kHz into a multi-bit stream at a rate of 11.2896MHz DAC Digital Filters I2S Interface Digital Gain Five Band Equalizer DRC Digital Filters INTERP SDM DAC Figure 16: DAC Digital Section Conexant Confidential 07/31/14 008DSR00 23 CX20745 Data Sheet Digital Signal Processing (DSP) Equalizer (EQ)/Dynamic Range Compressor (DRC) The CX20745 includes a five-band, bi-quad Infinite Impulse Response (IIR) hardware EQ (with bypass capability). The function of the EQ is to adjust the frequency characteristics of the output to compensate for unwanted frequency characteristics in the speakers or ear pieces. The EQ can also be used to tailor the response according to user preferences. Typical EQ band types include lo-shelf/pass, hi-shelf/pass, and band-pass/peaking. Each EQ band stage is a second order IIR filter. Each IIR has five branches that perform multiplication between the data and coefficients and an accumulator of the products. Dynamic Range Compression (DRC) Ou t C om pSlope LinGain T hreshold In Figure 17: DRC Threshold • • • • • • • Find maximum(abs(sample value)) over a block and convert to dB. At the quarter block interval, calculate a smoothed max_abs. If max_abs goes: – Down (release), slowly increase smoothed max-abs – Up (attack), set smoothed max_abs to max_abs If smoothed max-abs is in the linear region, select the linear gain—Otherwise, calculate the gain for compression. In the compression region, the preferred function is: – Out = CompSlope * in + (1 – CompSlope) * Threshold + LinearGain_dB – Define offset = (1 – CompSlope) * Threshold + LinearGain_dB – Gain = out – in = CompSlope * in + Offset – in Update the gain by (New_target_gain – Gain) * GAIN_STEP_FAST to ensure the gain changes are inaudible. Convert the dB Gain to Linear. Multiply the signal by gain, saturate, and then truncate. Conexant Confidential 07/31/14 008DSR00 24 CX20745 Data Sheet Digital Signal Processing (DSP) Digital Microphone Interface (DMIC) The clock sent to the DMIC device is 3.072MHz and 1.536MHz: • • • • • Two-wire interface (excluding power and ground)—Clock and data Single bit over the sampled output Supports stereo operation: – Left channel outputs on the positive edge of the clock – Right channel outputs on the negative edge of the clock Filtering and down sampling (decimation) is done in CODEC Additional stereo pairs can be added by adding one pin per pair—Shares the same clock V dd Cloc k Data M IC -L Au d io CODEC M IC -R Figure 18: DMIC Table 21: Pins Used Item No. Name Type Description 1 DMIC_CLK Digital Digital microphone clock. 2 DMIC_1/2 Digital Digital microphone inputs 1 and 2. Data Input • • VIL-0.3V (minimum) 0.94V (maximum)—Maximum value adjustable using an on-chip comparator VIH1.2V (minimum) 3.3V (maximum) Clock Output • • • • • Frequency: 3.072MHz VOL0.4V (maximum) VOH2.6V (minimum)—Using full drive output driver capability VOHadjustable (minimum)—Using open-drain output driver capability Default drive strength (4mA) Conexant Confidential 07/31/14 008DSR00 25 CX20745 Data Sheet Digital Signal Processing (DSP) Timing Diagram • • Left data = Output by the digital microphone on the rising edge of the digital microphone clock – Latched by the Conexant device on the falling edge of the digital microphone clock – Setup time = 36ns – Hold time = 0ns Right data = Output by the digital microphone on the falling edge of the digital microphone clock – Latched by the Conexant device on the rising edge of the digital microphone clock – Setup time = 36ns – Hold time = 0ns Th Tsu Digital Mic Clock Digital Mic Data Left Right Right Left Figure 19: DMIC Timing Automatic Gain Control (AGC) Record Path DRC Activity Detected Activity Detector Signal Energy Gain Control Gain Figure 20: AGC Record Path The microphone AGC function is supported by three sections: • • • Activity detector Gain control DRC It is assumed that because the microphone AGC is intended for voice conversation and both channels have similar energy characteristics, the gain is only calculated on one channel and applied to both channels. Conexant Confidential 07/31/14 008DSR00 26 CX20745 Data Sheet Digital Signal Processing (DSP) Activity Detector • • • • • • • • The microphone AGC block supports both 16kHz and 8kHz 16-bit samples. For 16kHz mode, samples are down-sampled to 8kHz by discarding every other sample. The 8kHz samples are then passed through a first order IIR High-Pass Filter (HPF) (DC rejection). Power energy and sample squared are summed in the frame energy current block. Use frame energy to estimate the: – Signal levels using a fast IIR average filter – Noise levels using a slow IIR average filter Has a noise level estimation tracking loop with stability control. In a noisy environment, the noise power level is clipped to a 1.5 times signal power level. If the PowerIn to PowerNoise ratio is above a programmable threshold, which signifies a valid block is detected, then the block frame energy calculated is used to calculate the gain in the gain control block. To reduce sensitivity due to miss detection, if a valid block is not detected, the transition to detection OFF is delayed by a programmable number of hysteresis blocks. Gain Control • • • Can determine the maximum block frame energy (while the detection is high) from the activity detector block in the programmable number of blocks. The sum of the maximum frame energy and gain in dB is used to update the gain. Compare the sum with the programmable energy threshold high and energy threshold low for decreasing or increasing the gain, respectively. Stability logic is used to stabilize the gain from switching between updating the gain up and down too frequently. Conexant Confidential 07/31/14 008DSR00 27 CX20745 Data Sheet Digital Signal Processing (DSP) General Purpose Input/Output (GPIO) Functions Rotary Mode • • GPIO1 -> Clockwise (CW) direction GPIO2 -> Counter Clockwise (CCW) direction Rotary Encoder The following figure shows the EC16B encoder that is used for the CX20745, which is manufactured by the ALPS electricity company in Japan. Figure 21: Rotary Encoder The encoder has three terminals—one is allocated for the common terminal (COM), and the other two are used as a terminal for the output. The output terminal becomes the condition, whether or not it connects with the common terminal. Two terminals for the output differ in the timing, which touches a common terminal when the axis of the encoder is turned. The following figure shows the output relation in the case of EC16B resembles. Figure 22: Rotary Encoder Block Diagram Conexant Confidential 07/31/14 008DSR00 28 CX20745 Data Sheet Digital Signal Processing (DSP) Table 22: EC16B Standard Data Item Description Pulses/Rotation 24. Output code Phase difference of two signals. Rotational Angle 360°. Mounting Method Fastened with a bushing nut. Ratings 5V DC, 0.5mA. Maximum Operating Current 0.5mA. Insulation Resistance 50V DC, 10MΩ minimum. Withstand Voltage 50V AC. Sliding Noise • • t: = Masking time to avoid chattering When R = 100kΩ, t = 5ms V1 = V2 = 1V maximum Chattering Prevention Circuit The chattering prevention circuit is using capacitor (C) to prevent chattering. This phenomenon occurs when using a mechanical switch. The electronic circuits have detected ON, OFF, and sometimes malfunctions. When the chattering prevention circuit is not used, more than one count may rise in spite of being only one count. The Schmidt trigger-type inverter (7414) uses the Darlington connection circuit, and is used to arrange a waveform. This circuit connects a collector at the pre-stage with the base at the following stage directly. In this way, the output turning-over of the inverter becomes high-speed. Vcc COM Rotary Encoder R C Figure 23: Chattering Prevention Circuit Block Diagram Conexant Confidential 07/31/14 008DSR00 29 CX20745 Data Sheet Digital Signal Processing (DSP) Up/Down Detection Circuit The up/down detection circuit determines whether it is a CW or CCW operation compared with two pieces of output from the encoder. This circuit uses a D-type flip-flop (7474) for the determination. The D-type flipflop performs the operation to output the output terminal (Q) in the condition of the D input terminal when the clock (CK) changes into the H condition from the L condition. Clockwise (CW) Operation 1. When the A point changes into H from the L, the ICB clock (CK): • Changes into H from the L • Becomes the condition to receive the D input Because the B point is then in the L condition and the clear terminal of ICB is in the L condition, the ICB output (the Y point) keeps an L condition. Because the clear terminal is always an L when the ICB clock (the A point) becomes H from the L in the CW, the condition of ICB does not change. 2. The B point changes into H from the L. This changes the ICA clock (CK) from the L to H, and the ICA becomes the condition to receive the D input. Because the A point becomes the H condition and a cleared condition is already canceled, the ICA output (the X point) changes into H from the L. 3. An ICA is initialized by the ICA’s clear terminal, the ICA output (the X point) changes into the L from H when the turn moves ahead, and the A point changes into the L from H. When moving an encoder to the right in one-click (as described in the previous explanation), one pulse is output on the X point. In the CW case, the pulse does not develop on the side of the Y point. The pulse occurs to the X point every time it clicks to the right. The process also works like the CW in the CCW case—because the B point changes into H from the L earlier than the A point, the pulse does not develop on the side of the X point. The pulse occurs to the Y point every time it clicks to the left. Through this operation, the circuit does the judgment of the CW and the CCW, and the pulse occurs at each output terminal every time it clicks. Conexant Confidential 07/31/14 008DSR00 30 CX20745 Data Sheet Digital Signal Processing (DSP) Figure 24: Up/Down Detection Circuit Push Button Mode • • GPIO1 -> Volume up GPIO2 -> Volume down The option for continuous push on GPIO1 or GPIO2 causes the volume to be incremented or decremented at a fixed rate. Conexant Confidential 07/31/14 008DSR00 31 CX20745 Data Sheet Clocking GPIO 3 Events Requiring an Interrupt to the Host • • • • Class-D error events Jack sense change events Head set volume change Rotary volume change Scheme • • • • • • • All events are stored in a read-only register Any change in the status register is gated with an associated interrupt enable signal Event changes are stored in the corresponding status register The host receives the interrupt immediately Because the interrupt status register is a sticky 1, the interrupt signal remains high until the host is freed to clear the event The host should read the event change register when it receives the interrupt, and can then read the information of the event from the individual status register The host must clear the interrupt status register by writing a 1 to the corresponding register GPIO 4 The GPIO pin under the driver control can be used to observe whether AGC and speaker DRC are in the compression region. Clocking Clock Inputs The following table defines the CX20745 clock inputs. Table 23: Clock Inputs Number Clock Frequency (Maximum) 1 MCLK 24.576MHz 2 DSCLK 6.144MHz 3 ASCLK 3.072MHz Note: The MCLK clock must be a derivative of I2S bit clocks for proper operation. Conexant Confidential 07/31/14 008DSR00 32 CX20745 Data Sheet Registers Registers Register Summary Note: Registers are in the analog domain. Table 24: Register Summary Register Name Offset (Byte) Default Equalizer Crossover Enable/Bypass Control 0x00 0x00 EQ Coeff B0 High 0x01 0x00 CODEC Control Registers EQ Coeff B0 Low 0x02 0x00 EQ Coeff B1 High 0x03 0x00 EQ Coeff B1 Low 0x04 0x00 EQ Coeff B2 High 0x05 0x00 EQ Coeff B2 Low 0x06 0x00 EQ Coeff A1 High 0x07 0x00 EQ Coeff A1 Low 0x08 0x00 EQ Coeff A2 High 0x09 0x00 EQ Coeff A2 Low 0x0A 0x00 Gain 0x0B 0x00 EQ Coef Load Control 0x0C 0x00 DRC_Gain High 0x0D 0x00 DRC_Gain Low 0x0E 0x00 DAC Sample Rate and Enables 0x0F 0x00 DAC Left Channel Volume Control 0x10 0x4A DAC Right Channel Volume Control 0x11 0x4A Digital Microphone Enables and Gain 0x12 0x02 ADC Sample Rate and Enables 0x13 0x00 ADC Left Channel Volume Control 0x14 0x4A ADC Right Channel Volume Control 0x15 0x4A HP Control 0x16 0x3F Line-out Control 0x17 0x77 Speaker Control 0x18 0x07 Analog ADC Left Channel Control 0x19 0x00 Analog ADC Right Channel Control 0x1A 0x00 Micbias Control 0x1B 0x00 I2S Tx Control 1 0x1C 0x00 I2S Tx Control 2 0x1D 0x00 I2S Rx Control 1 0x1E 0x00 I2S Rx Control 2 0x1F 0x00 Data Intermediate Frequency (IF) Registers Conexant Confidential 07/31/14 008DSR00 33 CX20745 Data Sheet Register Summary Table 24: Register Summary (Continued) Register Name Offset (Byte) Default I2S_PCM Control 1 0x20 0x00 I2S _PCM Control 2 0x21 0x00 PCM Tx Control 1 0x22 0x00 PCM Tx Control 2 0x23 0x00 PCM Tx Control 3 0x24 0x00 PCM Rx Control 1 0x25 0x00 PCM Rx Control 2 0x26 0x00 PCM Rx Control 3 0x27 0x00 0x28 0xC0 Activity Detect Beta Voice Shift 0x29 0x02 Activity Detect Beta Noise Shift 0x2A 0x0B Activity Detect Test Gain 0x2B 0x00 Activity Detect Release Delay MSB 0x2C 0x01 Activity Detect Release Delay LSB 0x2D 0x2C Activity Detect Power in Initial Value MSB 0x2E 0x0A Activity Detect Power in Initial Value LSB 0x2F 0x3D Activity Detect Minimum SNR MSB 0x30 0x09 AGC Registers Activity Detect DC Reject Pole Activity Detect Minimum SNR LSB 0x31 0x00 AGC Volume Ramp Step 0x32 0x08 Activity Detect Power Noise Initial Value MSB 0x33 0xE9 Activity Detect Power Noise Initial Value LSB 0x34 0x00 Activity Detect Minimum Threshold MSB 0x35 0xC1 Activity Detect Minimum Threshold LSB 0x36 0x00 Activity Detect ON2OFF Delay 0x37 0x14 AGC Update Block 0x38 0x0A AGC Energy Threshold Lo MSB 0x39 0xE8 AGC Energy Threshold Hi 0x3A 0xF7 AGC Stability Blocks 0x3B 0x3C AGC Step-up 0x3C 0x12 AGC Step-down MSB 0x3D 0xEE AGC Stability Counter Positive Inc 0x3E 0x01 AGC Stability Counter Negative Inc 0x3F 0x0C DRC Release Delay 0x40 0x40 DRC Gain Step Slow 0x41 0x10 DRC Gain Step Fast 0x42 0x40 DRC Maximum Line-out 0x43 0xE0 DRC Gain Shift 0x44 0x05 DRC Maximum Absolute Initial Value 0x45 0x3A AGC Gain Initial Value 0x46 0x00 Conexant Confidential 07/31/14 008DSR00 34 CX20745 Data Sheet Register Summary Table 24: Register Summary (Continued) Register Name Offset (Byte) Default DRC Output Limit 0x47 0x00 AGC Clipping Threshold 0x48 0xF9 DAC_HP_CNTRL 0x59 0x04 Line-in Loop (I S) Gain 0x5A 0x00 Volume GPIO 0x5B 0x3C Volume Control 0x5C 0x00 Interrupt Enable 0x5D 0x00 Interrupt Status 0x5E 0x00 SPKR_DRC_ATTACK_UPDATE_STEP 0x64 0x80 SPKR_DRC_RELEASE_UPDATE_STEP 0x65 0x10 SPKR_DRC_RELEASE_DELAY 0x66 0x40 SPKR_DRC_TRANSIENT_UPDATE_STEP 0x67 0x20 SPKR_DRC_TRANSIENT_RELEASE_DELAY 0x68 0x40 SPKR_DRC_BOOST_DB LSB 0x69 0x00 SPKR_DRC_BOOST_DB MSB 0x6A 0x00 SPKR_DRC_MAX_LIN_OUT_DBFS_MSB 0x6B 0x00 SPKR_DRC_MAX_LIN_OUT_DBFS_LSB 0x6C 0x00 SPKR_DRC_OUT_LIMIT_DB_MSB 0x6D 0x00 SPKR_DRC_OUT_LIMIT_DB_LSB 0x6E 0x00 SPKR_DRC_IN_LIMIT_DB MSB 0x6F 0x00 SPKR_DRC_IN_LIMIT_DB LSB 0x70 0x00 2 SPKR_DRC_BALANCE_RAMP_STEP_MSB 0x71 0x00 SPKR_DRC_BALANCE_RAMP_STEP_LSB 0x72 0x20 SPKR_DRC_GAIN_SHIFT 0x73 0x04 SPKR_DRC_MAXABS_INITVAL 0x74 0x34 SPKR_DRC_VOLUME_RAMP_STEP 0x75 0x03 SPKR_DRC_MAX_RAMP_STEP_SHIFT 0x76 0x0A SPKR_DRC_RELEASE_RATE_TH 0x77 0x00 Read-Only Registers Jack Status and Bond Option 0xE3 0x00 Class-D Protection Status 0xE4 0x00 Class-D Calibration Observe 0xE5 0x20 HP A Offset Calibration Observe 0xE6 0x40 HP B Offset Calibration Observe 0xE7 0x40 BIST Read Status 0xE8 0x00 AGC Gain-out LSB 0xE9 0x00 AGC Gain-out MSB 0xEA 0x00 SPKR DRC Gain LSB 0xEB 0x00 SPKR DRC Gain MSB 0xEC 0x00 Micbias Detect 0xED 0x40 Conexant Confidential 07/31/14 008DSR00 35 CX20745 Data Sheet Register Summary Table 24: Register Summary (Continued) Register Name Offset (Byte) Default 0xF1 0x00 GPIO Registers GPIO IN GPIO OUT 0xF2 0x00 GPIO Direction 0xF3 0x00 GPIO Control 0xF4 0xC7 I2S_data Out Control 0xF5 0xFF DMIC Control 0xF6 0x0D Device ID LSB 0xFD 0x07 Device ID MSB 0xFE 0x51 Bond Pad Read Status 0xFF - Digital Test 0 0x80 0x00 Digital Test 1 0x81 0x00 Digital Test 2 0x82 0x00 Digital Test 3 0x83 0x80 Digital Test 4 0x84 0x00 Digital Test 5 0x85 0x00 CODEC Test 0 0x88 0x00 CODEC Test 1 0x89 0x00 CODEC Test 2 0x8A 0x00 CODEC Test 3 0x8B 0x0F CODEC Test 4 0x8C 0x00 CODEC Test 5 0x8D 0x20 CODEC Test 6 0x8E 0x04 CODEC Test 7 0x8F 0x00 CODEC Test 8 0x90 0x00 Test Registers CODEC Test 9 0x91 0x00 CODEC Test 10 0x92 0x30 CODEC Test 11 0x93 0x00 CODEC Test 12 0x94 0x00 CODEC Test 13 0x95 0x06 CODEC Test 14 0x96 0x20 CODEC Test 15 0x97 0x00 CODEC Test 16 0x98 0x20 CODEC Test 17 0x99 0x00 CODEC Test 18 0x9A 0x00 CODEC Test 19 0x9B 0x00 CODEC Test 20 0x9C 0x00 CODEC Test 21 0x9D 0x00 CODEC Test 22 0x9E 0x04 Conexant Confidential 07/31/14 008DSR00 36 CX20745 Data Sheet Register Summary Table 24: Register Summary (Continued) Register Name Offset (Byte) Default CODEC Test 23 0x9F 0xA2 Analog Test 0 0xA4 0x00 Analog Test 1 0xA5 0x00 Analog Test 2 0xA6 0x00 Analog Test 3 0xA7 0x00 Analog Test 4 0xA8 0x00 Analog Test 5 0xA9 0xA0 Analog Test 6 0xAA 0x00 Analog Test 7 0xAB 0x00 Analog Test 8 0xAC 0x00 Analog Test 9 0xAD 0x00 Analog Test 10 0xAE 0x00 Analog Test 11 0xAF 0x00 Analog Test 12 0xB0 0x00 Analog Test 13 0xB1 0x0F Analog Test 14 0xB2 0x19 Analog Test 15 0xB3 0x00 Analog Test 16 0xB4 0x00 Analog Test 17 0xB5 0x00 Analog Test 18 0xB6 0x00 Analog Test 19 0xB7 0x00 Analog Test 20 0xB8 0x00 Analog Test 21 0xB9 0x00 Analog Test 22 0xBA 0x00 Analog Test 23 0xBB 0x00 Analog Test 24 0xBC 0x00 Analog Test 25 0xBD 0x00 Analog Test 26 0xBE 0x00 Analog Test 27 0xBF 0x00 Analog Test 28 0xC0 0x00 Analog Test 29 0xC1 0x00 Analog Test 30 0xC2 0x00 Analog Test 31 0xC3 0x50 Analog Test 32 0xC4 0x00 Analog Test 33 0xC5 0x00 Analog Test 34 0xC6 0x00 Analog Test 35 0xC7 0x00 Analog Test 36 0xC8 0x01 Analog Test 37 0xC9 0x00 Analog Test 38 0xCA 0x00 Conexant Confidential 07/31/14 008DSR00 37 CX20745 Data Sheet Register Details Table 24: Register Summary (Continued) Register Name Offset (Byte) Default Analog Test 39 0xCB 0x00 Analog Test 40 0xCC 0x00 Analog Test 41 0xCD 0x01 Analog Test 42 0xCE 0x01 Analog Test 43 0xCF 0x00 Analog Test 44 0xD0 0x00 Analog Test 45 0xD1 0x00 Analog Test 46 0xD2 0x00 Analog Test 47 0xD3 0x00 Analog Test 48 0xD4 0x00 Analog Test 49 0xD5 0x00 Analog Test 50 0xD6 0x00 Analog Test 51 0xD7 0x00 Register Details Coder-Decoder (CODEC) Control Registers Table 25: Equalizer Crossover Enable Bypass (0x00) Bits Name 7:4 Default R/W Description Reserved R Reserved. 3 Bypass 2 R/W 0 = Bypass equalizer/crossover in DAC2. 2 Bypass 1 R/W 0 = Bypass equalizer/crossover in DAC1. 1 Enable 2 R/W 1 = Enable equalizer/crossover in DAC2. 0 Enable 1 R/W 1 = Enable equalizer/crossover in DAC1. 0x00 Table 26: Equalizer Coefficient B0 High (0x01) Bits Name Default R/W Description 7:0 Coefficient High Byte 0x00 R/W CODEC IIR B0 feed forward coefficient high byte. Table 27: Equalizer Coefficient B0 Low (0x02) Bits Name Default R/W Description 7:0 Coefficient Low Byte 0x00 R/W CODEC IIR B0 feed forward coefficient low byte. Table 28: Equalizer Coefficient B1 High (0x03) Bits Name Default R/W Description 7:0 Coefficient High Byte 0x00 R/W CODEC IIR B1 feed forward coefficient high byte. Conexant Confidential 07/31/14 008DSR00 38 CX20745 Data Sheet Register Details Table 29: Equalizer Coefficient B1 Low (0x04) Bits Name Default R/W Description 7:0 Coefficient Low Byte 0x00 R/W CODEC IIR B1 feed forward coefficient low byte. Table 30: Equalizer Coefficient B2 High (0x05) Bits Name Default R/W Description 7:0 Coefficient High Byte 0x00 R/W CODEC IIR B2 feed forward coefficient high byte. Table 31: Equalizer Coefficient B2 Low (0x06) Bits Name Default R/W Description 7:0 Coefficient Low Byte 0x00 R/W CODEC IIR B2 feed forward coefficient low byte. Table 32: Equalizer Coefficient A0 High (0x07) Bits Name Default R/W Description 7:0 Coefficient High Byte 0x00 R/W CODEC IIR A0 feedback coefficient high byte. Table 33: Equalizer Coefficient A0 Low (0x08) Bits Name Default R/W Description 7:0 Coefficient Low Byte 0x00 R/W CODEC IIR A0 feedback coefficient low byte. Table 34: Equalizer Coefficient A1 High (0x09) Bits Name Default R/W Description 7:0 Coefficient High Byte 0x00 R/W CODEC IIR A1 feedback coefficient high byte. Table 35: Equalizer Coefficient A1 Low (0x0A) Bits Name Default R/W Description 7:0 Coefficient Low Byte 0x00 R/W CODEC IIR A1 feedback coefficient low byte. Default Table 36: Gain (0x0B) Bits Name R/W Description 7:3 Reserved R Reserved. 2:0 Gain R/W CODEC IIR output gain • 000b = –12dB • 001b = –6dB • 010b = 0dB • 011b = 6dB • 100b = 12dB • 101b = 18dB 0x00 Conexant Confidential 07/31/14 008DSR00 39 CX20745 Data Sheet Register Details Table 37: Coeff Load Control (0x0C) Bits Name R/W Description 7 Coeff_Done Default R The IIR is done with loading, so the next IIR coefficient set can be loaded. 6 Coeff_Latch_En R/W Set to 1 to indicate the coefficient set is complete and ready to load to the IIR. The bit is reset by a hardware function when Coeff_Done is asserted (so no firmware action is required to turn off this bit). 5:4 Coeff_CH R/W Selects which IIR channel is to be loaded • 00b = DAC_L • 01b = DAC_R • 10b = DAC_Mono • 11b = Reserved R/W Selects which IIR is to be loaded • 0000b = IIR 0 • 0001b = IIR 1 • 0010b = IIR 2 • ... • 1001b = IIR 9 • 1010b = IIR A • 1011b = IIR B • 1100b = DRC_G 0x00 3:0 Coeff_IIR Table 38: DRC_Gain High (0x0D) Bits Name Default R/W Description 7:0 DRC_Gain High Byte 0x00 R/W CODEC final DRC gain high byte. Table 39: DRC_Gain Low (0x0E) Bits Name Default R/W Description 7:0 DRC_Gain Low Byte 0x00 R/W CODEC final DRC gain high byte. Conexant Confidential 07/31/14 008DSR00 40 CX20745 Data Sheet Register Details Table 40: DAC 1:2 Sample Size/Rate (0x0F) Bits Name 7:4 DAC 1:2 Sample Rate Default R/W Description R/W • • • • • • • • • • • • • • 0x00 0x0 = 8K 0x1 = 12K 0x2 = 16K 0x3 = 24K 0x4 = 32K 0x5 = 48K 0x6 = 96K 0x8 = 8.0182K 0x9 = 11.025K 0xA = 16.0364K 0xB = 22.05K 0xC = 44.1K 0xE = 88.2K Others = Reserved 3 Reserved R Reserved. 2 DAC Swap Enable R/W Enables the swap enable. 1 DAC 2 Enable R/W Enables DAC2 or the right channel. 0 DAC 1 Enable R/W Enables DAC1 or the left channel. Table 41: DAC 1 (Left Channel) Volume/Mute Control (0x10) Bits Name Default R/W Description 7 DAC 1 Mute 1 = Mutes DAC 1 (left channel). 6:0 DAC 1 Volume Programmable gain stage in digital • 0x50 = 6dB • 0x4F = 5dB • 0x4E = 4dB • 0x4D = 3dB • 0x4C = 2dB • … • 0x3 = –71dB • 0x2 = –72dB • 0x1 = –73dB • 0x0 = –74dB 0x4A R/W Conexant Confidential 07/31/14 008DSR00 41 CX20745 Data Sheet Register Details Table 42: DAC 2 (Right Channel) Volume/Mute Control (0x11) Bits Name Default 7 DAC 2 Mute 1 = Mutes DAC 2. 6:0 DAC 2 Volume Programmable gain stage in digital • 0x50 = 6dB • 0x4F = 5dB • 0x4E = 4dB • 0x4D = 3dB • 0x4C = 2dB • … • 0x03 = –71dB • 0x02 = –72dB • 0x01 = –73dB • 0x00 = –74dB 0x4A R/W Description R/W Table 43: Digital Microphone Control (0x12) Bits Name 7:5 Digital Microphone Right Channel Gain 4:2 Digital Microphone Left Channel Gain Default 0x02 R/W R/W Description • • • • • 000b = 0dB 001b = 12dB 010b = 24dB 011b = 36dB 100b = 48dB • • • • • 000b = 0dB 001b = 12dB 010b = 24dB 011b = 36dB 100b = 48dB 1 Digital Power Down Disables the DMIC with the clock stopped and the microphone pad powered down. 0 Digital Input Enable Mutes the DMIC. Conexant Confidential 07/31/14 008DSR00 42 CX20745 Data Sheet Register Details Table 44: ADC Sample Rate/Enable Register (0x13) Bits Name 7:4 ADC Sample Rate Default 0x00 R/W R/W Description • • • • • • • • • • • • 0000b = 8K 0001b = 12K 0010b = 16K 0011b = 24K 0100b = 32K 0101b = 48K 1000b = 8.0182K 1001b = 11.025K 1010b = 16.0364K 1011b = 22.05K 1101b = 44.1K Others = Reserved 3 ADC Swap Swaps the left and right channel. 2 Agc_en Enables the AGC block. 1 ADC Connection Index • • 0 ADC Enable Enables the ADC stereo. 0 = Analog microphone 1 = Digital microphone Table 45: ADC Left Channel Volume/Mute Control (0x14) Bits Name Default 7 ADC Left Channel Mute 1 = Mutes the DAC left channel. 6:0 ADC Left Channel Volume Programmable gain stage in digital • 0x50 = 6dB • 0x4F = 5dB • 0x4E = 4dB • 0x4D = 3dB • 0x4C = 2dB • … • 0x03 = –71dB • 0x02 = –72dB • 0x01 = –73dB • 0x00 = –74dB 0x4A R/W R/W Description Conexant Confidential 07/31/14 008DSR00 43 CX20745 Data Sheet Register Details Table 46: ADC Right Channel Volume/Mute Control (0x15) Bits Name 7 ADC Right Channel Mute Default 1 = Mutes the ADC right channel. 6:0 ADC Right Volume Programmable gain stage in digital • 0x4F = 5dB • 0x4E = 4dB • 0x4D = 3dB • 0x4C = 2dB • … • 0x03 = –71dB • 0x02 = –72dB • 0x01 = –73dB • 0x00 = –74dB 0x4A R/W R/W Description Table 47: HP Control Register (0x16) Bits Name Default 7:6 Reserved Reserved. 5 HP B Output Enable • • 4:3 HP B Pwr HP B power state • 11b = D3 • 10b = D2 • 01b = D1 • 00b = D0 0x3F R/W R/W Description 1 = Enables the HP B output 0 = Disable 2 HP A Output Enable • • 1 = Enables the HP A output 0 = Disable 1:0 HP A Pwr HP A power state • 11b = D3 • 10b = D2 • 01b = D1 • 00b = D0 Conexant Confidential 07/31/14 008DSR00 44 CX20745 Data Sheet Register Details Table 48: Line-Out Control Register (0x17) Bits Name 7 Reserved Default R/W Reserved. 6 Line-out 2 Enable • • 5:4 Line-out 2 Pwr Line-out two power state • 11b = D3 • 10b = D2 • 01b = D1 • 00b = D0 3 Reserved 2 Line-out 1 Enable • • 1:0 Line-out 1 Pwr Line-out one power state • 11b = D3 • 10b = D2 • 01b = D1 • 00b = D0 0x77 Description R/W 0 = Disable 1 = Line-out two-output enable Reserved. 0 = Disable 1 = Line-out one output enable Table 49: SPKR Control Registers (0x18) Bits Name Default R/W 7:5 Reserved Reserved. 4 Spkr pwm_en i 1 = Enables the speaker PWM that is enabled from the input. 3 Spkr Mono Mode 1 = Enables the speaker mono mode. 2 Spkr Output Enable 1:0 Spkr Power 0x07 Description 1 = Speaker output enable. R/W Speaker power state • 11b = D3 • 10b = D2 • 01b = D1 • 00b = D0 Table 50: ADC Analog Left Channel Control Register (0x19) Bits Name 7 Default R/W Description ana_adc_l_mute R/W 1 = Mutes the analog ADC left channel. 6:5 Reserved R Reserved. 4 Monitor Mode R/W 1 = Enables the monitor mode with one ADC channel dedicated for the monitor. 3:1 Ana_adc_l_gain R/W Gain for the analog ADC. 0 Ana_adc_l_en R/W 1 = Enables the analog ADC left channel. 0x00 Conexant Confidential 07/31/14 008DSR00 45 CX20745 Data Sheet Register Details Table 51: ADC Analog Right Channels Control Register (0x1A) Bits Name Default 7 Adc_diffen 1 = Enables the differential input on the ADC. 6:5 Ana_adc_sel Selects the input to the ADC • 00b = Input is the line-in/microphone-in • 01b = Input is the volt monitor • 10b = Input is the volume 0x00 R/W R/W Description 4 Ana_adc_r_mute 1 = Mutes the analog ADC right channel. 3:1 Ana_adc_r_gain Gain for the analog ADC. 0 Ana_adc_r_en 1 = Enables the analog ADC left channel. Table 52: Micbias Control Register (0x1B) Bits Name 7:2 Reserved 1 Micbias Set 0 Micbias En Default R/W Description 0x00 R/W 1 = Sets the micbias. Reserved. 1 = Enables the micbias. Data I/F Registers Table 53: I2S Transmitter Control-1 (0x1C) Bits Name Default 7 I2s_tx_en Enables the I2S transmitter if the PCM is set. 6:3 Reserved Reserved. 2 Tx_right_just 1 Tx_mute Mutes the I2S transmitter (all zeros are sent). 0 Tx_sony_mode When set, the I2S transmitter works in the Sony mode. 0x00 R/W R/W Description When set, the I2S transmitter works in the right justified mode. Table 54: I2S Transmitter Control-2 (0x1D) Bits Name 7 Reserved 6:0 Bcnt_del Default R/W 0x00 R/W Description Reserved. If right justified, this value indicates the delay for the first valid data transmitter. Conexant Confidential 07/31/14 008DSR00 46 CX20745 Data Sheet Register Details Table 55: I2S Receiver Control-1 (0x1E) Bits Name Default 7 I2s_rx_en Enables the I2S receiver if the PCM is set. 6:3 Reserved Reserved. 3 I2s_rx_en_sh When set, the host sends the right channel first and then left channel second. 2 Rx_right_just 1 Rx_mute Mutes the I2S receiver (all zeros are sent). 0 Rx_sony_mode When set, then the I2S receiver works in the Sony mode. 0x00 R/W R/W Description When set, the I2S transmitter works in the right justified mode. Table 56: I2S Receiver Control-2 (0x1F) Bits Name 7 Reserved 6:0 Bcnt_del Default R/W Description Reserved. 0x00 R/W If right justified, this value indicates the delay for the first valid data on the receiver. Default R/W Description Table 57: I2S/PCM Control-1 (0x20) Bits Name 7:5 Reserved R Reserved. 4:3 tx_wdta R/W Sets the transmitter data width • 00b = 8-bit data • 01b = 16-bit data • 10b = 24-bit data 2:1 Rx_wdta R/W Sets the receiver data width • 00b = 8-bit data • 01b = 16-bit data • 10b = 24-bit data 0 I2S_PCM R/W • • R/W Description 0x00 0 = Enables the I2S data interface 1 = Enables the PCM data interface Table 58: I2S/PCM Control-2 (0x21) Bits Name 7:2 Reserved 1 dac_lrck_pol 0 adc_lrck_pol Default Reserved. 0x00 R/W Enables changes to the I2C Rx input LRCK polarity. Enables changes to the I2C Tx input LRCK polarity. Conexant Confidential 07/31/14 008DSR00 47 CX20745 Data Sheet Register Details Table 59: PCM Transmitter Control-1 (0x22) Bits Name Default 7 Reserved Reserved. 6 Dshift_sel • • 5 Dstart_del 4:0 Txck_sync_rate 0x00 R/W R/W Description 1 = LSB is first on the PCM’s Tx and Rx 0 = MSB is first on the PCM’s Tx and Rx 1 = Delays Tx and Rx one cc before sent out/lat. Specifies the maximum bit count/8–1 between frame syncs (e.g., set to 0x7 for a two-channel 32-bit stream or 64-bit between a frame sync [64/8–1]). Table 60: PCM Transmitter Control-2 (0x23) Bits Name Default 7:3 Tx Slot 1 Indicates which slot number that the left channel needs to be set to. 2 Tx Out Enable Enables the PCM Tx output—enable only for the slots it is driving. 1 Tx2 Enable 0 Tx1 Enable 0x00 R/W R/W Description Enables the right channel if the data interface is set to the PCM. Enables the left channel if the data interface is set to the PCM. Table 61: PCM Transmitter Control-3 (0x24) Bits Name 7:4 Reserved 3:0 Tx Slot 2 Default R/W Description 0x00 R/W Indicates which slot number that the right channel needs to be set to. R/W Description Reserved. Table 62: PCM Receiver Control-1 (0x25) Bits Name 7:5 Reserved 4:0 Rxck_sync_rate Default Reserved. 0x00 R/W Specifies the maximum bit count/8–1 between frame syncs (e.g., set to 0x7 for a two-channel 32-bit stream or 64-bit between a frame sync [64/8–1]). R/W Description Table 63: PCM Receiver Control-2 (0x26) Bits Name Default 7:4 Rx Slot 1 Indicates which slot number that the left channel needs to be set to. 3:2 Reserved Reserved. 1 Rx2 Enable 0 Rx1 Enable 0x00 R/W Enables the right channel if the data interface set to the PCM. Enables the left channel if the data interface set to the PCM. Conexant Confidential 07/31/14 008DSR00 48 CX20745 Data Sheet Register Details Table 64: PCM Receiver Control-3 (0x27) Bits Name 7:4 Reserved 3:0 Rx Slot 2 Default R/W Description 0x00 R/W Indicates which slot number that the right channel needs to be set to. Reserved. AGC Registers Table 65: AD_DC_REJECT_POLE (0x28) Bits Name Default R/W Description 7:0 AD_DC_REJECT_POLE 0xC0 R/W Pole location for the datIn DC rejection IIR filter Z = AD_DC_REJECT_POLE/215 AD_DC_REJECT_POLE is 16 bits Bit 14:7 is programmed using this register represented as 7:0 on the right Bit 15 is fixed at 0 for a positive-only value Bit 6 to 0 is fixed at 0 • • • • • Table 66: AD_BETA_VOICE SHFT (0x29) Bits Name 7:4 3:0 Default R/W Description Reserved R Reserved. AD_BETA_VOICE_SHFT R/W • PowerIn fast averaging IIR filter beta coefficient • PowerIn = PowerIn * (1–Beta/215) + FrameEnergy *(Beta/2^15) • Range is 0–15 for a beta range of 2(15–0) to 2(15– 15) —the default beta is 2(15–2) or 213 0x02 Table 67: AD_BETA_NOISE_SHFT (0x2A) Bits Name 7:4 3:0 Default R/W Description Reserved R Reserved. AD_BETA_NOISE_SHFT R/W • PowerNoiseAvg slow averaging IIR filter beta coefficient • PowerNoise = PowerNoise * (1–Beta/215) + FrameEnergy *(Beta/215) • Range is 0–15 for beta range of 2^(15–0) to 2(15– 0x0B 15) • Default beta is 2(15–11) or 24 Table 68: AD_TEST_GAIN (0x2B) Bits Name 7:4 Reserved 3:0 AD_TEST_GAIN Default 0x00 R/W Description R Reserved. R/W Test only register—left-shift the datIn input signal to the AGC module by the number of bits specified. Conexant Confidential 07/31/14 008DSR00 49 CX20745 Data Sheet Register Details Table 69: AD_RELEASE_DELAY MSB (0x2C) Bits Name Default R/W Description 7:0 AD_RELEASE_DELAY 0x01 R/W In units of ms—used to program the period of time passed before allowing the noise-power to increase. Table 70: AD_RELEASE_DELAY LSB (0x2D) Bits Name Default R/W Description 7:0 AD_RELEASE_DELAY 0x2C R/W In units of ms—used to program the period of time passed before allowing the noise-power to increase. Table 71: AD_POWERIN_INITVAL MSB (0x2E) Bits Name Default R/W Description 7:0 AD_POWERIN_INITVAL 0x0A R/W PowerIn is a 32-bit voice power register. This register programs the reset value for bits 30:23 of that register, represented by 7:0 on the left. • Bit 31 of the 32-bit register is fixed at 0 • Bits 22:15 are represented by AD_POWERIN_INITVAL LSB • Bit 14:0 of the 32-bit register are fixed at 0 Table 72: AD_POWERIN_INITVAL LSB (0x2F) Bits Name Default R/W Description 7:0 AD_POWERIN_INITVAL 0x3D R/W PowerIn is a 32-bit voice power register. This register programs the reset value for bits 22:15 of that register, represented by 7:0 on the left. • Bit 31 of the 32-bit register is fixed at 0 • Bits 30:23 are represented by AD_POWERIN_INITVAL MSB • Bit 14:0 of the 32-bit register are fixed at 0 Table 73: AD_MIN_SNR MSB (0x30) Bits Name Default R/W Description 7:0 AD_MIN_SNR 0x09 R/W AD_MIN_SNR[15:8]—minimum SNR in dB. Table 74: AD_MIN_SNR LSB (0x31) Bits Name Default R/W Description 7:0 AD_MIN_SNR 0x00 R/W AD_MIN_SNR[7:0]—minimum SNR in dB. Table 75: AGC_VOLUME_RAMP_STEP (0x32) Bits Name Default R/W Description 7:0 0x08 R/W AGC volume ramp step size in dB. AGC_VOLUME_RAMP_STEP Conexant Confidential 07/31/14 008DSR00 50 CX20745 Data Sheet Register Details Table 76: AD_POWERNOISE_INITVAL MSB (0x33) Bits Name Default R/W Description 7:0 0xE9 R/W PowerNoise is a 16-bit noise power register. These registers program the reset value for [15:8]. AD_POWERNOISE_INITVAL Table 77: AD_POWERNOISE_INITVAL LSB (0x34) Bits Name Default R/W Description 7:0 0x00 R/W PowerNoise is a 16-bit noise power register. These registers program the reset value for [7:0]. AD_POWERNOISE_INITVAL Table 78: AD_MIN_THRESH MSB (0x35) Bits Name Default R/W Description 7:0 AD_MIN_THRESH 0xC1 R/W AD_MIN_THRESH [15:8] offset for the decision threshold to prevent false detection of voice when the signal is low. This value is 16-bit unsigned. Table 79: AD_MIN_THRESH LSB (0x36) Bits Name Default R/W Description 7:0 AD_MIN_THRESH 0x00 R/W AD_MIN_THRESH [7:0] offset for the decision threshold to prevent false detection of voice when the signal is low. This value is 16-bit unsigned. Table 80: AD_ON2OFF_DELAY_BLOCKS (0x37) Bits Name 7:5 Reserved 4:0 AD_ON2OFF_DELAY_BLOCKS Default R/W Description R Reserved. R/W On to off delay in number of blocks. Default R/W Description R Reserved. 0x0A R/W Number of sample blocks used to calculate the new gain. 0x14 Table 81: AGC_UPDATE_BKS (0x38) Bits Name 7:5 Reserved 4:0 AGC_UPDATE_BKS Table 82: AGC_ENERGY_THRESH_LO MSB (0x39) Bits Name Default R/W Description 7:0 AGC_ENERGY_THRESH_LO 0xE8 R/W Threshold for the decision if the gain needs to be increased. Only the upper eight bits of the ETMP value are compared. Conexant Confidential 07/31/14 008DSR00 51 CX20745 Data Sheet Register Details Table 83: AGC_ENERGY_THRESH_HI MSB (0x3A) Bits Name Default 7:0 AGC_ENERGY_THRESH_HI 0xF7 R/W Description R/W Threshold for the decision if the gain needs to be decreased. Only the upper eight bits of the ETMP value are compared. Table 84: AGC_STABILITY_BLOCKS (0x3B) Bits Name 7 6:0 Default R/W Description Reserved R Reserved. AGC_STABILITY_BLOCKS 0x3C R/W Value compared to the stability counter to ensure the gain does not oscillate (increase/decrease) too rapidly. Table 85: AGC_STEP_UP (0x3C) Bits Name Default R/W Description 7:0 AGC_STEP_UP 0x12 R/W The amount that the gain is to be increased by. Table 86: AGC_STEP_DOW MSB (0x3D) Bits Name Default R/W Description 7:0 AGC_STEP_DOWN 0xEE R/W The amount that the gain is to be decreased by. R/W Description R Reserved. R/W The amount that the stability counter is to be increased by—the range is 0 to 15. Default R/W Description R Reserved. 0x0C R/W The amount that the stability counter is to be decreased by—the range is 0 to –16. Table 87: AGC_STAB_CNT_POS_INC (0x3E) Bits Name 7:4 3:0 Default Reserved AGC_STAB_CNT_POS_INC 0x01 Table 88: AGC_STAB_CNT_NEG_INC (0x3F) Bits Name 7:4 Reserved 3:0 AGC_STAB_CNT_NEG_INC Table 89: DRC_RELEASE_DELAY MSB (0x40) Bits Name Default R/W Description 7:0 DRC_RELEASE_DELAY 0x40 R/W In units of 1ms—used to program the period of time passed before MaxAbsIn can be decreased to a lower value if the input level is not increasing. Hysteresis for adjusting the gain upward. Conexant Confidential 07/31/14 008DSR00 52 CX20745 Data Sheet Register Details Table 90: DRC_GAIN_STEP_SLOW (0x41) Bits Name Default R/W Description 7:0 DRC_GAIN_STEP_SLOW 0x10 R/W • • • Coefficient for MaxAbsIn IIR filters the DRC_GAIN_STEP_SLOW coefficient is 10-bit unsigned Programs bit 9:2 of the 10-bit coefficient, represented on the left by 7:0 Bits 1:0 of the 10-bit coefficient are always fixed at 0 Table 91: DRC_GAIN_STEP_FAST (0x42) Bits Name Default R/W Description 7:0 DRC_GAIN_STEP_FAST 0x40 R/W • • • Coefficient for the target gain filters DRC_GAIN_STEP_FAST coefficient is 15-bit unsigned Programs bit 14:7 of the 15-bit coefficient, represented on the left by 7:0 Bits 6:0 of the 15-bit coefficient are fixed at 0 Table 92: DRC_MAX_LIN_OUT (0x43) Bits Name Default R/W Description 7:0 DRC_MAX_LIN_OUT 0xE0 R/W • • • • Maximum linear output of the DRC—the DRC_MAX_LIN_OUT is 16-bit signed Programs bit 11:4 of the 16-bit coefficient, represented on the left by 7:0 Bits 3:0 of the 16-bit coefficient are fixed at 0 Bits 15:12 of the 16-bit coefficient are fixed at 0xF Table 93: DRC_GAIN_SHIFT (0x44) Bits Name 7:3 Reserved 2:0 DRC_GAIN_SHIFT Default R/W Description R Reserved. 0x05 R/W Gain is in the Q6.10/Q6.26 format, which is a 5-bit scale-down from Q1.15/Q1.31. Table 94: DRC_MAXABS_INITVAL (0x45) Bits Name Default R/W Description 7:0 DRC_MAXABS_INITVAL 0x3A R/W • • • Initial value for MaxAbsIn is MaxAbsIn = DRC_MAXABS_INITVAL * 2^24; Initial value for MaxAbsPre is MaxAbsPre = DRC_MAXABS_INITVAL * 2^8 Range is –32 to 31 Conexant Confidential 07/31/14 008DSR00 53 CX20745 Data Sheet Register Details Table 95: AGC_GAIN_INITVAL (0x46) Bits Name Default R/W Description 7:0 AGC_GAIN_INITVAL 0x00 R/W Initial value for the AGC gainctrl gain output to the microphone DRC. Table 96: DRC_OUTPUT_LIMIT (0x47) Bits Name Default R/W Description 7:0 DRC_OUTPUT_LIMIT 0x00 R/W DRC output limit. This register programs the eight MSB bits of 16-bit signed value. Table 97: AGC_CLIPPING_THRESH (0x48) Bits Name 7:0 AGC_CLIPPING_THRESH 0xF9 Default R/W Description R/W AGC clipping threshold. R/W Description Table 98: DAC_HP_CNTRL (0x59) Bits Name Default 7 Manual Mode HP Enable When class-D is not mapped to the DAC, the HP can be enabled on the DAC chain using this bit. 6 Hp_bypass Bypasses the HP filter on the DAC chain. 5:0 Band Sel [5:0] Programmable cut-off for the HP • HPF frequency selection N * 30 • 0x00 = Disabled • 0x01 = 30Hz • 0x02 = 60Hz • … • 0x3E = 1860Hz • 0x3F = 1890Hz 0x04 R/W Conexant Confidential 07/31/14 008DSR00 54 CX20745 Data Sheet Register Details Table 99: Line In Loop (I2S Input) Gain Control (0x5A) Bits Name Default 7 Sum_r_mute Mutes the right channel data from the I2S. 6:4 Sum_r_gain Gain on the input data from the I2S right channel before going to the mixer • 000b = 1.9dB • 001b = 0dB • 010b = –2.5dB • 011b = –6dB • 100b = –12dB • 101b = –24dB • 110b = –36dB • 111b = –48dB 3 Sum_l_mute 2:0 Sum_l_gain 0x00 R/W R/W Description Mutes the left channel data from the I2S. Gain on the input data from the I2S right channel before going to the mixer • 000b = 1.9dB • 001b = 0dB • 010b = –2.5dB • 011b = –6dB • 100b = –12dB • 101b = –24dB • 110b = –36dB • 111b = –48dB Table 100: Volume GPIO Control (0x5B) Bits Name 7 Reserved 6:0 Vol_direct Default 0x3C R/W Description R Reserved. R/W Host can write and read the updated volume. Table 101: Volume Control (0x5C) Bits Name 7:6 Default R/W Description Reserved R Reserved. 5 Rotary Edge Pulse R/W Sets the rotary detection to the pulse and edge mode • 0 = Pulse mode • 1 = Edge mode 4 Vol_en R/W Enables the volume control through the GPIO bypassing register control. 3:1 Vol_deb_time R/W Selects the de-bounce time required on the GPIO pins—increments by every 10ms. 0 Rotary Mode R/W Selects whether the volume control is to be rotary or push up/down. 0x00 Conexant Confidential 07/31/14 008DSR00 55 CX20745 Data Sheet Register Details Table 102: Interrupt Enable (0x5D) Bits Name R/W Description 7:5 Reserved Default R Reserved. 4 Interrupt_en [4] R/W Enables the interrupt on the rotary or push button volume change. 3 Interrupt_en [3] R/W Enables the interrupt on the headset’s volume change. 0x00 2 Interrupt_en [2] R/W Enables the interrupt on the jack sense status change. 1 Interrupt_en [1] R/W Enables the interrupt on class-D errors. 0 Interrupt_en [0] R/W Reserved. R/W Description Table 103: Interrupt Status (0x5E) Bits Name Default 7:5 Reserved R Reserved. 4 Interrupt_status [4] R/W Interrupt status on the rotary or push button volume change. 3 Interrupt_status [3] R/W Interrupt status on the headset volume change. 2 Interrupt_status [2] R/W Interrupt status on the jack sense status change. 1 Interrupt_status [1] R/W Interrupt status for class-D errors. 0 Interrupt_status [0] R/W Reserved. 0x00 Table 104: SPKR_DRC_ATTACK_UPDATE_STEP (0x64) Bits Name 7:0 Default R/W Description SPKR_DRC_ATTACK_UPDATE_STEP 0x80 R/W Used to program the gain step required to compress the incoming signal in the compression region. Table 105: SPKR_DRC_RELEASE_UPDATE_STEP (0x65) Bits Name 7:0 Default R/W Description SPKR_DRC_RELEASE_UPDATE_STEP 0x10 R/W Used to program the gain step required to release the gain slowly when the signal is in the linear region. Table 106: SPKR_DRC_RELEASE_DELAY (0x66) Bits Name Default R/W Description 7:0 0x40 R/W In units of 1ms—used to program the period of time passed before MaxAbsIn can be decreased to a lower value if the input level is not increasing. Hysteresis for adjusting the gain upward. SPKR_DRC_RELEASE_DELAY Conexant Confidential 07/31/14 008DSR00 56 CX20745 Data Sheet Register Details Table 107: SPKR_DRC_TRANSIENT_UPDATE_STEP (0x67) Bits Name 7:0 Default R/W Description SPKR_DRC_TRANSIENT_UPDATE_STEP 0x20 R/W Used to: • Program the step value • Quickly update the MAXABS IN value Table 108: SPKR_DRC_TRANSIENT_RELEASE_DELAY (0x68) Bits Name 7:0 Default R/W Description SPKR_DRC_TRANSIENT_RELEASE_DELAY 0x40 R/W Used to: • Program the release delay value • Update the release delay value to make a quick transition in the gain value Table 109: SPKR_DRC_BOOST_DB MSB (0x69) Bits Name 1:0 Default SPKR_DRC_BOOST_DB[9:8] 0x00 R/W Description R/W The gain value initially set for the DRC. Table 110: SPKR_DRC_BOOST_DB LSB (0x6A) Bits Name Default R/W Description 7:0 0x00 R/W The gain value initially set for the DRC. SPKR_DRC_BOOST_DB[7:0] Table 111: SPKR_DRC_MAX_LIN_OUT_DBFS MSB (0x6B) Bits Name 1:0 Default R/W Description SPKR_DRC_MAX_LIN_OUT_DBFS[9:8] 0x00 R/W Used to set the threshold and limit values. Table 112: SPKR_DRC_MAX_LIN_OUT_DBFS LSB (0x6C) Bits Name Default R/W Description 7:0 0x00 SPKR_DRC_MAX_LIN_OUT_DBFS[7:0] R/W Used to set the threshold and limit values. Table 113: SPKR_DRC_OUT_LIMIT_DBFS MSB (0x6D) Bits Name 1:0 Default SPKR_DRC_OUT_LIMIT_DBFS [9:8] 0x00 R/W Description R/W Used to set the DRC output limit. R/W Description R/W Used to set the DRC output limit. Table 114: SPKR_DRC_OUT_LIMIT_DBFS LSB (0x6E) Bits Name 7:0 Default SPKR_DRC_OUT_LIMIT_DBFS [7:0] 0x00 Conexant Confidential 07/31/14 008DSR00 57 CX20745 Data Sheet Register Details Table 115: SPKR_DRC_IN_LIMIT_DB MSB (0x6F) Bits Name 1:0 Default R/W Description SPKR_DRC_IN_LIMIT_DB[7:0] 0x00 R/W Used to check if the input signal has reached the limit value. Table 116: SPKR_DRC_IN_LIMIT_DB LSB (0x70) Bits Name 7:0 Default R/W Description SPKR_DRC_IN_LIMIT_DB[2:0] 0x00 R/W Used to check if the input signal has reached the limit value. Table 117: SPKR_DRC_BALANCE_RAMP_STEP MSB (0x71) Bits Name Default R/W Description 1:0 0x00 SPKR_DRC_BALANCE_RAMP_STEP[9:8] R/W Determines the balance RAMP STEP. Table 118: SPKR_DRC_COMP_RATIO LSB (0x72) Bits Name Default R/W Description 7:0 0x20 SPKR_DRC_BALANCE_RAMP_STEP [7:0] R/W Determines the balance RAMP STEP. Table 119: SPKR_DRC_GAIN_SHIFT (0x73) Bits Name Default R/W Description 2:0 DRC_GAIN_SHIFT 0x04 R/W Gain shift value. Table 120: SPKR_DRC_MAXABS_INITVAL (0x74) Bits Name 7 SPKR_DRC_EN Default R/W Enable for the SPKR DRC. 6 DRC_REL_RATE_TH_DISABLE • • 0 = Release threshold used 1 = Release threshold not used 5:0 DRC_MAXABS_INITVAL • Initial value for MaxAbsIn is MaxAbsIn = DRC_MAXABS_INITVAL * 2^24 Initial value for MaxAbsPre is MaxAbsPre = DRC_MAXABS_INITVAL * 2^8 Range is –32 to 31 0x34 R/W Description • • Table 121: SPKR_DRC_VOLUME_RAMP_STEP (0x75) Bits Name Default R/W Description 7:0 DRC_VOLUME_RAMP_STEP 0x03 R/W Step-size for volume ramping. Table 122: SPKR_DRC_MAX_RAMP_STEP_SHIFT (0x76) Bits Name Default R/W Description 2:0 DRC_MAX_RAMP_STEP_SHIFT 0x0A R/W Maximum shift of step-size for volume ramping. Conexant Confidential 07/31/14 008DSR00 58 CX20745 Data Sheet Register Details Table 123: SPKR_DRC_RELEASE_RATE_TH (0x77) Bits Name Default R/W Description 7:0 SPKR_DRC_RELEASE_RATE_TH 0x00 R/W Threshold for deciding whether to use slow release (with RELEASE_UPDATE_STEP) or fast release (with TRANSIENT_UPDATE_STEP). Test Registers Table 124: CODEC Test 0 (0x88) Bits Name 7 Digmic_freq 6:0 Reserved Default R/W 0x00 R/W Default R/W Description Set to 0x1 for the 1.5MHz digital microphone. Reserved. Table 125: CODEC Test 21 (0x9D) Bits Name 7:6 Pulse_1ms 0x00 5:0 R/W Reserved Description Push button and rotary latching time • 00b = 1ms • 01b = 1ms • 10b = 500μs • 11b = Not valid Reserved. Table 126: CODEC Test 22 (0x9E) Bits Name 7:6 Reserved 5 Codec_test_regs22 [5] 4 Codec_test_regs22 [4] 3:0 Reserved Default R/W Description Reserved. 0x04 R/W 1 = Combo button enable. 1 = Combo jack enable. Reserved. Conexant Confidential 07/31/14 008DSR00 59 CX20745 Data Sheet Register Details Table 127: CODEC Test 23 (0x9F) Bits Name 7 Default R/W Description Codec_test_regs23 [7] R/W Temp-Error enable to power-down class-D, headphone, and interrupt generation. 6 Codec_test_regs23 [6] R/W Disable POR_5 error status and power-down class-D on this status. 5 Codec_test_regs23 [5] R/W Disable short circuit error detect result and powerdown class-D on this status. 4:3 Reserved 2 Codec_test_regs23 [2] 1:0 Codec_test_regs23 [1:0] 0xA2 R Reserved. - Threshold for the Temp-Error counter • 0b = 99% • 1b = 75% R/W Window selection for Temp-Error detection • 00b = Bypass • 01b = 100ms • 10b = 150ms • 11b = 200ms R/W Description Table 128: Analog Test 4 (0xA8) Bits Name Default 7:5 Reserved Reserved. 4:3 testctrl4[4:3] DAC channel selection for class-D • 00 = L + R • 01 = L + L • 10 = R + R • 11 = L + R 2:0 testctrl4[2:0] 0x00 R/W Class-D 5V supply POR rise threshold control • 000 = 4.22V • 001 = 4.02V • 010 = 3.85V • 011 = 3.61V • 100 = 3.4V • 101 = 3.19V • 110 = 2.99V • 111 = 2.79V Conexant Confidential 07/31/14 008DSR00 60 CX20745 Data Sheet Register Details Table 129: Analog Test 5 (0xA9) Bits Name 7:4 testctrl5[7:4] Default 0xA0 3:0 R/W R/W Reserved Description Class-D power in 4Ω load • 0000 = Reserved • 0001 = Reserved • 0010 = Reserved • 0011 = Reserved • 0100 = Reserved • 0101 = 2W • 0110 = 1.8W • 0111 = 1.5W • 1000 = 1.4W • 1001 = 1.2W • 1010 = 1W (default) • 1011 = 0.8W • 1100 = 0.6W • 1101 = 0.5W • 1110 = 0.4W • 1111 = 0.25W Reserved. Table 130: Analog Test 6 (0xAA) Bits Name 7:6 testctrl6[7:6] 5:4 testctrl6[5:4] 3:0 Reserved Default R/W Description DAC channel selection for the headphone • 00 = L + R • 01 = L + L • 10 = R + R • 11 = L+R + L+R 0x00 R/W DAC channel selection for the headphone • 00 = L + R • 01 = L + L • 10 = R + R • 11 = L+R + L+R (mono-mode summation) Reserved. Table 131: Analog Test 8 (0xAC) Bits Name 7:6 tstctrl8[7:6] Default 0x00 5:0 Reserved R/W R/W Description Class-D 5V supply POR hysteresis control • 00 = 740mV • 01 = 530mV • 1X = 320mV (set if class-D supply is 3V) Reserved. Conexant Confidential 07/31/14 008DSR00 61 CX20745 Data Sheet Register Details Table 132: Analog Test 13 (0xB1) Bits Name Default 7:5 Reserved Reserved. 4:0 testctrl13[4:0] Class-D short-circuit current threshold control • Threshold = (decimal code + 1)*100mA • 00000 = 100mA • 00001 = 200mA • … • 01111 = 1600mA (default) • … • 11110 = 3100mA • 11111 = 3200mA 0x0F R/W R/W Description Table 133: Analog Test 14 (0xB2) Bits Name 7:6 testctrl14[7:6] Default 0x19 R/W Description R/W Adjust temperature sensor capacitor ratio • 00b = 2:1 • 01b = 2.5:1 • 10b = 3:1 • 11b = 3.5:1 5:1 testctrl14[5:1] Adjust temperature sensor current mirror ratio from 10:1 (code 0) to 41:1 (code 31). 0 testctrl14[0] Power-on temperature sensor 1 = enable. Read Only Registers Table 134: Monitor ADC LSB (0xE1) Bits Name Default R/W Description 7:0 adc_out_r [7:0] 0x00 R Monitors the ADC LSB. Table 135: Monitor ADC MSB (0xE2) Bits Name Default R/W Description 7:0 adc_out_r [15:8] 0x00 R Monitors the ADC MSB. Table 136: Jack Sense Status and Bond Option (0xE3) Bits Name Default 7:5 Reserved Reserved. 4 Reserved Reserved. 3 Jack Sense 4 Status 2 Jack Sense 3 Status 1 Jack Sense 2 Status Status on the 2-bit. 0 Jack Sense 1 Status Status on the 1-bit (LSB). 0x00 R/W R Description Status on the 4-bit (MSB). Status on the 3-bit. Conexant Confidential 07/31/14 008DSR00 62 CX20745 Data Sheet Register Details Table 137: Class-D Protection Status (0xE4) Bits Name R/W Description 7:4 Reserved Default R Reserved. 3 Sc_8_tr_or R/W Short circuit error status (write on clear). 2 Temp_error R/W Temp error status (write on clear). 1 Por_5 R/W POR_5 error status (write on clear). 0 Class-D Error Sticky R Class-D error sticky status. Default R/W Description 0x20 R 0x00 Table 138: Class-D Calibration Observe (0xE5) Bits Name 7 Reserved 6:0 Calibration_observe[6:0] Reserved. 6-bit calibration value. Table 139: HP A Offset Calibration Observe (0xE6) Bits Name 7 Hp_offcal_en 6:0 Hp_offcal_a [6:0] Default R/W 0x40 R Description Calibration enable status. 6-bit calibration value. Table 140: HP B Offset Calibration Observe (0xE7) Bits Name 7 Hp_offcal_en 6:0 Hp_offcal_b [6:0] Default R/W 0x40 R Description Calibration enable status 6-bit calibration value. Table 141: Memory BIST Status (0xE8) Bits Name Default 7:4 Reserved Reserved. 3 EQ RAM Fail Indicates whether the EQ RAM failed the MBIST test. 2 DAC RAM Fail 0x00 R/W Description Indicates whether the DAC RAM failed the MBIST test. R 1 ADC RAM Fail Indicates whether the ADC RAM failed the MBIST test. 0 MBIST Test Done Indicates whether the MBIST test was done. Table 142: AGC Gain LSB Read Register (0xE9) Bits Name Default R/W Description 7:0 Agc_gain_out_l 0x00 R AGC gain LSB applied a read through a register. Conexant Confidential 07/31/14 008DSR00 63 CX20745 Data Sheet Register Details Table 143: AGC Gain MSB Read Register (0xEA) Bits Name Default R/W Description 7:0 Agc_gain_out_r 0x00 R AGC gain MSB applied a read through a register. Table 144: SPKR DRC Gain LSB Read Register (0xEB) Bits Name Default R/W Description 7:0 Spkr_drc_gain_l 0x00 R Speaker DRC gain LSB applied a read through a register. Table 145: SPKR DRC Gain MSB Read Register (0xEC) Bits Name Default R/W Description 7:0 spkr_drc_gain_r 0x00 R Speaker DRC gain MSB applied a read through a register. R/W Description Table 146: Micbias Detect Read Register (0xED) Bits Name Default 7 Agc_compression_region R Indicates whether AGC is in the compression region. 6 Spkr_drc_compression R Indicates whether spkr_drc is in the compression region. 5 Inc_vol_status R/W Rotary or push button status for incrementing the volume—status is write on clear. 4 Dec_vol_status R/W Rotary or push button status for incrementing the volume—status is write on clear. 3 Reserved R Reserved. 2 Micbias_down_up R/W Status on the volume down button, sticky on button press, and write on clear. 1 Micbias_menu_button R/W Status on the menu button, sticky on button press, and write on clear. 0 Micbias_volume_up R/W Status on the volume up button, sticky on button press, and write on clear. R/W Description 0x40 GPIO Registers Table 147: GPIO In Registers (0xF1) Bits Name Default 7:4 Reserved 3 GPIO4_ In 2 GPIO3_ In 1 GPIO2_ In GPIO 2 input status. 0 GPIO1_ In GPIO 1 input status. Reserved. GPIO 4 input status. 0x00 R GPIO 3 input status. Conexant Confidential 07/31/14 008DSR00 64 CX20745 Data Sheet Register Details Table 148: GPIO Out Registers (0xF2) Bits Name 7:4 Reserved Default Reserved. 3 GPIO4_ Out GPIO 4 output. 2 GPIO3_ Out 1 GPIO2_ Out GPIO 2 output. 0 GPIO1_ Out GPIO 1 output. 0x00 R/W R/W Description GPIO 3 output. Table 149: GPIO Direction Registers (0xF3) Bits Name Default 7:4 Reserved Reserved. 3 GPIO4_ OEN GPIO 4 output enable (active low). 2 GPIO3_ OEN 1 GPIO2_ OEN GPIO 2 output enable (active low). 0 GPIO1_ OEN GPIO 1 output enable (active low). 0x00 R/W R/W Description GPIO 3 output enable (active low). Table 150: GPIO Control Registers (0xF4) Bits Name 7:6 SPI_CSN_DCCTL 5 GPIO_DCCTL 4:3 GPIO_DCCTL 2:0 GPIO_DRVCTL Default R/W Description R/W SPI CSN pull-up control register. R GPIO pull-up control register. R/W GPIO pull-up control register. R/W GPIO drive control register. Default R/W Description 0xFF R/W Default R/W 0xC7 Table 151: I2S DATA Control (0xF5) Bits Name 7:3 Reserved 2:0 I2S_TX_DRVCTL Reserved. I2S Tx drive control register. Table 152: DMIC Drive Control (0xF6) Bits Name 7:6 VREG_CTRL R/W Voltage regulator control. 5 Reserved R Reserved. 4:3 DMIC_DATA_TRIG R/W Digital microphone data drive control register. 2:0 DMIC_DRVCTL R/W DIGMIC CLK drive control register. 0x0D Description Table 153: Device ID LSB (0xFD) Bits Name Default R/W Description 7:0 Device_ID_LSB 0x07 R Device ID [7:0]. Conexant Confidential 07/31/14 008DSR00 65 CX20745 Data Sheet Ordering Information Table 154: Device ID MSB (0xFE) Bits Name Default R/W Description 7:0 Device_ID_MSB 0x51 R Device ID [15:8]. Default R/W Description Table 155: Bond Option Read (0xFF) Bits Name 7:2 Reserved 1 Bond_opt 0 Bond_opt_r Reserved. - R Read bond option value. Read bond opt read pad value. Ordering Information Table 156: Ordering Information Device Part Number Part Number CX20745-11Z* CX20745 Low-Power I2S CODEC 48-pin QFN, Industrial Temperature Range of –40°C to 85°C Description Package Note: The CX20745 is lead-free (Pb-free) and RoHS compliant. www.conexant.com Headquarters: 1901 Main Street, Suite 300 Irvine, CA,92614 General Information: U.S. and Canada: 888-855-4562 | International: 1 + 949-483-3000 © 2014 Conexant Systems, Inc. Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to this document at any time, without notice. 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