EM MICROELECTRONIC - MARIN SA
EM3023
Very Low Power 8-Bit 32 kHz RTC Module with Digital
Trimming, User RAM and High Level Integration
Description
The V3023 is a low power CMOS real time clock with a
built in crystal. Standby current is typically 1.2 µA and the
access time is 50 ns. The interface is 8 bits with
multiplexed address and data bus. Multiplexing of address
and data is handled by the input line A /D. There are no
busy flags in the V3023, internal time update cycles are
invisible to the user's software. Time data can be read
from the V3023 in 12 or 24 hour data formats. An external
signal puts the V3023 in standby mode. Even in standby,
the V3023 pulls the IRQ pin active low on an internal
alarm interrupt. Calendar functions include leap year
correction and week number calculation. Time precision
can be achieved by digital trimming. The V3023 can be
synchronized to an external 50 Hz signal or to the nearest
second or minute.
Applications
Industrial controllers
Alarm systems with periodic wake up
PABX and telephone systems
Point of sale terminals
Automotive electronics
Typical Operating Configuration
Features
Built-in crystal with digital trimming
temperature compensation facilities
and
Can be synchronised to 50 Hz or nearest s/min
50 ns access time with 50 pF load capacitance
Standby on power down typically 1.2 µA
Universal interface compatible with both Intel and
Motorola
Simple 8 bit interface with no delays or busy flags
16 bytes of user RAM
Power fail input disables during power up / down of
reset
Bus can be in tri-state in power fail mode
Wide voltage range: 2.0 V to 5.5 V
12 or 24 hour data formats
Time to 1/100 of a second
Leap year correction and week number calculation
Alarm and timer interrupts
Programmable interrupts: 10 ms, 100 ms, s or min
Sleep mode capability
Alarm programmable up to one month
Timer measures elapsed time up to 24 hours
Temperature range: -40°C to +85°C
Package SO28
Pin Assignment
SO28
NC
SYNC
PF
AD7
AD0
AD6
AD1
AD5
NC
NC
AD2
AD4
AD3
RD
V3023
A/D
WR
IRQ
CS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
Fig. 2
Fig. 1
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3023-DS, Version {_UIVersionString}, 13-Mar-15
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EM3023
Absolute Maximum Ratings
Parameter
Symbol
Maximum voltage at VDD
VDDmax
Max. voltage at remaining pins Vmax
Min. voltage on all pins
Vmin
Maximum storage temperature TSTOmax
Minimum storage temperature TSTOmin
Maximum electrostatic
discharge to MIL-STD-883C
VSmax
method 3015.7 with ref. to VSS
Maximum soldering conditions TSmax
Shock resistance
Conditions
VSS + 7.0V
VDD + 0.3V
VSS – 0.3V
+85°C
-55°C
1000V
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when
all terminal voltages are kept within the voltage range.
Unused inputs must always be tied to a defined logic
voltage level.
Operating Conditions
260°C x 10s
5000 g.
0.3ms, ½ sine
Table 1
Stresses above these listed maximum ratings may cause
permanent damages to the device. Exposure beyond
specified operating conditions may affect device reliability
or cause malfunction.
Parameter
Symbol
Operating temperature
TA
Logic supply voltage
VDD
Supply voltage dv/dt
dv/dt
(power-up & down)
Decoupling capacitor
Electrical Characteristics
VDD= 5.0V ±10%, VSS = 0V, TA=-40 to +85°C, unless otherwise specified
Parameter
Symbol
Test Conditions
Standby current (note 2)
IDD
VDD = 3 V, PF = 0
Dynamic current (note 3)
IDD
Min
-40
2.0
Typ
5.0
100
Min
VDD = 5 V, PF = 0
CS = 4 MHz, RD = VSS
Max Unit
+85
°C
5.5
V
6
V/µs
(note 1)
nF
Table 2
Typ
Max
Unit
1.2
2
10
15
1.5
µA
µA
mA
0.4
0.4
V
V
0.2 VDD
V
V
V
V
V
mV
WR = VDD
IRQ (open drain)
Output low voltage
Output low voltage
Inputs and Outputs
Input logic low
Input logic high
Output logic low
Output logic high
PF activation voltage
PF hysteresis
Pullup on SYNC
Input leakage
Output tri-state leakage
Oscillator Characteristics
Starting voltage
Frequency Characteristics
Start-up time
Frequency tolerance
Frequency stability
Temperature stability
Aging
VOL
VOL
IOL = 8 mA
IOL = 1 mA, VDD = 2 V
VIL
VIH
VOL
VOH
VPFL
VH
TA = +25°C
TA = +25°C
IOL = 6 mA
IOH = 6 mA
ILS
VILS = 0.8 V
IIN
ITS
VSS < VIN < VDD
CS = 1
VSTA
VSTA
TSTA
f/f
fsta
tsta
tag
0.8 VDD
0.4
2.4
0.5 VDD
100
TA = +25°C
20
µA
10
10
TA ≥ +25°C
1000
1000
2
V
V
2.5
TA = +25°C addr. 10 hex = 00 hex
2.0 ≤ VDD ≤ 5.5 V (note 5)
addr. 10 hex = 00 hex
TA = +25°C, first year
150
1
210
(note 4)
1
see Fig.5
nA
nA
251
5
±5
s
ppm
ppm/V
ppm
ppm/year
Table 3
Note 1: For temperature below -20°C, dv/dt max 0.1V/ms.
Note 2: With PFO = 0 (VSS) all I/O pads can be tri-state, tested.
With PFO = 1 (VDD), CS = 1 (VDD) and all other I/O pads fixed to VDD or VSS: same standby current, not tested.
Note 3: All other inputs to VDD and all outputs open.
Note 4: See Fig. 4
Note 5: At a given temperature.
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EM3023
Typical Standby Current at VDD = 5 V
Fig. 3
Typical Frequency on IRQ
Fig. 4
Module Characteristic
F
ppm
= -0.035
(T – TO)2 ± 10%
FO
C2
F/FO
=
T
TO
=
=
the ratio of the change in frequency to the
nominal value expressed in ppm (it can be
thought of as the frequency deviation at any
temperature)
the temperature of interest in °C
the turnover temperature (25 ± 5°C)
To determine the clock error (accuracy) at a given
temperature, add the frequency tolerance at 25°C to the
value obtained from the formula above.
Fig. 5
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EM3023
Timing Characteristics (standard temperature range)
VDD= 5.0 ±10%, VSS = 0V and TA=-40 to +85°C
Parameter
Symbol Test Conditions
Chip select duration, write cycle
tCS
Min.
50
Typ.
Max.
Unit
ns
Write pulse duration
tWR
50
ns
Time between two transfers
tW
100
ns
RAM access time (note 1)
tACC
CLOAD = 50pF
50
60
ns
30
40
ns
Data valid to Hi-impedance (note 2)
tDF
10
Write data settle time (note 3)
tDW
50
ns
Data hold time (note 4)
tDH
10
ns
Advance write time
tADW
10
ns
PF response delay
tPF
100
ns
Rise time (all timing waveform
signals)
tR
200
ns
Fall time (all timing waveform
signals)
tF
200
ns
CS delay after A /D (note 5)
t A /Ds
5
ns
CS delay to A /D
t A /Dt
10
ns
Table 4
Note 1: tACC starts from RD ( DS ) or CS , whichever activates last
Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF
Note 2: tDF starts from RD ( DS ) or CS , whichever deactivates first
Note 3: tDW ends at WR (R/ W ) or CS , whichever deactivates first
Note 4: tDH starts from WR (R/ W ) or CS , whichever deactivates first
Note 5: A /D must come before a CS and RD or a CS and WR combination. The user has to guarantee this.
Timing Waveforms
Read Timing for Intel ( RD and WR Pulse) and Motorola ( DS or RD pin tied to CS and R/ W )
Fig. 6a
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EM3023
Intel Interface
Write Timing
Fig. 6b
Write
Fig. 6c
Read
Fig. 6d
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EM3023
Motorola Interface
Motorola Write
Fig. 6e
Write
Fig. 6f
Read
Fig. 6g
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EM3023
General Block Diagram
Fig. 7
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3023-DS, Version {_UIVersionString}, 13-Mar-15
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EM3023
Pin Description
SO28 Package
Pin
1
Name
SYNC
2
PF
3
AD0
4
AD1
5
NC
6
AD2
7
AD3
8
A /D
IRQ
VSS
VDD
9
10-14
15-19
20
CS
21
WR
22
RD
23
AD4
24
NC
25
AD5
26
AD6
27
AD7
28
NC
Description
Time synchronization
Power fail
Bit 0 from MUX address /
data bus
Bit 1 from MUX address /
data bus
No connection
Bit 2 from MUX address /
data bus
Bit 3 from MUX address /
data bus
Address / data decode
Interrupt request
Supply ground (substrate)
Positive supply terminal
Chip select
WR (Intel) or R/ W
(Motorola)
RD (Intel) or DS (Motorola)
Bit 4 from MUX address /
data bus
No connection
Bit 5 from MUX address /
data bus
Bit 6 from MUX address /
data bus
Bit 7 from MUX address /
data bus
No connection
I
I
I/O
I/O
I/O
I/O
I
O
GND
PWR
I
I
I
I/O
I/O
I/O
I/O
Table 5
Functional Description
Power Supply, Data Retention and Standby
The V3023 is put in standby mode by activating the PF
input. When pulled logic low, PF will disable the input
lines, and immediately take to high impedance the lines
AD 0-7. Input states must be under control whenever PF
is deactivated. If no specific power fail signal can be
provided, PF can be tied to the system RESET . Even in
standby the interrupt request pin IRQ will pull to ground
upon an unmasked alarm interrupt occurring.
Copyright 2015, EM Microelectronic-Marin SA
3023-DS, Version {_UIVersionString}, 13-Mar-15
Initialisation
When power is first applied to the V3023 all registers have
a random value.
To initialise the V3023, software must first write a 1 to the
initialisation bit (addr. 2 bit 4) and then a 0. This sets the
Frequency Tuning bit and clears all other status bits.
The time and date parameters should then be loaded into
the RAM (addr. 20 to 28 hex) and then transferred to the
reserved clock area using the clock command followed by
a write.
The digital trimming register must then be initialised
by writing 210 (D2 hex) to it, if Frequency Tuning is
not required. After having written a value to the
digital trimming register the frequency tuning mode
bit can be cleared.
RAM Configuration
The RAM area of the V3023 has a reserved clock and
time area, a data space, user RAM and an address
command space (see Table 9 or Fig. 7). The reserved
clock and timer area is not directly accessible to the user,
it is used for internal time keeping and contains the
current time and date plus the timer parameters.
Data Space
All locations in the data space are Read/Write. The data
space is directly accessible to the user and is divided into
five areas:
Status Registers – three registers used for status and
control data for the device (see Table 6, 7 and 8).
Digital Trimming Register – a special function described
under "Frequency Tuning".
Time and Date Registers – 9 time and date locations
which are loaded with, either the current time and date
parameters from the reserved clock area or the time and
date parameters to be transferred to the reserved clock
area.
Alarm Registers – 5 locations used for setting the alarm
parameters.
Timer Registers – 4 locations which are loaded with
either the timer parameters from the reserved timer area
or the timer parameters to be transferred to the reserved
timer area.
User RAM
The V3023 has 16 bytes of general purpose RAM
available for the users applications. This RAM block is
located at addresses 50 to 5F hex and is maintained even
in the standby mode ( PF active). The commands, or the
time set lock bit, have no effect on the user RAM block.
Reading or writing to the user RAM is similar to reading or
writing to any system RAM address.
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EM3023
Status Words
RAM Map
Address
Dec
Status 0 - Address 00 Hex
7 6 5 4 3 2 1 0
Read / Write bits
0 - disabled / 24 hour
1 - enabled / 12 hour
frequency tuning mode
pulse enable / disable
alarm enable / disable
timer enable / disable
24 hour / 12 hour (note 1)
time set lock
test bit 0
test bit 1
Table 6
Status 1 - Address 01 Hex
7 6 5 4 3 2 1 0
Read / Write bits
0 - masked / no event
1 - unmasked / event
pulse mask
alarm mask
timer mask
reserved
pulse flag
alarm flag
timer flag
reserved
Table 7
Status 2 - Address 02 Hex
7 6 5 4 3 2 1 0
Read / Write bits
0 - masked / no event
1 - unmasked / event
pulse every 10 ms
pulse every 100 ms
pulse every second
pulse every minute
initialisation bit
SYNC 50 Hz
SYNC second
SYNC minute
Table 8
Address Command Space
This space contains the three commands used for
carrying out the transfers between the Time and Data
Register and / or the Timer Registers and the reserved
clock and timer area.
Parameter
Range
Hex
Data Space
Status
00
00
status 0
01
01
status 1
02
02
status 2
Special purpose
16
10
digital trimming
Clock
32
20
1/100 second
33
21
seconds
34
22
minutes
35
23
hours (note 1)
36
24
date
37
25
month
38
26
year
39
27
week day
40
28
week number
Alarm
48
30
1/100 second
49
31
seconds
50
32
minutes
51
33
hours (note 1 & 2)
52
34
date
Timer
64
40
1/100 second
65
41
seconds
66
42
minutes
67
43
hours
User RAM
80
50
user RAM, byte 0
81
51
user RAM, byte 1
82
52
user RAM, byte 2
83
53
user RAM, byte 3
84
54
user RAM, byte 4
85
55
user RAM, byte 5
86
56
user RAM, byte 6
87
57
user RAM, byte 7
88
58
user RAM, byte 8
89
59
user RAM, byte 9
90
5A
user RAM, byte 10
91
5B
user RAM, byte 11
92
5C
user RAM, byte 12
93
5D
user RAM, byte 13
94
5E
user RAM, byte 14
95
5F
user RAM, byte 15
Address Command Space
240
F0
clock and timer transfer
241
F1
clock transfer
242
F2
timer transfer
0-255
00-99
00-59
00-59
00-23
01-31
01-12
00-99
01-07
00-53
00-99
00-59
00-59
00-23
01-31
00-99
00-59
00-59
00-23
Table 9
Note 1: The MSB (bit 7) of the hours byte (addr. 23 hex
for the clock and 33 hex for the alarm) are used
as AM/PM indicators in the 12 hour time data
format and reading of the hours byte must be
preceded by masking of the AM/PM bit. A set
AM/PM bit indicates PM. In the 24 hour time
data format the bit will always be zero.
Note 2: The alarm hours, addr. 33 hex, must always be
rewritten after a change between 12 and 24 hour
modes.
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3023-DS, Version {_UIVersionString}, 13-Mar-15
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EM3023
Communication
Data transfer is in 8 bit parallel form. All time data is in
packed BCD format with tens data on lines AD7-4 and
units on lines AD3-0. To access information within the
RAM (see Fig.7) first write the RAM address, then read or
write from or to this location. Fig.8 shows the two steps
needed.
The lines AD0-7 will be treated as an address when pin
A /D is low, and as data when A /D is high. Pin A /D
must not change state during any single read or write
access. One line of the address bus (e.g. A0) can be used
to implement the A /D signal (see "Typical Operating
Configuration", Fig.1). Until a new address is written, data
accesses (/D high) will always be to the same RAM
address.
Communication Sequence
A/D 0
Write RAM address to the V3023
A/D 1
Read or write data from or to the
above address
Fig. 8
Access Considerations
The communication sequence shown in Fig.8 is reentrant. When the address is written to the V3023 (ie. first
step of the communication sequence) it is stored in an
internal address latch. Software can read the internal
address latch at any time by holding the A /D line low
during a read from the V3023. So, for example, an
interrupt routine can read the address latch and push it on
to a stack, popping it when finished to restore the V3023.
N.B. Alarm and timer interrupt routines can reprogram the
alarm and timer without it being necessary to read or
reprogram the clock.
Commands
The commands allow software to transfer the clock and
timer parameters in a sequence (eg. seconds, minutes,
hours, etc.) without any danger of an internal time update
with carry over corrupting the data. They also avoid
delaying internal time updates while using the V3023, as
updates occurring in the reserved clock and timer area
are invisible to software. Software writes or reads
parameters to or from the RAM only.
There are three commands that occupy the command
address space in the RAM. The function of these
commands is to transfer data from the reserved clock and
timer area to the RAM or to transfer data in the opposite
direction, from the RAM to the reserved clock and timer
area.
The commands take place in two steps as do all other
communications. The command address is sent with
A /D low. This is followed by either a read ( RD ) or a
write ( WR ) , with A /D high, to determine the direction of
the transfer. If the second step is a read then the data is
transferred from the reserved clock and timer area to the
RAM and if the second step is a write then the data that
has already been loaded into the RAM clock and/or timer
Copyright 2015, EM Microelectronic-Marin SA
3023-DS, Version {_UIVersionString}, 13-Mar-15
locations is transferred to the reserved clock and/or timer
area.
Clock and Calendar
The time and date locations in RAM (see Table 9) provide
access to the 1/100 seconds, seconds, minutes, hours,
date, month, year, week day and week number. These
parameters have the ranges indicated in Table 9. The
V3023 may be programmed for 12 or 24 hour time format
(see section "12/24 Data Format"). If a parameter is found
to be out of range, it will be cleared when the units value
on its being next incremented is equal to or greater than 9
eg. B2 will be set to 00 after the units have incremented to
9 (ie. B9 to 00). The device incorporates leap year
correction and week number calculation at the beginning
of a year. If the first day of the year is day 05, 06 or 07 of
the week, then it is given a zero week number, otherwise
it becomes week 1. Week days are numbered from 1 to 7
with Monday as day 1.
Reading of the current time and date must be preceded
by a clock command. The time and date from the last
clock command is held unchanged in RAM.
When transferring data to the reserved clock and
timer area remember to clear the time set lock bit first.
Timer
The timer can be used either for counting elapsed time, or
for giving an interrupt ( IRQ ) on being incremented from
23:59:59:99 to 00:00:00:00. The timer counts up with a
resolution of 1/100 second in the timer reserved areas.
The timer enable/disable bit (addr. 00 hex, bit 3) must be
set by software to allow the timer to be incremented. The
timer is incremented in the reserved timer area, every
internal time update (10 ms). The timer flag (addr. 01
hex, bit 6) is set when the timer rolls over from
23:59:59:99 to 00:00:00:00 and the IRQ becomes active
if the timer mask bit (addr. 01, bit 2) is set. The IRQ will
remain active until software acknowledges the interrupt by
clearing the timer flag. The timer is incremented in the
standby mode, however it will not cause IRQ to become
active until power (VDD) has been restored.
Note: The user should ensure that a time lapse of at least
60 microseconds exists between the falling edge of the
IRQ and the clearing of the timer flag.
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EM3023
Reading the Clock
[Pin 7 = A/D]
Setting the Timer (Time Set Lock Bit = 0)
Start
A/D = 0
Write clock command
(addr. F1 hex) to the V3023
A/D = 1
Read data from the V3023 to
copy the timer parameters from
the reserved clock area to the
RAM.
[Pin 7 = A/D]
Start
A/D = 0
Write 1/100 sec. address
(40 hex) to the V3023
A/D = 1
Write 1/100 sec. data to the
RAM
A/D = 0
Write sec. address (41 hex) to
the V3023
A/D = 0
Write 1/100 sec. address
(20 hex) to the V3023
A/D = 1
Write sec. data to the RAM
A/D = 1
Read 1/100 sec. data from the
RAM
A/D = 0
Write min. address (42 hex) to
the V3023
A/D = 0
Write sec. address (21 hex) to
the V3023
A/D = 1
Write min. data to the RAM
A/D = 1
Read sec. data from the RAM
A/D = 0
Write hours address (43 hex) to
the V3023
A/D = 1
Write hours data to the RAM
A/D = 0
Write timer command
(addr. F2 hex) to the V3023
A/D = 1
Write F2 hex to the V3023 to
copy the timer parameters from
RAM to the reversed timer area
A/D = 0
A/D = 1
Write min. address (22 hex) to
the V3023
Read min. data from the RAM
End
Fig. 9
End
Fig. 10
Note: Commands are only valid as commands when the
A /D line is low. Writing F2 hex with the A /D line high,
as in the last box of Fig. 8, serves only to activate the
V3023 write pin which determines the direction of transfer.
Alarm
An alarm date and time may be preset in RAM addresses
30 to 34 hex. The alarm function can be activated by
setting the alarm enable / disable bit (addr. 00 hex, bit 2).
Once enabled the preset alarm time and date are
compared, every internal time update cycle (10 ms), with
the clock parameters in the reserved clock area. When
the clock parameters equal the alarm parameters the
alarm flag (addr. 01 hex, bit 5) is set. If the alarm mask bit
(addr. 01 hex, bit 1) is set, the IRQ pin goes active. The
alarm flag indicates to software the source of the interrupt.
IRQ will remain active until software acknowledges the
interrupt by clearing the alarm flag. If the alarm is
enabled, and an alarm address set to FF hex, this
parameters is not compared with the associated clock
parameter. Thus it is possible to achieve a repeat feature
where an alarm occurs every programmed number of
seconds, or seconds and minutes, or seconds, minutes
and hours. The V3023 pulls the open drain IRQ line
active low during standby when an alarm interrupt occurs.
If the 12/24 hour mode is changed then the alarm
hours must be re-initialised.
Copyright 2015, EM Microelectronic-Marin SA
3023-DS, Version {_UIVersionString}, 13-Mar-15
Note: The user should ensure that a time lapse of at least
60 microseconds exists between the falling edge of the
IRQ and the clearing of the alarm flag.
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EM3023
IRQ
The IRQ output is used by 4 of the V3023's features.
These are:
1. Pulse, to provide periodic interrupts to the
microprocessors at pre-programmed intervals;
2. Alarm to provide an interrupt to the microprocessor at
a pre-programmed time and date;
3. Timer, to provide an interrupt to the microprocessor
when the time rolls over from 23:59:59:99 to
00:00:00:00; and
4. Frequency trimming (see section "Frequency
Trimming").
The first 3 features listed are similar in the way they
provide interrupts to the microprocessor. Each o the 3
has an enable / disable bit, a flag bit, and an interrupt
mask bit. The enable / disable bit allows software to
select a feature or not. A set flag bit indicates that an
enable feature has reached its interrupt condition.
Software must clear the flag bit. The interrupt mask bit
allows or disallows the IRQ output to become active
when the flag bit is se. The IRQ output becomes active
whenever any interrupt flag is set which also has its mask
bit set. for all sources of maskable interrupts within the
V3023, the IRQ output will remain active until software
clears the interrupt flag. The IRQ output is the logical OR
of all the unmasked interrupt flags. The IRQ output is
open drain so an external pullup to V DD is needed. In
standby ( PF active) the IRQ output will be active if the
alarm mask bit (addr, 01 hex, bit 1) is set and the alarm
flag is also set. The timer or the pulse feature cannot
cause the IRQ output to become active while in standby.
Snychronization
There are 3 ways to synchronize the V3023. It can be
synchronized to 50 Hz, the nearest second, or the nearest
minute. Synchronization mode is selected by setting one
of the bits 5 to 7 at addr. 02 hex, in accordance with Table
8. If more than one bit is set then all the synchronization
bits are disabled. If the SYNC input is set low for longer
than 200 µs, while in the synchronization mode, the clock
will synchronize to the falling edge of the signal.
Synchronization to the nearest second implies that the
1/100 seconds are cleared to zero and if the contents
were > 50, the seconds register is incremented.
Synchronization to the nearest minute implies that the
seconds are cleared to zero and if the contents were > 30,
the minutes register is incremented. Fractions of seconds
are cleared.
Pulse
There are 4 programmable pulse frequencies available on
the V3023, these are every 10 ms, 100 ms, second or
minute. The pulse feature is activated by setting the pulse
enable / disable bit at address 00, bit 1. The pulse
frequency is selected by setting one of the bit 0 to 3 at
address 02 hex (see Table 8). If more than one of the
pulse bits is set then the feature is disabled. At the
selected interval the pulse flag bit (addr. 01 hex, bit 4) is
set. If the pulse mask bit (addr. 01 hex, bit 0) is set then
the IRQ pin goes active. The pulse flag indicates to
feature is enabled if enabled prior to standby. See also
the section "Frequency Tuning".
Note: The user should ensure that a time lapse of at least
60 microseconds exists between the falling edge of the
IRQ and the clearing of the pulse flag.
Time Set Lock
The time set lock control bit is located at address 00 hex,
bit 5 (see Table 6). When set by software, this bit
disables any transfer from the RAM to the reserved clock
and timer area as well as inhibiting any write to the digital
trimming register at address 10 hex. When the time set
lock bit is set the following transfer operations are
disabled:
The clock command followed by write,
the timer command followed by write,
the clock and timer command followed by write, and
writing to the digital trimming register
A set bit prevents unauthorized overwriting of the
reserved clock and timer area. Reading of the reserved
clock and timer area, using the commands, is not affected
by the time set lock bit. Clearing the time set lock bit by
software will re-enable the above listed commands. On
initialisation the time set lock bit is cleared. The time set
lock bit does not affect the user RAM (addr. 50 to 5F hex).
Frequency Tuning
The V3023 offers a key feature called "Digital Trimming",
which is used for the clock accuracy adjustment. Unlike
the traditional capacitor trimming method which tunes the
crystal oscillator, the digital trimming acts on the divider
chain, allowing the clock adjustment by software. The
oscillator frequency itself is not affected.
The Principle of Digital Trimming
With the digital trimming disabled (ie. digital trimming
register set to 00 hex), the oscillator and the first stages of
the divider chain will run slightly too fast (typ. 210 ppm:
ppm = parts per million), and will generate a 100 Hz signal
with a frequency of typically 100.021 Hz. To correct this
frequency, the digital trimming logic will inhibit every 31
seconds, a number of clock pulses, as set in the digital
trimming register. Since the duration of 31 seconds
corresponds to 1'015'808 oscillator cycles, the digital
trimming has a resolution of 0.984 ppm. In other words
every increment by 1 of the digital trimming value will slow
down the clock by 0.984 ppm, which permits the accuracy
of ± 0.5 ppm to be reached. Note that a 1 ppm error will
result in a 1 second difference after 11.5 days, or a 1
minute difference after 694 days ! The trimming range of
the V3023 is from 0 to 251 ppm. The 251 ppm correction
is obtained by writing 255 (FFhex) into the digital trimming
register.
software the source of the interrupt. IRQ will remain
active until software acknowledges the interrupt by
clearing the pulse flag. The pulse feature is disabled
while in standby. Upon power restoration the pulse
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EM3023
How to Determine the Digital Trimming Value
The value to write into the digital trimming register has to
be determined by the following procedure:
1. Initialise the V3023 by writing a 1 and then a 0 into the
"Initialisation Bit" of the status register 2 (addr. 02 hex,
bit 4). This activates the frequency tuning mode in
status register 0 (addr. 00 hex, bit 1) and clears the
other status bits.
2. Write the value 00 hex into the digital trimming register
(addr 10 hex). From now, the IRQ output (open
drain) will deliver the 100 Hz signal, which has a 20%
duty cycle.
3. Measure the duration of 21 pulses at the IRQ output,
with the trigger set for the falling edge. It is possible
also to divide the IRQ frequency by 21, using a TTL
or CMOS external circuit.
4. Compute the frequency error in ppm:
210ms measured value in ms
freq. error =
x 106
210ms
5. Compute the corrective value to write into the digital
trimming register.
Digital trimming value = frequency error / 0.984
6. Write this value into the digital trimming register.
7. Switch off the frequency tuning mode in status 0 (addr.
00 hex, bit 0 set to 0).
The Real Time Clock circuit will now run accurately at an
operating temperature equal to the calibration
temperature. If the operating temperature differs from the
one at calibration time, the graphs shown on Fig. 4 and 5
will help in determining the definitive value. If the mean
operating temperature of the equipment is not known at
calibration time, the equipment user will do the final
correction with a software provided by the system
designer. To avoid the calibration procedure, it is possible
also to set the digital trimming register to 210 (D2 hex) as
a standard starting value, and let the final equipment user
perform the final adjustment on site, which will take the
real temperature into account.
Time Correction at Room Temperature
Let us consider that the duration of 21 pulses of the IRQ
signal is 209.960 ms at room temperature.
12 / 24 Hour Data Format
The V3023 can run in 12 hour data format.
On
initialisation the 12/24 hour bit addr. 00 bit 4 is cleared
putting the V3023 in 24 hour data format. If the 12 hour
data format is required then bit 4 at addr. 00 must be set.
In the 12 hour data format the AM/PM indicator is the
MSB of the hours register addr. 23 bit 7. A set bit
indicates PM. When reading the hours in the 12 hour
data format software should mask the MSB of the hours
register. In the 24 hour data format the MSB is always
zero.
The internal clock registers change automatically between
12 and 24 hour mode when the 24/12 hour bit is changed.
The alarm hours however must be rewritten.
Test
From the various test features added to the V3023 some
may be activated by the user. Table 6 shows the test bits.
Table 10 shows the three available modes and how they
may be activated.
The first accelerates the incrementing of the parameters
in the reserved clock and timer area by 32.
The second causes all clock and timer parameters, in the
reserved clock and timer area, to be incremented in
parallel at 100 Hz with no carry over, ie. independently of
each other.
The third test mode combines the previous two resulting
in parallel incrementing at 3.2 kHz.
While test bit 1 is set (addr. 00 hex, bit 7) the digital
trimming action is disabled and no pulses are removed
from the divider chain. Test bit 0 (addr. 00 hex, bit 6) can
be combined with digital trimming (see section "Frequency
Tuning").
To leave test, the test bits (addr 00 hex, bits 6 and 7) must
be cleared by software. Test corrupts the clock and timer
parameters and so all parameters should be re-initialised
after a test session.
Test Modes
Addr.
00hex bit 7
0
0
1
Addr.
00hex bit 6
0
1
0
1
1
The frequency error is:
(210 – 209.960) / 210 x 106 = 190.476 ppm
The value for the digital trimming register is:
190.476 / 0.984 = 193.57, rounded to 194 ppm (C2 hex)
Time Correction with Change of Temperature
If the mean temperature on site is known to be 45°C, the
frequency error determined at room temperature has to be
modified using the graphs or the equation of Fig. 5
Function
Normal operation
Acceleration by 32
Parallel increment of all clock
and timer parameters at 100
Hz with no carry over;
dependent on the status of bit
3 at address 00 hex
Parallel increment of all clock
and timer parameters at 3.2
kHz with no carry over;
dependent on the status of bit
3 at address 00 hex
Table 10
f/f = -0.035 x (45-25)2 = -14.0 ppm
The trimming value for 45°C will be:
(190.476 ppm – 14.0 ppm) / 0.984 = 179.34, rounded to
179 (B3 hex)
Copyright 2015, EM Microelectronic-Marin SA
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EM3023
Battery or Supercap Connection
Note: The diodes must have a
forward voltage drop of less than
0.3V. BAT 85 s are recommended.
VDD
Power fail
(low for standby)
VDD
PF
V3023
+
+
or
Battery
Supercap
VSS
VSS
Fig. 11
Typical Applications
V3023 Interfaced with Intel CPU ( RD and WR pulse)
Fig. 12
V3023 Interfaced with Motorola CPU ( DS or RD pin tied to CS , and R/ W )
Fig. 13
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EM3023
Process Application
Temperature
sensor
Controller
Solenoid
valve
The formula in Fig. 4 is used by software to continually
update the digital trimming register and so compensate
the V3023 for the ambient temperature.
The timer is used to measure the duration the valve is
on.
The alarm feature is used to turn the controller power
on and off at the time programmed by software. The
V3023 pulls IRQ active low on an alarm even in
standby and thus can control the power on/off switch for
the controller.
The user RAM provides the controller with non-volatile
RAM for vital parameters, for example:
1. the total on time for the valve to enable software to
compute energy usage and also to identify when
service is needed
- 3 bytes
2. average on time for the valve
- 2 bytes
3. maximum temperature ever encountered together
with the time and date
- 6 bytes
4. date of last service and service man's ID - 4 bytes
5. identification code for the controller
- 1 byte
Fig. 14
Ordering and Package Information
Dimensions of 28-pin SOIC Package
Fig. 15
Ordering Information
When ordering, please specify the complete part number.
Part Number
Package
Delivery Form
V3023SO28B+
V3023SO28A+
28-pin SOIC
28-pin SOIC
Copyright 2015, EM Microelectronic-Marin SA
3023-DS, Version {_UIVersionString}, 13-Mar-15
Package Marking
(first line)
V3023 28S
V3023 28S
Tape & Reel
Stick
15
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EM3023
EM Microelectronic-Marin SA (“EM”) makes no warranties for the use of EM products, other than those expressly contained in EM's
applicable General Terms of Sale, located at http://www.emmicroelectronic.com. EM assumes no responsibility for any errors which may
have crept into this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein.
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nor implicitly.
In respect of the intended use of EM products by customer, customer is solely responsible for observing existing patents and other
intellectual property rights of third parties and for obtaining, as the case may be, the necessary licenses.
Important note: The use of EM products as components in medical devices and/or medical applications, including but not limited
to, safety and life supporting systems, where malfunction of such EM products might result in damage to and/or injury or death
of persons is expressly prohibited, as EM products are neither destined nor qualified for use as components in such medical
devices and/or medical applications. The prohibited use of EM products in such medical devices and/or medical applications is
exclusively at the risk of the customer
Copyright 2015, EM Microelectronic-Marin SA
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