Clock Networks and PLLs in Cyclone IV Devices

5. Clock Networks and PLLs in
Cyclone IV Devices
October 2012
CYIV-51005-2.4
CYIV-51005-2.4
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
with advanced features in the Cyclone® IV device family. It includes details about the
ability to reconfigure the PLL counter clock frequency and phase shift in real time,
allowing you to sweep PLL output frequencies and dynamically adjust the output
clock phase shift.
1
The Quartus® II software enables the PLLs and their features without external
devices.
This chapter contains the following sections:
■
“Clock Networks” on page 5–1
■
“PLLs in Cyclone IV Devices” on page 5–18
■
“Cyclone IV PLL Hardware Overview” on page 5–20
■
“Clock Feedback Modes” on page 5–23
■
“Hardware Features” on page 5–26
■
“Programmable Bandwidth” on page 5–32
■
“Phase Shift Implementation” on page 5–32
■
“PLL Cascading” on page 5–33
■
“PLL Reconfiguration” on page 5–34
■
“Spread-Spectrum Clocking” on page 5–41
■
“PLL Specifications” on page 5–41
Clock Networks
The Cyclone IV GX device provides up to 12 dedicated clock pins (CLK[15..4]) that
can drive the global clocks (GCLKs). Cyclone IV GX devices support four dedicated
clock pins on each side of the device except the left side. These clock pins can drive up
to 30 GCLKs.
The Cyclone IV E device provides up to 15 dedicated clock pins (CLK[15..1]) that can
drive up to 20 GCLKs. Cyclone IV E devices support three dedicated clock pins on the
left side and four dedicated clock pins on the top, right, and bottom sides of the device
except EP4CE6 and EP4CE10 devices. EP4CE6 and EP4CE10 devices only support
three dedicated clock pins on the left side and four dedicated clock pins on the right
side of the device.
© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Cyclone IV Device Handbook,
Volume 1
October 2012
Feedback Subscribe
5–2
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
f For more information about the number of GCLK networks in each device density,
refer to the Cyclone IV FPGA Device Family Overview chapter.
GCLK Network
GCLKs drive throughout the entire device, feeding all device quadrants. All resources
in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,
and M9K memory blocks) can use GCLKs as clock sources. Use these clock network
resources for control signals, such as clock enables and clears fed by an external pin.
Internal logic can also drive GCLKs for internally generated GCLKs and
asynchronous clears, clock enables, or other control signals with high fan-out.
Table 5–1, Table 5–2 on page 5–4, and Table 5–3 on page 5–7 list the connectivity of the
clock sources to the GCLK networks.
Table 5–1. GCLK Network Connections for EP4CGX15, EP4CGX22, and EP4CGX30 (1),
GCLK Network Clock
Sources
(2)
(Part 1 of 2)
GCLK Networks
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLK4/DIFFCLK_2n
— — — — — v — v — v — — — — — — — — — —
CLK5/DIFFCLK_2p
— — — — — — v v — — — — — — — — — — — —
CLK6/DIFFCLK_3n
— — — — — — v — v v — — — — — — — — — —
CLK7/DIFFCLK_3p
— — — — — v — — v — — — — — — — — — — —
CLK8/DIFFCLK_5n
— — — — — — — — — — v — v — v — — — — —
CLK9/DIFFCLK_5p
— — — — — — — — — — — v v — — — — — — —
CLK10/DIFFCLK_4n/RE
— — — — — — — — — — — v — v v — — — — —
FCLK1n
CLK11/DIFFCLK_4p/RE
— — — — — — — — — — v — — v — — — — — —
FCLK1p
CLK12/DIFFCLK_7p/RE
— — — — — — — — — — — — — — — v — v — v
FCLK0p
CLK13/DIFFCLK_7n/RE
— — — — — — — — — — — — — — — — v v — —
FCLK0n
CLK14/DIFFCLK_6p
— — — — — — — — — — — — — — — — v — v v
CLK15/DIFFCLK_6n
— — — — — — — — — — — — — — — v — — v —
PLL_1_C0
v — — v — — — — — — — — — — — v — — v —
PLL_1_C1
— v — — v — — — — — — — — — — — v — — v
PLL_1_C2
v — v — — — — — — — — — — — — v — v — —
PLL_1_C3
— v — v — — — — — — — — — — — — v — v —
PLL_1_C4
— — v — v — — — — — — — — — — — — v — v
PLL_2_C0
v — — v — — — — — — v — — v — — — — — —
PLL_2_C1
— v — — v — — — — — — v — — v — — — — —
PLL_2_C2
v — v — — — — — — — v — v — — — — — — —
PLL_2_C3
— v — v — — — — — — — v — v — — — — — —
PLL_2_C4
— — v — v — — — — — — — v — v — — — — —
PLL_3_C0
— — — — — v — — v — — — — — — v — — v —
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
5–3
Table 5–1. GCLK Network Connections for EP4CGX15, EP4CGX22, and EP4CGX30 (1),
GCLK Network Clock
Sources
(2)
(Part 2 of 2)
GCLK Networks
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
PLL_3_C1
— — — — — — v — — v — — — — — — v — — v
PLL_3_C2
— — — — — v — v — — — — — — — v — v — —
PLL_3_C3
— — — — — — v — v — — — — — — — v — v —
PLL_3_C4
— — — — — — — v — v — — — — — — — v — v
PLL_4_C0
(3)
— — — — — v — — v — v — — v — — — — — —
PLL_4_C1
(3)
— — — — — — v — — v — v — — v — — — — —
PLL_4_C2
(3)
— — — — — v — v — — v — v — — — — — — —
PLL_4_C3
(3)
— — — — — — v — v — — v — v — — — — — —
PLL_4_C4
(3)
— — — — — — — v — v — — v — v — — — — —
— — — — — — — — — — — — — — — — v — — —
DPCLK2
DPCLK3
(4)
— — — — — — — — — — — — — — — — — — v —
DPCLK4
(4)
— — — — — — — — — — — — — — — — — v — —
— — — — — — — — — — — — — — — — — — — v
DPCLK5
DPCLK6
— — — — — — — — v — — — — — — — — — — —
(4)
— — — — — — v — — — — — — — — — — — — —
DPCLK7
— — — — — — — — — v — — — — — — — — — —
DPCLK8
DPCLK9
— — — — — — — v — — — — — — — — — — — —
(4)
— — — — — — — — — — — — — — v — — — — —
DPCLK10
DPCLK11
(4)
— — — — — — — — — — — — v — — — — — — —
DPCLK12
(4)
— — — — — — — — — — — — — v — — — — — —
— — — — — — — — — — — v — — — — — — — —
DPCLK13
Notes to Table 5–1:
(1)
(2)
(3)
(4)
EP4CGX30 information in this table refers to all EP4CGX30 packages except F484 package.
PLL_1 and PLL_2 are multipurpose PLLs while PLL_3 and PLL_4 are general purpose PLLs.
PLL_4 is only available in EP4CGX22 and EP4CGX30 devices in F324 package.
This pin applies to EP4CGX22 and EP4CGX30 devices.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
GCLK Network Clock
Sources
(2)
5–4
Cyclone IV Device Handbook,
Volume 1
Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices (1),
(Part 1 of 4)
GCLK Networks
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Altera Corporation
— — — — — — — — — — — — v — v — v — — — — — — — — — — — — —
CLKIO5/DIFFCLK_2p
— — — — — — — — — — — — — v v — — v — — — — — — — — — — — —
CLKIO6/DIFFCLK_3n
— — — — — — — — — — — — — v — v v — — — — — — — — — — — — —
CLKIO7/DIFFCLK_3p
— — — — — — — — — — — — v — — v — v — — — — — — — — — — — —
CLKIO8/DIFFCLK_5n
— — — — — — — — — — — — — — — — — — v — v — v — — — — — — —
CLKIO9/DIFFCLK_5p
— — — — — — — — — — — — — — — — — — — v v — — v — — — — — —
CLKIO10/DIFFCLK_4n/RE
FCLK3n
— — — — — — — — — — — — — — — — — — — v — v v
CLKIO11/DIFFCLK_4p/RE
FCLK3p
— — — — — — — — — — — — — — — — — — v — — v — v — — — — — —
CLKIO12/DIFFCLK_7p/RE
FCLK2p
— — — — — — — — — — — — — — — — — — — — — — — — v — v — v —
CLKIO13/DIFFCLK_7n/RE
FCLK2n
— — — — — — — — — — — — — — — — — — — — — — — — — v v — — v
CLKIO14/DIFFCLK_6p
— — — — — — — — — — — — — — — — — — — — — — — — — v — v v —
CLKIO15/DIFFCLK_6n
— — — — — — — — — — — — — — — — — — — — — — — — v — — v — v
PLL_1_C0
v — — v — v — — — — — — — — — — — — — — — — — — v — — v — v
PLL_1_C1
— v — — v — — — — — — — — — — — — — — — — — — — — v — — v —
PLL_1_C2
v — v — — — — — — — — — — — — — — — — — — — — — v — v — — —
PLL_1_C3
— v — v — — — — — — — — — — — — — — — — — — — — — v — v — —
PLL_1_C4
— — v — v v — — — — — — — — — — — — — — — — — — — — v — v v
PLL_2_C0
— — — — — — v — — v — v — — — — — — v — — v — v — — — — — —
PLL_2_C1
— — — — — — — v — — v — — — — — — — — v — — v — — — — — — —
PLL_2_C2
— — — — — — v — v — — — — — — — — — v — v — — — — — — — — —
PLL_2_C3
— — — — — — — v — v — — — — — — — — — v — v — — — — — — — —
PLL_2_C4
— — — — — — — — v — v v — — — — — — — — v — v v — — — — — —
— — — — — —
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
October 2012
CLKIO4/DIFFCLK_2n
GCLK Network Clock
Sources
(2)
(Part 2 of 4)
GCLK Networks
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Altera Corporation
— — — — — — — — — — — — v — — v — v — — — — — — v — — v — v
PLL_3_C1
— — — — — — — — — — — — — v — — v — — — — — — — — v — — v —
PLL_3_C2
— — — — — — — — — — — — v — v — — — — — — — — — v — v — — —
PLL_3_C3
— — — — — — — — — — — — — v — v — — — — — — — — — v — v — —
PLL_3_C4
— — — — — — — — — — — — — — v — v v — — — — — — — — v — v v
PLL_4_C0
— — — — — — — — — — — — v — — v — v v — — v — v — — — — — —
PLL_4_C1
— — — — — — — — — — — — — v — — v — — v — — v — — — — — — —
PLL_4_C2
— — — — — — — — — — — — v — v — — — v — v — — — — — — — — —
PLL_4_C3
— — — — — — — — — — — — — v — v — — — v — v — — — — — — — —
PLL_4_C4
— — — — — — — — — — — — — — v — v v — — v — v v — — — — — —
PLL_5_C0
v — v — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_5_C1
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_5_C2
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_5_C3
— v — v — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_5_C4
— — v — v v — — — — — — — — — — — — — — — — — — — — — — — —
PLL_6_C0
v — — v — v — — — — — — — — — — — — — — — — — — — — — — — —
PLL_6_C1
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_6_C2
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_6_C3
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_6_C4
— v — — v — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_7_C0
(3)
— — — — — — v — — v — v — — — — — — — — — — — — — — — — — —
PLL_7_C1
(3)
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_7_C2
(3)
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_7_C3
(3)
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_7_C4
(3)
— — — — — — — v — — v — — — — — — — — — — — — — — — — — — —
5–5
Cyclone IV Device Handbook,
Volume 1
PLL_3_C0
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
October 2012
Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices (1),
GCLK Network Clock
Sources
(2)
(Part 3 of 4)
5–6
Cyclone IV Device Handbook,
Volume 1
Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices (1),
GCLK Networks
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
PLL_8_C0
(3)
— — — — — — v — v — — — — — — — — — — — — — — — — — — — — —
PLL_8_C1
(3)
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_8_C2
(3)
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
PLL_8_C3
(3)
— — — — — — — v — v — — — — — — — — — — — — — — — — — — — —
PLL_8_C4
(3)
— — — — — — — — v — v v — — — — — — — — — — — — — — — — — —
— — — — — — — — — — — — — — — — — — — — — — — — — v — — — —
DPCLK1
— — — — — — — — — — — — — — — — — — — — — — — — — — — v — —
DPCLK2
— — — — — — — — — — — — — — — — — — — — — — — — — — — — — v
DPCLK3
— — — — — — — — — — — — — — — — — — — — — — — — v — — — — —
DPCLK4
— — — — — — — — — — — — — — — — — — — — — — — — — — v — — —
DPCLK5
— — — — — — — — — — — — — — — — — — — — — — — — — — — — v —
DPCLK6
— — — — — — — — — — — — — — — — — v — — — — — — — — — — — —
DPCLK7
— — — — — — — — — — — — — — — v — — — — — — — — — — — — — —
DPCLK8
— — — — — — — — — — — — — v — — — — — — — — — — — — — — — —
DPCLK9
— — — — — — — — — — — — — — — — v — — — — — — — — — — — — —
DPCLK10
— — — — — — — — — — — — — — v — — — — — — — — — — — — — — —
DPCLK11
— — — — — — — — — — — — v — — — — — — — — — — — — — — — — —
DPCLK12
— — — — — — — — — — — — — — — — — — — — — — v — — — — — — —
October 2012
DPCLK13
— — — — — — — — — — — — — — — — — — — — v — — — — — — — — —
DPCLK14
— — — — — — — — — — — — — — — — — — v — — — — — — — — — — —
DPCLK15
— — — — — — — — — — — — — — — — — — — — — — — v — — — — — —
Altera Corporation
DPCLK16
— — — — — — — — — — — — — — — — — — — — — v — — — — — — — —
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
DPCLK0
(2)
(Part 4 of 4)
GCLK Networks
GCLK Network Clock
Sources
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Altera Corporation
— — — — — — — — — — — — — — — — — — — v — — — — — — — — — —
DPCLK17
Notes to Table 5–2:
(1) EP4CGX30 information in this table refers to only EP4CGX30 device in F484 package.
(2) PLL_1, PLL_2, PLL_3, and PLL_4 are general purpose PLLs while PLL_5, PLL_6, PLL_7, and PLL_8 are multipurpose PLLs.
(3) PLL_7 and PLL_8 are not available in EP4CXGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices in F484 package.
Table 5–3. GCLK Network Connections for Cyclone IV E Devices (1) (Part 1 of 3)
GCLK Network Clock
Sources
GCLK Networks
0
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15
16
17
18 19
CLK1
— v v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLK2/DIFFCLK_1p
— v —
v v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLK3/DIFFCLK_1n
v —
—
v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLK4/DIFFCLK_2p
—
—
—
—
—
v — v —
v —
—
—
—
—
—
—
—
—
—
CLK5/DIFFCLK_2n
—
—
—
—
—
— v v —
—
—
—
—
—
—
—
—
—
—
—
CLK6/DIFFCLK_3p
—
—
—
—
—
— v —
v v —
—
—
—
—
—
—
—
—
—
CLK7/DIFFCLK_3n
—
—
—
—
—
v —
— v —
—
—
—
—
—
—
—
—
—
v — v —
—
—
—
—
—
—
—
—
—
v v —
—
—
—
—
—
—
—
—
—
CLK8/DIFFCLK_5n
(2)
—
—
—
—
—
—
—
—
—
— v —
CLK9/DIFFCLK_5p
(2)
—
—
—
—
—
—
—
—
—
—
— v v —
—
—
—
—
—
—
—
—
—
—
— v —
—
—
—
—
—
—
—
—
—
— v —
—
v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
CLK10/DIFFCLK_4n
(2)
CLK11/DIFFCLK_4p
(2)
(2)
CLK13/DIFFCLK_7p
(2)
CLK14/DIFFCLK_6n
(2)
—
v — v
—
v v
5–7
Cyclone IV Device Handbook,
Volume 1
CLK12/DIFFCLK_7n
—
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
October 2012
Table 5–2. GCLK Network Connections for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 Devices (1),
GCLK Network Clock
Sources
CLK15/DIFFCLK_6p
(2)
5–8
Cyclone IV Device Handbook,
Volume 1
Table 5–3. GCLK Network Connections for Cyclone IV E Devices (1) (Part 2 of 3)
GCLK Networks
0
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v —
— v —
—
v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLL_1_C0
(3)
v —
PLL_1_C1
(3)
— v —
PLL_1_C2
(3)
v —
PLL_1_C3
(3)
— v —
PLL_1_C4
(3)
—
PLL_2_C0
(3)
PLL_2_C1
(3)
PLL_2_C2
(3)
PLL_2_C3
(3)
PLL_2_C4
(3)
v —
16 17
18
19
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v — v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
— v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
—
—
—
—
—
—
—
—
—
—
—
—
—
— v — v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLL_3_C0
—
—
—
—
PLL_3_C1
—
—
—
PLL_3_C2
—
—
PLL_3_C3
—
PLL_3_C4
—
v —
—
—
—
v — v —
—
—
—
—
—
—
—
—
—
—
—
—
v — v —
—
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v —
— v —
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— v —
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v —
—
—
—
—
—
—
—
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—
—
—
—
—
—
—
—
—
—
PLL_4_C0
—
—
—
—
—
—
—
—
PLL_4_C1
—
—
—
—
—
—
—
PLL_4_C2
—
—
—
—
—
—
—
October 2012
PLL_4_C3
—
—
—
—
—
—
PLL_4_C4
—
—
—
—
—
DPCLK0
v —
—
—
Altera Corporation
DPCLK1
— v —
DPCLK7
v —
—
—
—
—
—
—
—
v — v —
—
—
—
—
—
—
—
—
v — v —
—
—
—
—
—
—
—
—
—
—
—
v —
—
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
—
—
v — v —
—
—
—
—
—
—
—
—
—
—
—
v — v —
—
—
—
—
—
—
—
—
—
—
—
— v —
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
v —
(4)
CDPCLK0, or
CDPCLK7
v —
(2), (5)
—
—
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
—
GCLK Network Clock
Sources
GCLK Networks
Altera Corporation
0
1
2
3
5
6
7
8
9
10
11
12
13 14
15
16
17
18 19
—
—
—
v v —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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—
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v —
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— v —
—
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—
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—
— v —
—
—
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—
—
—
—
—
—
—
—
—
—
— v v —
—
—
—
—
—
—
—
—
—
DPCLK8
—
—
—
—
—
—
—
—
—
— v —
—
—
—
—
—
—
—
—
DPCLK11
—
—
—
—
—
—
—
—
—
—
— v —
—
—
—
—
—
—
—
DPCLK9
—
—
—
—
—
—
—
—
—
—
—
—
v —
—
—
—
—
—
—
DPCLK10
—
—
—
—
—
—
—
—
—
—
—
—
—
v v —
—
—
—
—
DPCLK5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
—
—
—
DPCLK2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v —
—
—
DPCLK4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
v —
—
DPCLK3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DPCLK2
CDPCLK1, or
CDPCLK2
(2), (5)
DPCLK5
(4)
DPCLK7
(2)
DPCLK4
(4)
DPCLK6
(2)
DPCLK6
(4)
CDPCLK5, or
CDPCLK6
DPCLK3
(2), (5)
(4)
CDPCLK4, or
CDPCLK3
4
(4)
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
October 2012
Table 5–3. GCLK Network Connections for Cyclone IV E Devices (1) (Part 3 of 3)
(2), (5)
v v
(1)
(2)
(3)
(4)
(5)
EP4CE6 and EP4CE10 devices only have GCLK networks 0 to 9.
These pins apply to all Cyclone IV E devices except EP4CE6 and EP4CE10 devices.
EP4CE6 and EP4CE10 devices only have PLL_1 and PLL_2.
This pin applies only to EP4CE6 and EP4CE10 devices.
Only one of the two CDPCLK pins can feed the clock control block. You can use the other pin as a regular I/O pin.
5–9
Cyclone IV Device Handbook,
Volume 1
Notes to Table 5–3:
5–10
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
If you do not use dedicated clock pins to feed the GCLKs, you can use them as
general-purpose input pins to feed the logic array. However, when using them as
general-purpose input pins, they do not have support for an I/O register and must
use LE-based registers in place of an I/O register.
f For more information about how to connect the clock and PLL pins, refer to the
Cyclone IV Device Family Pin Connection Guidelines.
Clock Control Block
The clock control block drives the GCLKs. Clock control blocks are located on each
side of the device, close to the dedicated clock input pins. GCLKs are optimized for
minimum clock skew and delay.
Table 5–4 lists the sources that can feed the clock control block, which in turn feeds the
GCLKs.
Table 5–4. Clock Control Block Inputs
Input
Description
Dedicated clock inputs
Dedicated clock input pins can drive clocks or global signals, such as
synchronous and asynchronous clears, presets, or clock enables onto
given GCLKs.
Dual -purpose clock
(DPCLK and CDPCLK)
I/O input
DPCLK and CDPCLK I/O pins are bidirectional dual function pins that
are used for high fan-out control signals, such as protocol signals,
TRDY and IRDY signals for PCI, via the GCLK. Clock control blocks
that have inputs driven by dual-purpose clock I/O pins are not able to
drive PLL inputs.
PLL outputs
PLL counter outputs can drive the GCLK.
Internal logic
You can drive the GCLK through logic array routing to enable internal
logic elements (LEs) to drive a high fan-out, low-skew signal path.
Clock control blocks that have inputs driven by internal logic are not
able to drive PLL inputs.
In Cyclone IV devices, dedicated clock input pins, PLL counter outputs, dual-purpose
clock I/O inputs, and internal logic can all feed the clock control block for each GCLK.
The output from the clock control block in turn feeds the corresponding GCLK. The
GCLK can drive the PLL input if the clock control block inputs are outputs of another
PLL or dedicated clock input pins. There are five or six clock control blocks on each
side of the device periphery—depending on device density; providing up to 30 clock
control blocks in each Cyclone IV GX device. The maximum number of clock control
blocks per Cyclone IV E device is 20. For the clock control block locations, refer to
Figure 5–2 on page 5–12, Figure 5–3 on page 5–13, and Figure 5–4 on page 5–14.
1
The clock control blocks on the left side of the Cyclone IV GX device do not support
any clock inputs.
The control block has two functions:
■
Dynamic GCLK clock source selection (not applicable for DPCLK, CDPCLK, and
internal logic input)
■
GCLK network power down (dynamic enable and disable)
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
5–11
Figure 5–1 shows the clock control block.
Figure 5–1. Clock Control Block
Clock Control Block
Internal Logic
Enable/
Disable
DPCLK
Static Clock Select (3)
Static Clock
Select (3)
C0
C1
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n] (6)
inclk1
inclk0
fIN
PLL
C2
C3
C4
CLKSWITCH (1)
Global
Clock
CLKSELECT[1..0] (2)
Internal Logic (5)
C0
C1
inclk1
inclk0
fIN
PLL
C2
(4)
Not applicable to
Cyclone IV E devices
CLKSWITCH (1)
C3
C4
Notes to Figure 5–1:
(1) The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The
output of the multiplexer is the input clock (fIN) for the PLL.
(2) The clkselect[1..0] signals are fed by internal logic and are used to dynamically select the clock source for the GCLK when the device is in
user mode.
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.
(4) Two out of four PLL clock outputs are selected from adjacent PLLs to drive into the clock control block.
(5) You can use internal logic to enable or disable the GCLK in user mode.
(6) CLK[n] is not available on the left side of Cyclone IV E devices.
Each PLL generates five clock outputs through the c[4..0] counters. Two of these
clocks can drive the GCLK through a clock control block, as shown in Figure 5–1.
f For more information about how to use the clock control block in the Quartus II
software, refer to the ALTCLKCTRL Megafunction User Guide.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–12
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
GCLK Network Clock Source Generation
Figure 5–2, Figure 5–3, and Figure 5–4 on page 5–14 show the Cyclone IV PLLs, clock
inputs, and clock control block location for different Cyclone IV device densities.
Figure 5–2. Clock Networks and Clock Control Block Locations in EP4CGX15, EP4CGX22, and EP4CGX30 Devices (1),
DPCLK[13..12] (5)
(2)
DPCLK[11..10] (5)
CLK[11..8]
2
2
4
4
PLL_2
4
5
PLL_4 (4)
(6)
5
Clock
Control
Block (3)
4
5
5
GCLK[19..0]
20
Clock
Control
Block (3)
HSSI
DPCLK[9..8] (5)
2
20
Clock
Control
Block (3)
20
20
4
GCLK[19..0]
2
CLK[7..4]
DPCLK[7..6] (5)
4
5
5
Clock
Control
Block (3)
5
PLL_1
5
4
4
2
4
(6)
PLL_3
2
CLK[15..12]
DPCLK[3..2] (5)
DPCLK[5..4] (5)
Notes to Figure 5–2:
(1) The clock networks and clock control block locations apply to all EP4CGX15, EP4CGX22, and EP4CGX30 devices except EP4CGX30 device in F484
package.
(2) PLL_1 and PLL_2 are multipurpose PLLs while PLL_3 and PLL_4 are general purpose PLLs.
(3) There are five clock control blocks on each side.
(4) PLL_4 is only available in EP4CGX22 and EP4CGX30 devices in F324 package.
(5) The EP4CGX15 device has two DPCLK pins on three sides of the device: DPCLK2 and DPCLK5 on bottom side, DPCLK7 and DPCLK8 on the right
side, DPCLK10 and DPCLK13 on the top side of device.
(6) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
5–13
Figure 5–3. Clock Networks and Clock Control Block Locations in EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and
EP4CGX150 Devices (1), (2)
DPCLK[17..15]
3
4
PLL_8
(5)
(6)
(6)
3
4
4
4
PLL_2
4
5
HSSI
DPCLK[14..12]
CLKIO[11..8]
REFCLK[4,5]p/n (4)
PLL_4
(6)
5
Clock
Control
Block (3)
4
3
5
5
GCLK[29..0]
Clock
Control
Block (3)
(6)
PLL_7
(5)
2
PLL_6
3
30
Clock
Control
Block (3)
30
Clock
Control
Block (3)
2
(6)
30
30
4
3
GCLK[29..0]
DPCLK[11..9]
CLKIO[7..4]
DPCLK[8..6]
4
HSSI
5
3
5
Clock
Control
Block (3)
5
5
(6)
PLL_1
PLL_5
4
4
(6)
PLL_3
4
4
(6)
3
REFCLK[0,1]p/n (4)
4
3
CLKIO[15..12]
DPCLK[2..0]
DPCLK[5..3]
Notes to Figure 5–3:
(1) The clock networks and clock control block locations in this figure apply to only the EP4CGX30 device in F484 package and all EP4CGX50,
EP4CGX75, EP4CGX110, and EP4CGX150 devices.
(2) PLL_1, PLL_2, PLL_3, and PLL_4 are general purpose PLLs while PLL_5, PLL_6, PLL_7, and PLL_8 are multipurpose PLLs.
(3) There are 6 clock control blocks on the top, right and bottom sides of the device and 12 clock control blocks on the left side of the device.
(4) REFCLK[0,1]p/n and REFCLK[4,5]p/n can only drive the general purpose PLLs and multipurpose PLLs on the left side of the device. These
clock pins do not have access to the clock control blocks and GCLK networks. The REFCLK[4,5]p/n pins are not available in devices in F484
package.
(5) Not available for EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices in F484 package.
(6) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–14
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
Figure 5–4. Clock Networks and Clock Control Block Locations in Cyclone IV E Devices
DPCLK[11.10]
CDPCLK7
DPCLK[9..8]
CDPCLK6
CLK[11..8]
2
2
4
(3)
PLL_3
(4)
4
4
PLL_2
5
Clock
Control
Block (1)
CDPCLK0
(3)
(2)
CDPCLK5
(2)
2
4
4
5
2
GCLK[19..0]
DPCLK0
CLK[3..1]
DPCLK7
20
Clock
Control
Block (1)
3
20
Clock
Control
Block (1)
20
4
CLK[7..4]
20
DPCLK1
DPCLK6
GCLK[19..0]
2
4
5
2
Clock
Control
Block (1)
(2)
CDPCLK1
4
(2)
(3)
CDPCLK4
5
PLL_1
PLL_4
(4)
4
(3)
4
2
4
2
CDPCLK3
CDPCLK2
CLK[15..12]
DPCLK[3..2]
DPCLK[5..4]
Notes to Figure 5–4:
(1) There are five clock control blocks on each side.
(2) Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. You can use the other CDPCLK pins as
general-purpose I/O (GPIO) pins.
(3) Dedicated clock pins can feed into this PLL. However, these paths are not fully compensated.
(4) PLL_3 and PLL_4 are not available in EP4CE6 and EP4CE10 devices.
The inputs to the clock control blocks on each side of the Cyclone IV GX device must
be chosen from among the following clock sources:
■
Four clock input pins
■
Ten PLL counter outputs (five from each adjacent PLLs)
■
Two, four, or six DPCLK pins from the top, bottom, and right sides of the device
■
Five signals from internal logic
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
5–15
From the clock sources listed above, only two clock input pins, two out of four PLL
clock outputs (two clock outputs from either adjacent PLLs), one DPCLK pin, and one
source from internal logic can drive into any given clock control block, as shown in
Figure 5–1 on page 5–11.
Out of these six inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–5 shows a simplified version of the clock control blocks on each side of the
Cyclone IV GX device periphery.
Figure 5–5. Clock Control Blocks on Each Side of Cyclone IV GX Device
Clock Input Pins
PLL Outputs
DPCLK (1)
Internal Logic
4
10
2, 4, or 6
Clock
Control
Block
5 or 6 (2)
GCLK
5
Five or six clock control
blocks on each side
of the device
Notes to Figure 5–5:
(1) The EP4CGX15 device has two DPCLK pins; the EP4CGX22 and EP4CGX30 devices have four DPCLK pins; the
EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices have six DPCLK pins.
(2) Each clock control block in the EP4CGX15, EP4CGX22, and EP4CGX30 devices can drive five GCLK networks. Each
clock control block in the EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices can drive six GCLK
networks.
The inputs to the five clock control blocks on each side of the Cyclone IV E device
must be chosen from among the following clock sources:
■
Three or four clock input pins, depending on the specific device
■
Five PLL counter outputs
■
Two DPCLK pins and two CDPCLK pins from both the left and right sides and four
DPCLK pins from both the top and bottom
■
Five signals from internal logic
From the clock sources listed above, only two clock input pins, two PLL clock outputs,
one DPCLK or CDPCLK pin, and one source from internal logic can drive into any given
clock control block, as shown in Figure 5–1 on page 5–11.
Out of these six inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–16
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
Figure 5–6 shows a simplified version of the five clock control blocks on each side of
the Cyclone IV E device periphery.
Figure 5–6. Clock Control Blocks on Each Side of Cyclone IV E Device (1)
Clock Input Pins
PLL Outputs
CDPCLK
3 or 4
5
2
2 or 4
Clock
Control
Block
5
GCLK
DPCLK
Internal Logic
5
Five Clock Control
Blocks on Each Side
of the Device
Note to Figure 5–6:
(1) The left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins.
GCLK Network Power Down
You can disable a Cyclone IV device’s GCLK (power down) using both static and
dynamic approaches. In the static approach, configuration bits are set in the
configuration file generated by the Quartus II software, which automatically disables
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to
control clock enable or disable the GCLKs in Cyclone IV devices.
When a clock network is disabled, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. This function
is independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–1 on page 5–11.
You can set the input clock sources and the clkena signals for the GCLK multiplexers
through the Quartus II software using the ALTCLKCTRL megafunction.
f For more information, refer to the ALTCLKCTRL Megafunction User Guide.
clkena Signals
Cyclone IV devices support clkena signals at the GCLK network level. This allows
you to gate-off the clock even when a PLL is used. Upon re-enabling the output clock,
the PLL does not need a resynchronization or re-lock period because the circuit gates
off the clock at the clock network level. In addition, the PLL can remain locked
independent of the clkena signals because the loop-related counters are not affected.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
5–17
Figure 5–7 shows how to implement the clkena signal with a single register.
Figure 5–7. clkena Implementation
clkena
D
Q
clkena_out
clkin
clk_out
1
The clkena circuitry controlling the output C0 of the PLL to an output pin is
implemented with two registers instead of a single register, as shown in Figure 5–7.
Figure 5–8 shows the waveform example for a clock output enable. The clkena signal
is sampled on the falling edge of the clock (clkin).
1
This feature is useful for applications that require low power or sleep mode.
Figure 5–8. clkena Implementation: Output Enable
clkin
clkena
clk_out
The clkena signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during PLL resynchronization.
Altera recommends using the clkena signals when switching the clock source to the
PLLs or the GCLK. The recommended sequence is:
1. Disable the primary output clock by de-asserting the clkena signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control
block.
3. Allow some clock cycles of the secondary clock to pass before reasserting the
clkena signal. The exact number of clock cycles you must wait before enabling the
secondary clock is design-dependent. You can build custom logic to ensure
glitch-free transition when switching between different clock sources.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–18
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLLs in Cyclone IV Devices
PLLs in Cyclone IV Devices
Cyclone IV GX devices offer two variations of PLLs: general purpose PLLs and
multipurpose PLLs. Cyclone IV E devices only have the general purpose PLLs.
The general purpose PLLs are used for general-purpose applications in the FPGA
fabric and periphery such as external memory interfaces. The multipurpose PLLs are
used for clocking the transceiver blocks. When the multipurpose PLLs are not used
for transceiver clocking, they can be used for general-purpose clocking.
f For more details about the multipurpose PLLs used for transceiver clocking, refer to
the Cyclone IV Transceivers chapter.
Cyclone IV GX devices contain up to eight general purpose PLLs and multipurpose
PLLs while Cyclone IV E devices have up to four general purpose PLLs that provide
robust clock management and synthesis for device clock management, external
system clock management, and high-speed I/O interfaces.
f For more information about the number of general purpose PLLs and multipurpose
PLLs in each device density, refer to the Cyclone IV Device Family Overview chapter.
1
The general I/O pins cannot drive the PLL clock input pins.
Table 5–5 lists the features available in Cyclone IV GX PLLs.
Table 5–5. Cyclone IV GX PLL Features (Part 1 of 2)
Availability
General Purpose PLLs
Features
PLL_1
PLL_2
(1), (10)
(1), (10)
PLL_
3 (2)
Multipurpose PLLs
PLL_
4 (3)
PLL_1 PLL_2
(4)
C (output counters)
(4)
PLL_5
PLL_6
(1), (10)
(1), (10)
PLL_7 PLL_8
(1)
(1)
5
M, N, C counter sizes
(5)
1 to 512
Dedicated clock outputs
1 single-ended or 1 differential pair
12 single-ended or 6 differential pairs (6)
and 4 differential pairs (7)
Clock input pins
Spread-spectrum input clock
tracking
v
PLL cascading
(8)
Through GCLK
Source-Synchronous Mode
v
v
v
v
v
v
v
—
—
v
No Compensation Mode
v
v
v
v
v
v
v
v
v
v
Normal Mode
v
v
v
v
v
v
v
—
—
v
Zero Delay Buffer Mode
v
v
v
v
v
v
v
—
—
v
Deterministic Latency
Compensation Mode
v
v
—
—
v
v
v
v
v
v
Phase shift resolution
(9)
Down to 96 ps increments
Programmable duty cycle
v
Output counter cascading
v
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLLs in Cyclone IV Devices
5–19
Table 5–5. Cyclone IV GX PLL Features (Part 2 of 2)
Availability
General Purpose PLLs
Features
PLL_1
PLL_2
(1), (10)
(1), (10)
PLL_
3 (2)
Multipurpose PLLs
PLL_
4 (3)
PLL_1 PLL_2
(4)
(4)
Input clock switchover
v
User mode reconfiguration
v
Loss of lock detection
v
PLL drives TX Serial Clock, TX Load
Enable, and TX Parallel Clock
v
v
VCO output drives RX clock data
recovery (CDR) clock
—
PLL_5
PLL_6
(1), (10)
(1), (10)
v
v
(1)
(1)
v
—
v
—
PLL drives FREF for ppm detect
PLL_7 PLL_8
—
v
—
Notes to Table 5–5:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
This is only applicable to EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices in F672 and F896 package.
This is applicable to all Cyclone IV devices.
This is applicable to all Cyclone IV devices except EP4CGX15 devices in all packages, EP4CGX22, and EP4CGX30 devices in F169 package.
This is only applicable to EP4CGX15, EP4CGX22, and all EP4CGX30 devices except EP4CGX30 in the F484 package..
C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a non-50% duty cycle, the
post -scale counters range from 1 through 256.
These clock pins can access the GCLK networks.
These clock pins are only available in EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices and cannot access the GCLK networks.
CLK[17,19,20,21]p can be used as single-ended clock input pins.
Only applicable if the input clock jitter is in the input jitter tolerance specifications.
The smallest phase shift is determined by the voltage -controlled oscillator (VCO) period divided by eight. For degree increments, Cyclone IV GX
devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and
divide parameters.
This is applicable to the EP4CGX30, EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices in F484 package.
Table 5–6 lists the features available in Cyclone IV E PLLs.
Table 5–6. Cyclone IV E PLL Features (Part 1 of 2)
Hardware Features
C (output counters)
M, N, C counter sizes
5
1 to 512
(1)
Dedicated clock outputs
1 single-ended or 1 differential pair
Clock input pins
4 single-ended or 2 differential pairs
Spread-spectrum input clock tracking
PLL cascading
Compensation modes
Phase shift resolution
October 2012
Availability
v
(2)
Through GCLK
Source-Synchronous Mode, No Compensation
Mode, Normal Mode, and Zero Delay Buffer Mode
Down to 96-ps increments
Programmable duty cycle
v
Output counter cascading
v
Input clock switchover
v
User mode reconfiguration
v
Altera Corporation
(3)
Cyclone IV Device Handbook,
Volume 1
5–20
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
Table 5–6. Cyclone IV E PLL Features (Part 2 of 2)
Hardware Features
Availability
v
Loss of lock detection
Notes to Table 5–6:
(1) C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a
non-50% duty cycle, the post-scale counters range from 1 through 256.
(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications.
(3) The smallest phase shift is determined by the VCO period divided by eight. For degree increments, Cyclone IV E
devices can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible
depending on the frequency and divide parameters.
Cyclone IV PLL Hardware Overview
This section gives a hardware overview of the Cyclone IV PLL.
Figure 5–9 shows a simplified block diagram of the major components of the PLL of
Cyclone IV GX devices.
Figure 5–9. Cyclone IV GX PLL Block Diagram (1)
To RX CDR clocks
(MPLLs only)
lock
FREF for ppm detect
(MPLLs, GPLL1, and GPLL2 only)
LOCK
circuit
÷2, ÷4
÷C0
8
Clock inputs
from pins
4 (2)
GCLK (4)
inclk0
Clock
Switchover
inclk1
Block
÷n
clkswitch
clkbad0
clkbad1
activeclock
PFD
CP
LF
VCO
8
÷2 (3)
GCLKs (5)
8
÷C1
÷C2
VCO
Range
Detector
÷C3
VCOOVRR
VCOUNDR
÷C4
External clock output
PLL
output
mux
TX serial clock (MPLLs,
GPLL1, and GPLL2 only) (6)
TX load enable (MPLLs,
GPLL1, and GPLL2 only) (7)
TX parallel clock (MPLLs ,
GPLL1, and GPLL2only) (8)
pfdena
÷M
no compensation;
ZDB mode
source-synchronous;
normal mode
GCLK networks
Notes to Figure 5–9:
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) There are additional 4 pairs of dedicated differential clock inputs in EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150 devices that can only
drive general purpose PLLs and multipurpose PLLs on the left side of the device. CLK[19..16] can access PLL_2, PLL_6, PLL_7, and PLL_8
while CLK[23..20] can access PLL_1, PLL_5, PLL_6, and PLL_7. For the location of these clock input pins, refer to Figure 5–3 on page 5–13.
(3) This is the VCO post -scale counter K.
(4) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
(5) For the general purpose PLL and multipurpose PLL counter outputs connectivity to the GCLKs, refer to Table 5–1 on page 5–2 and Table 5–2 on
page 5–4.
(6) Only the CI output counter can drive the TX serial clock.
(7) Only the C2 output counter can drive the TX load enable.
(8) Only the C3 output counter can drive the TX parallel clock.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
5–21
Figure 5–10 shows a simplified block diagram of the major components of the PLL of
Cyclone IV E devices.
Figure 5–10. Cyclone IV E PLL Block Diagram (1)
lock
LOCK
circuit
÷C0
GCLKs
4
Clock inputs
from pins
÷n
inclk0
Clock
Switchover
inclk1
Block
GCLK (3)
clkswitch
clkbad0
clkbad1
activeclock
PFD
CP
LF
VCO
8
÷2 (2)
÷C1
8
÷C2
VCO
Range
Detector
÷C3
VCOOVRR
External clock output
PLL
output
mux
÷C4
VCOUNDR
pfdena
÷M
no compensation;
ZDB mode
source-synchronous;
normal mode
GCLK networks
Notes to Figure 5–10:
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
1
The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the fVCO specification specified in the Cyclone IV Device Datasheet chapter.
External Clock Outputs
Each PLL of Cyclone IV devices supports one single-ended clock output or one
differential clock output. Only the C0 output counter can feed the dedicated external
clock outputs, as shown in Figure 5–11, without going through the GCLK. Other
output counters can feed other I/O pins through the GCLK.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–22
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
Figure 5–11 shows the external clock outputs for PLLs.
Figure 5–11. External Clock Outputs for PLLs
C0
C1
C2
PLL#
C3
C4
clkena 0 (1)
clkena 1 (1)
PLL#_CLKOUTp (2)
PLL#_CLKOUTn (2)
Notes to Figure 5–11:
(1) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
(2) PLL#_CLKOUTp and PLL#_CLKOUTn pins are dual-purpose I/O pins that you can use as one single-ended clock
output or one differential clock output. When using both pins as single-ended I/Os, one of them can be the clock
output while the other pin is configured as a regular user I/O.
Each pin of a differential output pair is 180° out of phase. The Quartus II software
places the NOT gate in your design into the I/O element to implement 180° phase
with respect to the other pin in the pair. The clock output pin pairs support the same
I/O standards as standard output pins.
f To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the Cyclone IV Device I/O Features chapter.
Cyclone IV PLLs can drive out to any regular I/O pin through the GCLK. You can also
use the external clock output pins as GPIO pins if external PLL clocking is not
required.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Feedback Modes
5–23
Clock Feedback Modes
Cyclone IV PLLs support up to five different clock feedback modes. Each mode
allows clock multiplication and division, phase shifting, and programmable duty
cycle. For the supported feedback modes, refer to Table 5–5 on page 5–18 for
Cyclone IV GX PLLs and Table 5–6 on page 5–19 for Cyclone IV E PLLs.
1
Input and output delays are fully compensated by the PLL only if you are using the
dedicated clock input pins associated with a given PLL as the clock sources.
When driving the PLL using the GCLK network, the input and output delays may not
be fully compensated in the Quartus II software.
Source-Synchronous Mode
If the data and clock arrive at the same time at the input pins, the phase relationship
between the data and clock remains the same at the data and clock ports of any I/O
element input register.
Figure 5–12 shows an example waveform of the data and clock in this mode. Use this
mode for source-synchronous data transfers. Data and clock signals at the I/O
element experience similar buffer delays as long as the same I/O standard is used.
Figure 5–12. Phase Relationship Between Data and Clock in Source-Synchronous Mode
Data pin
PLL reference
clock at input pin
Data at register
Clock at register
Source-synchronous mode compensates for delay of the clock network used,
including any difference in the delay between the following two paths:
1
October 2012
■
Data pin to I/O element register input
■
Clock input pin to the PLL phase frequency detector (PFD) input
Set the input pin to the register delay chain in the I/O element to zero in the
Quartus II software for all data pins clocked by a source-synchronous mode PLL.
Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II
software.
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Feedback Modes
No Compensation Mode
In no compensation mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because clock feedback into the PFD does not pass
through as much circuitry. Both the PLL internal and external clock outputs are phase
shifted with respect to the PLL clock input.
Figure 5–13 shows a waveform example of the phase relationship of the PLL clock in
this mode.
Figure 5–13. Phase Relationship Between PLL Clocks in No Compensation Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
(1), (2)
External PLL Clock
Outputs (2)
Notes to Figure 5–13:
(1) Internal clocks fed by the PLL are phase -aligned to each other.
(2) The PLL clock outputs can lead or lag the PLL input clocks.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software timing analyzer reports any phase difference between
the two. In normal mode, the PLL fully compensates the delay introduced by the
GCLK network.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Feedback Modes
5–25
Figure 5–14 shows a waveform example of the phase relationship of the PLL clocks in
this mode.
Figure 5–14. Phase Relationship Between PLL Clocks in Normal Mode
Phase Aligned
PLL Reference
Clock at the Input pin
PLL Clock at the
Register Clock Port
External PLL Clock
Outputs (1)
Note to Figure 5–14:
(1) The external clock output can lead or lag the PLL internal clock signals.
Zero Delay Buffer Mode
In zero delay buffer (ZDB) mode, the external clock output pin is phase-aligned with
the clock input pin for zero delay through the device. When using this mode, use the
same I/O standard on the input clock and output clocks to guarantee clock alignment
at the input and output pins.
Figure 5–15 shows an example waveform of the phase relationship of the PLL clocks
in ZDB mode.
Figure 5–15. Phase Relationship Between PLL Clocks in ZDB Mode
Phase Aligned
PLL Reference Clock
at the Input Pin
PLL Clock
at the Register Clock Port
External PLL Clock Output
at the Output Pin
October 2012
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Cyclone IV Device Handbook,
Volume 1
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Hardware Features
Deterministic Latency Compensation Mode
The deterministic latency mode compensates for the delay of the multipurpose PLLs
through the clock network and serializer in Common Public Radio Interface (CPRI)
applications. In this mode, the PLL PFD feedback path compensates the latency
uncertainty in Tx dataout and Tx clkout paths relative to the reference clock.
Hardware Features
Cyclone IV PLLs support several features for general-purpose clock management.
This section discusses clock multiplication and division implementation,
phase shifting implementations, and programmable duty cycles.
Clock Multiplication and Division
Each Cyclone IV PLL provides clock synthesis for PLL output ports using
M/(N*post-scale counter) scaling factors. The input clock is divided by a pre-scale
factor, N, and is then multiplied by the M feedback factor. The control loop drives the
VCO to match fIN (M/N). Each output port has a unique post-scale counter that
divides down the high-frequency VCO. For multiple PLL outputs with different
frequencies, the VCO value is the least common multiple of the output frequencies
that meets its frequency specifications. For example, if output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz in the VCO range). Then, the post-scale
counters scale down the VCO frequency for each output port.
There is one pre-scale counter, N, and one multiply counter, M, per PLL, with a range
of 1 to 512 for both M and N. The N counter does not use duty cycle control because
the purpose of this counter is only to calculate frequency division. There are five
generic post-scale counters per PLL that can feed GCLKs or external clock outputs.
These post-scale counters range from 1 to 512 with a 50% duty cycle setting. The
post-scale counters range from 1 to 256 with any non-50% duty cycle setting. The sum
of the high/low count values chosen for a design selects the divide value for a given
counter.
The Quartus II software automatically chooses the appropriate scaling factors
according to the input frequency, multiplication, and division values entered into the
ALTPLL megafunction.
1
Phase alignment between output counters is determined using the tPLL_PSERR
specification.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Hardware Features
5–27
Post-Scale Counter Cascading
PLLs of Cyclone IV devices support post-scale counter cascading to create counters
larger than 512. This is implemented by feeding the output of one C counter into the
input of the next C counter, as shown in Figure 5–16.
Figure 5–16. Counter Cascading
VCO Output
VCO Output
VCO Output
C0
C1
C2
VCO Output
C3
VCO Output
C4
VCO Output
When cascading counters to implement a larger division of the high-frequency VCO
clock, the cascaded counters behave as one counter with the product of the individual
counter settings.
For example, if C0 = 4 and C1 = 2, the cascaded value is C0 × C1 = 8.
1
Post-scale counter cascading is automatically set by the Quartus II software in the
configuration file. Post-scale counter cascading cannot be performed using the PLL
reconfiguration.
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable
duty cycle. This feature is supported on the PLL post-scale counters. You can achieve
the duty cycle setting by a low and high time count setting for the post-scale counters.
The Quartus II software uses the frequency input and the required multiply or divide
rate to determine the duty cycle choices. The post-scale counter value determines the
precision of the duty cycle. The precision is defined by 50% divided by the post-scale
counter value. For example, if the C0 counter is 10, steps of 5% are possible for duty
cycle choices between 5 to 90%.
Combining the programmable duty cycle with programmable phase shift allows the
generation of precise non-overlapping clocks.
PLL Control Signals
You can use the pfdena, areset, and locked signals to observe and control the PLL
operation and resynchronization.
f For more information about the PLL control signals, refer to the ALTPLL Megafunction
User Guide.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–28
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Hardware Features
Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops running.
Your design can automatically perform clock switchover when the clock is no longer
toggling, or based on the user control signal, clkswitch.
Automatic Clock Switchover
PLLs of Cyclone IV devices support a fully configurable clock switchover capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also sends
out three status signals—clkbad0, clkbad1, and activeclock—from the PLL to
implement a custom switchover circuit. You can select a clock source at the backup
clock by connecting it to the inclk1 port of the PLL in your design.
Figure 5–17 shows the block diagram of the switchover circuit built into the PLL.
Figure 5–17. Automatic Clock Switchover Circuit
clkbad0
clkbad1
activeclock
Switchover
State
Machine
Clock
Sense
clksw
clkswitch
(provides manual
switchover support)
inclk0
n Counter
inclk1
muxout
PFD
refclk
fbclk
There are two ways to use the clock switchover feature:
■
Use the switchover circuitry for switching from inclk0 to inclk1 running at the
same frequency. For example, in applications that require a redundant clock with
the same frequency as the reference clock, the switchover state machine generates
a signal that controls the multiplexer select input shown in Figure 5–17. In this
case, inclk1 becomes the reference clock for the PLL. This automatic switchover
can switch back and forth between the inclk0 and inclk1 clocks any number of
times, when one of the two clocks fails and the other clock is available.
■
Use the clkswitch input for user- or system-controlled switch conditions. This is
possible for same-frequency switchover or to switch between inputs of different
frequencies. For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must
control the switchover because the automatic clock-sense circuitry cannot monitor
primary and secondary clock frequencies with a frequency difference of more than
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Hardware Features
5–29
20%. This feature is useful when clock sources can originate from multiple cards
on the backplane, requiring a system-controlled switchover between frequencies
of operation. Choose the secondary clock frequency so the VCO operates in the
recommended frequency range. Also, set the M, N, and C counters accordingly to
keep the VCO operating frequency in the recommended range.
Figure 5–18 shows a waveform example of the switchover feature when using
automatic loss of clock detection. Here, the inclk0 signal remains low. After the
inclk0 signal remains low for approximately two clock cycles, the clock-sense
circuitry drives the clkbad0 signal high. Also, because the reference clock signal is not
toggling, the switchover state machine controls the multiplexer through the clksw
signal to switch to inclk1.
Figure 5–18. Automatic Switchover Upon Clock Loss Detection
(1)
inclk0
inclk1
(1)
muxout
clkbad0
clkbad1
activeclock
Note to Figure 5–18:
(1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure,
switchover is enabled on the falling edge of inclk1.
Manual Override
If you are using the automatic switchover, you must switch input clocks with the
manual override feature with the clkswitch input.
Figure 5–19 shows an example of a waveform illustrating the switchover feature
when controlled by clkswitch. In this case, both clock sources are functional and
inclk0 is selected as the reference clock. A low-to-high transition of the clkswitch
signal starts the switchover sequence. The clkswitch signal must be high for at least
three clock cycles (at least three of the longer clock period if inclk0 and inclk1 have
different frequencies). On the falling edge of inclk0, the reference clock of the counter,
muxout, is gated off to prevent any clock glitching. On the falling edge of inclk1, the
reference clock multiplexer switches from inclk0 to inclk1 as the PLL reference, and
the activeclock signal changes to indicate which clock is currently feeding the PLL.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Hardware Features
In this mode, the activeclock signal mirrors the clkswitch signal. As both blocks are
still functional during the manual switch, neither clkbad signals go high. Because the
switchover circuit is positive edge-sensitive, the falling edge of the clkswitch signal
does not cause the circuit to switch back from inclk1 to inclk0. When the clkswitch
signal goes high again, the process repeats. The clkswitch signal and the automatic
switch only works depending on the availability of the clock that is switched to. If the
clock is unavailable, the state machine waits until the clock is available.
1
When CLKSWITCH = 1, it overrides the automatic switch-over function. As long as
clkswitch signal is high, further switch-over action is blocked.
Figure 5–19. Clock Switchover Using the clkswitch Control
(1)
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
Note to Figure 5–19:
(1) Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start a manual clock switchover
event.
Manual Clock Switchover
PLLs of Cyclone IV devices support manual switchover, in which the clkswitch
signal controls whether inclk0 or inclk1 is the input clock to the PLL. The
characteristics of a manual switchover are similar to the manual override feature in an
automatic clock switchover, in which the switchover circuit is edge-sensitive. When
the clkswitch signal goes high, the switchover sequence starts. The falling edge of the
clkswitch signal does not cause the circuit to switch back to the previous input clock.
f For more information about PLL software support in the Quartus II software, refer to
the ALTPLL Megafunction User Guide.
Guidelines
Use the following guidelines to design with clock switchover in PLLs:
■
Cyclone IV Device Handbook,
Volume 1
Clock loss detection and automatic clock switchover require the inclk0 and
inclk1 frequencies be within 20% of each other. Failing to meet this requirement
causes the clkbad0 and clkbad1 signals to function improperly.
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Hardware Features
5–31
■
When using manual clock switchover, the difference between inclk0 and inclk1
can be more than 20%. However, differences between the two clock sources
(frequency, phase, or both) can cause the PLL to lose lock. Resetting the PLL
ensures that the correct phase relationships are maintained between the input and
output clocks.
■
Both inclk0 and inclk1 must be running when the clkswitch signal goes high to
start the manual clock switchover event. Failing to meet this requirement causes
the clock switchover to malfunction.
■
Applications that require a clock switchover feature and a small frequency drift
must use a low-bandwidth PLL. When referencing input clock changes, the
low-bandwidth PLL reacts slower than a high-bandwidth PLL. When the
switchover happens, the low-bandwidth PLL propagates the stopping of the clock
to the output slower than the high-bandwidth PLL. The low-bandwidth PLL
filters out jitter on the reference clock. However, the low-bandwidth PLL also
increases lock time.
■
After a switchover occurs, there may be a finite resynchronization period for the
PLL to lock onto a new clock. The exact amount of time it takes for the PLL to
re-lock is dependent on the PLL configuration.
■
If the phase relationship between the input clock to the PLL and output clock from
the PLL is important in your design, assert areset for 10 ns after performing a
clock switchover. Wait for the locked signal (or gated lock) to go high before
re-enabling the output clocks from the PLL.
■
Figure 5–20 shows how the VCO frequency gradually decreases when the primary
clock is lost and then increases as the VCO locks on to the secondary clock. After
the VCO locks on to the secondary clock, some overshoot can occur (an
over-frequency condition) in the VCO frequency.
Figure 5–20. VCO Switchover Operating Frequency
Primary Clock Stops Running
Frequency Overshoot
Switchover Occurs
VCO Tracks Secondary Clock
Fvco
■
October 2012
Disable the system during switchover if the system is not tolerant to frequency
variations during the PLL resynchronization period. You can use the clkbad0 and
clkbad1 status signals to turn off the PFD (pfdena = 0) so the VCO maintains its
last frequency. You can also use the switchover state machine to switch over to the
secondary clock. Upon enabling the PFD, output clock enable signals (clkena) can
disable clock outputs during the switchover and resynchronization period. After
the lock indication is stable, the system can re-enable the output clock or clocks.
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Programmable Bandwidth
Programmable Bandwidth
The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its
associated jitter. PLLs of Cyclone IV devices provide advanced control of the PLL
bandwidth using the programmable characteristics of the PLL loop, including loop
filter and charge pump. The closed-loop gain 3-dB frequency in the PLL determines
the PLL bandwidth. The bandwidth is approximately the unity gain point for open
loop PLL response.
Phase Shift Implementation
Phase shift is used to implement a robust solution for clock delays in Cyclone IV
devices. Phase shift is implemented with a combination of the VCO phase output and
the counter starting time. The VCO phase output and counter starting time are the
most accurate methods of inserting delays, because they are based only on counter
settings that are independent of process, voltage, and temperature.
You can phase shift the output clocks from the PLLs of Cyclone IV devices in one of
two ways:
■
Fine resolution using VCO phase taps
■
Coarse resolution using counter starting time
Fine resolution phase shifts are implemented by allowing any of the output counters
(C[4..0]) or the M counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution.
Equation 5–1 shows the minimum delay time that you can insert using this method.
Equation 5–1. Fine Resolution Phase Shift
T VCO
1
N
 fine = -------------- = ---------------- = -------------------8
8f VCO
8Mf RE F
in which fR EF is the input reference clock frequency.
For example, if fREF is 100 MHz, N = 1, and M = 8, then fVCO = 800 MHz, and
fine = 156.25 ps. The PLL operating frequency defines this phase shift, a value that
depends on reference clock frequency and counter settings.
Coarse resolution phase shifts are implemented by delaying the start of the counters
for a predetermined number of counter clocks. Equation 5–2 shows the coarse phase
shift.
Equation 5–2. Coarse Resolution Phase Shift
 C – 1 N
C–1
 coarse = ------------- = ---------------------Mf RE F
f VCO
C is the count value set for the counter delay time (this is the initial setting in the PLL
usage section of the compilation report in the Quartus II software). If the initial value
is 1, C – 1 = 0° phase shift.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Cascading
5–33
Figure 5–21 shows an example of phase shift insertion using fine resolution through
VCO phase taps method. The eight phases from the VCO are shown and labeled for
reference. In this example, CLK0 is based on 0° phase from the VCO and has the C
value for the counter set to one. The CLK1 signal is divided by four, two VCO clocks
for high time and two VCO clocks for low time. CLK1 is based on the 135° phase tap
from the VCO and has the C value for the counter set to one. The CLK1 signal is also
divided by four. In this case, the two clocks are offset by 3 fine . CLK2 is based on the
0° phase from the VCO but has the C value for the counter set to three. This creates a
delay of two  coarse (two complete VCO periods).
Figure 5–21. Delay Insertion Using VCO Phase Output and Counter Delay Time
1/8 tVCO
tVCO
0
45
90
135
180
225
270
315
CLK0
td0-1
CLK1
td0-2
CLK2
You can use the coarse and fine phase shifts to implement clock delays in
Cyclone IV devices.
Cyclone IV devices support dynamic phase shifting of VCO phase taps only. The
phase shift is configurable for any number of times. Each phase shift takes about one
scanclk cycle, allowing you to implement large phase shifts quickly.
PLL Cascading
Cyclone IV devices allow cascading between general purpose PLLs and multipurpose
PLLs in normal or direct mode through the GCLK network. If your design cascades
PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the
destination (downstream) PLL must have a high-bandwidth setting.
October 2012
1
PLL_6 and PLL7 have upstream cascading capability only.
1
PLL cascading is not supported when used in transceiver applications.
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–34
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
PLL Reconfiguration
PLLs use several divide counters and different VCO phase taps to perform frequency
synthesis and phase shifts. In PLLs of Cyclone IV devices, you can reconfigure both
counter settings and phase shift the PLL output clock in real time. You can also change
the charge pump and loop filter components, which dynamically affects PLL
bandwidth. You can use these PLL components to update the output clock frequency,
PLL bandwidth, and phase shift in real time, without reconfiguring the entire FPGA.
The ability to reconfigure the PLL in real time is useful in applications that might
operate at multiple frequencies. It is also useful in prototyping environments,
allowing you to sweep PLL output frequencies and adjust the output clock phase
dynamically. For instance, a system generating test patterns is required to generate
and send patterns at 75 or 150 MHz, depending on the requirements of the device
under test. Reconfiguring PLL components in real time allows you to switch between
two such output frequencies in a few microseconds.
You can also use this feature to adjust clock-to-out (tCO ) delays in real time by
changing the PLL output clock phase shift. This approach eliminates the need to
regenerate a configuration file with the new PLL settings.
PLL Reconfiguration Hardware Implementation
The following PLL components are configurable in real time:
■
Pre-scale counter (N)
■
Feedback counter (M)
■
Post-scale output counters (C0–C4)
■
Dynamically adjust the charge pump current (ICP ) and loop filter components
(R, C) to facilitate on-the-fly reconfiguration of the PLL bandwidth
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
5–35
Figure 5–22 shows how to adjust PLL counter settings dynamically by shifting their
new settings into a serial shift register chain or scan chain. Serial data shifts to the scan
chain via the scandataport, and shift registers are clocked by scanclk. The maximum
scanclk frequency is 100 MHz. After shifting the last bit of data, asserting the
configupdate signal for at least one scanclk clock cycle synchronously updates the
PLL configuration bits with the data in the scan registers.
Figure 5–22. PLL Reconfiguration Scan Chain
FVCO
from M counter
from N counter
PFD
LF/K/CP
VCO
scandata
scanclkena
configupdate
inclk
/C4
/C3
/C2
/C1
/C0
/M
/N
scandataout
scandone
scanclk
1
The counter settings are updated synchronously to the clock frequency of the
individual counters. Therefore, not all counters update simultaneously.
To reconfigure the PLL counters, perform the following steps:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the
first bit of scandata (D0).
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
scanclk.
3. After all 144 bits have been scanned into the scan chain, the scanclkena signal is
de-asserted to prevent inadvertent shifting of bits in the scan chain.
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
counters with the contents of the scan chain.
5. The scandone signal goes high indicating that the PLL is being reconfigured. A
falling edge indicates that the PLL counters have been updated with new settings.
6. Reset the PLL using the areset signal if you make any changes to the M, N,
post-scale output C counters, or the ICP , R, C settings.
7. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–36
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Figure 5–23 shows a functional simulation of the PLL reconfiguration feature.
Figure 5–23. PLL Reconfiguration Scan Chain
scandata
D0 (LSB)
Dn (MSB)
scanclk
scanclkena
scandataout
D0_old
Dn_old
Dn
configupdate
scandone
areset
1
When reconfiguring the counter clock frequency, the corresponding counter phase
shift settings cannot be reconfigured using the same interface. You can reconfigure
phase shifts in real time using the dynamic phase shift reconfiguration interface. If
you reconfigure the counter frequency, but wish to keep the same non-zero phase shift
setting (for example, 90°) on the clock output, you must reconfigure the phase shift
after reconfiguring the counter clock frequency.
Post-Scale Counters (C0 to C4)
You can configure multiply or divide values and duty cycle of post-scale counters in
real time. Each counter has an 8-bit high time setting and an 8-bit low time setting.
The duty cycle is the ratio of output high or low time to the total cycle time, that is the
sum of the two. Additionally, these counters have two control bits, rbypass, for
bypassing the counter, and rselodd, to select the output clock duty cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by one.
When this bit is set to 0, the PLL computes the effective division of the VCO output
frequency based on the high and low time counters. For example, if the post-scale
divide factor is 10, the high and low count values are set to 5 and 5, to achieve a
50–50% duty cycle. The PLL implements this duty cycle by transitioning the output
clock from high-to-low on the rising edge of the VCO output clock. However, a 4 and
6 setting for the high and low count values, respectively, would produce an output
clock with a 40–60% duty cycle.
The rselodd bit indicates an odd divide factor for the VCO output frequency with a
50% duty cycle. For example, if the post-scale divide factor is three, the high and low
time count values are 2 and 1, respectively, to achieve this division. This implies a
67%–33% duty cycle. If you need a 50%–50% duty cycle, you must set the rselodd
control bit to 1 to achieve this duty cycle despite an odd division factor. The PLL
implements this duty cycle by transitioning the output clock from high-to-low on a
falling edge of the VCO output clock. When you set rselodd = 1, subtract 0.5 cycles
from the high time and add 0.5 cycles to the low time.
For example:
■
Cyclone IV Device Handbook,
Volume 1
High time count = 2 cycles
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
5–37
■
Low time count = 1 cycle
■
rselodd = 1 effectively equals:
■
High time count = 1.5 cycles
■
Low time count = 1.5 cycles
■
Duty cycle = (1.5/3)% high time count and (1.5/3)% low time count
Scan Chain Description
Cyclone IV PLLs have a 144-bit scan chain.
Table 5–7 lists the number of bits for each component of the PLL.
Table 5–7. Cyclone IV PLL Reprogramming Bits
Number of Bits
Block Name
Counter
C4
(1)
Other
16
C3
16
C2
16
C1
16
C0
16
Total
2
(2)
18
2
(2)
18
2
(2)
18
2
(2)
18
2
(2)
18
18
18
M
16
2
(2)
N
16
2
(2)
Charge Pump
9
0
9
(3)
9
0
9
Loop Filter
Total number of bits:
144
Notes to Table 5–7:
(1) LSB bit for C4 low-count value is the first bit shifted into the scan chain.
(2) These two control bits include rbypass, for bypassing the counter, and rselodd, to select the output clock duty
cycle.
(3) MSB bit for loop filter is the last bit shifted into the scan chain.
Figure 5–24 shows the scan chain order of the PLL components.
Figure 5–24. PLL Component Scan Chain Order
DATAIN
LF
MSB
DATAOUT
October 2012
Altera Corporation
CP
LSB
C4
N
M
C0
C3
C2
C1
Cyclone IV Device Handbook,
Volume 1
5–38
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Figure 5–25 shows the scan chain bit order sequence for one PLL post-scale counter in
PLLs of Cyclone IV devices.
Figure 5–25. Scan Chain Bit Order
DATAOUT
HB
HB
HB
HB
HB
HB
HB
HB
HB
HB
0
1
2
3
4
5
6
7
8
9
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
0
1
2
3
4
5
6
7
8
9
DATAIN
rbypass
rselodd
Charge Pump and Loop Filter
You can reconfigure the charge pump and loop filter settings to update the PLL
bandwidth in real time. Table 5–8 through Table 5–10 list the possible settings for
charge pump current (ICP), loop filter resistor (R), and capacitor (C) values for PLLs of
Cyclone IV devices.
Table 5–8. Charge Pump Bit Control
CP[2]
CP[1]
CP[0]
Setting (Decimal)
0
0
0
0
1
0
0
1
1
1
0
3
1
1
1
7
Table 5–9. Loop Filter Resistor Value Control
Cyclone IV Device Handbook,
Volume 1
LFR[4]
LFR[3]
LFR[2]
LFR[1]
LFR[0]
Setting
(Decimal)
0
0
0
0
0
0
0
0
0
1
1
3
0
0
1
0
0
4
0
1
0
0
0
8
1
0
0
0
0
16
1
0
0
1
1
19
1
0
1
0
0
20
1
1
0
0
0
24
1
1
0
1
1
27
1
1
1
0
0
28
1
1
1
1
0
30
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
5–39
Table 5–10. Loop Filter Control of High Frequency Capacitor
LFC[1]
LFC[0]
Setting (Decimal)
0
0
0
0
1
1
1
1
3
Bypassing a PLL Counter
Bypassing a PLL counter results in a divide (N, C0 to C4 counters) factor of one.
Table 5–11 lists the settings for bypassing the counters in PLLs of Cyclone IV devices.
Table 5–11. PLL Counter Settings
PLL Scan Chain Bits [0..8] Settings
Description
LSB
MSB
X
X
X
X
X
X
X
X
1
(1)
PLL counter bypassed
X
X
X
X
X
X
X
X
0
(1)
PLL counter not bypassed
Note to Table 5–11:
(1) Bypass bit.
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are then ignored.
Dynamic Phase Shifting
The dynamic phase shifting feature allows the output phase of individual PLL
outputs to be dynamically adjusted relative to each other and the reference clock
without sending serial data through the scan chain of the corresponding PLL. This
feature simplifies the interface and allows you to quickly adjust tCO delays by
changing output clock phase shift in real time. This is achieved by incrementing or
decrementing the VCO phase-tap selection to a given C counter or to the M counter.
The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active
during this phase reconfiguration process.
Table 5–12 lists the control signals that are used for dynamic phase shifting.
Table 5–12. Dynamic Phase Shifting Control Signals (Part 1 of 2)
Signal Name
Description
Source
Destination
phasecounterselect[2..0]
Counter Select. Three bits decoded to select
either the M or one of the C counters for
phase adjustment. One address map to
select all C counters. This signal is registered
in the PLL on the rising edge of scanclk.
Logic array or I/O
pins
PLL
reconfiguration
circuit
phaseupdown
Selects dynamic phase shift direction; 1= UP,
0 = DOWN. Signal is registered in the PLL on
the rising edge of scanclk.
Logic array or I/O
pins
PLL
reconfiguration
circuit
phasestep
Logic high enables dynamic phase shifting.
Logic array or I/O
pins
PLL
reconfiguration
circuit
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–40
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Table 5–12. Dynamic Phase Shifting Control Signals (Part 2 of 2)
Signal Name
Description
Source
Destination
scanclk
Free running clock from core used in
combination with phasestep to enable or
disable dynamic phase shifting. Shared with
scanclk for dynamic reconfiguration.
GCLK or I/O pins
phasedone
When asserted, it indicates to core logic that
the phase adjustment is complete and PLL is
ready to act on a possible second adjustment
pulse. Asserts based on internal PLL timing.
De-asserts on the rising edge of scanclk.
PLL reconfiguration Logic array or
circuit
I/O pins
PLL
reconfiguration
circuit
Table 5–13 lists the PLL counter selection based on the corresponding
PHASECOUNTERSELECT setting.
Table 5–13. Phase Counter Select Mapping
phasecounterselect
Selects
[2]
[1]
[0]
0
0
0
All Output Counters
0
0
1
M Counter
0
1
0
C0 Counter
0
1
1
C1 Counter
1
0
0
C2 Counter
1
0
1
C3 Counter
1
1
0
C4 Counter
To perform one dynamic phase-shift, follow these steps:
1. Set PHASEUPDOWN and PHASECOUNTERSELECT as required.
2. Assert PHASESTEP for at least two SCANCLK cycles. Each PHASESTEP pulse allows one
phase shift.
3. Deassert PHASESTEP after PHASEDONE goes low.
4. Wait for PHASEDONE to go high.
5. Repeat steps 1 through 4 as many times as required to perform multiple phaseshifts.
PHASEUPDOWN and PHASECOUNTERSELECT signals are synchronous to SCANCLK and must
meet the tsu and th requirements with respect to the SCANCLK edges.
1
You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180, in other words, a phase shift of 5 ns.
Cyclone IV Device Handbook,
Volume 1
October 2012
Altera Corporation
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Spread-Spectrum Clocking
5–41
Figure 5–26 shows the dynamic phase shifting waveform.
Figure 5–26. PLL Dynamic Phase Shift
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
a
b
c
d
PHASEDONE goes low
synchronous with SCANCLK
The PHASESTEP signal is latched on the negative edge of SCANCLK (a,c) and must remain
asserted for at least two SCANCLK cycles. Deassert PHASESTEP after PHASEDONE goes low.
On the second SCANCLK rising edge (b,d) after PHASESTEP is latched, the values of
PHASEUPDOWN and PHASECOUNTERSELECT are latched and the PLL starts dynamic
phase-shifting for the specified counters, and in the indicated direction. PHASEDONE is
deasserted synchronous to SCANCLK at the second rising edge (b,d) and remains low
until the PLL finishes dynamic phase-shifting. Depending on the VCO and SCANCLK
frequencies, PHASEDONE low time may be greater than or less than one SCANCLK cycle.
You can perform another dynamic phase-shift after the PHASEDONE signal goes from
low to high. Each PHASESTEP pulse enables one phase shift. PHASESTEP pulses must be
at least one SCANCLK cycle apart.
f For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager,
refer to the ALTPLL_RECONFIG Megafunction User Guide.
Spread-Spectrum Clocking
Cyclone IV devices can accept a spread-spectrum input with typical modulation
frequencies. However, the device cannot automatically detect that the input is a
spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the
input of the PLL. PLLs of Cyclone IV devices can track a spread-spectrum input clock
as long as it is in the input jitter tolerance specifications and the modulation frequency
of the input clock is below the PLL bandwidth, that is specified in the fitter report.
Cyclone IV devices cannot generate spread-spectrum signals internally.
PLL Specifications
f For information about PLL specifications, refer to the Cyclone IV Device Datasheet
chapter.
October 2012
Altera Corporation
Cyclone IV Device Handbook,
Volume 1
5–42
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Document Revision History
Document Revision History
Table 5–14 lists the revision history for this chapter.
Table 5–14. Document Revision History
Date
Version
October 2012
November 2011
December 2010
July 2010
February 2010
November 2009
Cyclone IV Device Handbook,
Volume 1
2.4
2.3
2.2
2.1
2.0
1.0
Changes
■
Updated “Manual Override” and “PLL Cascading” sections.
■
Updated Figure 5–9.
■
Updated the “Dynamic Phase Shifting” section.
■
Updated Figure 5–26.
■
Updated for the Quartus II software version 10.1 release.
■
Updated Figure 5–3 and Figure 5–10.
■
Updated “GCLK Network Clock Source Generation”, “PLLs in Cyclone IV Devices”,
and “Manual Override” sections.
■
Minor text edits.
■
Updated Figure 5–2, Figure 5–3, Figure 5–4, and Figure 5–10.
■
Updated Table 5–1, Table 5–2, and Table 5–5.
■
Updated “Clock Feedback Modes” section.
■
Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1
release.
■
Updated “Clock Networks” section.
■
Updated Table 5–1 and Table 5–2.
■
Added Table 5–3.
■
Updated Figure 5–2, Figure 5–3, and Figure 5–9.
■
Added Figure 5–4 and Figure 5–10.
Initial release.
October 2012
Altera Corporation