CS5101AN/D Secondary Side Post Regulator (SSPR) for Switching Power Supplies with Mulitple Outputs http://onsemi.com APPLICATION NOTE This application note describes the common post regulation methods used in power supply design and introduces the CS5101 Secondary Side Post Regulator Control IC. It also shows a detailed design example of a dual output, current mode control, forward converter using the CS3842A and CS5101 controllers. Introduction In Switch Mode Power Supplies (SMPS) a transformer provides isolation between the primary source and the secondary load(s). If the SMPS controller is located on the primary side of the transformer, the feedback voltage from the secondary is fed back to the primary side through another isolation barrier, usually an opto coupler. Tight output regulation is more difficult in multiple output power supplies. The following are the most popular techniques. 1.The Linear Regulator, Figure 1, is the simplest and the most popular for low current (3.0 A) applications. The major disadvantage of the linear regulator is its poor efficiency. 2.A Step–Down Buck Regulator, Figure 2, can be used as a post regulator. Efficiencies up to 90% can be achieved by using this method. This solution looks very attractive in the low and medium power range (3.0 A to 8.0 A). However, several additional high cost components are required, including, a power switch, inductor and capacitors. 3.A Magnetic Amplifier Post Regulator, Figure 3, offers high efficiency and tight regulation for output currents greater than 5.0 A . Its drawbacks include: the difficulty in implementing overcurrent protection, poor regulation characteristics at light or no load conditions and the cost of the high frequency (200 kHz) magnetic amplifier inductor. 4.A Secondary Side Post Regulator (SSPR), Figure 4, uses a semiconductor switch with either leading edge (delayed turn–on) or trailing edge (delayed turn–off) modulation. An SSPR provides excellent regulation, high efficiency, high frequency operation, lossless overcurrent protection and remote ON/OFF control. LO1 VSY VIN + CO1 Linear Regulator VO1 + CO2 LO2 VO2 P W M + CO3 VFB Figure 1. Linear Regulator Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 1 1 Publication Order Number: CS5101AN/D CS5101AN/D LO1 VSY DC/DC Regulator VIN + CO1 VO1 + CO2 LO2 VO2 P W M + CO3 VFB Figure 2. Switching Post Regulator MA LO1 VSY VO1 VIN + CO1 MA Control LOX VOX P W M + COX VFB Figure 3. MAGAMP LOX VSY VIN QX VOX + COX SSPR Control LO1 VO1 P W M + CO1 VFB Figure 4. SSPR http://onsemi.com 2 CS5101AN/D SSPR Operation An SSPR regulator allows the designer to build multiple output power supplies with each output individually controlled without any feedback to the primary side. The SSPR switch is connected in series with the secondary side rectifier and output inductor. In a forward converter topology using current mode control, the primary controller maintains a constant volt–second product. The primary side current waveforms for both leading edge and trailing edge operation are shown in Figure 5. There is a step change in the primary current when the SSPR turns on, or turns off. Trailing edge modulation will cause loop instability in current mode control using peak current sensing. This is not a problem with voltage mode control regulators. Leading edge modulation does not have this limitation. ÉÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ IPK SSPR Current Leading Edge SSPR threshold, the output stage is low and the external power switch (usually an N–FET) is off. The output stage is disabled until the VCC voltage and VREF are within specification. The switching cycle begins when the synchronization voltage at the SYNC pin exceeds 2.5 V. This synchronization signal is derived from the voltage on the secondary side of the transformer. The ramp capacitor connected to the RAMP pin charges towards 3.5 V. The capacitor voltage is compared to the buffered control voltage, VC by the PWM comparator C1. When the ramp capacitor voltage exceeds the VC voltage, the output of C1 goes high and turns on the external power switch connected to VG. As C1 goes high it also sets flip–flop F1 which latches the output. During the trailing edge of the pulse, the ramp capacitor is discharged. The output stage turns off only on the trailing edge of the synchronization pulse when the voltage at the SYNC and RAMP pins are below the thresholds of comparators C2 and C4 respectively. G2 resets the flip–flop F1. The error amplifier, EA, monitors the output voltage and compares it to an internal 2.0 V reference. The buffer amplifier inverts the error signal and applies it to the input of C1. The current sense amplifier, IS, monitors the output current. During normal operation the output of IS is high and the diode is reverse biased. When the overcurrent threshold is exceeded, the output goes low, the diode is forward biased and the current sense amplifier sinks current from the error amplifier. This pulls the error amplifier output low and shuts off the output stage through G3. Since all three pins of the differential amplifier are accessible, high side or low side current sensing is possible. The circuit is designed so that the current sense amplifier is guaranteed to sink more current than the error amplifier, EA, can source. The external power switch is driven by a grounded totem–pole output stage. The output stage remains off until the output of C1 goes high. Since the external power switch turns off on the trailing edge of the secondary pulse, lossless turn–off is achieved. If the output controlled by the SSPR is shut down or disabled while the main output is still operational, a DC voltage equal to a peak secondary voltage will build up at the drain of the power switch. The drain pin VD monitors this voltage and keeps the output stage off, even if the supply voltage, VCC, disappears. The output stage remains off as long as any abnormal conditions exist. If normal operating conditions are restored while there is no synchronization pulse, the controller will process the next available pulse. If normal operating conditions are restored during a pulse, the rest of the pulse is ignored and the controller will resume the normal operation at the rising edge of the next pulse. Trailing Edge SSPR Figure 5. Primary Switch Current Waveforms The CS5101 SSPR from ON Semiconductor Corporation is designed for leading edge modulation and is compatible with both voltage and current mode control. CS5101 Functional Pin Description Pin Symbol SYNC Function Frequency synchronization input. VCC Logic supply (8.0 V to 45 V). VREF 5.0 V output voltage reference. LGND Logic level ground (analog and digital ground tied). VFB Inverting input providing feedback through error amplifier. COMP Error amplifier output and compensation pin. RAMP Programmable ramp input. IS+ Noninverting input for current sense amplifier. IS– Inverting input for current sense amplifier. IS COMP PGND Compensation pin for current sense amplifier. Power ground. VG Gate drive for output stage. VC Collector for output power stage. VD DRAIN connection for external FET. AGND Analog ground. DGND Digital ground. A block diagram of the CS5101 SSPR is shown in Figure 6. When the voltage at the VCC pin is below the start–up http://onsemi.com 3 CS5101AN/D VCC VD VCC VC REF VREF 5.0 V OK + SLEEP – + UVL + – + – 8.0 V/7.0 V LGND Q1 VG Q2 0.7 V +– PGND IS COMP VCC 5.0 V VFB 5.0 V 24.6 k – EA 10 k + – BUF + 10 k + – 2.0 V VC + IS+ I = 200 µA 5.0 V + – 1.65 V Q3 5.0 V S LATCH Q + – 1.5 V + RAMP – 5.0 V – – + PWM + Q SYNC IS– + 2.4 V – 5.0 V COMP RAMP – IS 0.7 V +– R – VCC–OK + 5.0 V + Q4 G1 REF_OK – 5.0 V VCC + – 4.5 V/4.4 V + SYNC – G2 + – 2.5 V Figure 6. CS5101 Block Diagram LO If the RAMP pin voltage is pulled below 0.7 V, the controller goes into a sleep mode where the output is disabled and the quiescent current is reduced. 1 2 VO 3 Q IL + CO 4 Connecting the SSPR in a Circuit The SSPR can be used in a variety of topologies including both single and dual ended buck or flyback converters operating with current or voltage mode control. In each case, usually the N–FET power switch is connected in series with the forward diode as shown in Figure 7. Since the N–FET is connected between two diodes it is impossible to use a single package center–tap rectifier. The source voltage of the N–FET changes from the secondary side peak voltage to approximately –0.7 V (the flyback diode forward drop) so the user must create a floating gate drive. If it is not necessary to have a common ground connection between all outputs on the secondary side, the inductor can be connected on the ground side as shown in Figure 8. SSPR RTN 1 VSY VSY 0 Q 2 VDS 0 VLD 0 3 4 IL 0 VSY VO + VD IO Figure 7. Primary Switch Current Waveforms http://onsemi.com 4 CS5101AN/D VSYX 1 2 VOX QX LOX VSYX VOX QX + COX + COX SSPR 4 ILX SSPR RTN 3 LOX 1 VSYX VSYX VOX 0 Figure 11. Dual Ended SSPR 2 VDS VSY 0 VSYX QX VO + VD 3 VLOX 0 D1 VSY – VOX ILX + COX Q1 R1 4 VOX DX R2 IO 0 ILX T1 Figure 8. SSPR Connected in the Return In this configuration the source of the N–FET is effectively a DC voltage, equal to the output voltage VO. This makes the gate drive circuit for the FET simple and reliable. The VC and VCC voltages can be derived from the same point. Because the positive voltage transition across the inductor is clamped by the output voltage it may be necessary to generate the SYNC pulse from another secondary output. There are two ways to generate a negative output voltage. One way is simply to reverse the ground and output connections as is shown in Figure 9. The SSPR circuit is referenced to the negative output. LX C1 SSPR Figure 12. SSPR with Gate Drive Transformer Another method is shown in Figure 10. The SSPR gate drive circuit is referenced to ground. An additional feedback signal inversion is required in this case. With dual ended topologies such as a push–pull or bridge, only one power switch is required to control the output voltage. The output inductor can be connected in either the positive or return path. The SSPR should switch at twice the rate of the primary controller. For the high power application, when a single package center–tapped rectifier is required, SSPR power switch can be driven by the gate drive transformer as shown in Figure 12. LOX VSY QX COX + SSPR –VOX Figure 9. SSPR for Negative Output R3 SSPR VFB Design Example As an example, we show the design of a dual output current mode control forward converter. The 5.0 V output is controlled by the main loop with feedback connected to the primary side PWM controller (CS3842A). The second 3.3 V output is controlled by the CS5101. R1 VREF Q2 R4 VSYX QX Design Specifications COX + Input Voltage Range . . . . . . . . . . . . . . . . . . . 18 to 36 VDC Output Voltage, VO1 . . . . . . . . . . . . . . . . . . . . . . 5.0 VDC Output Voltage, VO2 . . . . . . . . . . . . . . . . . . . . . . 3.3 VDC Output Current, IO1 . . . . . . . . . . . . . . . . . . 0.2 to 3.0 ADC Output Current, IO2 . . . . . . . . . . . . . . . . . . 0.3 to 2.0 ADC R2 LOX RTN –VOX Figure 10. Ground Referenced Negative Output SSPR http://onsemi.com 5 CS5101AN/D Output Inductor Design We must maintain continuous mode operation at minimum load and maximum input voltage conditions. Switching Frequency . . . . . . . . . . . . . . . . . . . . . 100 kHz Line/Load Regulation at all outputs . . . . . . . . . . . . . 1.0% 1. Power Transformer Design 5.0 V Output Inductor, L1 To leave enough head room for SSPR operation at high line, assume the duty cycle at low line, DLL is 0.6. Voltage at the 5.0 V winding: IO5(MIN) = 0.25 A; DMIN = 0.293; fSW = 100 kHz; ∆I = 2.0 × IO(MIN) = 0.5 A. Rectifier diode forward drop VD = 0.75 @ 3.0 A. (MBR360) The output inductor is calculated with the following equation: VSY5 5.0 0.6 9.33 V 0.6 Transformer turns ratio: (V VD) tOFF(MAX) LMIN O I (5.0 0.75) (1.0 0.293) LMIN 81 H 100 k 0.5 V n SY 9.33 0.518 18 VPY Use TDK core PC40EER25.5 – Z. Minimum number of primary turns: Allowing for a 20% tolerance in the inductor, L1 = 100 µH. Use a T72–26 Powdered Iron Core from Micrometals. Winding data: 34T, #24AWG. V tON 8 NPY IN(MIN) 10 Bm Ae where: Bm = Flux Density, in Gauss; Ae = Effective core cross section area, in cm2; tON = Power switch on–time at low line; VIN(MIN) = Minimum input voltage. Rewriting this equation, in terms of duty cycle, D, and switching frequency, fSW,: 3.3 V Output Inductor, L2 IO3(MIN) = 0.3 A; ∆I = 0.6 A. Using the equation for output inductor, determine L2. LO3(MIN) L2 = 50 µH. Use a T80–26 Powdered Iron Core from Micrometals. Winding data: 42T, #24AWG. Use a 330 µF, 15 V Aluminum Electrolytic Capacitor with ESR = 0.12 Ω on both outputs. Ripple due to the ESR on the 5.0 V output: V DMAX 8 NPY IN(MIN) 10 fSW Bm Ae NPY (3.3 0.75) (1.0 0.293) 48 H 100 k 0.6 18 0.6 108 20 turns 100 k 1.2 k 0.448 Secondary turns for 5.0 V output: VO5 0.12 0.5 60 mVP–P NSY5 20 n 20 0.518 10.36 turns Ripple due to the ESR on the 3.3 V output: NSY5 = 11 T. Use the same number of turns for both the 3.3 V and 5.0 V outputs. The turns ratio of the power transformer NPY:NSY5:NSY3:NAUX is equal to 20:11:11:8. The transformer is reset with the clamp reset circuit comprising D8, R10, C18. At turn–off, the drain voltage of Q2 is clamped to a voltage equal to the input voltage plus the voltage across capacitor C18. Actual duty cycle at low line: VO3 0.12 0.6 72 mVP–P Because the regulator uses current mode control, the primary side peak current is sensed across the current sense resistor, R10. This primary side current is the combination of currents from both outputs. The effective slope of the current in the primary side is influenced by both output inductors. The outputs are reflected to the main output based on the turns ratio. The combined equivalent circuit is shown in Figure 13. Inductance and capacitance reflected from the 3.3 V output to the main output is given by: VO VD VIN(MIN) n (5.0 0.8) 20 DLL 0.586 18 11 DLL L LO3 O3 n2 C O3 CO3 n2 Duty cycle at high line: VIN(MIN) VIN(MAX) DHL 0.586 18 0.293 36 DHL DLL Voltage and current reflected from the 3.3 V output to the main output is given by: http://onsemi.com 6 CS5101AN/D The compensation voltage, VCOMP, is given by: V VO3 O3 n IO3 IO3 n VCOMP Reflected ESR is: ESRO3 LO5 mCOMP(SY) NSY R10 NPY ESRO3 n2 1.5 V LIO5 7.0 µs DO5 CO5 + L′O3 L′IO3 10 µs RLO5 ESR VSY – 3.0 µs Figure 15. CS3842A Oscillator Voltage VCOMP 0.104 11 0.25 14.3 10–3 Vs 20 ′ DO3 PWM controller oscillator slope (see Figure 15), ∆VOSC = 1.7 V; ∆tOSC = 7.0 µs: ′ CO3 R′LO3 ESR′ mOSC 1.7 0.243 Vs 7.0 R4 Main Loop Compensation Figure 16 shows the main components for loop compensation. In general, for peak current mode control, the following expressions apply: IL = KVC and VO = ILRL, where VC = ∆Ve (the error amplifier dynamic range). For CS3842A, VC = 2.5 V, and Figure 13. Secondary Side Normalized Current LOe VO5 COe 660 µF R11 mOSC 100 0.243 1.7 k mCOMP 14.3 10–3 RL 0.06 V VO K R L C 3.0 From Figure 16, Figure 14. Main Output Equivalent Circuit The turns ratio for the secondary windings is 1:1. Then, effective inductance: K NPY 1.0 NSY R10 Equivalent circuit for the output is shown in Figure 14. LOe = 37.5 µH; COe = 660 µF. The output power range is: L LO3 LOe O5 LO5 LO3 100 50 LOe 33.3 H 100 50 POMAX 5.0 3.0 3.3 2.0 21.6 W POMIN 5.0 0.25 1.25 W Effective capacitance: RLMAX = 20 Ω; RLMIN = 1.16 Ω. Sliding pole: COe CO3 CO5 330 330 660 F Slope Compensation Because the duty cycle exceeds 50% at low input voltage, slope compensation is required to avoid instability. Output inductor effective down slope, me is given by 1.0 fP 2.0RLCO 1.0 fPMIN 12 Hz 2.0 20 660 F V me I L 5.0 0.75 0.173 Vs t Le 33.3 H 1.0 208 Hz fPMAX 2.0 1.16 660 F Output capacitor ESR zero: The recommended slope compensation is one half of me. Due to the increased noise created by the SSPR at turn–on, the slope compensation should be increased to 0.6. 1.0 fZ 2.0(ESR)C mCOMP(SY) 0.7 me 0.104 Vs http://onsemi.com 7 O 1.0 4.02 kHz 2.0 0.06 660 F CS5101AN/D T1 IL L1 D2 V C N PY 3R10 N SY V O5 V C N PY R LO5 3R10 N SY VIN C10 + D3 11 T 20 T RLO5 ESR L2 D5 Q2 Q3 VO3 C11 + V e 3 CS3842A D4 11 T R11 C2 V C 3R CS RLO3 ESR SSPR ID R10 Figure 16. Main Loop Circuit Control to output gain (see Figure 16): 80 dVO N RL G PY dVC NSY 3.0 R10 60 GMODMAX Gain at high line: Gain (dB) 40 20 GHL 20 48.5 (33.7 dB) 11 3.0 0.25 Gain at low line: 0 –20 It is good practice to make the crossover frequency between fP (pole at high load) and fZESR (zero of output capacitor), i.e., fCO = 3.0 kHz Error amplifier gain needed to cross at 3.0 kHz: –40 –60 1 10 100 1000 1 × 104 1 × 105 1 × 106 Frequency (Hz) f G3.0 kHz GHL 20 log CO fPMIN G3.0 kHz 33.7 20 log 3.0 K 14.2 dB (5.13 times) 12 Figure 17. Main Loop Frequency Characteristics The loop crossover frequency is 3.0 kHz with an adequate phase margin. The error amplifier feedback resistor, R3, is equal to: SSPR Controlled Output Calculation The following data from the specification and the previous calculations are important for the design. Switching frequency: 100 kHz; Transfer turns ratio: NPY:NO5:NO3 = 20:11:11; Input voltage range: 18 to 36 VDC; Duty cycle range determined by the 5.0 V output, DMAX = 0.586, DMIN = 0.293; LO3 = 50 µH; CO3 = 330 µF; ESR = 0.12 Ω; R3 5.13 R1 5.13 4.99 k 25.5 k Pole to cancel the ESR zero: fPESR = fZESR = 4.02 kHz, then 1.0 1.5 nF 2.0 4.02 kHz 25.5 k Another zero is placed at low frequency: fZ1 = fPMIN = 12 Hz, then C13 GEA 20 GMODMIN 1.16 GLL 20 2.81 (9.0 dB) 11 3.0 0.25 C1 GTOTAL 1.0 520 10–9 0.47 F 2.0 12 25.5 k The frequency response diagram of the main loop is shown in Figure 17. http://onsemi.com 8 CS5101AN/D Voltage at the 3.3V winding at low line:VSY3 = 18(11/20) = 9.90 V. Assuming the Schottky rectifier forward drop is 0.75 V and the DC voltage drop across the FET plus the winding resistance is 0.1 V at full load, the duty cycle required to maintain regulation: Ramp charge current, ICHARGE = 0.2 mA. I t CRAMP CHARGE ON(MIN) VR 0.2 mA 0.293 s CRAMP 293 10–12 2.0 V CRAMP = C16 = 300 pF. DO3LL 3.3 0.75 0.1 0.419 9.9 DO3HL 3.3 0.75 0.1 0.209 19.8 Drain Resistor A small current is needed to keep the output stage in a low impedance state during abnormal or shutdown conditions. Drain pin current should be checked at the extremes of the supply voltage. The difference between the actual duty cycle and required, is calculated at high line; DO3HL 0.293 0.209 0.084 IDMAX 19.8 V 1.98 mA 10 k IDMIN 9.9 V 0.99 mA 10 k For 100 kHz, switching frequency tO3HL 10 s 0.084 840 ns The delay time through the SSPR is typically 300 ns, leaving enough head room for a good regulation within the specified voltage range. Overcurrent Protection Output current is sensed by the current sense resistor, R19, in the return path of the output. A voltage divider, comprised of resistors R16, R17, R20, and R21, is connected to the current sense amplifier. It is capable of sensing voltages below ground, up to 0.3 V. Overcurrent protection is set to: ISCO3 = 25 A; RCS = R19 = 0.1 Ω. Current sense voltage: Supply Voltage VCC and VC The supply voltage is derived directly from the 3.3 V winding. VCC varies with the input voltage, i.e., VCC = 9.0 V to 19 V. VCC is referenced to ground while the gate drive voltage, VC is bootstrapped and referenced to the source of Q3, i.e., VC = 8.0 V to 18 V. VCS 2.5 0.1 0.25 V Both dividers are connected to the 5.0 V reference voltage, provided by the CS5101. Set current through the dividers to 0.5 mA. The voltage at IS– pin (inverting input) is set to 2.5 V, so R17 = R20 = 5.11 k. The values of resistors R16 and R21, connected to IS+ (non–inverting input) are calculated using superposition. Synchronization Voltage The synchronization voltage threshold of the CS5101 is 2.5 V. For reliable operation, the voltage at the SYNC pin has to be higher than 2.5 V at all times during the pulse. Voltage at SYNC pin: R14 R13 R14 15 k VSYNC(MIN) 18 11 7.39 V 20 5.1 k 15 k VSYNC(MIN) VSY(MIN) R21 R19 (zero load current) R16 R21 R19 R16 VCS (V is shorted) VIS+ R16 R21 R19 REF VIS+ VREF VSYNC(MAX) 36 11 15 k 14.87 V 20 5.1 k Since R19 is small, it is ignored. Since the voltage at the winding is negative during the reset time, a clamp diode, D9, is placed across R14. A small capacitor C15, helps to reduce the negative going voltage spike at the turn–on of the power switch. This spike is due to the leakage inductance between primary and secondary windings. VIS+ VIS+ VIS+ VREF R16 R21 VCS R16 R21 R16 R21 At trip point, VIS+ VIS– 2.5 V R16 R21 10 k, then Ramp Capacitor The value of the ramp capacitor is calculated using the minimum on–time (at high line), and the current from the internal current source. Ramp dynamic range: 2.5 5 R21 0.25 R16 10 k 10 k R16 10 k R21 Substituting R21 = 5.23 kΩ, R16 = 4.75 kΩ. With C22 = 0.22 µF, current sense amplifier crossover frequency is: VR 3.5 1.5 2.0 V Minimum pulse duration at 36 V input voltage: D tON(MIN) MIN 0.293 2.93 s 100 kHz fSW 1 fCSO 2 R17 C22 1 fCSO 142 Hz 2 5.11 k 0.22 F The goal is, during the pulse, to charge the ramp capacitor CRAMP to a peak voltage. http://onsemi.com 9 CS5101AN/D SSPR Loop Compensation The SSPR operates in voltage control mode. The control loop model is shown in Figure 18. The modulator gain varies with input voltage, and from ref [3] is: GMAX 10 Gain (dB) Gm 20 DVO VSY He(s) DVC VC He(s) is represented by the double pole of the output filter and zero of the output capacitor’s ESR, i.e., GMIN 0 fCOMAX fCOMIN –10 fP 1 1 ; fZ 2C11ESR 2 L2C11 Modulator gain at input voltage extremes: –20 GO3(MAX) 19.8 7.92 (17.97 dB) 2.5 9.9 GO3(MIN) 3.96 (11.95 dB) 2.5 fPO3 1 2 50 H 330 F Performance Results and Waveforms The complete schematic, component placement and PC board layout are shown in Figures 22 through 25. The electrical performance characteristics of the demo board are shown in Table 1. The load and line regulation of the 3.3 V output is better than 0.3%. Actual waveforms of the demo board are shown in Figures 20 and 21. 1.24 kHz Crossover frequencies: fCO1 1.24 10(11.9540) 2.47 kHz fCO2 1.24 10(17.9740) 3.49 kHz Because of the interactions between the main loop and the loop controlled by the SSPR, it is recommended that the SSPR crossover frequency is at least one decade below the crossover frequency of the main loop (3.0 kHz, in our case). A simple single pole compensation is used. The interaction is especially severe with current mode control at light load because of the high impedance of the driving source ref [2]. Techniques to reduce these effects are outlined in ref [4]. Table 1. Demo Board Performance Measurements Main Output 1 fCO3 2 C17 R25 1 fCO3 122 Hz 2 0.1 F 43 k In general, voltage mode control with feed forward gives the best result for this type of application. Power Stage VSYX(D – D′) VIN Current Voltage 18 V 0.25 A 18 V 0.25 A 18 V Voltage 5.04 0A 3.273 5.04 2.25 A 3.268 3.0 A 5.04 0A 3.274 18 V 3.0 A 5.04 2.25 A 3.269 36 V 0.25 A 5.05 0A 3.277 36 V 0.25 A 5.04 2.25 A 3.272 36 V 3.0 A 5.04 2.25 A 3.276 36 V 3.0 A 5.04 2.25 A 3.272 Z2 Z1 RA VC Ae + Delay D – VR SYNC RB + – VREF Figure 18. Modular Gain Block Diagram http://onsemi.com 10 SSPR Output Current VOX LC Filter 10,000 Figure 19. SSPR Loop Frequency Characteristics 1 4.02 kHz fZO3 2 0.12 330 F VSYX × D 1000 Frequency (Hz) CS5101AN/D Special thanks to Kieran O’Malley for his help, and Bob Kent and German Martinez for their significant contributions to the development of the demo board. References 1. Design Techniques for Synchronous Switch Post Regulators, Clifford Jamerson, Tony Long, HFPC, 1993 Proceedings, pp. 10–20. 2. Coupled Filter Inductors in Multiple Output Buck Regulators Provide Dramatic Performance Improvement, Lloyd H. Dixon, Jr., Unitrode Power Supply Seminar Manual, SEM700, Unitrode Corporation, 1990. 3. Designing with a New Secondary Side Post Regulator (SSPR) PWM Controller for Multiple Output Power Supplies, Gedaly Levin, Proceedings of APEC, 1995, pp. 736–742. 4. Techniques for Reduction of Control Loop Interactions in Magamp Supplies, Clifford Jamerson, Ahmad Hossini, Magnetics, Inc. Application Note. 5. A New Synchronous Switch Post Regulator for Multi–Output Forward Converters, Yung–Lin Lin, Kwang H. Lin, Proceedings of APEC, 1990, pp. 693–696. Figure 20. Primary Side Waveforms Figure 21. SSPR Waveforms http://onsemi.com 11 http://onsemi.com 12 C7 120 µF DZ2 1N4746 Figure 22. Forward Converter with SSPR Controlled Output R7 1.0 k C6 6.8 nF R6 2.0 k C3 10 µF 4 OSC VREF C4 0.1 µF 8 R5 360 R27 10 k 7 3 6 5 GND C5 0.1 µF FB 2 SENSE CS3843 1 COMP U1 OUT DZ1 1N4746 VCC Q4 2N3904 T1:TDK PC40EER25.5–Z – Core Primary: 2 × 27 AWG, 20 T 5.0 V Secondary: 2 × 27 AWG, 11 T SSPR Secondary: 2 × 27 AWG, 11 T Q1 2N3904 C8 0.1 µF GND 18 V <> 36 V R4 2.0 k R2 4.99 k C1 1.5 nF R3 24 k C13 0.47 µF CP1 R12 10 k C2 1.0 nF CP3 3 T1P 20 T C18 0.01 µF 2 T1 AUX 8.0 T CP2 R10A 0.5 D8 MUR140 R9 10 k R11 100 R8 10 D1 BYV26C R23 10 7 8 CP6 R13 5.1 k R22 100 R10B 0.5 C9 0.1 µF R28 10 C17 0.1 µF 7 RAMP VFB COMP C16 300 µF CP11 5 6 2 1 VSYNC VCC D9 1N4148 C15 47 pF CP7 C19 56 µF R14 15 k D3 MBR360 13 IS– IS+ 4 11 LGND PGND GND 5.0 VOUT C22 0.22 µF R16 4.7 k R21 5.1 k D4 MBR360 C27 1.5 µF R17 5.1 k R19 0.1 C11 330 µF L2 50 µH C14 0.1 µF C20 0.1 µF R20 5.1 k L2 = T80–26, 32 T C12 0.1 µF CP12 10 9 8 VG 3 VREF 12 CP9 IS COMP CS5101 U2 VD VC 14 R15 100 k CP8 C10 330 µF L1 100 µH L1 = T72–26, 34 T, 23 AWG D5 MBR360 D6 1N4148 C23 100 pF T1S D7 11 T 1N4148 Q2 MTP10N15 CP4 4 1 5 T1S 11 T 6 D2 MBR360 R1 4.99 k R26 20 k R25 13 k GND 3.3 VOUT CS5101AN/D CS5101AN/D Figure 23. Component Placement Figure 24. Bottom Metal Layer CS5101 SSPR Demo Board Figure 25. Top Metal Layer http://onsemi.com 13 CS5101AN/D Table 2. Parts List of Discrete Components Qty Type Value Designator Manufacturer Distributor Part # 1 Monolithic 47 pF C15 Panasonic Digi–Key P4845–ND 1 Monolithic 100 pF C23 Panasonic Digi–Key P4800–ND 1 Monolithic 330 pF C16 Panasonic Digi–Key P4806–ND 1 Monolithic 1.0 nF C2 Panasonic Digi–Key P4812–ND 1 Monolithic 1.5 nF C1 Panasonic Digi–Key P4814–ND 1 Monolithic 6.8 nF C6 Panasonic Digi–Key P4880–ND 2 Monolithic 10 nF C18, C21 Panasonic Digi–Key P4881–ND 8 Monolithic 0.1 µF C4, C5, C8, C9, C12, C14, C17, C20 Panasonic Digi–Key P4887–ND 1 Monolithic 0.22 µF C22 Panasonic Digi–Key P4889–ND 1 Monolithic 0.47 µF C13 Panasonic Digi–Key P4891–ND 1 Tant/25 V 1.5 µF C27 Panasonic Digi–Key P2044–ND 1 Tant/25 V 10 µF C3 Panasonic Digi–Key P2049–ND 1 Electro/25 V 56 µF C19 Panasonic Digi–Key P5696–ND 1 Electro/50 V 120 µF C7 Panasonic Digi–Key P5764–ND 2 Electro/16 V 330 µF C10, C11 Panasonic Digi–Key P5670–ND 1 Metal Film 0.1 R19 Caddock Allied 524–6010 2 Metal Film 0.5 R10A, R10B Caddock Allied 524–6015 3 5.0%, 1/4 W 10 R8, R23, R28 Yageo Digi–Key 10QBK–ND 2 5.0%, 1/4 W 100 R11, R22 Yageo Digi–Key 100QBK–ND 1 5.0%, 1/4 W 360 R5 Yageo Digi–Key 360QBK–ND 1 5.0%, 1/4 W 1.0 k R7 Yageo Digi–Key 1KQBK–ND 2 5.0%, 1/4 W 2.0 k R4, R6 Yageo Digi–Key 2KQBK–ND 1 5.0%, 1/4 W 4.7 k R16 Yageo Digi–Key 4.7KQBK–ND 2 1.0%, 1/4 W 4.99 k R1, R2 Yageo Digi–Key 4.99KXBK–ND 4 5.0%, 1/4 W 5.1 k R13, R17, R20, R21 Yageo Digi–Key 5.1KQBK–ND 3 5.0%, 1/4 W 10 k R9, R12, R27 Yageo Digi–Key 10KQBK–ND 1 5.0%, 1/4 W 100 k R15 Yageo Digi–Key 10KQBK–ND 1 5.0%, 1/4 W 13 k R25 Yageo Digi–Key 13KQBK–ND 1 5.0%, 1/4 W 15 k R14 Yageo Digi–Key 15KQBK–ND 1 5.0%, 1/4 W 20 k R26 Yageo Digi–Key 20KQBK–ND 1 5.0%, 1/4 W 24 k R3 Yageo Digi–Key 24KQBK–ND 2 MUR140 UFRD D1, D8 Motorola Newark MUR140 2 1n4148 Diode D6, D7 DIODES Digi–Key 1N4148CT–ND 2 1n4744 18 V Zener DZ1, DZ2 ITT Digi–Key 1N4746ACT–ND 4 MBR360 30 V, 6.0 A Scht D2, D3, D4, D5 Motorola Newark MBR360 2 2n3904 NPN Q1, Q4 National Digi–Key 2N3904–ND 2 MTP10N15 MOSFET–N Q2, Q3 Motorola Newark MTP10N15 2 Heat Sinks TO–220 HS1, HS2 Aavid Digi–Key HS120–ND http://onsemi.com 14 CS5101AN/D Notes http://onsemi.com 15 CS5101AN/D ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). 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