IDT IDT49FCT806APY

FAST CMOS
BUFFER/CLOCK DRIVER
IDT49FCT805/A
IDT49FCT806/A
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
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The IDT49FCT805/A and IDT49FCT806/A are clock
drivers built using advanced dual metal CMOS technology.
The IDT49FCT805/A is a non-inverting clock driver and the
IDT49FCT806/A is an inverting clock driver. Each device
consists of two banks of drivers. Each bank drives five output
buffers from a standard TTL compatible input. The devices
feature a "heartbeat" monitor for diagnostics and PLL driving.
The MON output is identical to all other outputs and complies
with the output specifications in this document. The
IDT49FCT805/A and IDT49FCT806/A offer low capacitance
inputs with hysteresis. Rail-to-rail output swing improves
noise margin and allows easy interface with CMOS inputs.
0.5 MICRON CMOS Technology
Guaranteed low skew < 700ps (max.)
Low duty cycle distortion < 1ns (max.)
Low CMOS power levels
TTL compatible inputs and outputs
Rail-to-rail output voltage swing
High drive: -24mA IOH, 64mA IOL
Two independent output banks with 3-state control
1:5 fanout per bank
‘Heartbeat’ monitor output
Available in DIP, SOIC, SSOP (805 only), QSOP (805
only), Cerpack and LCC packages
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
IDT49FCT805
IDT49FCT806
OEA
OEA
INA
5
INB
5
OA1-OA5
INA
5
OB1-OB5
INB
5
OA1-OA5
OB1-OB5
OEB
OEB
MON
MON
2574 drw 02
2574 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
9.1
SEPTEMBER 1996
DSC-2574/10
1
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
OA2
3
18
OB2
OA3
4
17
OB3
5
OA4
6
OA5
7
NC (1)
16
GNDB
15
OB4
14
OB5
8
13
MON
OEA
9
12
OEB
INA
10
11
INB
4
GNDA
5
OA4
6
OA5
7
NC
(1)
3
2
1
20 19
L20-2
8
18
OB2
17
OB3
16
GNDB
15
OB4
14
OB5
9 10 11 12 13
OEA
GNDA
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
OA3
OB1
OB1
MON
19
VCCB
2
OEB
OA1
INDEX
VCCA
VCCB
INB
20
OA1
1
INA
VCCA
OA2
IDT49FCT805
LCC
TOP VIEW
2574 drw 04
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
2574 drw 03
OA2
3
18
OB2
OA3
4
17
OB3
16
GNDB
15
OB4
INDEX
GNDA
5
OA4
6
7
14
OB5
4
GNDA
5
OA4
6
OA5
7
NC (1)
8
3
2
20 19
1
L20-2
NC (1)
8
13
MON
9
OEA
9
12
OEB
INA
10
11
INB
OEA
OA5
P20-1
D20-1
SO20-2
&
E20-1
OA3
18
OB2
17
OB3
16
GNDB
15
OB4
14
OB5
10 11 12 13
LCC
TOP VIEW
DIP/SOIC/CERPACK
TOP VIEW
OB1
OB1
MON
19
VCCB
2
OEB
OA1
VCCA
VCCB
INB
20
OA1
1
INA
VCCA
OA 2
IDT49FCT806
2574 drw 06
2574 drw 05
PIN DESCRIPTION
Pin Names
OEA, OEB
Description
3-State Output Enable Inputs (Active LOW)
INA, INB
Clock Inputs
OAn, OBn
Clock Outputs (FCT805)
OAn, OBn
Clock Outputs (FCT806)
MON
Monitor Output (FCT805)
MON
Monitor Output (FCT806
NOTE:
2574 tbl 01
1. Pin 8 is not internally connected on devices with a "K" prefix in the date
code. On older devices, pin 8 is internally connected to GND. To insure
compatibility with all products, pin 8 should be connected to GND at the
board level.
9.1
2
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Description
VTERM(2) Terminal Voltage with Respect to
GND
(3)
VTERM
Terminal Voltage with Respect to
GND
TSTG
Storage Temperature
Max.
–0.5 to +7.0
Unit
V
–0.5 to
VCC +0.5
–65 to +150
V
°C
I OUT
–60 to +120
mA
DC Output Current
Symbol
Parameter(1)
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
4.5
VOUT = 0V
5.5
Max. Unit
6.0
pF
8.0
pF
2574 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
2574 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Output and I/O terminals.
FUNCTION TABLE(1)
Outputs
Inputs
OEA, OEB
49FCT805
INA, INB OAn, OBn
49FCT806
MON
OAn, OBn
MON
H
L
L
L
L
H
L
H
H
H
L
L
H
L
Z
L
Z
H
H
H
Z
H
Z
L
NOTE:
1. H = HIGH, L = LOW, Z = High Impedance
2574 tbl 02
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
Guaranteed Logic LOW Level
II H
Input HIGH Current (5)
VCC = Max.
VI = VCC
II L
Input LOW Current (5)
VCC = Max.
VI = GND
Z)(5)
VCC = Max.
Symbol
VIH
IOZH
Off State (HIGH
IOZL
Output Current (5)
VIK
Clamp Diode Voltage
Typ.(2)
—
Max.
—
—
—
0.8
V
—
—
±1
µA
—
—
±1
µA
VO = VCC
—
—
±1
µA
VO = GND
—
—
±1
µA
—
–0.7
–1.2
V
VCC = Min., IIN= –18mA
Max.(3) ,
Min.
2.0
Unit
V
IOS
Short Circuit Current
VCC =
VO = GND
–60
–120
—
mA
VOH
Output HIGH Voltage
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VHC
VCC
—
V
VCC = Min.
VHC
VCC
—
3.6
4.3
—
2.4
3.8
—
—
GND
VLC
IOH = –300µA
VIN = VIH or VIL
VOL
Output LOW Voltage
VCC = 3V, VIN
IOH = –12mA MIL.
IOH = –15mA COM'L.
IOH = -24mA MIL.
IOH = -24mA COM'L.
= VLC or VHC, IOL= 300µA
VCC = Min.
IOH = 300µA
—
GND
VLC(4)
VIN = VIH or VIL
IOL = 48mA MIL.
—
0.3
0.55
—
200
—
—
5
500
V
IOL = 64mA COM'L.
VH
Input Hysteresis for all inputs
ICC
Quiescent Power Supply Current
—
VCC = Max., VIN = GND or VCC
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
9.1
mV
µA
2574 tbl 05
3
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
—
1.0
2.5
mA
VIN = VCC
VIN = GND
—
0.15
0.20
mA/
MHz/bit
VCC = Max.
Outputs Open
fo= 10MHz
50% Duty Cycle
OEA = OEB =VCC
Mon. Output Toggling
VIN = VCC
VIN = GND
—
1.5
2.5
mA
VIN = 3.4V
VIN = GND
—
2.0
3.8
VCC = Max.
Outputs Open
fo = 2.5MHz
50% Duty Cycle
OEA = OEB = GND
Eleven Outputs
Toggling
VIN = VCC
VIN = GND
—
4.1
6.0 (5)
VIN = 3.4V
VIN = GND
—
5.1
8.5 (5)
Symbol
Parameter
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current (4)
VCC = Max.
Outputs Open
OEA = OEB = GND
50% Duty Cycle
IC
Total Power Supply Current (6)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO= Output Frequency
NO= Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
9.1
2574 tbl 06
4
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
IDT49FCT805/806
Com'l.
Symbol
Parameter
tPLH
Propagation Delay
tPHL
INA to OAn, INB to OBn
Mil.
IDT49FCT805A/806A
Com'l.
Mil.
Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max.
1.5
5.6
1.5
6.3
1.5
5.3
1.5
6.0
CL = 50pF
RL = 500Ω
Unit
ns
tR
Output Rise Time
—
1.5
—
1.5
—
1.5
—
1.5
ns
tF
Output Fall Time
—
1.5
—
1.5
—
1.5
—
1.5
ns
tSK(o)
Output skew: skew between outputs of all
banks of same package (inputs tied together)
—
0.7
—
0.9
—
0.7
—
0.9
ns
tSK(p)
Pulse skew: skew between opposite
transitions of same output (|tPHL-tPLH|)
—
1.0
—
1.1
—
1.0
—
1.1
ns
tSK(t)
Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
—
1.5
—
1.5
—
1.5
—
1.5
ns
tPZL
tPZH
Output Enable Time
OEA to OAn, OEB to OBn
1.5
8.0
1.5
8.5
1.5
8.0
1.5
8.5
ns
tPLZ
tPHZ
Output Disable Time
OEA to OAn, OEB to OBn
1.5
7.0
1.5
7.5
1.5
7.0
1.5
7.5
ns
2574 tbl 07
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
9.1
5
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIME
SWITCH POSITION
VCC
7.0V
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
Switch
Closed
Open
2574 lnk 11
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
500Ω
CL
2574 drw 07
PACKAGE DELAY
OUTPUT SKEW - tSK(o)
3V
1.5V
INPUT
INPUT
0V
tPLH
tPLH1
3V
1.5V
0V
VOH
tPHL1
tPHL
VOH
2.0V
0.8V
OUTPUT
1.5V
VOL
OUTPUT 1
tSK(o)
1.5V
tSK(o)
VOL
1.5V
VOL
OUTPUT 2
tF
tR
VOH
tPLH2
tPHL2
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
2574 drw 08
2574 drw 09
PACKAGE SKEW - tSK(t)
PULSE SKEW - tSK(p)
3V
1.5V
0V
INPUT
tPHL
tPLH
OUTPUT
VOH
1.5V
VOL
INPUT
tPHL1
tPLH1
PACKAGE 1 OUTPUT
tSK(t)
PACKAGE 2 OUTPUT
tSK(p) = |tPHL - tPLH|
3V
1.5V
0V
2574 drw 10
tPLH2
tSK(t)
tPHL2
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Package 1 and Package 2 are same device type and speed grade
2574 drw 11
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
CONTROL
INPUT
1.5V
0V
t
OUTPUT
NORMALLY
LOW
t PLZ
PZL
SWITCH
CLOSED
0.3V V OL
t
t PZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3.5V
3.5V
1.5V
PHZ
0.3V VOH
1.5V
0V
0V
2574 drw 12
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
9.1
6
IDT49FCT805/806/A
FAST CMOS BUFFER/CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT49FCT
XXX
Device Type
XX
Package
X
Process/
Temperature Range
Blank
B
Commercial (0°C to +70°C)
MIL-STD-883, Class B (–55°C to +125°C)
P
D
E
L
SO
PY
Q
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
805
806
805A
806A
Non-Inverting Buffer/Clock Driver
Inverting Buffer/Clock Driver
2574 drw 17
9.1
7