IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Equivalent to AMD’s Am29841-46 bipolar registers in pinout/function, speed and output drive over full temperature and voltage supply extremes • IDT54/74FCT841A equivalent to FAST speed • IDT54/74FCT841B 25% faster than FAST • IDT54/74FCT841C 40% faster than FAST • Buffered common latch enable, clear and preset inputs • IOL = 48mA (commercial) and 32mA (military) • Clamp diodes on all inputs for ringing suppression • CMOS power levels (1mW typ. static) • TTL input and output level compatible • CMOS output level compatible • Substantially lower input current levels than AMD’s bipolar Am29800 series (5µA max.) • Product available in Radiation Tolerant and Radiation Enhanced versions • Military product compliant to MIL-STD-883, Class B The IDT54/74FCT800 series is built using an advanced dual metal CMOS technology. The IDT54/74FCT840 series bus interface latches are designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/ data paths or buses carrying parity. The IDT54/74FCT841 is a buffered, 10-bit wide version of the popular ‘373 function. All of the IDT54/74FCT800 high-performance interface family are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high-impedance state. FUNCTIONAL BLOCK DIAGRAM D0 DN PRE D P LE Q D P LE Q CLR CLR CLR LE OE Y0 YN 2607 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1994 Integrated Device Technology, Inc. 7.22 APRIL 1994 DSC-4603/2 1 IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES 1 24 2 23 22 3 4 5 6 7 8 P24-1 D24-1 E24-1 & SO24-2 21 20 19 18 17 9 16 10 15 11 14 12 13 INDEX VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 LE 4 D2 D3 D4 NC D5 D6 D7 3 5 2 1 28 27 26 25 24 6 7 23 8 22 L28-1 9 21 10 20 19 11 Y2 Y3 Y4 NC Y5 Y6 Y7 12 13 14 15 16 17 18 D8 D9 GND NC LE Y9 Y8 OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND D1 D0 OE NC VCC Y0 Y1 PIN CONFIGURATIONS LCC TOP VIEW DIP/CERPACK/SOIC TOP VIEW 2607 drw 02 FUNCTION TABLE(1) PIN DESCRIPTION Name CLR I/O I DI I LE I YI O OE I PRE I 2607 drw 03 Description When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. The latch data inputs. Inputs CLR PRE OE The latch enable input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-to-LOW transition. The 3-state latch outputs. The output enable control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs (Y I) are in the high-impedance (off) state. Preset line. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR. 2607 tbl 01 LE DI Inter- Out- nal QI puts YI Function H H H X X X Z High Z H H H H L L Z High Z H H H H H H Z High Z H H H L X NC Z Latched (High Z) H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC H L L X X H H Preset L H L X X L L Clear Latched L L L X X H H Preset L H H L X L Z Latched (High Z) H L H L X H Z Latched (High Z) NOTE: 1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, Z = High Impedance 7.22 2607 tbl 02 2 IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating (2) VTERM Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature PT Power Dissipation I OUT Commercial –0.5 to +7.0 CAPACITANCE (TA = +25°C, f = 1.0MHz) Military Unit –0.5 to +7.0 V Symbol CIN COUT –0.5 to VCC –0.5 to VCC V 0 to +70 –55 to +125 °C –55 to +125 –65 to +135 °C –55 to +125 –65 to +150 °C 0.5 0.5 W 120 120 mA DC Output Current Parameter Input Capacitance Output Capacitance (1) Conditions VIN = 0V Typ. 6 Max. 10 Unit pF 8 12 pF VOUT = 0V NOTE: 1. This parameter is measured at characterization but not tested. 2607 tbl 04 NOTE: 2607 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level VIL Input LOW Level II H Input HIGH Current Symbol VIH II L IOZH Min. 2.0 Typ.(2) — Max. — Unit V Guaranteed Logic LOW Level — — 0.8 V VCC = Max. — — 5 µA VI = VCC Input LOW Current Off State (High Impedance) VCC = Max. Output Current IOZL VI = 2.7V — — 5(4) VI = 0.5V — — –5(4) VI = GND — — –5 VO = VCC — — 10 VO = 2.7V — — 10(4) VO = 0.5V — — –10(4) VO = GND VIK Clamp Diode Voltage VCC = Min., IN = –18mA Max.(3) , IOS Short Circuit Current VCC = VOH Output HIGH Voltage VCC = 3V, VIN = VLC or VHC, IOH = –32µA VOL Output LOW Voltage VO = GND — — –10 — –0.7 –1.2 V –75 –120 — mA V VHC VCC — VCC = Min. IOH = –300µA VHC VCC — VIN = VIH or VIL IOH = –15mA MIL. 2.4 4.3 — IOH = –24mA COM'L. 2.4 4.3 — — GND VLC VCC = 3V, VIN = VLC or VHC, IOL = 300µA VCC = Min. IOL = 300µA — GND VLC(4) VIN = VIH or VIL IOL = 32mA MIL. — 0.3 0.5 IOL = 48mA COM'L. — 0.3 0.5 NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested. 7.22 µA V 2607 tbl 05 3 IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC – 0.2V Symbol ICC ∆ICC ICCD IC Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (6) Test Conditions(1) VCC = Max. VIN ≥ VHC; V IN ≤ V LC VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND LE = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling Min. Typ.(2) Max. Unit — 0.2 1.5 mA — 0.5 2.0 mA VIN ≥ VHC VIN ≤ VLC — 0.15 0.25 mA/ MHz VIN ≥ VHC VIN ≤ VLC (FCT) — 1.7 4.0 mA VIN = 3.4V VIN = GND — 2.0 5.0 VIN ≥ VHC VIN ≤ VLC (FCT) — 3.2 6.5 (5) VIN = 3.4V VIN = GND — 5.2 14.5 (5) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 7.22 2607 tbl 06 4 IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT841A Com'l. Symbol tPLH tPHL tPLH tPHL tPLH Parameter CL = 50pF Propagation Delay DI to YI (LE = HIGH) RL = 500Ω CL = 300pF(4) RL = 500Ω CL = 50pF Propagation Delay LE to YI RL = 500Ω CL = 300pF(4) tPHZ tPLZ Propagation Delay, PRE to YI Output Enable Time OE to YI Output Disable Time OE to Y I Data to LE Set-up Time tH Data to LE Hold Time tW LE Pulse Width (3) tW tW tREM tREM Com'l. Mil. HIGH 1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 Unit ns 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 1.5 6.4 1.5 6.8 ns 1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 1.5 15.0 1.5 16.0 1.5 10.0 1.5 7.0 1.5 RL = 500Ω 1.5 14.0 1.5 17.0 1.5 10.0 1.5 13.0 1.5 9.0 1.5 12.0 1.5 13.0 1.5 14.0 1.5 10.0 1.5 11.0 1.5 9.0 1.5 10.0 1.5 14.0 1.5 17.0 1.5 10.0 1.5 10.0 1.5 9.0 1.5 8.0 9.0 ns ns 9.0 CL = 50pF 1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 1.5 6.5 1.5 7.3 RL = 500Ω CL = 300pF(4) 1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 1.5 12.0 1.5 13.0 RL = 500Ω CL = 5pF(4) 1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 5.7 1.5 6.0 RL = 500Ω CL = 50pF 1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 1.5 6.0 1.5 6.3 RL = 500Ω CL = 50pF 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — 2.5 — RL = 500Ω PRE LOW CLR Pulse Width(3) LOW Recovery Time PRE to LE Recovery Time CLR to LE Pulse Width(3) Mil. 1.5 12.0 1.5 14.0 1.5 Propagation Delay, CLR to YI tSU Com'l. RL = 500Ω CL = 50pF tPLH tPZH tPZL Mil. FCT841C Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. tPHL tPHL FCT841B ns ns ns 2.5 — 3.0 — 2.5 — 2.5 — 2.5 — 2.5 — ns 4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns 5.0 — 7.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns 4.0 — 5.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns 4.0 — 4.0 — 4.0 — 4.0 — 4.0 — 4.0 — ns 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested. 4. These conditions are guaranteed but not tested. 2607 tbl 07 7.22 5 IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC 500Ω VOUT VIN Pulse Generator D.U.T. 50pF RT Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: 2607 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. Test 7.0V tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED tPLZ 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V 0V 3.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2607 drw 04 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 7.22 6 IDT54/74FCT841A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX IDT XX FCT Temp. Range Device Type X Package X Process Blank B Commercial MIL-STD-883, Class B P D E L SO Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC 841A 841B 841C 10-Bit Non-Inverting Latch 54 74 –55°C to +125°C 0°C to +70°C 2607 drw 05 7.22 7