IDT IDT23S09E-1HDC

IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT23S09E
3.3V ZERO DELAY
CLOCK BUFFER, SPREAD
SPECTRUM COMPATIBLE
FEATURES:
DESCRIPTION:
• Phase-Lock Loop Clock Distribution
• 10MHz to 200MHz operating frequency
• Distributes one clock input to one bank of five and one bank of
four outputs
• Separate output enable for each output bank
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT23S09E-1 for Standard Drive
• IDT23S09E-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 200MHz.
The IDT23S09E is a 16-pin version of the IDT23S05E. The IDT23S09E
accepts one reference input, and drives two banks of four low skew clocks.
The -1H version of this device operates up to 200MHz frequency and has
higher drive than the -1 device. All parts have on-chip PLLs which lock
to an input clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad. In the absence of an input clock, the
IDT23S09E enters power down. In this mode, the device will draw less
than 12µA for Commercial Temperature range and less than 25µA for
Industrial temperature range, and the outputs are tri-stated.
The IDT23S09E is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
16
1
2
PLL
CLKOUT
CLKA1
REF
3
CLKA2
14
CLKA3
15
S2
S1
CLKA4
8
9
Control
Logic
6
7
10
11
CLKB1
CLKB2
CLKB3
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER 2003
1
c
2003 Integrated Device Technology, Inc.
DSC - 6399/8
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
REF
1
16
CLKOUT
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
6
Unit
Supply Voltage Range
Rating
–0.5 to +4.6
V
VI (2)
Input Voltage Range (REF)
–0.5 to +5.5
V
VI
Input Voltage Range
–0.5 to
V
(except REF)
Input Clamp Current
–50
mA
IO (VO = 0 to VDD)
Continuous Output Current
±50
mA
VDD or GND
Continuous Current
±100
mA
TA = 55°C
Maximum Power Dissipation
0.7
W
–65 to +150
°C
0 to +70
°C
-40 to +85
°C
CLKB4
CLKB3
TSTG
Storage Temperature Range
S1
Operating
Commercial Temperature
CLKB2
7
10
S2
8
9
(in still air)
(3)
Temperature
Range
Operating
Industrial Temperature
Temperature
Range
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150°C and a board trace length of 750 mils.
APPLICATIONS:
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
PIN DESCRIPTION
Pin Name
REF
(1)
CLKA1(2)
CLKA2
Pin Number
Type
Functional Description
1
IN
Input reference clock, 5 Volt tolerant input
2
Out
Output clock for bank A
Output clock for bank A
3
Out
VDD
4, 13
PWR
GND
(2)
3.3V Supply
5, 12
GND
CLKB1(2)
6
Out
Output clock for bank B
CLKB2(2)
7
Out
Output clock for bank B
S2(3)
8
IN
Select input Bit 2
S1
Ground
9
IN
Select input Bit 1
CLKB3(2)
10
Out
Output clock for bank B
CLKB4(2)
11
Out
Output clock for bank B
CLKA3(2)
14
Out
Output clock for bank A
CLKA4
15
Out
Output clock for bank A
16
Out
Output clock, internal feedback on this pin
(3)
(2)
CLKOUT(2)
VDD+0.5
IIK (VI < 0)
11
SOIC/ TSSOP
TOP VIEW
•
•
•
•
•
Max.
VDD
NOTES:
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
2
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
S2
S1
CLKA
CLKB
CLKOUT (2)
Output Source
PLL Shut Down
L
L
Tri-State
Tri-State
Driven
PLL
N
L
H
Driven
Tri-State
Driven
PLL
N
H
L
Driven
Driven
Driven
REF
Y
H
H
Driven
Driven
Driven
PLL
N
NOTES:
1. H = HIGH Voltage Level.
L = LOW Voltage Level
2. This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol
Parameter
Conditions
VIL
Input LOW Voltage Level
VIH
Input HIGH Voltage Level
IIL
Input LOW Current
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
VOL
Output LOW Voltage
VOH
IDD_PD
IDD
Output HIGH Voltage
Standard Drive
IOL = 8mA
High Drive
IOL = 12mA (-1H)
Standard Drive
IOH = -8mA
High Drive
IOH = -12mA (-1H)
Min.
Max.
Unit
—
0.8
V
2
—
V
—
50
µA
—
100
µA
—
0.4
V
2.4
—
V
Power Down Current
REF = 0MHz (S2 = S1 = H)
—
12
µA
Supply Current
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
—
32
mA
OPERATING CONDITIONS - COMMERCIAL
Symbol
Min.
Max.
Unit
VDD
Supply Voltage
3
3.6
V
TA
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance < 100MHz
—
30
pF
Load Capacitance 100MHz - 200MHz
—
10
Input Capacitance
—
7
CIN
Parameter
pF
SWITCHING CHARACTERISTICS (23S09E-1) - COMMERCIAL(1,2)
Symbol
t1
Parameter
Conditions
Output Frequency
Min.
Typ.
Max.
Unit
10pF Load
10
—
200
MHz
30pF Load
10
—
100
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
2.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
2.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge(2)
Measured at VDD/2 in PLL bypass mode (IDT23S09E only)
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
tLOCK
(2)
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
3
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (23S09E-1H) - COMMERCIAL(1,2)
Symbol
Min.
Typ.
Max.
Unit
Output Frequency
10pF Load
30pF Load
10
10
—
—
200
100
MHz
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45
50
55
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
1.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
1.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2 in PLL bypass mode (IDT23S09E only)
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
t8
Output Slew Rate
Measured between 0.8V and 2V using Test Circuit 2
1
—
—
V/ns
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
t1
tLOCK
Parameter
Conditions
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol
Parameter
Conditions
Min.
Max.
Unit
VIL
Input LOW Voltage Level
—
0.8
V
VIH
Input HIGH Voltage Level
2
—
V
IIL
Input LOW Current
VIN = 0V
—
50
µA
IIH
Input HIGH Current
VIN = VDD
VOL
Output LOW Voltage
Standard Drive
VOH
Output HIGH Voltage
IDD_PD
IDD
IOL = 8mA
High Drive
IOL = 12mA (-1H)
Standard Drive
IOH = -8mA
High Drive
IOH = -12mA (-1H)
—
100
µA
—
0.4
V
2.4
—
V
Power Down Current
REF = 0MHz (S2 = S1 = H)
—
25
µA
Supply Current
Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND
—
35
mA
OPERATING CONDITIONS - INDUSTRIAL
Symbol
Parameter
Min.
Max.
Unit
3
3.6
V
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
-40
+85
°C
CL
Load Capacitance < 100MHz
—
30
pF
Load Capacitance 100MHz - 200MHz
—
10
Input Capacitance
—
7
CIN
4
pF
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS (23S09E-1) - INDUSTRIAL(1,2)
Symbol
t1
Parameter
Output Frequency
Conditions
Min.
Typ.
Max.
Unit
10pF Load
10
—
200
MHz
30pF Load
10
—
100
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
2.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
2.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2 in PLL bypass mode (IDT23S09E only)
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
tLOCK
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (23S09E-1H) - INDUSTRIAL(1,2)
Symbol
t1
Min.
Typ.
Max.
Unit
Output Frequency
Parameter
10pF Load
30pF Load
Conditions
10
10
—
—
200
100
MHz
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT = 66.66MHz
40
50
60
%
Duty Cycle = t2 ÷ t1
Measured at 1.4V, FOUT <50MHz
45
50
55
%
t3
Rise Time
Measured between 0.8V and 2V
—
—
1.5
ns
t4
Fall Time
Measured between 0.8V and 2V
—
—
1.5
ns
t5
Output to Output Skew
All outputs equally loaded
—
—
250
ps
t6A
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2
—
0
±350
ps
t6B
Delay, REF Rising Edge to CLKOUT Rising Edge
Measured at VDD/2 in PLL bypass mode (IDT23S09E only)
1
5
8.7
ns
t7
Device-to-Device Skew
Measured at VDD/2 on the CLKOUT pins of devices
—
0
700
ps
t8
Output Slew Rate
Measured between 0.8V and 2V using Test Circuit 2
1
—
—
V/ns
tJ
Cycle-to-Cycle Jitter
Measured at 66.66MHz, loaded outputs
—
—
200
ps
PLL Lock Time
Stable power supply, valid clock presented on REF pin
—
—
1
ms
tLOCK
NOTES:
1. REF Input has a threshold voltage of VDD/2.
2. All parameters specified with loaded outputs.
5
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
All outputs should be uniformly loaded in order to achieve Zero I/O Delay. Since the CLKOUT pin is the internal feedback for the PLL, its relative
loading can affect and adjust the input/output delay.
For designs utilizing zero I/O Delay, all outputs including CLKOUT must be equally loaded. Even if the output is not used, it must have a capacitive
load equal to that on the other outputs in order to obtain true zero I/O Delay. For zero output-to-output skew, all outputs must be loaded equally.
SPREAD SPECTRUM COMPATIBLE
Many systems being designed now use a technology called Spread Spectrum Frequency Timing Generation. This product is designed not to filter
off the Spread Spectrum feature of the reference input, assuming it exists. When a zero delay buffer is not designed to pass the Spread Spectrum feature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
6
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS
VDD
VDD
0.1µF
CLKOUT
OUTPUTS
0.1µF
1KΩ
CLOAD
1KΩ
VDD
VDD
0.1µF
0.1µF
GND
GND
GND
GND
Test Circuit 2 (t8, Output Slew Rate On -1H Devices)
Test Circuit 1 (all Parameters Except t8)
SWITCHING WAVEFORMS
t1
1.4V
Output
t2
1.4V
1.4V
1.4V
1.4V
Output
t5
Output to Output Skew
Duty Cycle Timing
Output
CLKOUT
OUTPUTS
0.8V
t3
2V
2V
0.8V
3.3V
VDD/2
REF
0V
t4
VDD/2
Output
t6
Input to Output Propagation Delay
All Outputs Rise/Fall Time
CLKOUT
Device 1
CLKOUT
Device 2
VDD/2
t7
VDD/2
Device to Device Skew
7
10pF
IDT23S09E
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXXX
Device Type
XX
Package
X
Process
Blank
I
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
DC
PG
Small Outline
Thin Shrink Small Outline Package
Zero Delay Clock Buffer with High Drive,
23S09E-1
23S09E-1H Spread Spectrum Compatible
Ordering Code
IDT23S09E-1DC
Package Type
16-Pin SOIC
Operating Range
Commercial
IDT23S09E-1DCI
16-Pin SOIC
Industrial
IDT23S09E-1HDC(1)
16-Pin SOIC
Commercial
IDT23S09E-1HDCI(1)
16-Pin SOIC
Industrial
IDT23S09E-1HPG
16-Pin TSSOP
Commercial
IDT23S09E-1HPGI(1)
16-Pin TSSOP
Industrial
(1)
NOTE:
1. Contact factory for availability.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
8
for Tech Support:
[email protected]
(408) 654-6459