IDT77252 155 Mbps ATM SAR Controller With ABR Support for PCI-based Networking Applications ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Utility Bus Interface for PHY Management Serial EEPROM Interface ◆ EPROM Interface ◆ PCI 2.1 Compliant ◆ UNI 3.1, TM 4.0 Compliant ◆ Meets PCI Bus Power Management and Interface Specification Revision 1.1 ◆ Pin Compatible with IDT 77211 SAR ◆ Commercial and Industrial Temperature Ranges ◆ 208-Lead PQFP Package (28 x 28mm) ◆ Software Drivers: – SARWIN 2 Demonstration Program – NDIS Driver – Vx Works (3rd party) – Linux (3rd party) ◆ Full-duplex Segmentation and Reassembly (SAR) at 155 Mbps "wire-speed" (310 Mbps aggregate speed) Operates with ATM Networks up to 155.52 Mbps Stand-alone Controller: Embedded Processor not required Performs ATM Layer Protocol Functions Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR), and Unassigned Bit Rate (UBR), and Available Bit Rate (ABR) Service Classes Segments and Reassembles CS-PDUs into Host Memory Up to 16K Open Transmit Connections Up to 16K Simultaneous Receive Connections ABR, VBR, UBR Selectable per VC Time-out Automatic AAL5 Padding Four Buffer Pools for Independent or Chained Reassembly Supports Any Buffer Alignment Condition Free Buffer Queues Mapped Into PCI Memory Space Rx FIFO Size (Configurable to 1024 Kbytes) Configurable Transmit FIFO Depth for Reduced Latency Supports Big and Little Endian Data Transfers Null Cell Disable Option During Transmit NAND Test Mode RM Cell Handling UTOPIA Level 1 Interface to PHY The IDT77252 NICStAR™ is a member of IDT's family of products for Asynchronous Transfer Mode (ATM) networks. The ABR SAR performs both the ATM Adaptation Layer (AAL) Segmentation and Reassembly (SAR) function and the ATM layer protocol functions. A Network Interface Card (NIC) or internetworking product based on the ABR SAR uses host memory, rather than local memory, to reassemble Convergence Sublayer Protocol Data Units (CS-PDUs) from ATM cell payloads received from the network. When transmitting, as CSPDUs become ready, they are queued in host memory and segmented 16K x 32 to 512K x 32 SRAM PCI BUS 32 EPROM 8 PCI Interface Rx UTOPIA Bus 8 33MHZ 32 IDT77252 155Mbps PCI ATM ABR SAR 155Mbps 2 Tx UTOPIA Bus 8 PHY 2 Utility Bus 8 80.0MHZ OSC. EEPROM 4057 drw 01 1 of 17 2001 Integrated Device Technology, Inc. March 26, 2001 DSC 4057/8 IDT77252 by the ABR SAR into ATM cell payloads. From this, the ABR SAR then creates complete 53-byte ATM cells which are sent through the network. The ABR SAR's on-chip PCI bus master interface provides efficient, low latency DMA transfers with the host system, while its UTOPIA interface provides direct connection to PHY components used in 25.6 Mbps to 155 Mbps ATM networks. The IDT77252 is fabricated using state-of-the-art CMOS technology, providing the highest levels of integration, performance and reliability, with the low-power consumption characteristics of CMOS. Transm it C ontrol Tx U topia Interface T x U topia Bus 8 / 32 PCI Bus . 32 / SRAM Bus / S R A M IN T E R FA CE PCI Interface Receive C ontrol Rx U topia Interface 8 R x U topia / Bus 8 / U tility EE PRO M O U T E E P R O M IN 4057 drw 02 GND Vcc REQ GNT CLK RST GND NAND_EN GND GND CLK_OUT Vcc Vcc ADD18_17_EN GND NAND_OUT GND TXPARITY PHY_CLK RXCLK GND RXEMPTY/RxCLAV RXENB RXSOC RXDATA(7) RXDATA(6) RXDATA(5) RXDATA(4) GND RXDATA(3) RXDATA(2) RXDATA(1) RXDATA(0) GND TXCLK TXFULL/TxCLAV TXENB TXSOC GND TXDATA(7) TXDATA(6) VCC TXDATA(5) TXDATA(4) GND TXDATA(3) TXDATA(2) TXDATA(1) TXDATA(0) UTL_CS(1) UTL_CS(0) Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000000009999999999888888888877777777776666666666555 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7156 155 Index 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 IDT77252 SAR Controller 135 With ABR Support 134 133 208 Pin PQFP 132 Pinout 131 130 PU-208 129 DUI-208 128 127 126 Refer to PSC-4053 for 125 124 detailed package drawing 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 1 1 1 1 1 106 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 0 0 0 0 0 105 34567 890 123 456789 012 345 678901234 56789 012345 67890 1234 Vcc GND C/BE(0) AD(7) Vcc AD(6) AD(5) AD(4) GND SR_A17 AD(3) AD(2) AD(1) AD(0) GND SR_A15 SR_WE SR_A13 SR_A8 SR_A9 SR_A11 SR_OE SR_A10 SR_CS SR_A16 GND SR_A14 Vcc SR_A12 SR_A7 SR_A6 SR_A5 SR_A4 SR_A3 SR_A2 SR_A1 SR_A0 SR_A18 GND SR_I/O(0) SR_I/O(1) SR_I/O(2) SR_I/O(3) SR_I/O(4) SR_I/O(5) GND SR_I/O(6) SR_I/O(7) SR_I/O(8) SR_I/O(9) SR_I/O(10) GND Vcc AD(31) AD(30) AD(29) AD(28) AD(27) AD(26) GND GND AD(25) AD(24) C/BE(3) IDSEL AD(23) AD(22) GND GND AD(21) Vcc AD(20) AD(19) AD(18) AD(17) AD(16) GND GND C/BE(2) Vcc FRAME IRDY TRDY DEVSEL STOP GND GND INTA Vcc PERR SERR PAR C/BE(1) AD(15) GND GND AD(14) AD(13) AD(12) AD(11) AD(10) AD(9) AD(8) GND 2 of 17 GND PHY_INT PHY_RST UTL_ALE UTL_RD UTL_WR GND UTL_AD(7) UTL_AD(6) UTL_AD(5) UTL_AD(4) Vcc UTL_AD(3) GND UTL_AD(2) UTL_AD(1) UTL_AD(0) Vcc SAR_CLK GND EEDO EEDI EESCLK EECS Vcc E_CE SR_I/O(31) SR_I/O(30) SR_I/O(29) GND SR_I/O(28) SR_I/O(27) SR_I/O(26) SR_I/O(25) SR_I/O(24) Vcc SR_I/O(23) GND SR_I/O(22) SR_I/O(21) SR_I/O(20) SR_I/O(19) SR_I/O(18) SR_I/O(17) GND SR_I/O(16) SR_I/O(15) SR_I/O(14) SR_I/O(13) SR_I/O(12) SR_I/O(11) Vcc 4057 drw 03 March 26, 2001 IDT77252 ! 1.228 ±0.016 (31.2 ±0.4) 1.10 ±0.004 (28.0 ±0.1) 208 1 157 Index 156 1.10 ±0.004 (28.0 ±0.1) 1.228 ±0.016 (31.2 ±0.4) 0.02 ±0.004 (0.5 ±0.1) 0.008 ±0.004 (0.2 ±0.1) 105 52 104 53 0.133 ±0.004 (3.37 ±0.1) 0.013 ±0.002 (0.33 ±0.06) 0.024 ±0.008 (0.6 ±0.2) 0.063 (1.6) 4057 drw 04 1 VCC I power 2 AD(31) I/O PCI address/data line 3 AD(30) I/O PCI address/data line 4 AD(29) I/O PCI address/data line 5 AD(28) I/O PCI address/data line 6 AD(27) I/O PCI address/data line 7 AD(26) I/O PCI address/data line 8 GND I power 9 GND I power 10 AD(25) I/O PCI address/data line 11 AD(24) I/O PCI address/data line 12 C/BE(3) I/O PCI bus command 13 IDSEL I PCI bus ID select 3 of 17 March 26, 2001 IDT77252 14 AD(23) I/O PCI address/data line 15 AD(22) I/O PCI address/data line 16 GND I power 17 GND I power 18 AD(21) I/O PCI 19 VCC I power 20 AD(20) I/O PCI address/data line 21 AD(19) I/O PCI address/data line 22 AD(18) I/O PCI address/data line 23 AD(17) I/O PCI address/data line 24 AD(16) I/O PCI address/data line 25 GND I power 26 GND I power 27 C/BE(2) I/O PCI 28 VCC I power 29 Frame I/O PCI cycle frame 30 IRDY I/O PCI initiator ready 31 TRDY I/O PCI target ready 32 DEVSEL I/O PCI target indicating address decode 33 STOP I/O PCI target requesting master to stop 34 GND I power 35 GND I power 36 INTA O PCI 37 VCC I power 38 PERR I/O PCI data parity error 39 SERR O PCI system error 40 PAR I/O PCI parity (for AD[0:31] and C/BE[0:3]) 41 C/BE(1) I/O PCI bus command 42 AD(15) I/O PCI address/data line 43 GND I power 44 GND I power 45 AD(14) I/O PCI address/data line 46 AD(13) I/O PCI address/data line 47 AD(12) I/O PCI address/data line 48 AD(11) I/O PCI address/data line 49 AD(10) I/O PCI address/data line 50 AD(9) I/O PCI address/data line 51 AD(8) I/O PCI address/data line 52 GND I power 4 of 17 address/data line bus command "interrupt" "A" "request" March 26, 2001 IDT77252 53 VCC I power 54 GND I power 55 C/BE(0) I/O PCI bus command 56 AD(7) I/O PCI address/data line 57 VCC I power 58 AD(6) I/O PCI address/data line 59 AD(5) I/O PCI address/data line 60 AD(4) I/O PCI address/data line 61 GND I power 62 SR_A17 O SRAM Address line 63 AD(3) I/O PCI address/data line 64 AD(2) I/O PCI address/data line 65 AD(1) I/O PCI address/data line 66 AD(0) I/O PCI address/data line 67 GND I power 68 SR_A15 O SRAM Address line 69 SR_WE O SRAM Write enable 70 SR_A13 O SRAM Address line 71 SR_A8 O SRAM Address line 72 SR_A9 O SRAM Address line 73 SR_A11 O SRAM Address line 74 SR_OE O SRAM Output Enable control 75 SR_A10 O SRAM Address line 76 SR_CS O SRAM Chip Select 77 SR_A16 O SRAM Address line 78 GND I power 79 SR_A14 O SRAM 80 VCC I power 81 SR_A12 O SRAM Address line 82 SR_A7 O SRAM Address line 83 SR_A6 O SRAM Address line 84 SR_A5 O SRAM Address line 85 SR_A4 O SRAM Address line 86 SR_A3 O SRAM Address line 87 SR_A2 O SRAM Address line 88 SR_A1 O SRAM Address line 89 SR_A0 O SRAM Address line 90 SR_A18 O SRAM Address line 91 GND I power 5 of 17 Address line March 26, 2001 IDT77252 92 SR_I/O(0) I/O SRAM Data input/output line 93 SR_I/O(1) I/O SRAM Data input/output line 94 SR_I/O(2) I/O SRAM Data input/output line 95 SR_I/O(3) I/O SRAM Data input/output line 96 SR_I/O(4) I/O SRAM Data input/output line 97 SR_I/O(5) I/O SRAM Data input/output line 98 GND I power 99 SR_I/O(6) I/O SRAM Data input/output line 100 SR_I/O(7) I/O SRAM Data input/output line 101 SR_I/O(8) I/O SRAM Data input/output line 102 SR_I/O(9) I/O SRAM Data input/output line 103 SR_I/O(10) I/O SRAM Data input/output line 104 GND I power 105 VCC I power 106 SR_I/O(11) I/O SRAM Data input/output line 107 SR_I/O(12) I/O SRAM Data input/output line 108 SR_I/O(13) I/O SRAM Data input/output line 109 SR_I/O(14) I/O SRAM Data input/output line 110 SR_I/O(15) I/O SRAM Data input/output line 111 SR_I/O(16) I/O SRAM Data input/output line 112 GND I power 113 SR_I/O(17) I/O SRAM Data input/output line 114 SR_I/O(18) I/O SRAM Data input/output line 115 SR_I/O(19) I/O SRAM Data input/output line 116 SR_I/O(20) I/O SRAM Data input/output line 117 SR_I/O(21) I/O SRAM Data input/output line 118 SR_I/O(22) I/O SRAM Data input/output line 119 GND I power 120 SR_I/O(23) I/O SRAM 121 VCC I power 122 SR_I/O(24) I/O SRAM Data input/output line 123 SR_I/O(25) I/O SRAM Data input/output line 124 SR_I/O(26) I/O SRAM Data input/output line 125 SR_I/O(27) I/O SRAM Data input/output line 126 SR_I/O(28) I/O SRAM Data input/output line 127 GND I power 128 SR_I/O(29) I/O SRAM Data input/output line 129 SR_I/O(30) I/O SRAM Data input/output line 130 SR_1/O(31) I/O SRAM Data input/output line 6 of 17 Data input/output line March 26, 2001 IDT77252 131 E_CE O EPROM EPROM chip select 132 VCC I power 133 EECS O EEPROM chip select 134 EESCLK O EEPROM clock 135 EEDI I EEPROM Data input 136 EEDO O EEPROM Data output 137 GND I power 138 SAR_CLK I 139 VCC I power 140 UTL_AD(0) I/O Utility address/data bus 141 UTL_AD(1) I/O Utility address/data bus 142 UTL_AD(2) I/O Utility address/data bus 143 GND I power 144 UTL_AD(3) I/O Utility 145 VCC I power 146 UTL_AD(4) I/O Utility address/data bus 147 UTL_AD(5) I/O Utility address/data bus 148 UTL_AD(6) I/O Utility address/data bus 149 UTL_AD(7) I/O Utility address/data bus 150 GND I power 151 UTL_WR O Utility write control 152 UTL_RD O Utility read control 153 UTL_ALE O Utility address latch enable 154 PHY_RST O PHY rest control 155 PHY_INT I PHY interrupt input from PHY 156 GND I power 157 VCC I power 158 UTL_CS(0) O Utility chip select (0) 159 UTL_CS(1) O Utility chip select (1) 160 TxData(0) O UTOPIA transmit data bit 0 161 TxData(1) O UTOPIA transmit data bit 1 162 TxData(2) O UTOPIA transmit data bit 2 163 TxData(3) O UTOPIA transmit data bit 3 164 GND I power 165 TxData(4) O UTOPIA transmit data bit 4 166 TxData(5) O UTOPIA transmit data bit 5 167 VCC I power 168 TxData(6) O UTOPIA transmit data bit 6 169 TxData(7) O UTOPIA transmit data bit 7 SAR clock input 7 of 17 address/data bus March 26, 2001 IDT77252 170 GND I power 171 TxSOC O UTOPIA transmit start of cell 172 TxEnb O UTOPIA transmit enable control 173 TxFull/TxCLAV I UTOPIA transmit buffer full 174 TxCLK O UTOPIA transmit data sync clock 175 GND I power 176 RxData(0) I UTOPIA receive data bit 0 177 RxData(1) I UTOPIA receive data bit 1 178 RxData(2) I UTOPIA receive data bit 2 179 RxData(3) I UTOPIA receive data bit 3 180 GND I power 181 RxData(4) I UTOPIA receive data bit 4 182 RxData(5) I UTOPIA receive data bit 5 183 RxData(6) I UTOPIA receive data bit 6 184 RxData(7) I UTOPIA receive data bit 7 185 RxSOC I UTOPIA receive start of cell 186 RxEnb O UTOPIA receive enable control 187 RxEmpty/RxCLAV I UTOPIA receive buffer empty 188 GND I power 189 RxClk O UTOPIA receive data sync clock 190 PHY_Clk I UTOPIA Transmit sync clock input 191 TxParity O UTOPIA transmit data parity bit 192 GND I power 193 NAND_OUT O power 194 GND I power 195 ADD17_18_EN I power 196 VCC I power 197 VCC I power 198 CLK_OUT O power 199 GND I power 200 GND I power 201 NAND_EN I power 202 GND I power 203 RST I PCI system bus reset 204 CLK I PCI bus clock 205 GNT I PCI bus grant signal from arbiter 206 REQ O PCI bus request 207 VCC I power 208 GND I power 8 of 17 NAND output chain enables or tristates SR_A17 and SR_A18 SAR_Clk divided by 3 NAND input chain March 26, 2001 IDT77252 " #$ $ VCC Supply Voltage -0.3 6.5 V VIN Input Voltage VSS - 0.3 VCC + 0.3 V VOUT Output Voltage VSS - 0.3 VCC + 0.3 V Tstg Storage Temperature -55 125 deg.C %% %%& '% % VCC Supply Voltage 4.75 5.25 V VI Input Voltage 0 VCC V TA1 Commercial Operating temperature 0 70 deg.C TA2 Industrial Operating temperature -40 85 deg.C titr Input TTL rise time — 2 ns titf Input TTL fall time — 2 ns ' SAR_CLK SAR clock input freq. PHY_CLK PHY clock input freq. PCI_CLK ' PCI clock input freq. 155Mb/s 77 80 MHz 25Mb/s 25 80 MHz 155Mb/s 19.44 40 MHz 25Mb/s 3 40 MHz 33MHz 0 33.3 MHz CIN Input Capacitance except PCI Bus — — 4 pF COUT Output Capacitance all outputs — — 6 pF Cbid Bi-Directional Capacitance all bi-directional pins — — 10 pF Cinpci PCI Bus Input Capacitance PCI Bus inputs — 10 — pF Cclkpci PCI Bus Clock Input Capacitance — 5 12 — pF Cidsel PCI Bus ID Select Input Capacitance — — 8 — pF ' '& '% % Vil Low-level TTL input voltage — -0.7V 0.8 — V Vih High-level TTL input voltage — 2 VCC + 0.2V — V Vol Low-level TTL output voltage except PCI Bus — 0.4 — V Vol PCI Bus Low-level TTL output voltage PCI Bus voltage — 0.55 — V Voh High-level TTL output voltage — 2.4 — — V 9 of 17 March 26, 2001 IDT77252 Iol Low-level TTL output current: SR_A(18-0) VSS + 0.4V 12 — — mA Ioh High-level TTL output current: SR_A(18-0) 2.4V -4 — — mA Iol Low-level TTL output current: RxEnb, RxClk, TxSOC, TxData (7-0), TxEnb, TxParity, TxClk, WE#, OE#, CS#, SR_D31-0 VSS + 0.4V 6 — — mA Ioh High-level TTL output current: RxEnb#, RxClk, TxSoc, TxData7-0, TxEnb#, TxParity, TxClk, SR_WE, SR, OE, SR_CS, SR_I/O(31-0) 2.4V -2 — — mA Iol Low-level TTL output current: UTL_AD(7-0), UTL_RD, UTL_WR, UTL_ALE, UTL_CS0/1, EESCLK, EECS, EEDO, PHY_RST VSS + 0.4V 3 — — mA Ioh High-level TTL output current: UTL_AD(7-0), UTL_RD, UTL_WR, UTL_ALE, UTL_CS0/1, EESCLK, EECS, EEDO, PHY_RST 2.4V -1 — — mA Iil Input leakage current VSS ≤ VIN ≤ Vdd -1 1 — uA Ityp Dynamic Supply Current — — 300 250 mA '& '% % Input Pulse Levels 0 to 3.0V Input Rise/Fall Times 2ns Input Timing Ref. Level 1.5V Output Ref. Level 1.5V AC Test Load See Figure Below Table 1 AC Test Conditions 6 5 1.5V 50Ω I/O Z0 = 50Ω 4 ∆tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200 4057 drw 05 (() The NAND Chain provides a simple test to verify that all bond wires are installed correctly and that all pads are correctly soldered on a PCB. All signal pads are linked in a NAND chain, which is enabled by asserting a high, or “1”, on NAND_EN (pin 201). Asserting a “1” on the other inputs forces NAND_OUT (pin 193) to “1”. By successively setting the inputs to “0”, starting at CLK_OUT (pin 198) and moving to TXPARITY (pin 191), NAND_OUT will toggle with each change. 1. Apply a "1" to NAND_EN. 2. Set all the I/O's in the chain to "0" and NAND_OUT should be a "1".The connection order of the pins in the chain are shown in the NAND Tree Pin Order table located on the following page. 3. Set CLK_OUT to a "0" and the NAND_OUT should be a "0". 4. Leaving pin 198 at a "1" set RST (pin 203) to "1" and NAND_OUT should be a "1". 5. Repeat for all remaining I/O's in the NAND chain. 10 of 17 March 26, 2001 IDT77252 ! ! ! ! CLK_OUT 198 AD[12] 47 SR_I/O[06] 99 UTL_AD[5] 147 RST 203 AD[11] 48 SR_I/O[07] 100 UTL_AD[6] 148 CLK 204 AD[10] 49 SR_I/O[08] 101 UTL_AD[7] 149 GNT 205 AD[9] 50 SR_I/O[09] 102 UTL_WR 151 REQ 206 AD[8] 51 SR_I/O[10] 103 UTL_RD 152 AD[31] 2 C/BE[0] 55 SR_I/O[11] 106 UTL_ALE 153 AD[30] 3 AD[7] 56 SR_I/O[12] 107 PHY_RST 154 AD[29] 4 AD[6] 58 SR_I/O[13] 108 PHY_INT 155 AD[28] 5 AD[5] 59 SR_I/O[14] 109 UTL_CS[0] 158 AD[27] 6 AD[4] 60 SR_I/O[15] 110 UTL_CS[1] 159 AD[26] 7 AD[3] 63 SR_I/O[16] 111 TxData[0] 160 AD[25] 10 AD[2] 64 SR_I/O[17] 113 TxData[1] 161 AD[24] 11 AD[1] 65 SR_I/O[18] 114 TxData[2] 162 C/BE[3] 12 AD[0] 66 SR_I/O[19] 115 TxData[3] 163 IDSEL 13 SR_WE 69 SR_I/O[20] 116 TxData[4] 165 AD[23] 14 SR_A[13] 70 SR_I/O[21] 117 TxData[5] 166 AD[22] 15 SR_A[8] 71 SR_I/O[22] 118 TxData[6] 168 AD[21] 18 SR_A[9] 72 SR_I/O[23] 120 TxData[7] 169 AD[20] 20 SR_A[11] 73 SR_I/O[24] 122 TxSOC 171 AD[19] 21 SR_OE 74 SR_I/O[25] 123 TxEnb 172 AD[18] 22 SR_A[10] 75 SR_I/O[26] 124 TxCLAV 173 AD[17] 23 SR_CS 76 SR_I/O[27] 125 TxCLK 174 AD[16] 24 SR_A[12] 81 SR_I/O[28] 126 RxData[0] 176 C/BE[2] 27 SR_A[7] 82 SR_I/O[29] 128 RxData[1] 177 Frame 29 SR_A[6] 83 SR_I/O[30] 129 RxData[2] 178 IRDY 30 SR_A[5] 84 SR_I/O[31] 130 RxData[3] 179 TRDY 31 SR_A[4] 85 E_CE 131 RxData[4] 181 DEVSEL 32 SR_A[3] 86 EECS 133 RxData[5] 182 STOP 33 SR_A[2] 87 EESCLK 134 RxData[6] 183 INITA 36 SR_A[1] 88 EEDI 135 RxData[7] 184 PERR 38 SR_A[0] 89 EEDO 136 RxSOC 185 SERR 39 SR_I/O[00] 92 SAR_CLK 138 RxEnb 186 PAR 40 SR_I/O[01] 93 UTL_AD[0] 140 RxCLAV 187 C/BE[1] 41 SR_I/O[02] 94 UTL_AD[1] 141 RxCLK 189 AD[15] 42 SR_I/O[03] 95 UTL_AD[2] 142 PHY_CLK 190 AD[14] 45 SR_I/O[04] 96 UTL_AD[3] 144 TxParity 191 AD[13] 46 SR_I/O[05] 97 UTL_AD[4] 146 Table 2 NAND Tree Pin Order 11 of 17 March 26, 2001 IDT77252 '*+ ,% % tval CLK to Output Signal Valid Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR 2 11 ns tval(ptp) CLK to Output Signal Valid Delay: REQ 2 12 ns ton Float to Signal Active Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR 2 — ns toff Signal Active to Float Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR — 28 ns tsu Input Setup Time to CLK: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR 7 — ns tsu(ptp) Input Setup Time to CLK: GNT, (REQ) 10(12) — ns th Input Hold Time from CLK: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, GNT 21 — ns trst-pwr Reset Active Time After Power Stable 1 — ns trst-clk Reset Active Time After CLK Stable 100 — ns trst-off Reset Active to Output Float Delay: AD31-0, C/BE3-0, PAR, FRAME, IRDY, DEVSEL, TRDY, STOP, PERR, SERR — 40 ns thigh Clock high time 11n — ns tlow Clock low time 11n — ns 1. Does not meet PCI Local Bus revision 2.1 timing specification .)& *+ / t1 TxClk, RxClk Delay from PHY_CLK — 5 ns t2 TxData(7-0), TxSOC, TxEnb, TxParity Output Valid from TxClk 1 15 ns t3 TxFull/TxCLAV Setup Time to TxClk 10 — ns t4 TxFull/TxCLAV Hold Time from TxClk 31 — ns t5 RxEnb Output Valid from RxClk 1 15 ns t6 RxData(7-0), RxSOC Setup Time to RxClk 10 — ns t7 RxData(7-0), RxSOC Hold Time from RxClk 21 — ns t8 RxEmpty/RxCLAV Setup Time to RxClk 10 — ns RxEmpty/RxCLAV Hold Time from TxClk 21 — ns t9 1. Does not meet UTOPIA 1 timing specification (Af-phy-0017.00) . 0 ' + 1 tw1 UTL_ALE Pulse Width 25 — ns tw2 UTL_CS0/1 Output Valid to UTL_ALE falling edge 25 — ns tw3 UTL_WR Output Valid from UTL_ALE falling edge — 80 ns tw4 UTL_CS0/1 Pulse Width 275 — ns tw5 UTL_WR Pulse Width 175 — ns tw6 UTL_ALE falling edge to UTL_WR rising edge 225 — ns tw7 UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge 30 — ns tw8 UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge 10 — ns tw9 UTL_AD(7-0) Data Setup Time to UTL_WR rising edge 185 — ns tw10 UTL_AD(7-0) Data Hold Time from UTL_WR rising edge 10 — ns tw11 UTL_ALE falling edge to UTL_CS0/1 rising edge 250 — ns 12 of 17 March 26, 2001 IDT77252 . %' + tr1 UTL_ALE Pulse Width 25 — ns tr2 UTL_CS0/1 Output Valid to UTL_ALE falling edge 25 — ns tr3 UTL_RD Output Valid from UTL_ALE falling edge — 80 ns tr4 UTL_CS0/1 Pulse Width 250 — ns tr5 UTL_RD Pulse Width 185 — ns tr6 UTL_ALE falling edge to UTL_RD rising edge 250 — ns tr7 UTL_AD(7-0) Address Setup Time to UTL_ALE falling edge 30 — ns tr8 UTL_AD(7-0) Address Hold Time from UTL_ALE falling edge 10 — ns tr9 UTL_AD(7-0) Data Setup Time to UTL_CS0/1 rising edge 80 — ns tr10 UTL_AD(7-0) Data Hold Time from UTL_CS0/1 rising edge 10 — ns tr11 UTL_ALE falling edge to UTL_CS0/1 rising edge 225 — ns # #0 ' + 2 t1 SR_A(18-0) Setup Time to SR_WE falling edge 2 — ns t2 SR_CS falling edge to SR_WE falling edge 0 — ns t3 SR_CS pulse width 25 — ns t4 SR_I/O(31-0) Setup Time to SR_WE rising edge 6 — ns t5 SR_I/O(31-0) Hold Time from SR_WE rising edge 0 — ns t6 SR_WE Pulse Width 10 — ns # #% % %' + t1 SR_A(18-0) to SR_I/O(31-0) Valid1 — 15 ns t2 SR_OE pulse width 25 — ns 1. SR_I/O (31-0) Setup and Hold times are guaranteed by design when t1 access time is met. 3 &#+ 4 t1 SR_I/O(7-0) Hold Time from E_CE rising edge 0 — ns t2 E_CE Pulse Width 75 — ns t3 SR_A(18-0) Change to SR_I/O(7-0) Valid — 70 ns t4 SR_A(18-0) Pulse Width 75 — ns 3 &#+ 5 t1 SAR_CLK to Output Signal Valid Delay: EECS, EEDO, EECLK 100 — ns software controlled t2 EEDI Input Setup Time to SAR_CLK 10 — ns software controlled t3 EEDI Input Hold Time from SAR_CLK 0 — ns software controlled 13 of 17 March 26, 2001 IDT77252 ton tcyc tlow thigh tval tval (ptp) toff PCI_CLK(I) AD31-0(O) Add C/BE3-0 (O) Cmd Data0 Data2 Data1 Data3 BE3-0 tval toff FRAME(O) ton tval IRDY (O) tval tsu tsu DEVSEL(I) toff th tsu TRDY(I) REQ (O) ParA PAR(O) tval(ptp) tval ton ParD0 ParD1 ParD2 toff ParD3 tsu(ptp) GNT(I) th 4057 drw 06 Figure 1 The ABR SAR as a PCI Master (illustrates a 4-word write by the ABR SAR to host memory) tsu th (1) PCI_CLK AD31-0(1) Add C/BE3-0(1) Cmd Data2 Data3 BE3-0 tsu ParA PAR(1) Data1 Data0 ParD0 ParD1 ParD2 ParD3 th FRAME(1) th tsu IRDY (1) toff th DEVSEL(1) toff tval, ton TRDY(O) toff tval, ton PERR(O) SERR(O) tval, ton REQ(1) tsu (O) REQ 4057 drw 07 tval Figure 2 The ABR SAR as a PCI Target (illustrates a 4-word write operation by the host device driver to the ABR SAR) 14 of 17 March 26, 2001 IDT77252 t1 (I) PHY_Clk t3 t7 t5 t2 t6 t8 t9 t4 (O) TxClk,RxClk (O) TxData 7-0 TxSOC TxEnb (O) (O) (O) TxParity Txfull/ (I) TxCLAV (O) RxEnb (I) RxData 7-0 RxSOC (I) RxEmpty/ RxCLAV (I) 5349 drw 08 Figure 3 UTOPIA Bus Timing tw1 tw7 tw2 tw11 tw6 tw8 tw3 UTL_ALE(O) tw4 UTL_CS0/1(O) tw5 tw10 tw9 UTL_WR(O) UTL_AD(7-0)(I/O) (O) Address (O) Valid Data 4057 drw 09 Figure 4 Utility Bus Write Cycle tr6 tr1 tr7 tr2 tr11 tr8 tr3 UTL_ALE tr4 UTL_CS0/1 tr5 tr10 tr9 UTL_RD UTL_AD7-0 Address (O) (I) Valid Data 4057 drw 10 Figure 5 Utility Bus Read Cycle 15 of 17 March 26, 2001 IDT77252 t1 SR_A(18-0) t3 t2 SR_CS t6 t4 t5 SR_WE SR_I/O(31-0) 5349 drw 11 Figure 6 SRAM Bus Write Cycle Timing t1 SR_A(18-0) SR_CS t2 SR_OE SR_I/O(31-0) 5349 drw 12 Figure 7 SRAM Bus Read Cycle Timing t3 t4 SR-A (18-0) t1 t2 E_CE Valid Data SR_I/O(7-0) 4057 drw 13 Figure 8 EPROM Timing t1 SAR_CLK EECS EECLK t3 EEDO t2 EEDI 5349 drw 14 Figure 9 EEPROM Timing ! % %! Several software vendors have written IDT77252 software drivers for various operating systems. Please contact your local IDT sales representative for a vendor list, or e-mail [email protected]. IDT offers the Sarwin2 demo driver and application suite, which can be used to evaluate the IDT77252 when used with a IDT NIC reference or evaluation adapter. It may also be used as a reference for sample source code when developing a proprietary device driver. Please contact your IDT sales representative or e-mail [email protected] to obtain a free CD-ROM. 16 of 17 March 26, 2001 IDT77252 (*' % %3% NIC Reference and Evaluation adapters are available in several form factors. Bill of Materials (BOM) and schematics are available upon request for each of the NIC adapters. A list of current NIC adapter offerings can be found at www.idt.com. Note: ABR SAR User Manual provides a detailed description of the 77252 operation and registers. &% % * IDT NNNNN Device Type A Power NNN Speed A Package PG PGI DUI Commerical 208-pin Plastic Quad Flatpack Revisions A, B, C, D, E, and F Industrial 208-pin Plastic Quad Flatpack Revisions A, B, C, D, and E Industrial 208-pin Plastic Quad Flatpack Revision F 155 Speed in Mps L Low Power CMOS 77252 155Mbs ATM Segmentation & Reassembly (SAR) Controller for the PCI Local Bus 4057 drw 15 Note: Refer to Errata list for revision history and how to identify revision. Refer to PSC-4053 for detailed package drawing. , ,,! The 77252 PG package is the same package as the 77211 PQF. The 77252 is a direct replacement to the 77211 SAR. To use the 77252 in a 155 Mbps application, a 80 MHz oscillator is required (replace the 50 MHz oscillator used with the 77211). 6 12/01/97: Created new document. 01/27/98: Corrected designation of pins 58, 75, and 90 plus made miscellaneous edits. 05/01/98: Changed package designation from PQF to PG. Added AC operating conditions. Edited timing diagrams. 08/11/98: Corrected descriptions for the following pins (pin 62, 90, 193). Edited package pin out diagram (pin 195). 07/07/99: Added Industrial Temp range. 09/15/99: Updated software section. 05/02/99: Added DUI package information, updated SRAM timing diagrams, updated Utility Bus timing diagrams, updated PCI timing parameters, updated UTOPIA bus timing parameters, updated AC Test Conditions section, updated EEPROM timing diagrams, added NAND Tree description and pin order, updated software section, and added NIC section. 06/22/00: Corrected Utility Bus Write, Utility Bus Read, and SRAM Write timing tables. Corrected NAND Tree pin order. 03/26/01: Changed from Preliminary to Final data sheet. Added to and rearranged the Features list. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for Tech Support: email:[email protected] phone: 408-492-8208 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 17 of 17 March 26, 2001