AN240
EP9312 USB version 1.1 Slave Schematic
The attached schematic shows a reference design for attaching the USB bus to the SRAM interface.
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Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
MAY ‘03
AN240REV1
1
D
C
B
A
R10
560K, 0603
SENSE/EOT
R11
1M, 0603
Notes:
5
L2
SHIELD
SHIELD
P1
GND
DD+
PWR
FERRITE_BEAD, 0603
1
2
5
6
USB-B
1
2
3
4
L1
FERRITE_BEAD, 0603
-EP9312 symbol is incomplete as this is meant
only for reference purposes.
R9
1.5K, 0603
-SENSE/EOT signal acts as both a USB Vbus detect
AND the end-of-transfer signal for DMA operations.
This is intentional. Please see the Philips PDIUSBD12
datasheet for additional details.
4
R5
1
1
1
VCC3
X2
R159
2
4.7K, 0603
INT1
DREQ
1
VCC3
25
26
21
14
17
22
23
27
24
5
DD+
*GL
*INT
*DMREQ
XTAL1
XTAL2
V3.3
VCC
3
U3
D0
D1
D2
D3
D4
D5
D6
D7
*DMACK
*EOT
ALE
A0
*CS
*RD
*WR
*RST
SUSPEND
PDIUSBD12, TSSOP28
GND
3
1
2
3
4
6
7
8
9
18
19
11
15
16
10
28
20
12
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
SENSE/EOT
1
2
R12
4.7K
1
2
R8
4.7K
R7
4.7K
1
2
2
R4
4.7K
2
1
2
R3
4.7K
DA[7:0]
1
VCC3
R1
4.7K
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DREQ
INT1
Document Number
<Doc>
EP9312 USB 1.1 Slave
R2
4.7K
1
2
Tuesday, June 24, 2003
U5
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
1
EGPIO7/DREQ0
EGPIO8/DACK0
EGPIO9/DEOT0
INT1
/CS7
/RD
/WR
AD0
AD1
AD2
AD3
1
Sheet
1
of
EP9312-D partial SRAM interface
Date:
Size
B
Title
2
VCC3
1
2
VCC3
2
18.2_1%, 0603
R6
2
2
6MHZ, HC49-US
C11
22PF, 0603
18.2_1%, 0603
C12
22PF, 0603
4
1
2
1
2
-Likewise, R10/R11 form a 3.3V pullup network for the EOT
signal via the USB +5V bus rail. Thus, there is no pullup resistor
for the SENSE/EOT signal.
-This schematic assumes minimal or no loading of the buses
between the EP9312 and the PDIUSBD12. Depending on your
design, you may need additional buffering to reduce
the overall load on these signals.
5
1
2
2
1
1
2
1
2
1
Rev
0
D
C
B
A