AN46 Application Note CDB5509 CAPTURE INTERFACE By John Lis INTRODUCTION The CDB5509 evaluation board requires a simple modification to interface with the CAPTURE board. The CAPTURE board requires an SCLK input signal to collect data. However, the SCLK pin on the CS5509 is a digital input only. For the CDB5509 to interface with the CAPTURE board, an SCLK signal needs to be created. One possible solution is to derive the SCLK from the XOUT signal. The frequency of the XOUT pin is within the specifications for the SCLK signal and the serial port can accept a continuous clock. The CAPTURE board is designed to ignore extra clock signals on the SCLK line when using a continuous serial clock. Next the 74HC125 buffer needs to be modified. U3-3 is isolated from the circuit, so there aren’t two devices driving the SCLK node. Finally U3-8 is isolated, allowing U3B to be active and able to drive the SCLK output signal to the CAPTURE board. Figure 1 is a schematic for the modified evaluation board. The following check list summarizes the modifications. q q q q REMOVE R25 JUMPER U1-5 to U1-14 ISOLATE U3-3 ISOLATE U3-8 Using XOUT as the SCLK input signal is a simple modification of the evaluation board. It is easy to implement, requiring no extra components. The following steps describe the modifications. The source of the SCLK signal is the XOUT pin on the CS5509. Install a jumper on the CS5509 from U1-5 to U1-14. (Make sure that adjustments are made for the CAB5509 adapter board. U1-5 translates to U1-6 and U1-14 translates to U1-21 on the bottom of the evaluation board.) The 100 kΩ resistor R25 needs to be removed to reduce the load upon XOUT. Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved) FEB ‘98 AN46REV1 1 2 MODIFICATIONS TO THE CDB5509 FOR INTERFACING TO CDBCAPTURE +5 R22 +5 10 +5 +5V D1 6.8V C5 + C2 +5 C7 0.1 uF AGND 0.1 uF 0.1 uF 10 uF 11 DGND GND 2 +5 C9 0.1 uF External VREF 5 1B R26 1K R10 R8 C8 25k CAL 9 C19 10nF CONV 3 C17 VD+ 1 0.1 uF U2A 10 CS VREF- 1 U2C 10 DRDY 11 9 VD+ R20 100k 7 R4 402 C15 U2E 8 U3D SCLKO 5 6 U3B SCLKI 14 VD+ 3 100k 0.1 uF VD+ 4 R16 11 15 U2F R24 100k 2 C18 U3A R1 BP/UP 1 100k 12 13 AIN+ J1 7 R21 TP15 VD+ U3C 8 AIN- R13 12 SDATA 14 TP13 14 6 A1 R23 100k TP12 15 TP14 BP/UP A0 47k DRDY TP11 16 R25 100k TP6 U2D R18 R19 100k TP7 CS5509 SCLK R12 100k VD+ 7 U1 2B SDATA AIN- 5 U2B TP8 3B R31 100k CS 4 6 402 CONV 47k 2 3A AIN+ 3 TP9 0.1 uF - R17 VD+ 2 VREF+ 4 + J2 20k TP10 C20 10nF 2A 6 LT1019 -2.5 V 1A SDATA R11 100k VD+ CAL R27 1K C11 0.01 uF 13 VA+ DRDY SCLK C10 10 +5 C16 10 uF CAL VD+ R9 + 47k 0.01 uF 9 8 10 S2 U2 74HC4050 U3 74HC125 A1 A0 R3 50 CLKIN R2 200 XIN 4 XOUT 5 GND CONV 12 Y1 32.768 kHz Remove R25 Isolate U3-3 Isolate U3-8 Jumper U1-5 to U1-14 AN46 AN46REV1 Figure 1. Schematic of CDB5509 Modified for the CAPTURE Interface BP/UP Note: • Notes •