7542 Group REJ03B0006-0303 Rev.3.03 Jul 11, 2008 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION FEATURES • • • • • • • • • • • Basic machine-language instructions ...................................... 71 The minimum instruction execution time ............................. 0.25 µs (at 8 MHz oscillation frequency, double-speed mode for the shortest instruction) Memory size Flash memory version: ROM ..................... 16 to 32K + 4K bytes RAM ..................................... 1024 bytes Mask ROM version: ROM ............................. 8K to 16K bytes RAM ............................ 384 to 512 bytes RSS version RAM ..................................... 1024 bytes Programmable I/O ports 29 (25 in 32-pin version and PWQN0036KA-A package version) Interrupts ................................................. 18 sources, 16 vectors Timers ............................................................................. 8-bit ✕ 2 ...................................................................................... 16-bit ✕ 2 Output compare ............................................................ 4-channel Input capture ................................................................ 2-channel Serial interface ............ 8-bit ✕ 2 (UART or Clock-synchronized) A/D converter ............................................... 10-bit ✕ 8 channels (6 channels in 32-pin version and PWQN0036KA-A package version) Clock generating circuit ............................................. Built-in type (low-power dissipation by an on-chip oscillator) (connected to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Watchdog timer ............................................................ 16-bit ✕ 1 Power source voltage XIN oscillation frequency at ceramic oscillation, in double-speed mode At 8 MHz .................................................................... 4.5 to 5.5 V XIN oscillation frequency at ceramic oscillation, in high-speed mode At 8 MHz .................................................................... 4.0 to 5.5 V At 4 MHz .................................................................... 2.4 to 5.5 V At 2 MHz .................................................................... 2.2 to 5.5 V XIN oscillation frequency at RC oscillation in high-speed mode or middle-speed mode At 4 MHz .................................................................... 4.0 to 5.5 V At 2 MHz .................................................................... 2.4 to 5.5 V At 1 MHz .................................................................... 2.2 to 5.5 V • Power dissipation ................................................ 27.5 mW (Typ.) • Operating temperature range ................................... –20 to 85 °C • The 7542 Group is the 8-bit microcomputer based on the 740 family core technology. The 7542 Group has serial interfaces, 8-bit timers, 16-bit timers, and an A/D converter, and is useful for control of home electric appliances and office automation equipment. Page 1 of 117 • APPLICATION Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, etc. 7542 Group P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 PIN CONFIGURATION (TOP VIEW) 24 23 22 21 20 19 18 17 P07(LED07)/SRDY2 P10/RXD1/CAP0 P11/TXD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0 P21/AN1 25 16 26 15 14 27 28 29 M37542Mx-XXXGP M37542FxGP 13 12 30 11 31 10 32 9 2 3 4 5 6 7 8 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 1 P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11)/CMP2 P30(LED10)/CAP1 VSS XOUT XIN Outline PLQP0032GB-A (32P6U-A) Fig. 1 Pin configuration (Package type: PLQP0032GB-A) P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS 1 36 2 35 3 34 4 5 6 7 8 9 10 11 12 13 33 M37542Mx-XXXFP M37542FxFP P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 32 31 30 29 28 27 26 25 24 14 23 15 22 16 21 17 20 18 19 P11/TXD1 P10/RXD1/CAP0 P07(LED07)/SRDY2 P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 P36(LED16)/INT1 P35(LED15) P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11)/CMP2 P30(LED10)/CAP1 Package type: PRSP0036GA-A (36P2R-A) Fig. 2 Pin configuration (Package type: PRSP0036GA-A) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 2 of 117 7542 Group P12/SCLK1 P13/SRDY1 P14/CNTR0 32 P11/TXD1 2 31 3 30 P10/RXD1/CAP0 P07(LED07)/SRDY2 P20/AN0 4 29 P06(LED06)/SCLK2 P21/AN1 P22/AN2 5 28 P23/AN3 P24/AN4 7 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P25/AN5 VREF 9 M37542Mx-XXXSP M37542FxSP 1 6 8 10 RESET CNVSS VCC XIN 11 27 26 25 24 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 23 22 21 P34(LED14) 13 20 14 19 P33(LED13)/INT1 P32(LED12)/CMP3 XOUT 15 18 P31(LED11)/CMP2 VSS 16 17 P30(LED10)/CAP1 12 Package type: PRDP0032BA-A (32P4B) [N.C.] P34(LED14) P37(LED17)/INT0 P00(LED00)/CAP0 P01(LED01)/CMP0 P03(LED03)/TXOUT P02(LED02)/CMP1 P05(LED05)/TxD2 P04(LED04)/RxD2 Fig. 3 Pin configuration (Package type: PRDP0032BA-A) 27 26 25 24 23 22 21 20 19 28 18 [N.C.] P07(LED07)/SRDY2 29 17 P33(LED13)/INT1 P10/RxD1/CAP0 30 16 P32(LED12)/CMP3 P11/TxD1 31 15 P31(LED11)/CMP2 14 P30(LED10)/CAP1 13 Vss P06(LED06)/SCLK2 M37542Mx-XXXHP P12/SCLK1 32 P13/SRDY1 33 P14/CNTR0 34 12 XOUT P20/AN0 35 11 XIN P21/AN1 36 10 [N.C.] 1 2 3 4 5 6 7 8 9 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVss Vcc [N.C.] M37542F8HP (Note) Package type: PWQN0036KA-A (36PJW-A) Fig. 4 Pin configuration (Package type: PWQN0036KA-A) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 3 of 117 N.C.: Non Connection Note: Only ES version (MP: no plan) 7542 Group P14/CNTR0 1 42 NC NC P20/AN0 P21/AN1 NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 NC NC VREF RESET CNVSS Vcc XIN XOUT 2 41 3 40 39 5 38 6 37 7 36 8 9 10 11 12 13 14 15 M37542RSS VSS 4 33 32 31 30 29 28 27 17 26 18 25 19 24 20 23 21 22 Fig. 5 Pin configuration (Package type: 42S1M) Page 4 of 117 34 16 Package type 42S1M Rev.3.03 Jul 11, 2008 REJ03B0006-0303 35 P13/SRDY1 P12/SCLK1 P11/TXD1 P10/RXD1/CAP0 P07(LED07)/SRDY2 P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 NC P37(LED17)/INT0 P36(LED16)/INT1 P35(LED15) P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11)/CMP2 P30(LED10)/CAP1 7542 Group Table 1 Performance overview Parameter Function Number of basic instructions Instruction execution time Oscillation frequency Memory sizes Mask ROM ROM RAM ROM RAM FLASH ROM I/O port 71 0.25 µs (Minimum instruction, oscillation frequency 8 MHz: double-speed mode) 8 MHz (max.) 8 K to 16 K bytes 384 to 512 bytes 16 K to 32 K + 4 K bytes 1024 bytes •8-bit ✕ 3, 5-bit ✕ 1 (8-bit ✕ 1, 6-bit ✕ 2, 5-bit ✕ 1 for 32-pin version and PWQN0036KA-A package version) 18 sources, 16 vectors •8-bit ✕ 2, 16-bit ✕ 2 4 channel 2 channel 8-bit ✕ 2 (UART or clock synchronous) 10-bit ✕ 8 channel (6 channel for 32-pin version and PWQN0036KA-A package version) 16-bit ✕ 1 Built-in P0, P1, P2, P3 Interrupts Timer Output compare Input capture Serial interface A/D converter Watchdog timer Clock generating circuit Power source High-speed mode voltage Middle-speed mode (at ceramic resonance) At 8MHz oscillation At 4MHz oscillation At 2MHz oscillation Double-speed mode At 8MHz oscillation At 6.5MHz oscillation At 2MHz oscillation At 1MHz oscillation Power source High-speed mode At 4MHz voltage Middle-speed mode oscillation (at RC oscillation) At 2MHz oscillation At 1MHz oscillation Power dissipation Operating temperature range Device structure Package Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 5 of 117 Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM (external ceramic resonator or quartz-crystal oscillator, RC oscillation available) (Low consumption current by on-chip oscillator available) 4.0 to 5.5 V 2.4 to 5.5 V 2.7 to 5.5 V 2.2 to 5.5 V 2.7 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V 2.4 to 5.5 V 2.7 to 5.5 V 2.2 to 5.5 V 2.7 to 5.5 V 4.5 to 5.5 V 2.4 to 5.5 V 2.7 to 5.5 V 2.2 to 5.5 V 2.7 to 5.5 V 27.5 mW (Typ.) 24.0 mW (Typ.) -20 to 85 °C CMOS silicon gate 32-pin plastic molded SDIP/LQFP, 36-pin plastic molded SSOP/WQFN Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 6 of 117 10 X OUT Fig. 6 Functional block diagram (Package type: PLQP0032GB-A) VREF 5 A/D converter (10) Watchdog timer 0 PC H I/O port P3 I/O port P2 4 3 2 1 32 31 17 16 15 14 13 12 Output Compare ROM P2(6) INT0 INT1 Input Capture RAM 8 11 PS PC L S Y X A SI/O2(8) CPU VCC VSS P3(6) Reset Clock generating circuit 9 X IN Clock input Clock output SI/O1(8) P1(5) I/O port P1 30 29 28 27 26 6 RESET Reset input CNTR0 Timer X (8) Timer 1 (8) I/O port P0 25 24 23 22 21 20 19 18 P0(8) Timer B (16) Timer A (16) Prescaler X (8) Prescaler 1 (8) 7 CNVSS Key-on wakeup FUNCTIONAL BLOCK DIAGRAM (Package type: PLQP0032GB-A) 7542 Group FUNCTIONAL BLOCK Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 7 of 117 Fig. 7 Functional block diagram (Package type: PRSP0036GA-A) VREF 12 A/D converter (10) Watchdog timer 0 PC H I/O port P3 I/O port P2 11 10 9 8 7 6 5 4 26 25 24 23 22 21 20 19 Output Compare ROM P2(8) INT0 INT1 Input Capture RAM PS PC L S Y X A SI/O2(8) CPU 15 18 P3(8) Reset Clock generating circuit 17 SI/O1(8) P1(5) I/O port P1 3 2 1 36 35 13 RESET 16 Reset input VCC X IN X OUT VSS Clock input Clock output CNTR0 Timer X (8) Timer 1 (8) I/O port P0 34 33 32 31 30 29 28 27 P0(8) Timer B (16) Timer A (16) Prescaler X (8) Prescaler 1 (8) 14 CNVSS Key-on wakeup FUNCTIONAL BLOCK DIAGRAM (Package type: PRSP0036GA-A) 7542 Group Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 8 of 117 Fig. 8 Functional block diagram (Package type: PRDP0032BA-A) VREF 10 A/D converter (10) Watchdog timer 0 PC H I/O port P3 I/O port P2 9 8 7 6 5 4 22 21 20 19 18 17 Output Compare ROM P2(6) INT0 INT1 Input Capture RAM PS PC L S Y X A SI/O2(8) CPU 13 16 P3(6) Reset Clock generating circuit 15 SI/O1(8) P1(5) I/O port P1 3 2 1 32 31 11 RESET 14 Reset input VCC X IN X OUT VSS Clock input Clock output CNTR0 Timer X (8) Timer 1 (8) I/O port P0 30 29 28 27 26 25 24 23 P0(8) Timer B (16) Timer A (16) Prescaler X (8) Prescaler 1 (8) 12 CNVSS Key-on wakeup FUNCTIONAL BLOCK DIAGRAM (Package type: PRDP0032BA-A) 7542 Group Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 9 of 117 12 11 Fig. 9 Functional block diagram (Package type: PWQN0036KA-A) VREF 5 A/D converter (10) Watchdog timer 0 PC H I/O port P3 I/O port P2 4 3 2 1 36 35 21 20 17 16 15 14 Output Compare ROM P2(6) INT0 INT1 Input Capture RAM 8 13 PS PC L S Y X A SI/O2(8) CPU VCC VSS P3(6) Reset Clock generating circuit X OUT X IN Clock input Clock output SI/O1(8) P1(5) I/O port P1 34 33 32 31 30 6 RESET Reset input CNTR0 Timer X (8) Timer 1 (8) I/O port P0 29 28 27 26 25 24 23 22 P0(8) Timer B (16) Timer A (16) Prescaler X (8) Prescaler 1 (8) 7 CNVSS Key-on wakeup FUNCTIONAL BLOCK DIAGRAM (Package type: PWQN0036KA-A) 7542 Group 7542 Group PIN DESCRIPTION Table 2 Pin description Name Pin Power source Vcc, Vss VREF CNVss RESET XIN Function Function expect a port function Mask ROM version Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss. FLASH ROM version Apply voltage of 2.7 to 5.5 V to Vcc, and 0 V to Vss. Analog refer- •Reference voltage input pin for A/D converter. ence voltage CNVss •Chip operating mode control pin, which is always connected to Vss. Reset input •Reset input pin for active “L” Clock input •Input and output pins for main clock generating circuit. XOUT Clock output P00(LED00)/CAP0 P01(LED01)/CMP0 I/O port P0 P02(LED02)/CMP1 P03(LED03)/TXOUT P04(LED04)/RxD2 P05(LED05)/TxD2 P06(LED06)/SCLK2 P07(LED07)/SRDY2 I/O port P1 P10/RxD1/CAP0 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0–P27/AN7 P30(LED10)/CAP1 P31(LED11)/CMP2 P32(LED12)/CMP3 P33(LED13)/INT1 P34(LED14) P35(LED15) P36(LED16)/INT1 P37(LED17)/INT0 I/O port P2 (Note 1) I/O port P3 (Note 2) •Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. •For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. •If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. •When the on-chip oscillator is selected as the main clock, connect X IN pin to VCC and leave XOUT open. •8-bit I/O port. • Capture function pin • Key-input •I/O direction register allows each pin to be individually pro- • Compare function pin (key-on wake up grammed as either input or output. •CMOS compatible input level • Timer X function pin interrupt •CMOS 3-state output structure • Serial I/O2 function pin input) pin •Whether a built-in pull-up resistor is to be used or not can be determined by program. • High drive capacity for LED drive port can be selected by program. •5-bit I/O port •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level •CMOS 3-state output structure •CMOS/TTL level can be switched for P10, P12 and P13 •8-bit I/O port having almost the same function as P0 •CMOS compatible input level •CMOS 3-state output structure •8-bit I/O port •I/O direction register allows each pin to be individually programmed as either input or output. •CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37). •CMOS 3-state output structure •Whether a built-in pull-up resistor is to be used or not can be determined by program. • High drive capacity for LED drive port can be selected by program. • Serial I/O1 function pin • Capture function pin • Serial I/O1 function pin • Timer X function pin • Input pins for A/D converter • Capture function pin • Compare function pin • Interrupt input pin • Interrupt input pin Notes 1: P26/AN6 and P27/AN7 do not exist for the 32-pin version and PWQN0036KA-A package, so that Port P2 is a 6-bit I/O port. 2: P35 and P36/INT1 do not exist for the 32-pin version and PWQN0036KA-A package, so that Port P3 is a 6-bit I/O port. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 10 of 117 7542 Group GROUP EXPANSION Renesas plans to expand the 7542 group as follow: Memory type Support for Mask ROM version, Flash memory version, and Emulator MCU . Memory size Flash memory size ...................................... 16 to 32 K + 4 K bytes Mask ROM size ................................................... 8 K to 16 K bytes RAM size ............................................................ 384 to 1024 bytes Package PRDP0032BA-A .................................. 32-pin plastic molded SDIP PLQP0032GB-A .......... 0.8 mm-pitch 32-pin plastic molded LQFP PRSP0036GA-A .......... 0.8 mm-pitch 36-pin plastic molded SSOP PWQN0036KA-A ........ 0.5 mm-pitch 36-pin plastic molded WQFN 42S1M .................................... 42-pin shrink ceramic PIGGY BACK ROM size (bytes) 32K +4K M37542F8 16K +4K M37542F4 16K 8K M37542M4 M37542M2 0 384 512 1024 RAM size (bytes) Fig. 10 Memory expansion plan Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 11 of 117 7542 Group Currently supported products are listed below. Table 3 List of supported products ROM size (bytes) RAM size Product ROM size for User ( ) (bytes) 384 M37542M2-XXXSP 8192 M37542M2-XXXHP (8062) M37542M2-XXXFP M37542M2-XXXGP 512 M37542M4-XXXSP 16384 M37542M4-XXXHP (16254) M37542M4-XXXFP M37542M4-XXXGP 1024 M37542F4SP 16384 + 4096 M37542F4FP (Note 2) M37542F4GP 1024 M37542F8SP 32768 + 4096 M37542F8FP (Note 2) M37542F8GP M37542F8HP (Note 1) 1024 M37542RSS Notes 1: Only ES version (MP: no plan) 2: ROM size includes the ID code area. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 12 of 117 Package PRDP0032BA-A PWQN0036KA-A PRSP0036GA-A PLQP0032GB-A PRDP0032BA-A PWQN0036KA-A PRSP0036GA-A PLQP0032GB-A PRDP0032BA-A PRSP0036GA-A PLQP0032GB-A PRDP0032BA-A PRSP0036GA-A PLQP0032GB-A PWQN0036KA-A 42S1M Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Flash memory version Flash memory version Flash memory version Flash memory version Flash memory version Flash memory version Flash memory version Emulator MCU 7542 Group FUNCTIONAL DESCRIPTION Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig. 12. Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL for details on each instruction set. Machine-resident 740 family instructions are as follows: 1. The FST and SLW instructions cannot be used. 2. The MUL and DIV instructions can be used. 3. The WIT instruction can be used. 4. The STP instruction can be used. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the second OPERAND. b7 Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b0 Accumulator A b7 b0 Index Register X X b7 b0 Index Register Y Y b7 b0 Stack Pointer S b15 b7 PCH b0 Program Counter PCL b7 b0 N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig. 11 740 Family CPU register structure Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 13 of 117 7542 Group On-going Routine Interrupt request (Note) M (S) Execute JSR M (S) Store Return Address on Stack (S) (PC H) (S) (S – 1) M (S) (PCL) (S) (S – 1) M (S) Subroutine Restore Return Address (S + 1) (PCL) M (S) (S) (S + 1) (PCH) M (S) (S – 1) (PC L) (S) (S – 1) M (S) (PS) (S) (S – 1) Interrupt Service Routine Execute RTS (S) (PC H) Execute RTI Note : The condition to enable the interrupt (S) (S + 1) (PS) M (S) (S) (S + 1) (PC L) M (S) (S) (S + 1) (PC H) M (S) Store Return Address on Stack Store Contents of Processor Status Register on Stack I Flag “0” to “1” Fetch the Jump Vector Restore Contents of Processor Status Register Restore Return Address Interrupt enable bit is “1” Interrupt disable flag is “0” Fig. 12 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack PHA PHP Accumulator Processor status register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 14 of 117 Pop instruction from stack PLA PLP 7542 Group Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”. (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Z flag – – Page 15 of 117 I flag SEI CLI D flag SED CLD B flag – – T flag SET CLT V flag – CLV N flag – – 7542 Group [CPU mode register] CPUM The CPU mode register contains the stack page selection bit, etc.. This register is allocated at address 003B16. Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method. b7 b0 CPU mode register (CPUM: address 003B16, initial value: 8016) Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 0 1 Not available 1 0 1 1 Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f(φ) = f(XIN)/2 (High-speed mode) 0 1 : f(φ) = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2) Note 1: These bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to bits. However, by reset bits are initialized and can be rewritten, again. (It is not disable to write any data to bits for emulator MCU “M37542RSS”.) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 13 Structure of CPU mode register After releasing reset Switch the oscillation mode selection bit (bit 5 of CPUM) Wait by on-chip oscillator operation until establishment of oscillator clock Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Start with an on-chip oscillator An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). Select 1/1, 1/2, 1/8 or on-chip oscillator. Main routine Note: After system is released from reset, an on-chip oscillator turns active automatically and system operation is started. Fig. 14 Switching method of CPU mode register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 16 of 117 7542 Group Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. The reserved ROM area can program/erase in the flash memory version. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. 000016 SFR area Zero page 004016 RAM 010016 RAM area RAM capacity (bytes) address XXXX16 384 512 1024 01BF16 023F16 043F16 XXXX16 Reserved area 044016 0FE016 0FFF16 YYYY16 Not used SFR area (Note 1) Not used Reserved ROM area (128 bytes) ZZZZ16 ROM FF0016 ROM area ROM capacity (bytes) address YYYY16 address ZZZZ16 8192 16384 32768 E00016 C00016 800016 E08016 C08016 808016 Special page FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Notes 1: Only flash memory version has this SFR area. 2: The reserved ROM area can program/erase in the flash memory version. Note the difference of the mask version. Fig. 15 Memory map diagram Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 17 of 117 7542 Group Port P0 (P0) 002016 Capture mode register (CAPM) 000116 Port P0 direction register (P0D) 002116 Compare output mode register (CMOM) 000216 Port P1 (P1) 002216 Capture/compare status register (CCSR) 000316 Port P1 direction register (P1D) 002316 Compare interrupt source set register (CISR) 000416 Port P2 (P2) 002416 Timer A (low-order) (TAL) 000516 Port P2 direction register (P2D) 002516 Timer A (high-order) (TAH) 000616 Port P3 (P3) 002616 Timer B (low-order) (TBL) 000716 Port P3 direction register (P3D) 002716 Timer B (high-order) (TBH) 000816 Reserved 002816 Prescaler 1 (PRE1) 000916 Reserved 002916 Timer 1 (T1) Interrupt source set register (INTSET) 002A16 Timer count source set register (TCSS) 000016 000A16 000B16 Interrupt source discrimination register (INTDIS) 002B16 Timer X mode register (TXM) 000C16 Capture register 0 (low-order) (CAP0L) 002C16 Prescaler X (PREX) 000D16 Capture register 0 (high-order) (CAP0H) 002D16 Timer X (TX) 000E16 Capture register 1 (low-order) (CAP1L) 002E16 Transmit 2 / Receive 2 buffer register (TB2/RB2) 000F16 Capture register 1 (high-order) (CAP1H) 002F16 Serial I/O2 status register (SIO2STS) 001016 Compare register (low-order) (CMPL) 003016 Serial I/O2 control register (SIO2CON) 001116 Compare register (high-order) (CMPH) 003116 UART2 control register (UART2CON) 001216 Capture/compare register R/W pointer (CCRP) 003216 Baud rate generator 2 (BRG2) 001316 Capture software trigger register (CSTR) 003316 Reserved 001416 Compare register re-load register (CMPR) 003416 A/D control register (ADCON) 001516 Port P0P3 drive capacity control register (DCCR) 003516 A/D conversion register (low-order) (ADL) 001616 Pull-up control register (PULL) 003616 A/D conversion register (high-order) (ADH) 001716 Port P1P3 control register (P1P3C) 003716 On-chip oscillation division ratio selection register (RODR) 001816 Transmit 1 /Receive 1 buffer register (TB1/RB1) 003816 MISRG 001916 Serial I/O1 status register (SIO1STS) 003916 Watchdog timer control register (WDTCON) 001A16 Serial I/O1 control register (SIO1CON) 003A16 Interrupt edge selection register (INTEDGE) 001B16 UART1 control register (UART1CON) 003B16 CPU mode register (CPUM) 001C16 Baud rate generator 1 (BRG1) 003C16 Interrupt request register 1 (IREQ1) 001D16 Timer A, B mode register (TABM) 003D16 Interrupt request register 2 (IREQ2) 001E16 Capture/compare port register (CCPR) 003E16 Interrupt control register 1 (ICON1) 001F16 Timer source selection register (TMSR) 003F16 Interrupt control register 2 (ICON2) 0FE016 Flash memory control register 0 (FMCR0) (Note 2) 0FE116 Flash memory control register 1 (FMCR1) (Note 2) 0FE216 Flash memory control register 2 (FMCR2) (Note 2) Notes 1: Do not access to the SFR area including nothing. 2: Only flash memory version has this SFR area. Fig. 16 Memory map of special function register (SFR) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 18 of 117 7542 Group I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When “1” is set to the bit corresponding to a pin, this pin becomes an output port. When “0” is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. b7 b0 Port P0P3 drive capacity control register (DCCR: address 001516, initial value: 0016) Port P00 drive capacity bit Ports P01, P02 drive capacity bit Ports P03–P07 drive capacity bit Port P30 drive capacity bit Ports P31, P32 drive capacity bit Port P33 drive capacity bit Ports P34, P35 drive capacity bit Ports P36, P37 drive capacity bit 0 : Low 1 : High Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin version and PWQN0036KA-A package. Accordingly, the following settings are required; • Select P33 for the INT1 function. • Set direction registers of ports P26 and P27 to output. • Set direction registers of ports P35 and P36 to output. Note: Number of LED drive port (drive capacity is HIGH) is 8-port. Fig. 17 Structure of port P0P3 drive capacity control register b7 b0 Pull-up control register (PULL: address 001616, initial value: 0016) [Port P0P3 drive capacity control register] DCCR By setting the Port P0P3 drive capacity control register (address 001516), the drive capacity of the N-channel output transistor for the port P0 and port P3 can be selected. P00 pull-up control bit P01, P02 pull-up control bit P03–P07 pull-up control bit P30 pull-up control bit P31, P32 pull-up control bit [Pull-up control register] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. P33 pull-up control bit P34, P35 pull-up control bit 0 : Pull-up Off 1 : Pull-up On P36, P37 pull-up control bit Note : Pins set to output ports are disconnected from pull-up control. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 0017 16 ), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36, and P37 by program. Fig. 18 Structure of pull-up control register b7 b0 Port P1P3 control register (P1P3C: address 001716, initial value: 0016) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit 0 : CMOS level 1 : TTL level P10,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used Note: Keep setting the P36/INT1 input level selection bit to “0” (initial value) for 32-pin version and 36PJW-A package. Fig. 19 Structure of port P1P3 control register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 19 of 117 7542 Group Table 6 I/O port function table Pin Name P00(LED00)/CAP0 I/O format I/O port P0 •CMOS compatible • Capture function input input level (Note 1) • Key input interrupt •CMOS 3-state output P01(LED01)/CMP0 P02(LED02)/CMP1 P04(LED04)/RxD2 P05(LED05)/TxD2 P06(LED06)/SCLK2 P07(LED07)/SRDY2 I/O port P1 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0–P27/AN7 P30(LED10)/CAP1 SFRs related each pin Capture/Compare port register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register • Timer X function output Timer X mode register • Key input interrupt Pull-up control register Port P0P3 drive capacity control register • Serial I/O2 function input/output Serial I/O2 control register • Key input interrupt Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Pull-up control register Port P0P3 drive capacity control register • Serial I/O1 function input Serial I/O1 control register • Capture function input Capture/Compare port register Port P1P3 control register • Serial I/O1 function input/output Serial I/O1 control register Serial I/O1 control register Port P1P3 control register Serial I/O1 control register Port P1P3 control register • Timer X function input/output Timer X mode register • External interrupt input • A/D conversion input A/D control register • Compare function output • Key input interrupt P03(LED03)/TXOUT P10/RxD1/CAP0 Non-port function I/O port P2 (Note 2) I/O port P3 (Note 3) • Capture function input P31(LED11)/CMP2 P32(LED12)/CMP3 • Compare function output P33(LED13)/INT1 • External interrupt input P34(LED14) P35(LED15) P36(LED16)/INT1 • External interrupt input P37(LED17)/INT0 Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. 2: P26/AN6 and P27/AN7 do not exist for the 32-pin version and PWQN0036KA-A package. 3: P35 and P36/INT1 do not exist for the 32-pin version and PWQN0036KA-A package. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 20 of 117 Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Pull-up control register Port P0P3 drive capacity control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Port P1P3 control register Diagram No. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) 7542 Group (1) Port P00 (2) Ports P01, P02 Pull-up control Compare output control Direction register Direction register Port latch Data bus Data bus Port latch Drive capacity control Capture 0 input Capture 0 input control To key input interrupt generating circuit Drive capacity control Compare output To key input interrupt generating circuit P00 key-on wakeup selection bit (3) Port P03 (4) Port P04 Pull-up control P03/TXOUT output valid Serial I/O2 enable bit Receive enable bit Direction register Direction register Data bus Port latch Pull-up control Port latch Data bus Drive capacity control Drive capacity control Timer output Serial I/O2 input To key input interrupt generating circuit To key input interrupt generating circuit (5) Port P05 P04 key-on wakeup selection bit (6) Port P06 Pull-up control Serial I/O2 enable bit Transmit enable bit Direction register Data bus Pull-up control Serial I/O2 synchronous clock selection bit Serial I/O2 enable bit Serial I/O2 mode selection bit Serial I/O2 enable bit Direction register Port latch Drive capacity control Data bus Pull-up control Port latch Drive capacity control Serial I/O2 output To key input interrupt generating circuit Serial I/O2 clock output Serial I/O2 clock input To key input interrupt generating circuit (7) Port P07 Serial I/O2 mode selection bit Serial I/O2 enable bit SRDY2 output enable bit Direction register Data bus Pull-up control Port latch Drive capacity control Serial I/O2 ready output To key input interrupt generating circuit Fig. 20 Block diagram of ports (1) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 21 of 117 P06 key-on wakeup selection bit 7542 Group (8) Port P10 (9) Port P11 Serial I/O1 enable bit Receive enable bit P11/TxD1 P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Data bus Direction register Port latch P10, P12, P13 input level selection bit Data bus Port latch * Serial I/O1 input Capture 0 input control Capture 0 input Serial I/O1 output (11) Port P13 (10) Port P12 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Direction register Data bus Data bus Port latch P10, P12, P13 input level selection bit Port latch P10, P12, P13 input level selection bit Serial I/O1 ready output * Serial I/O1 clock output Serial I/O1 clock input * (13) Ports P20–P27 (12) Port P14 Pulse output mode Direction register Data bus Direction register Port latch Data bus Port latch Timer output CNTR0 interrupt input * P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 21 Block diagram of ports (2) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 22 of 117 A/D converter input Analog input pin selection bit 7542 Group (15) Ports P31, P32 (14) Port P30 Pull-up control Compare output control Direction register Direction register Data bus Pull-up control Data bus Port latch Port latch Drive capacity control Drive capacity control Capture 1 input Capture 1 input control Compare output (16) Port P33 (17) Ports P34, P35 Pull-up control Pull-up control Direction register Data bus Direction register Data bus Port latch Port latch Drive capacity control Drive capacity control INT1 input control INT1 input (18) Port P36 (19) Port P37 Pull-up control Pull-up control Direction register Data bus Direction register Data bus Port latch P3 input level selection bit INT1 input control INT1 input * Port latch Drive capacity control * P3 input level selection bit INT0 input P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 22 Block diagram of ports (3) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 23 of 117 * Drive capacity control 7542 Group Termination of unused pins • Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). We recommend processing unused pins through a resistor which can secure IOH(avg) or IOL(avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. Table 7 Termination of unused pins Termination 2 Termination 3 Termination 4 - When selecting key-on wakeup function, perform termination of input port. P34 When selecting CAP function, perform termination of input port. When selecting CMP 0 function, perform termination of output port. When selecting CMP 1 function, perform termination of output port. When selecting TX OUT function, perform termination of output port. When selecting RxD 2 function, perform termination of input port. When selecting TxD 2 function, perform termination of output port. When selecting external clock input, perform termination of output port. When selecting S RDY2 function, perform termination of output port. When selecting RxD 1 function, perform termination of input port. When selecting TxD 1 function, perform termination of output port. When selecting external clock input, perform termination of input port. When selecting S RDY1 function, perform termination of output port. When selecting CNTR input function, perform termination of input port. When selecting AN function, perform termination of input port. When selecting CAP function, perform termination of input port. When selecting CMP 2 function, perform termination of output port. When selecting CMP 3 function, perform termination of output port. When selecting INT function, perform termination of input port. - P35 Pin P00/CAP0 Termination 1 (recommend) I/O port P01/CMP0 P02/CMP1 P03/TXOUT P04/RxD2 P05/TxD2 P06/SCLK2 P07/SRDY2 P10/RxD1/CAP0 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0–P27/AN7 P30/CAP1 P31/CMP2 P32/CMP3 P33/INT1 P36/INT1 P37/INT0 VREF XIN XOUT Connect to Vss. When only on-chip oscillator is used, connect to VCC through a resistor. When external clock is input or when on-chip oscillator is used, open. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 When selecting internal clock output, perform termination of output port. When selecting CAP function, perform termination of input port. - - When selecting internal clock output, perform termination of output port. - - When selecting CNTR output function, perform termination of output port. - - - - - - - - - - - - - - - When selecting INT function, perform termination of input port. When selecting INT function, perform termination of input port. - - - - - - - - - - Page 24 of 117 - - 7542 Group Interrupts The 7542 Group interrupts are vector interrupts with a fixed priority scheme, and generated by 16 sources among 18 sources: 6 external, 11 internal, and 1 software. The interrupt sources, vector addresses(1) , and interrupt priority are shown in Table 8. Each interrupt except the BRK instruction interrupt has the interrupt request bit and the interrupt enable bit. These bits and the interrupt disable flag (I flag) control the acceptance of interrupt requests. Figure 23 shows an interrupt control diagram. An interrupt request is accepted when all of the following conditions are satisfied: • Interrupt disable flag.................................“0” • Interrupt request bit...................................“1” • Interrupt enable bit....................................“1” Though the interrupt priority is determined by hardware, priority processing can be performed by software using the above bits and flag. Table 8 Interrupt vector addresses and priority Interrupt source Priority Vector addresses (Note 1) High-order Low-order Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit 1 2 3 FFFD16 FFFB16 FFF916 FFFC16 FFFA16 FFF816 Serial I/O2 receive Serial I/O2 transmit 4 5 FFF716 FFF516 FFF616 FFF416 INT0 6 FFF316 FFF216 INT1 7 FFF116 FFF016 Key-on wake-up/ UART1 bus collision detection (Note 3) CNTR0 8 FFEF16 FFEE16 9 FFED16 FFEC16 Capture 0 10 FFEB16 FFEA16 Capture 1 11 FFE916 FFE816 Compare Timer X Timer A Timer B A/D conversion/ Timer 1 (Note 4) BRK instruction 12 13 14 15 16 FFE716 FFE516 FFE316 FFE116 FFDF16 FFE616 FFE416 FFE216 FFE016 FFDE16 17 FFDD16 FFDC16 Interrupt request generating conditions At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At completion of serial I/O2 data receive At completion of serial I/O2 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of UART1 bus collision detection At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of Capture 0 input At detection of either rising or falling edge of Capture 1 input At compare matched At timer X underflow At timer A underflow At timer B underflow At completion of A/D conversion At timer 1 underflow At BRK instruction execution Remarks Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Valid only when serial I/O2 is selected Valid only when serial I/O2 is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling edge) When UART1 bus collision detection interrupt is enabled. External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Compare interrupt source is selected. STP release timer underflow Non-maskable software interrupt Notes1: Vector addresses contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are discriminated by interrupt source discrimination register. 4: A/D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are discriminated by interrupt source discrimination register. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 25 of 117 7542 Group Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt acceptance Fig. 23 Interrupt control • Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor status register. This flag controls the acceptance of all interrupt requests except for the BRK instruction. When this flag is set to “1”, the acceptance of interrupt requests is disabled. When it is set to “0”, the acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and set to “0” with the CLI instruction. When an interrupt request is accepted, the contents of the processor status register are pushed onto the stack while the interrupt disable flag remains set to “0”. Subsequently, this flag is automatically set to “1” and multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI instruction within the interrupt processing routine. The contents of the processor status register are popped off the stack with the RTI instruction. • Interrupt Request Bits Once an interrupt request is generated, the corresponding interrupt request bit is set to “1” and remains “1” until the request is accepted. When the request is accepted, this bit is automatically set to “0”. Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software. • Interrupt Enable Bits The interrupt enable bits control the acceptance of the corresponding interrupt requests. When an interrupt enable bit is set to “0”, the acceptance of the corresponding interrupt request is disabled. If an interrupt request occurs in this condition, the corresponding interrupt request bit is set to “1”, but the interrupt request is not accepted. When an interrupt enable bit is set to “1”, the acceptance of the corresponding interrupt request is enabled. Each interrupt enable bit can be set to “0” or “1” by software. The interrupt enable bit for an unused interrupt should be set to “0”. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 26 of 117 • Interrupt Enable Setting The following interrupt sources can be set to valid or invalid by the interrupt source set register (000A16). • Key-on wakeup • UART1 bus collision detection interrupt • A/D conversion • Timer 1 interrupt • External Interrupt Pin Selection For the external interrupt INT1, the external input pin P33 or P36 can be selected by the INT1 input port selection bit in the interrupt edge selection register (bit 2 of address 003A16). However, since there is no P3 6 /INT1 pin in the 32-pin version PWQN0036KA-A package, select P3 3/INT 1 pin. By the key-on wakeup selection bit, enable/disable of a key-on wakeup of P00, P04, and P06 pins can be selected, respectively. 7542 Group b7 b0 Interrupt source set register (INTSET: address 000A16, initial value: 0016) Key-on wakeup interrupt valid bit b7 Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up/UART1 bus collision detection interrupt request bit CNTR0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued UART1 bus collision detection interrupt valid bit A/D conversion interrupt valid bit Timer 1 interrupt valid bit Not used (returns “0” when read) 0: Interrupt invalid 1: Interrupt valid b7 b0 Interrupt source discrimination register (INTDIS: address 000B16, initial value: 0016) Key-on wakeup interrupt discrimination bit b7 UART1 bus collision detection interrupt discrimination bit Timer 1 interrupt discrimination bit Not used (returns “0” when read) 0 : No interrupt request issued 1 : Interrupt request issued b0 0 : No interrupt request issued 1 : Interrupt request issued Interrupt edge selection register (INTEDGE : address 003A16, initial value: 0016) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 input port selection bit (Note 1) 0 : P36 1 : P33 Not used (returns “0” when read) P00 key-on wakeup selection bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled P04 key-on wakeup selection bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled P06 key-on wakeup selection bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled Note 1: P36 does not exist for the 32-pin version and the PWQN0036KA-A package. Select P33 for the INT1 function. b0 Interrupt request register 2 (IREQ2 : address 003D16, initial value : 0016) Capture 0 interrupt request bit Capture 1 interrupt request bit Compare interrupt request bit Timer X interrupt request bit Timer A interrupt request bit Timer B interrupt request bit A/D conversion/Timer 1 interrupt request bit Not used (returns “0” when read) (Do not write “1” to this bit.) A/D conversion interrupt discrimination bit b7 b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) b7 b0 Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up/UART1 bus collision detection interrupt enable bit CNTR0 interrupt enable bit b7 0 : Interrupts disabled 1 : Interrupts enabled b0 Interrupt control register 2 (ICON2 : address 003F16, initial value : 0016) Capture 0 interrupt enable bit Capture 1 interrupt enable bit Compare interrupt enable bit Timer X interrupt enable bit Timer A interrupt enable bit Timer B interrupt enable bit A/D conversion/Timer 1 interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit.) 0 : Interrupts disabled 1 : Interrupts enabled Fig. 24 Structure of Interrupt-related registers Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 27 of 117 7542 Group • Interrupt Request Generation, Acceptance, and Handling Interrupts have the following three phases. (i) Interrupt Request Generation An interrupt request is generated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the corresponding request bit is set to “1”. (ii) Interrupt Request Acceptance Based on the interrupt acceptance timing in each instruction cycle, the interrupt control circuit determines acceptance conditions (interrupt request bit, interrupt enable bit, and interrupt disable flag) and interrupt priority levels for accepting interrupt requests. When two or more interrupt requests are generated simultaneously, the highest priority interrupt is accepted. The value of the interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next interrupt acceptance timing point. (iii) Handling of Accepted Interrupt Request The accepted interrupt request is processed. Figure 25 shows the time up to execution in the interrupt processing routine, and Figure 26 shows the interrupt sequence. Figure 27 shows the timing of interrupt request generation, interrupt request bit, and interrupt request acceptance. • Interrupt Handling Execution When interrupt handling is executed, the following operations are performed automatically. (1) Once the currently executing instruction is completed, an interrupt request is accepted. (2) The contents of the program counters and the processor status register at this point are pushed onto the stack area in order from 1 to 3. 1.High-order bits of program counter (PCH) 2.Low-order bits of program counter (PCL) 3.Processor status register (PS) (3) Concurrently with the push operation, the jump address of the corresponding interrupt (the start address of the interrupt processing routine) is transferred from the interrupt vector to the program counter. (4) The interrupt request bit for the corresponding interrupt is set to “0”. Also, the interrupt disable flag is set to “1” and multiple interrupts are disabled. (5) The interrupt routine is executed. (6) When the RTI instruction is executed, the contents of the registers pushed onto the stack area are popped off in the order from 3 to 1. Then, the routine that was before running interrupt processing resumes. As described above, it is necessary to set the stack pointer and the jump address in the vector area corresponding to each interrupt to execute the interrupt processing routine. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 28 of 117 ■ Notes on Interrupts When setting the followings, the interrupt request bit may be set to “1”. •When switching external interrupt active edge Related registers: Interrupt edge selection register (address 003A16) Timer X mode register (address 002B16) Capture mode register (address 002016) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge select bit (active edge switch bit, trigger mode bit). ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). Interrupt request generated Interrupt request acceptance Interrupt sequence Stack push Vector fetch Main routine Interrupt routine starts Interrupt handling routine 7 cycles 0 to 16* cycles 7 to 23 cycles * When executing DIV instruction Fig. 25 Time up to execution in interrupt routine 7542 Group Push onto stack Vector fetch Execute interrupt routine φ SYNC RD WR Address bus PC Data bus S,SPS Not used S-1,SPS S-2,SPS PCH PCL PS BL BH AL AL,AH AH SYNC : CPU operation code fetch cycle (This is an internal signal that cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : “0016” or “0116” ([SPS] is a page selected by the stack page selection bit of CPU mode register.) Fig. 26 Interrupt sequence Push onto stack Vector fetch Instruction cycle Instruction cycle Internal clock φ SYNC ➀ T1 ➁ IR1 T2 IR2 T3 T1 T2 T3 : Interrupt acceptance timing points IR1 IR2 : Timings points at which the interrupt request bit is set to “1”. Note : Period 2 indicates the last φ cycle during one instruction cycle. (1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1. (2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2. The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2 separately. Fig. 27 Timing of interrupt request generation, interrupt request bit, and interrupt acceptance Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 29 of 117 7542 Group Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 28, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports. Port PXx “L” level output PULL register bit 3 = “0” * ** P07 output Port P07 Direction register = “1” Key input interrupt request Port P07 latch Falling edge detection PULL register bit 3 = “0” * ** P06 output Port P06 Direction register = “1” Port P06 latch Falling edge detection Port P06 key-on wakeup selection bit PULL register bit 3 = “0” * ** P05 output Port P05 Direction register = “1” Port P05 latch Falling edge detection PULL register bit 3 = “0” * ** P04 output Port P04 Direction register = “1” Port P04 latch Falling edge detection Port P04 key-on wakeup selection bit PULL register bit 2 = “1” * ** P03 input Port P03 Direction register = “0” Port P03 latch Falling edge detection PULL register bit 2 = “1” * ** P02 input Port P02 Direction register = “0” Port P02 latch Falling edge detection PULL register bit 1 = “1” * ** P01 input Port P01 Direction register = “0” Port P01 latch Falling edge detection PULL register bit 0 = “1” * ** P00 input Port P00 Direction register = “0” Port P00 latch Falling edge detection Port P00 key-on wakeup selection bit * P-channel transistor for pull-up ** CMOS output buffer Fig. 28 Connection example when using key input interrupt and port P0 block diagram Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 30 of 117 Port P0 Input read circuit 7542 Group Timers ●Timer X The 7542 Group has 4 timers: timer 1, timer X, timer A and timer B. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches “0”, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”. Timer X is an 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to “1”. Prescaler X is an 8-bit prescaler and counts the signal selected by the timer X count source selection bit. Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value, respectively. The value of prescaler X latch is set to Prescaler X when Prescaler X underflows. The value of timer X latch is set to Timer X when Timer X underflows. When writing to Prescaler X (PREX) is executed, the value is written to both the prescaler X latch and Prescaler X. When writing to Timer X (TX) is executed, the value is written to both the timer X latch and Timer X. When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out. • Frequency divider for timer According to the clock division selection bits (b7 and b6) of CPU mode register (003B16), the count source of frequency divider is set as follows; b7b6 = “00”(high-speed), “01”(middle-speed), “11”(double-speed): XIN b7b6 = “10”(On-chip oscillator): On-chip oscillator ●Timer 1 Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to “1”. Prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows. The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the signal which is the oscillation frequency divided by 16. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach “0016”, an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1 reach “0016”, an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. Timer X can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register. (1) Timer mode Prescaler X counts the count source selected by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach “0016”, an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X reach “0016”, an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is 1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and the value of Timer X is m. (2) Pulse output mode In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the CNTR0 pin. The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is “0”, the output of CNTR0 pin is started at “H” level. When this bit is “1”, the output is started at “L” level. Also, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting “1” to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P14 and P03 direction registers to output mode. (3) Event counter mode The timer A counts signals input from the P14/CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit . Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 31 of 117 7542 Group (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin. When the CNTR0 active edge switch bit is “0”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is “H”. The count is stopped while the pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is “L”. The count is stopped while the pin is “H”. b7 b0 Timer X mode register (TXM : address 002B16, initial value: 0016) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop Timer X can stop counting by setting “1” to the timer X count stop bit in any mode. Also, when Timer X underflows, the timer X interrupt request bit is set to “1”. Note on Timer X is described below; ■ Note on Timer X (1) CNTR0 interrupt active edge selection-1 CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. (2) CNTR0 interrupt active edge selection-2 According to the setting value of CNTR0 active edge switch bit, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the active edge switch bit. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). P03/TXOUT output valid bit 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR0 output) Not used (return “0” when read) Fig. 29 Structure of timer X mode register b7 b0 Timer count source set register (TCSS : address 002A16, initial value: 0016) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Timer A count source selection bits b4 b3 b2 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : On-chip oscillator output (Note 2) 1 1 1 : Not available Timer B count source selection bits b7 b6 b5 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : Timer A underflow 1 1 1 : Not available Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: On-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of CPUM. Fig. 30 Timer count source set register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 32 of 117 7542 Group Data bus Prescaler 1 latch (8) Timer 1 latch (8) Prescaler 1 (8) 1/16 “00” “01” “11” Clock division ratio selection bits XIN On-chip “10” oscillator CPU mode register Data bus Frequency Timer X count source selection bits divider 1/16 1/2 1/1 Prescaler X latch (8) Timer X latch (8) Pulse width measurement Timer mode Pulse output mode mode Prescaler X (8) P14/CNTR0 Timer 1 interrupt request Timer 1 (8) CNTR0 active edge switch bit “0” Event counter mode Timer X (8) Timer X count stop bit CNTR0 interrupt request bit “1” CNTR0 active “1” edge switch bit Q Q Port P14 latch Port P14 direction register Pulse output mode P03/TXOUT Port P03 latch P03/TXOUT output valid Port P03 direction register Fig. 31 Block diagram of timer 1 and timer X Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 33 of 117 Timer X interrupt request bit “0” Toggle flip-flop T R Writing to timer X latch Pulse output mode 7542 Group ●Timer A,B ■ Notes on Timer A, B Timer A and Timer B are 16-bit timers and counts the signal which is the oscillation frequency selected by setting of the timer count source set register (TCSS). Timer A and Timer B have the same function except of the count source clock selection. (1) Setting of timer value When “1: Write to only latch” is set to the timer A (B) write control bit, written data to timer register is set to only latch even if timer is stopped. Accordingly, in order to set the initial value for timer when it is stopped, set “0: Write to latch and timer simultaneously” to timer A (B) write control bit. The count source clock of Timer A is selected from among 1/2,1/ 16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and on-chip oscillator clock. The count source clock of Timer B is selected from among 1/2, 1/ 16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and Timer A underflow. Timer A (B) consists of the low-order of Timer A: TAL (Timer B: TBL) and the high-order of Timer A: TAH (Timer B: TBH). Timer A (B) is decremented by 1 when each time of the count clock is input. When the contents of Timer A (B) reach “0000 16 ”, an underflow occurs at the next count clock, and the timer latch is reloaded into timer. When Timer A (B) underflows, the Timer A (B) interrupt request bit is set to “1”. Timer A (B) has the Timer A (B) latch to retain the load value. The value of timer A (B) latch is set to Timer A (B) at the timing of Timer A (B) underflow. The division ratio of Timer A (B) is 1/(n+1) provided that the value of Timer A (B) is n. When writing to both the low-order of Timer A (B) and the high order of Timer A (B) is executed, writing to “latch only” or “latch and timer” can be selected by the setting value of the timer A (B) write control bit. When reading from Timer A (B) register is executed, the count value of Timer A (B) is read out. Be sure to write to/read out the low-order of Timer A (B) and the high-order of Timer A (B) in the following order; • Read Read the high-order of Timer A (B) first, and the low-order of Timer A (B) next and be sure to read both high-order and low-order. • Write Write to the low-order of Timer A (B) first, and the high-order of Timer A (B) next and be sure to write both low-order and high order. Timer A and Timer B can be used for the timing timer of Input capture and Output compare function. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 34 of 117 (2) Read/write of timer A Stop timer A to read/write its data when the system is in the following state; • CPU operation clock source: XIN oscillation • Timer A count source: On-chip oscillator output (3) Read/write of timer B Stop timer B to read/write its data when the system is in the following state; • CPU operation clock source: XIN oscillation • Timer B count source: Timer A underflow • Timer A count source: On-chip oscillator output 7542 Group b7 b0 b7 Timer A, B mode register (TABM : address 001D16, initial value: 0016) b0 Timer count source set register (TCSS : address 002A16, initial value: 0016) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Timer A write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer A count stop bit 0 : Count start 1 : Count stop Timer A count source selection bits b4 b3 b2 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : On-chip oscillator output (Note 2) 1 1 1 : Not available Timer B count source selection bits b7 b6 b5 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : Timer A underflow 1 1 1 : Not available Timer B write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer B count stop bit 0 : Count start 1 : Count stop Not used (return “0” when read) Compare 0, 1 modulation mode bit 0: Disabled 1: Enabled Compare 2, 3 modulation mode bit 0: Disabled 1: Enabled Fig. 32 Structure of timer A, B mode register Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: On-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of CPUM. Fig. 33 Timer count source set register Clock division ratio selection “00” bits “01” “11” XIN On-chip oscillator “10” CPU mode register Frequency divider Data bus 1/2 1/16 1/32 Timer A (low-order) latch (8) 1/64 Timer A (high-order) latch (8) Timer A write control bit 1/128 1/256 On-chip oscillator Timer A (low-order) (8) Timer A count source selection bits Timer A (high-order) (8) Timer A count stop bit Frequency divider 1/2 Timer A interrupt request Compare Capture Data bus 1/16 1/32 Timer B (low-order) latch (8) 1/64 Timer B (high-order) latch (8) Timer B write control bit 1/128 1/256 Timer B (low-order) (8) Timer B count source selection bits Timer B count stop bit Fig. 34 Block diagram of timer A and timer B Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 35 of 117 Timer B (high-order) (8) Timer B interrupt request Compare Capture 7542 Group Output compare 7542 group has 4-output compare channels. Each channel (0 to 3) has the same function and can be used to output waveform by using count value of either Timer A or Timer B. The source timer for each channel is selected by setting value of the compare x (x = 0, 1, 2, 3) timer source bit. Timer A and Timer B can be selected for the source timer to each channel, respectively. To use each compare channel, set “1” to the compare x output port bit and set the port direction register corresponding to compare channel to output mode. The compare value for each channel is set to the compare register (low-order) and compare register (high-order). Writing to the register for each channel is controlled by setting value of compare register write pointer. Writing to each register is in the following order; 1.Set the value of corresponded output compare channel to the compare register write pointer. 2.Write a value to the compare register (low-order) and compare register (high-order). 3.Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31) re-load bit. When “1” is set to the compare latch y re-load bit, the value set to the compare register is loaded to compare latch when the next timer underflow. ■ Notes on Output Compare • When the selected source timer of each compare channel is stopped, written data to compare register is loaded to the compare latch simultaneously. • Do not write the same data to both of compare latch x0 and x1. • When setting value of the compare latch is larger than timer setting value, compare match signal is not generated. Accordingly, the output waveform is fixed to “L” or “H” level. However, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. Accordingly, compare match interrupt occurs. • When the compare x trigger enable bit is cleared to “0” (disabled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to “L” or “H” level. However, in this case, the compare match signal is generated. Accordingly, compare match interrupt occurs. b7 b0 Capture/compare register R/W pointer (CCRP : address 001216, initial value: 0016) Compare register R/W pointer b2 b1 b0 0 0 0 : Compare latch 00 0 0 1 : Compare latch 01 0 1 0 : Compare latch 10 0 1 1 : Compare latch 11 1 0 0 : Compare latch 20 1 0 1 : Compare latch 21 1 1 0 : Compare latch 30 1 1 1 : Compare latch 31 When count value of timer and setting value of compare latch is matched, compare output trigger occurs. When “1: Enabled” is set to the compare trigger x enable bit, the output waveform from port is inverted by compare trigger. When “0: Disabled” is set to the compare trigger x enable bit, the output waveform is not inverted, so port output can be fixed to “H” or “L”. When “0: Positive” is set to the compare x output level latch, the compare output waveform is turned to “H level” at compare latch x0’s match and turned to “L level” at compare latch x1’s match. When “1 :Negative” is set to the compare x output level latch, the compare output waveform is turned to “L level” at compare latch x0’s match and turned to “H level” at compare latch x1’s match. The compare output level of each channel can be confirmed by reading the compare x output status bit. Compare output interrupt is available when match of each compare channel and timer count value. The interrupt request from each channel can be disabled or enabled by setting value of compare latch y interrupt source bit. Compare 0,1 (2,3) modulation mode In compare modulation mode, modulation waveform can be generated by using compare channel 0 and 1, or compare channel 2 and 3. To use this mode, • Set “1: Enabled” to the compare 0,1 (2, 3) modulation mode bit. • Set Timer A underflow for Timer B count source. • Set Timer A for the timer source of compare channel 0 (2). • Set Timer B for the timer source of compare channel 1 (3). In this mode, AND waveform of compare 0 (1) and compare 2 (3) is generated from Port P01 and P31, respectively. Accordingly, in order to use this mode, set “1” to the compare 0 output port bit or compare 2 output port bit. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 36 of 117 Not used (returns “0” when read) Capture register 0 R/W pointer 0: Capture latch 00 1: Capture latch 01 Capture register 1 R/W pointer 0: Capture latch 10 1: Capture latch 11 Not used (returns “0” when read) Fig. 35 Structure of capture/compare register R/W pointer b7 b0 Compare register re-load register (CMPR : address 001416, initial value: 0016) Compare latch 00, 01 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 10, 11 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 20, 21 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 30, 31 re-load bit 0: Re-load disabled 1: Re-load at next underflow Not used (returns “0” when read) Fig. 36 Structure of compare register re-load register 7542 Group b7 b0 Capture/Compare port register (CCPR : address 001E16, initial value: 0016) Capture 0 input port bits b1 b0 0 0: Capture from P00 0 1: Capture from P10 1 0: Ring/512 1 1: Not available b7 b0 Capture/Compare status register (CCSR : address 002216, initial value: 0016) Compare 0 output status bit 0: “L” level output 1: “H” level output Compare 1 output status bit 0: “L” level output 1: “H” level output Compare 0 output port bit 0: P01 is I/O port 1: P01 is Compare 0 Compare 2 output status bit 0: “L” level output 1: “H” level output Compare 1 output port bit 0: P02 is I/O port 1: P02 is Compare 1 Capture 1 input port bit 0: Capture from P30 1: Ring/512 Compare 3 output status bit 0: “L” level output 1: “H” level output Compare 2 output port bit 0: P31 is I/O port 1: P31 is Compare 2 Capture 0 status bit 0: latch 00 captured 1: latch 01 captured Compare 3 output port bit 0: P32 is I/O port 1: P32 is Compare 3 Capture 1 status bit 0: latch 10 captured 1: latch 11 captured Not used (returns “0” when read) Not used (returns “0” when read) Fig. 37 Structure of capture/compare port register b7 Fig. 40 Structure of capture/compare status register b0 Timer source selection register (TMSR : address 001F16, initial value: 0016) Compare 0 timer source bit Compare 1 timer source bit b7 b0 Compare interrupt source set register (CISR : address 002316, initial value: 0016) Compare latch 00 interrupt source bit Compare 2 timer source bit Compare latch 01 interrupt source bit Compare 3 timer source bit Compare latch 10 interrupt source bit Capture 0 timer source bit Compare latch 11 interrupt source bit Capture 1 timer source bit Compare latch 20 interrupt source bit Not used (returns “0” when read) Compare latch 21 interrupt source bit 0: Timer A 1: Timer B Compare latch 30 interrupt source bit Compare latch 31 interrupt source bit Fig. 38 Structure of timer source selection register b7 0: Disabled 1: Enabled b0 Compare output mode register (CMOM : address 002116, initial value: 0016) Compare 0 output level latch 0: Positive 1: Negative Compare 1 output level latch 0: Positive 1: Negative Compare 2 output level latch 0: Positive 1: Negative Compare 3 output level latch 0: Positive 1: Negative Compare 0 trigger enable bit 0: Disabled 1: Enabled Compare 1 trigger enable bit 0: Disabled 1: Enabled Compare 2 trigger enable bit 0: Disabled 1: Enabled Compare 3 trigger enable bit 0: Disabled 1: Enabled Fig. 39 Structure of compare output mode register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 37 of 117 Fig. 41 Structure of compare interrupt source register 7542 Group Compare latch 00 Compare latch 01 P01/CMP0 Timer A latch Wave latch channel 0 Timer A counter Compare 0 timer source bit Timer B counter Compare channel 0 P02/CMP1 P31/CMP2 P32/CMP3 Timer B latch Compare channel 1 Compare channel 2 Compare channel 3 Fig. 42 Block diagram of output compare Data bus Compare register write pointer (001216, bits 0 to 2) Compare buffer 00 (16) Compare buffer 01 (16) Compare latch 00, 01 re-load bit (001416, bit 0) Compare latch 00 (16) Compare 0 output port bit (001E16, bit 2) Compare 0 output status bit (002216, bit 0) Compare 0 trigger enable bit (002116, bit 4) Compare latch 01 (16) Compare register I/O port Output latch P01/CMP0 Timer A counter (16) Compare 0 output level latch (002116, bit 0) Compare interrupt Fig. 43 Block diagram of compare channel 0 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 38 of 117 Compare latch 00 interrupt source bit (002316, bit 0) Compare latch 01 interrupt source bit (002316, bit 1) Timer B counter (16) Compare 0 timer source bit (001F16, bit 0) 7542 Group Data bus P01/CMP0 Compare register write pointer (001216, bits 0 to 2) I/O port Compare buffer 00 (16) Compare buffer 01 (16) Compare latch 00, 01 re-load bit (001416, bit 0) Compare 0 output port bit (001E16, bit 2) Compare latch 00 (16) Compare 0 output status bit (002216, bit 0) Compare latch 01 (16) Compare register Compare 0 trigger enable bit (002116, bit 4) Output latch Timer A counter (16) Compare 0 output level latch (002116, bit 0) Compare 0 (1) timer source bits (001F16, bit 0 (bit 1) Compare 1 output status bit (002216, bit 1) Underflow Compare 1 trigger enable bit (002116, bit 5) Timer B counter (16) Output latch Compare 1 output level latch (002116, bit 1) Compare register Compare latch 10 (16) Compare latch 11 (16) Compare latch 10, 11 re-load bit (001416, bit 1) Compare buffer 10 (16) Compare register write pointer (001216, bits 0 to 2) Data bus Fig. 44 Block diagram at modulation mode Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 39 of 117 Compare buffer 11 (16) 7542 Group Timer count clock Re-load the count value Timer underflow Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Compare latch 00 000B Compare latch 01 0005 Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit 0 1 0 Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Fig. 45 Output compare mode (general waveform) Timer count clock Re-load the count value Timer underflow Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Compare latch 00 000B 000E Compare latch 01 0005 000C Compare latch 00 write Compare latch 01 write Compare latch 00, 01 re-load bit Compare latch 00, 01 re-load signal Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit 0 1 Fig. 46 Output compare mode (compare register write timing) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 40 of 117 0 1 0 7542 Group Carrier wave generated by Compare 0 Timer A count clock Timer A underflow Timer A count value 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 Compare latch 00 0006 Compare latch 01 0002 Compare 00 match Compare 01 match Compare 0 output Compare 0 output status bit 1 0 1 0 1 Modulation of output waveform generated by Compare 1 Timer A underflow Compare 0 output Timer B count value 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 Compare latch 10 0004 Compare latch 11 0001 Compare 10 match Compare 11 match Compare 1 output Compare interrupt Compare 1 output status bit 0 1 0 1 0 Port outptu wavefowm Modulation output Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Fig. 47 Output compare mode (compare 0, 1 modulation mode) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 41 of 117 1 7542 Group 1. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Positive”. Compare 0 output Compare 1 output Modulation output 2. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Positive”. Compare 0 output Compare 1 output Modulation output 3. When Compare 0 output level latch is “Positive”, Compare 1 output level latch is “Negative”. Compare 0 output Compare 1 output Modulation output 4. When Compare 0 output level latch is “Negative”, Compare 1 output level latch is “Negative”. Compare 0 output Compare 1 output Modulation output Fig. 48 Output compare mode (compare 0, 1 modulation mode: effect of output level latch) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 42 of 117 7542 Group Input capture ■ Notes on Input Capture 7542 group has 2-input capture channels. Each channel (0 and 1) has the same function and can be used to capture count value of either Timer A or Timer B. The source timer for each channel is selected by setting value of the capture x (x = 0, 1) timer source bit. Timer A and Timer B can be selected for the source timer to each channel, respectively. • If the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. Accordingly, some countermeasure by software is recommended, for example comparing the values that twice of read. • When the on-chip-oscillator is selected for Timer A count source, Timer A cannot be used for the capture source timer. Timer B cannot be used for the capture source timer when the system is in the following state; • CPU operation clock source: XIN oscillation • Timer B count source: Timer A underflow • Timer A count source: On-chip oscillator output • When writing “1” to capture latch x0 (x1) software trigger bit of capture latch x0 and x1 at the same time, or external trigger and software trigger occur simultaneously, the set value of capture x status bit is undefined. • When setting the interrupt active edge selection bit and noise filter clock selection bit of external interrupt CAP 0 , CAP1 , the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ➀ Set the corresponding interrupt enable bit to “0” (disabled). ➁ Set the interrupt edge selection bit or noise filter clock selection bit. ➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the corresponding interrupt enable bit to “1” (enabled). • When the capture interrupt is used as the interrupt for return from stop mode, set the capture x noise filter clock selection bits to “00 (Filter stop)”. To use each capture channel, set the capture x input port bits and set the port direction register corresponding to capture channel to input mode. The input capture circuit retains the count value of selected timer when external trigger is input. The timer count value is retained to the capture latch x0 when rising edge is input and is retained to the capture latch x1 when falling edge is input. The count value of timer can be retained by software by capture y (y = 00, 01, 10, 11) software trigger bit too. When “1” is set to this bit, count value of timer is retained to the corresponded capture latch. When reading from the capture y software trigger bit is executed, “0” is read out. The latest status of capture latch can be confirmed by reading of the capture x status bit. This bit indicates the capture latch which latest data is in. The valid trigger edge for capture interrupt is set by the capture x interrupt edge selection bits. (Regardless of the setting value of capture x interrupt edge selection bits, timer count values for both edges are retained to the capture latch.) Each capture input has the noise filter circuit that judges continuous 4-time same level with sampling clock to be valid. The sampling clock of noise filter is set by the capture x noise filter clock selection bits. Reading from the register for each channel is controlled by setting value of the capture register read pointer. Reading from each register is in the following order; 1.Set the value of the corresponded input capture channel to the capture register read pointer. 2.Read from the capture register (low-order) and capture register (high-order). Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 43 of 117 7542 Group b7 b7 b0 b0 Capture software trigger register (CSTR : address 001316, initial value: 0016) Capture latch 00 software trigger bit Capture register 0 (Low-order) (CAP0L : address 000C16) b7 b7 b7 Capture latch 01 software trigger bit b0 Capture register 0 (High-order) (CAP0H : address 000D16) Capture latch 10 software trigger bit Capture register 1 (Low-order) (CAP1L : address 000E16) Each software trigger occurs by setting “1” to corresponding bit. (returns “0” when read) Capture latch 11 software trigger bit b0 Not used (returns “0” when read) b0 Capture register 1 (High-order) (CAP1H : address 000F16) Fig. 49 Structure of capture software trigger register b7 b0 Capture mode register (CAPM : address 002016, initial value: 0016) Capture 0 interrupt edge selection bits b1 b0 0 0: Rising and falling edge 0 1: Rising edge 1 0: Falling edge 1 1: Not available Capture 1 interrupt edge selection bits b3 b2 0 0: Rising and falling edge 0 1: Rising edge 1 0: Falling edge 1 1: Not available Capture 0 noise filter clock selection bits b5 b4 0 0: Filter stop 0 1: f(XIN) 1 0: f(XIN)/8 1 1: f(XIN)/32 Capture 1 noise filter clock selection bits b7 b6 0 0: Filter stop 0 1: f(XIN) 1 0: f(XIN)/8 1 1: f(XIN)/32 Fig. 50 Structure of capture software trigger register/capture mode register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 44 of 117 7542 Group P00/CAP0 Trigger input channel 0 Capture latch 00 P10/CAP0 Timer A latch Capture latch 01 Ring /512 Timer A counter Capture 0 timer source bit Timer B counter P30/CAP1 Capture channel 0 Ring /512 Timer B latch Capture channel 1 Fig. 51 Block diagram of input capture Data bus Capture register 0 read pointer (001216, bit 4) Capture register Capture latch 00 (16) Capture 0 status bit (002216, bit 4) Capture pointer (001316, bits 4, 5) Capture latch 00 software trigger bit (001316, bit 0) Ring/512 Digital filter P10/CAP0 P00/CAP0 Capture 0 input port bits (001E16, bits 0, 1) Capture 0 noise filter clock selection bits (002016, bits 4, 5) Fig. 52 Block diagram of capture channel 0 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 45 of 117 Capture latch 01 (16) Rising Capture trigger Capture 0 interrupt edge selection bits (002016, bits 0, 1) Falling Capture latch 0 (16) Capture interrupt Capture 0 timer source bit (001F16, bit 4) Timer A counter (16) Timer B counter (16) 7542 Group Re-load the timer count value Timer underflow Capture input wave Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Overwrite Capture latch 00 XXXX Capture latch 01 000A 0001 XXXX 000C 000F 0005 Capture interrupt Capture x (x=0, 1) status bit 1 0 1 0 1 0 Fig. 53 Capture interrupt edge selection = “rising edge” Re-load the timer count value Timer underflow Capture input wave Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Overwrite Capture latch 00 XXXX 000A 0001 XXXX Capture latch 01 000C 000F 0005 Capture interrupt Capture x (x=0, 1) status bit 1 0 Fig. 54 Capture interrupt edge selection = “rising and falling edge” Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 46 of 117 1 0 1 0 7542 Group Serial Interface (1) Clock Synchronous Serial I/O1 Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6) to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. The 7542 Group has Serial I/O1 and Serial I/O2. Except that Serial I/O1 has the bus collision detection function and the TXD2 output structure for Serial I/O2 is CMOS only, they have the same function. ●Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Serial I/O1 control register Address 001816 Receive buffer register 1 P10/RXD1/CAP0 Address 001A16 Receive buffer full flag (RBF) Receive shift register 1 Receive interrupt request (RI) Shift clock Clock control circuit P12/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit XIN Baud rate generator 1 Address 001C16 1/4 P13/SRDY1 F/F 1/4 Clock control circuit Falling-edge detector Shift clock P11/TXD1 Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 55 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD1 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD1 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register 1 (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD1 pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 56 Operation of clock synchronous serial I/O1 function Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 47 of 117 7542 Group The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. (2) Asynchronous Serial I/O1 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. Data bus Address 001816 P10/RXD1/CAP0 Serial I/O1 control register Address 001A16 Receive buffer register 1 OE Character length selection bit ST detector 7 bits Receive shift register 1 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 8 bits PE FE UART1 control register Address 001B16 SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P12/SCLK1 XIN BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 Address 001C16 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P11/TXD1 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 1 Character length selection bit Transmit buffer register 1 Address 001816 Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Data bus Fig. 57 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer 1 write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 TBE=0 TSC=1✽ TBE=1 ST D0 D1 SP ST D0 ✽ 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Receive buffer 1 read signal SP D1 Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 Serial input RXD1 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 58 Operation of UART serial I/O1 function Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 48 of 117 7542 Group [Transmit buffer register 1/receive buffer register 1 (TB1/ RB1)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O1 status register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O1 control register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 control register (UART1CON)] 001B16 The UART1 control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TxD1 pin. [Baud rate generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 49 of 117 ■ Notes on Serial I/O1 • Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➃ Set the serial I/O transmit interrupt enable bit to “1” (enabled). • I/O pin function when serial I/O1 is enabled. The functions of P12 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0” : P12 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY1 output pin. (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit “0”: P12 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. 7542 Group b7 b0 Serial I/O1 status register (SIO1STS : address 001916, initial value: 8016) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16, initial value: 0016) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P13 pin operates as ordinary I/O pin 1: P13 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P10 to P13 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P10 to P13operate as serial I/O pins) b7 b0 UART1 control register (UART1CON : address 001B16, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P11/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) Fig. 59 Structure of serial I/O1-related registers Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 50 of 117 7542 Group Bus collision detection (SIO1) b7 b0 Interrupt source set register (INTSET: address 000A16, initial value: 0016) SIO1 can detect a bus collision by setting UART1 bus collision detection interrupt enable bit. When transmission is started in the clock synchronous or asynchronous (UART) serial I/O mode, the transmit pin TxD 1 is compared with the receive pin RxD1 in synchronization with rising edge of transmit shift clock. If they do not coincide with each other, a bus collision detection interrupt request occurs. When a transmit data collision is detected between LSB and MSB of transmit data in the clock synchronous serial I/O mode or between the start bit and stop bit of transmit data in UART mode, a bus collision detection can be performed by both the internal clock and the external clock. Key-on wakeup interrupt valid bit UART1 bus collision detection interrupt valid bit A/D conversion interrupt valid bit Timer 1 interrupt valid bit Not used (returns “0” when read) 0: Interrupt invalid 1: Interrupt valid b7 b0 Interrupt source discrimination register (INTDIS: address 000B16, initial value: 0016) Key-on wakeup interrupt discrimination bit UART1 bus collision detection interrupt discrimination bit A/D conversion interrupt discrimination bit A block diagram is shown in Fig. 61. A timing diagram is shown in Fig. 62. Timer 1 interrupt discrimination bit Not used (returns “0” when read) 0: Interrupt does not occur 1: Interrupt occurs Note: Bus collision detection can be used when SIO1 is operating at full-duplex communication. When SIO1 is operating at half-duplex communication, set bus collision detection interrupt to be disabled. b7 b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up/UART1 bus collision detection interrupt request bit CNTR0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up/UART1 bus collision detection interrupt enable bit CNTR0 interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled Fig. 60 Bus collision detection circuit related registers UART1 bus collision detection interrupt discrimination bit (Address 000B16, bit 1) TxD1 RxD1 D Q Shift clock Key-on wakeup/ UART1 bus collision detection interrupt request bit (Address 003C16, bit 6) Key-on wakeup interrupt request UART1 bus collision detection interrupt valid bit (Address 000A16, bit 1) Fig. 61 Block diagram of bus collision detection interrupt circuit Transmit shift clock Bus collision detection interrupt generation Transmit pin TxD1 Receive pin RxD1 Data collision Fig. 62 Timing diagram of bus collision detection interrupt Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 51 of 117 7542 Group ●Serial I/O2 (1) Clock Synchronous Serial I/O2 Mode Clock synchronous serial I/O2 mode can be selected by setting the serial I/O2 mode selection bit of the serial I/O2 control register (bit 6) to “1”. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus Serial I/O2 control register Address 002E16 Receive buffer register 2 Receive buffer full flag (RBF) Receive shift register 2 P04/RXD2 Shift clock Address 003016 Receive interrupt request (RI) Clock control circuit P06/SCLK2 XIN Serial I/O2 synchronous clock selection bit Frequency division ratio 1/(n+1) BRG count source selection bit Baud rate generator 2 Address 003216 1/4 P07/SRDY2 Clock control circuit Falling-edge detector F/F P05/TXD2 1/4 Shift clock Transmit shift completion flag (TSC) Transmit shift register 2 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer register 2 Address 002E16 Transmit buffer empty flag (TBE) Serial I/O2 status register Address 002F16 Data bus Fig. 63 Block diagram of clock synchronous serial I/O2 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD2 D0 D1 D2 D3 D4 D5 D6 D7 Serial input RxD2 D0 D1 D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Write pulse to receive/transmit buffer register 2 (address 002E16) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD2 pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Fig. 64 Operation of clock synchronous serial I/O2 function Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 52 of 117 7542 Group The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. (2) Asynchronous Serial I/O2 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O2 mode selection bit of the serial I/O2 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. Data bus Address 002E16 P04/RXD2 Serial I/O2 control register Address 003016 Receive buffer full flag (RBF) Receive interrupt request (RI) Receive buffer register 2 OE Character length selection bit ST detector 7 bits Receive shift register 2 1/16 8 bits PE FE UART2 control register SP detector Address 003116 Clock control circuit Serial I/O2 synchronous clock selection bit P06/SCLK2 XIN BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator 2 Address 003216 1/4 ST/SP/PA generator Transmit shift completion flag (TSC) 1/16 P05/TXD2 Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit shift register 2 Character length selection bit Transmit buffer register 2 Address 002E16 Transmit buffer empty flag (TBE) Serial I/O2 status register Address 002F16 Data bus Fig. 65 Block diagram of UART serial I/O2 Transmit or receive clock Transmit buffer 2 write signal TBE=0 TSC=0 TBE=1 Serial output TXD2 TBE=0 TSC=1✽ TBE=1 ST D0 D1 SP ST D0 Receive buffer 2 read signal SP D1 ✽ 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) Generated at 2nd bit in 2-stop-bit mode RBF=0 RBF=1 Serial input RXD2 ST D0 D1 SP RBF=1 ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 66 Operation of UART serial I/O2 function Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 53 of 117 7542 Group [Transmit buffer register 2/receive buffer register 2 (TB2/ RB2)] 002E16 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O2 status register (SIO2STS)] 002F16 The read-only serial I/O2 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O2 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O2 enable bit SIOE (bit 7 of the serial I/O2 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O2 status register are initialized to “0” at reset, but if the transmit enable bit of the serial I/O2 control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O2 control register (SIO2CON)] 003016 The serial I/O2 control register consists of eight control bits for the serial I/O2 function. [UART2 control register (UART2CON)] 003116 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. [Baud rate generator 2 (BRG2)] 003216 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 54 of 117 ■ Notes on Serial I/O2 • Serial I/O interrupt When setting the transmit enable bit to “1”, the serial I/O transmit interrupt request bit is automatically set to “1”. When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. ➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled). ➁ Set the transmit enable bit to “1”. ➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or more instructions have been executed. ➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled). • I/O pin function when serial I/O2 is enabled. The functions of P06 and P07 are switched with the setting values of a serial I/O2 mode selection bit and a serial I/O2 synchronous clock selection bit as follows. (1) Serial I/O2 mode selection bit → “1” : Clock synchronous type serial I/O is selected. Setup of a serial I/O2 synchronous clock selection bit “0” : P06 pin turns into an output pin of a synchronous clock. “1” : P06 pin turns into an input pin of a synchronous clock. Setup of a SRDY2 output enable bit (SRDY) “0” : P07 pin can be used as a normal I/O pin. “1” : P07 pin turns into a SRDY2 output pin. (2) Serial I/O2 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O2 synchronous clock selection bit “0”: P06 pin can be used as a normal I/O pin. “1”: P06 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P07 pin. It can be used as a normal I/O pin. 7542 Group b7 b0 Serial I/O2 status register (SIO2STS : address 002F16, initial value: 8016) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) b7 b0 Serial I/O2 control register (SIO2CON : address 003016, initial value: 0016) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O2 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY2 output enable bit (SRDY) 0: P07 pin operates as ordinary I/O pin 1: P07 pin operates as SRDY2 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O2 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O2 enable bit (SIOE) 0: Serial I/O2 disabled (pins P04 to P07 operate as ordinary I/O pins) 1: Serial I/O2 enabled (pins P04 to P07 operate as serial I/O pins) b7 b0 UART2 control register (UART2CON : address 003116, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits Not used (return “0” when read) (Do not write “1” to this bit.) Not used (return “1” when read) Fig. 67 Structure of serial I/O2-related registers Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 55 of 117 7542 Group A/D Converter b7 b0 The functional blocks of the A/D converter are described below. A/D control register (ADCON : address 003416, initial value: 1016) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 (Note 1) 111 : P27/AN7 (Note 1) A/D conversion clock selection bit (Note 2) 0 : f(XIN)/2 1 : f(XIN) A/D conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns “0” when read) [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/ D conversion. [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 3 is the A/D conversion clock selection bit. When “0” is set to this bit, the A/D conversion clock is f(XIN)/2 and the A/D conversion time is 122 cycles of f(XIN). When “1” is set to this bit, the A/D conversion clock is f(XIN) and the A/D conversion time is 61 cycles of f(X IN). Bit 4 is the A/D conversion completion bit. The value of this bit remains at “0” during A/D conversion, and changes to “1” at completion of A/D conversion. A/D conversion is started by setting this bit to “0”. Notes 1: These can be used only for 36 pin version. 2: A/D conversion clock=f(XIN) can be used only when ceramic oscillation or on-chip oscillator is used. Select f(XIN)/2 when RC oscillation is used. Fig. 68 Structure of A/D control register [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF by 1024, and outputs the divided voltages. Read 8-bit (Read only address 003516) b7 [Channel selector] The channel selector selects one of ports P27/AN7 to P2 0/AN0, and inputs the voltage to the comparator. Read 10-bit (read in order address 003616, 003516) b7 [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the control circuit sets the A/D conversion completion bit and the A/D interrupt request bit to “1”. Because the comparator is constructed linked to a capacitor, set f(XIN) in order that the A/D conversion clock is 250 kHz or over during A/D conversion. ■ Notes on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value.. (2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 56 of 117 (Address 003516) b9 b8 b7 b0 b6 b5 b4 b3 b0 b9 (Address 003616) b7 (Address 003516) b7 b6 b2 b8 b0 b5 b4 b3 b2 b1 b0 Note: High-order 6-bit of address 003616 returns “0” when read. Fig. 69 Structure of A/D conversion register 7542 Group Data bus b7 b0 A/D control register (Address 003416) 3 A/D interrupt request A/D control circuit Channel selector P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 Comparator A/D conversion register (high-order) (Address 003616) A/D conversion register (low-order) (Address 003516) 10 Resistor ladder f(XIN) f(XIN)/2 VREF Fig. 70 Block diagram of A/D converter Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 57 of 117 VSS 7542 Group Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. Standard operation of watchdog timer The watchdog timer stops when the watchdog timer control register (address 0039 16) is not set after reset. Writing an optional value to the watchdog timer control register (address 0039 16 ) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 0039 16) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction function selection bit and watchdog timer H count source selection bit are read. Initial value of watchdog timer By a reset or writing to the watchdog timer control register (address 0039 16 ), the watchdog timer H is set to “FF 16 ” and the watchdog timer L is set to “FF16”. Operation of watchdog timer H count source selection bit A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is “0”, the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz. When this bit is “1”, the count source becomes f(XIN)/16. In this case, the detection time is 512 µs at f(XIN)=8 MHz. This bit is cleared to “0” after reset. Operation of STP instruction function selection bit When “0” is set to STP instruction function selection bit, system enters into the stop mode at the STP instruction execution. When “1” is set to this bit, internal reset occurs at the STP instruction execution. This bit is set to “1” by program, but it cannot be changed to “0” . This bit is cleared to “0” after reset. ■ Notes on Watchdog Timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the oscillation stabilizing time after the STP instruction is released. In order to avoid the underflow of the watchdog timer, the watchdog timer control register must be written just before executing the STP instruction. 3. The STP instruction function selection bit (bit 6 of watchdog timer control register (address 0039 16)) can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. 4. A count source of watchdog timer is affected by the clock division selection bit of the CPU mode register. The f(XIN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the CPU clock. Source clock selection (auto-switch depending on setting of CPUM) Data bus Write “FF16” to the watchdog timer control register Watchdog timer L (8) 1/16 XIN clock On-chip oscillator “0” “1” Watchdog timer H (8) Write "FF16" to the watchdog timer control register Watchdog timer H count source selection bit STP Instruction function selection bit STP Instruction Reset circuit RESET Fig. 71 Block diagram of watchdog timer b7 b0 Watchdog timer control register (WDTCON: address 003916, initial value: 3F16) Watchdog timer H (read only for high-order 6-bit) STP instruction function selection bit 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(XIN)/16 or on-chip oscillator/16 Fig. 72 Structure of watchdog timer control register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 58 of 117 Internal reset 7542 Group Reset Circuit Poweron The 7542 group starts operation by the on-chip oscillator after system is released from reset. Accordingly, when the rising of power supply voltage passes 2.2V, set the reset input voltage to become below 0.2Vcc (0.44V). Moreover, switch CPU clock to the external oscillator after the rising of power supply voltage passes the minimum operation voltage and after an oscillation is stabilized. RESET VCC Power source voltage 0V Reset input voltage 0V (Note) 0.2 VCC Note : Reset release voltage Vcc = 2.2 V Note: The minimum operation voltage is decided by the division ratio of an external oscillator's frequency and a CPU clock. Decide on an external oscillator's oscillation stabilizing time after fully evaluating an oscillator's stabilizing time used. RESET VCC Power source voltage detection circuit Fig. 73 Example of reset circuit Clock from on-chip oscillator RING φ RESET RESETOUT SYNC Address ? Data ? ? 8-13 clock cycles Fig. 74 Timing diagram at reset Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 59 of 117 ? ? ? ? FFFC ? ? ? FFFD ADL ADH,ADL ADH Reset address from the vector table Notes 1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock at average of Vcc = 5 V. 2 : The mark “?” means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET. 7542 Group Address Register contents 0016 (1) Port P0 direction register (P0D) 000116 (2) Port P1 direction register (P1D) 000316 (3) Port P2 direction register (P2D) 000516 0016 (4) Port P3 direction register (P3D) 000716 0016 (5) Interrupt source set register (INTSET) 000A16 0016 (6) Interrupt source discrimination register (INTDIS) 000B16 0016 (7) Compare register (low-order) (CMPL) 001016 0016 (8) Compare register (high-order) (CMPH) 001116 0016 (9) Capture/Compare register R/W pointer (CCRP) 001216 0016 (10) Capture software trigger register (CSTR) 001316 0016 (11) Compare register re-load register (CMPR) 001416 0016 (12) Port P0P3 drive capacity control register (DCCR) 001516 0016 X X X 0 0 (13) Pull-up control register (PULL) 001616 0016 (14) Port P1P3 control register (P1P3C) 001716 0016 (15) Serial I/O1 status register (SIO1STS) 001916 (16) Serial I/O1 control register (SIO1CON) 001A16 (17) UART1 control register (UART1CON) 001B16 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0016 1 1 1 0 0 (18) Timer A, B mode register (TABM) 001D16 0016 (19) Capture/Compare port register (CCPR) 001E16 0016 (20) Timer source selection register (TMSR) 001F16 0016 (21) Capture mode register (CAPM) 002016 0016 (22) Compare output mode register (CMOM) 002116 0016 (23) Capture/Compare status register (CCSR) 002216 0016 (24) Compare interrupt source register (CISR) 002316 0016 (25) Timer A (low-order) (TAL) 002416 FF16 (26) Timer A (high-order) (TAH) 002516 FF16 (27) Timer B (low-order) (TBL) 002616 FF16 (28) Timer B (high-order) (TBH) 002716 FF16 (29) Prescaler 1 (PRE1) 002816 FF16 (30) Timer 1 (T1) 002916 0116 (31) Timer count source set register (TCSS) 002A16 0016 (32) Timer X mode register (TXM) 002B16 0016 (33) Prescaler X (PREX) 002C16 FF16 (34) Timer X (TX) 002D16 (35) Serial I/O2 status register (SIO2STS) 002F16 (36) Serial I/O2 control register (SIO2CON) 003016 FF16 1 0 0 0 0 0016 (37) UART2 control register (UART2CON) 003116 1 1 1 0 0 0 0 0 (38) A/D control register (ADCON) 003416 0 0 0 1 0 0 0 0 (39) On-chip oscillation division ratio selection register (RODR) 003716 0 0 0 0 0 0 1 0 1 1 1 0 0 0 (40) MISRG 003816 (41) Watchdog timer control register (WDTCON) 003916 (42) Interrupt edge selection register (INTEDGE) 003A16 0016 0 0 1 1 1 0016 1 0 0 0 0 (43) CPU mode register (CPUM) 003B16 (44) Interrupt request register 1 (IREQ1) 003C16 0016 (45) Interrupt request register 2 (IREQ2) 003D16 0016 (46) Interrupt control register 1 (ICON1) 003E16 0016 (47) Interrupt control register 2 (ICON2) 003F16 0016 (48) Flash memory control register 0 (FMCR0) (Note 3) 0FE016 0 0 0 0 0 0 0 1 (49) Flash memory control register 1 (FMCR1) (Note 3) 0FE116 (50) Flash memory control register 2 (FMCR2) (Note 3) 0FE216 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X X X X X 1 X X (51) Processor status register (52) Program counter (PS) (PCH) Contents of address FFFD16 (PCL) Contents of address FFFC16 Notes 1: X : Undefined 2:The content of other registers is undefined when the microcomputer is reset. The initial values must be surely set before you use it. 3:Only flash memory version has this register. Fig. 75 Internal status of microcomputer at reset Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 60 of 117 7542 Group Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between X IN and X OUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.) (1) On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VCC through a resistor and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. M37542 XI N R Note: The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. XOUT Be careful that variable frequencies and obtain Open the sufficient margin. Fig. 76 Processing of XIN and XOUT pins at on-chip oscillator operation M37542 XIN XOUT Rd (2) Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. (3) RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. (4) External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. Select “0” (ceramic oscillation) to oscillation mode selection bit of CPU mode register (003B16). COUT CI N Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer’s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between X IN and X OUT following the instruction. Fig. 77 External circuit of ceramic resonator Note: Connect the external M37542 XI N XOUT circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, R a resistor and a microcomputer. C So, set the constants within the range of the frequency limits. Fig. 78 External circuit of RC oscillation M37542 XIN External oscillation circuit VCC VSS Fig. 79 External clock input circuit Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 61 of 117 XOUT Open 7542 Group (1) Oscillation control • Stop mode When the STP instruction is executed, the internal clock φ stops at an “H” level and the XIN oscillator stops. At this time, timer 1 is set to “0116” and prescaler 1 is set to “FF16” when the oscillation stabilization time set bit after release of the STP instruction is “0”. On the other hand, timer 1 and prescaler 1 are not set when the above bit is “1”. Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock φ remains at “H” until timer 1 underflows. As soon as timer 1 underflows, the internal clock φ is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable, or set the wait time by on-chip oscillator operation after system is released from reset until the oscillation is stabled. With the FLASH version, the internal power supply circuit is changed to low power consumption mode for consumption current reduction at the time of STP instruction execution. Although an internal power supply circuit is usually changed to the normal operation mode at the time of the return from an STP instruction, since a certain time is required to start the power supply to FLASH and operation of FLASH to be enabled, set wait time 100 µs or more with the FLASH version by the oscillation stabilization time set function after release of the STP instruction which used the timer 1. • Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. ■ Notes on Clock Generating Circuit For use with the oscillation stabilization set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. • Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. • Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 62 of 117 • CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU “M37542RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. • Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 84 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 84. • Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O, Serial I/O2, A/D converter, Watchdog timer) A count source of watchdog timer is affected by the clock division selection bit of the CPU mode register. The f(XIN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the CPU clock. b7 b0 CPU mode register (CPUM: address 003B16, initial value: 8016) Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 0 1 1 0 Not available 1 1 Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Clock division ratio selection bits b7 b6 0 0 : f(φ) = f(XIN)/2 (High-speed mode) 0 1 : f(φ) = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2) Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU “M37542RSS”.) 2: These bits are used only when a ceramic oscillation is selected. Do not use these when an RC oscillation is selected. Fig. 80 Structure of CPU mode register 7542 Group ● On-chip oscillation division ratio At on-chip oscillator mode, division ratio of on-chip oscillator for CPU clock is selected by setting value of on-chip oscillation division ratio selection register. The division ratio of on-chip oscillation for CPU clock is selected from among 1/1, 1/2, 1/8, 1/128. The operation clock for the peripheral function block is not changed by setting value of this register. ■ Notes on On-chip Oscillation Division Ratio • When system is released from reset, ROSC/8 (on-chip oscillator middle-speed mode) is selected for CPU clock. • When state transition from the ceramic or RC oscillation to onchip oscillator, ROSC/8 (on-chip oscillator middle-speed mode) is selected for CPU clock. • When the MCU operates by on-chip oscillator for the main clock without external oscillation circuit, connect X IN pin to V CC through a resistor and leave XOUT pin open. Set “10010x002” (x = 0 or 1) to CPUM. b7 b0 On-chip oscillation division ratio selection register (RODR: address 003716, initial value: 0216) On-chip oscillator division ratio b1 b0 0 0: On-chip oscillator double-speed mode (ROSC/1) 0 1: On-chip oscillator high-speed mode (ROSC/2) 1 0: On-chip oscillator middle-speed mode (ROSC/8) 1 1: On-chip oscillator low-speed mode (ROSC/128) Not used (returns “0” when read) Fig. 81 Structure of on-chip oscillation division ratio selection register Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 63 of 117 7542 Group XIN XOUT (Note) Clock division ratio selection bits Middle-, high-, double-speed mode 1/2 1/4 Timer 1 Prescaler 1 1/2 On-chip oscillator mode Clock division ratio selection bits Middle-speed mode Timing φ (Internal clock) High-speed mode Double-speed mode On-chip oscillator 1/2 1/4 1/16 ROSC/128 ROSC/8 ROSC/2 ROSC/1 On-chip oscillator division ratio selection bits On-chip oscillator mode Q S Q S Q S RESET WIT instruction STP instruction R R R STP instruction Reset Interrupt disable flag l Interrupt request Note: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig. 82 Block diagram of internal clock generating circuit (for ceramic resonator) XOUT XIN Clock division ratio selection bits Middle-, high-, double-speed mode 1/2 1/4 Timer 1 Prescaler 1 1/2 On-chip oscillator mode Delay Clock division ratio selection bits Middle-speed mode Timing φ (Internal clock) High-speed mode Double-speed mode RING 1/2 On-chip oscillator 1/4 1/16 On-chip oscillator division ROSC/128 ratio selection bits ROSC/8 ROSC/2 On-chip oscillator mode ROSC/1 S Q S R STP instruction WIT instruction R Reset Interrupt disable flag l Interrupt request Fig. 83 Block diagram of internal clock generating circuit (for RC oscillation) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 64 of 117 Q Q S RESET R STP instruction 7542 Group STP mode f(XIN) oscillation: stop On-chip oscillator: stop Interrupt f(XIN) oscillation: enabled On-chip oscillator: stop WAIT mode 2 WIT instruction Interrupt Interrupt STP instruction WIT instruction Interrupt STP instruction f(XIN) oscillation: enabled On-chip oscillator: enabled f(XIN) oscillation: stop On-chip oscillator: enabled WAIT mode 3 WAIT mode 4 Interrupt WIT instruction CPUM76=102 (Note 3) CPUM3=02 State 1 STP instruction Interrupt f(XIN) oscillation: enabled On-chip oscillator: enabled WAIT mode 1 Interrupt STP instruction State 2 MISRG1=12 MISRG1=02 WIT instruction State 4 CPUM4=12 MISRG1=12 (Note 4) MISRG1=02 CPUM76=102 (Note 3) State 2’ CPUM76=002 012 112 Interrupt WIT instruction CPUM4=02 State 3 CPUM76=002 012 112 (Note 4) CPUM3=12 Interrupt State 3’ WIT instruction Reset released (Note 3) RESET state f(XIN) oscillation: enabled On-chip oscillator: enabled Interrupt WAIT mode 2’ WAIT mode 3’ f(XIN) oscillation: enabled On-chip oscillator: enabled f(XIN) oscillation: enabled On-chip oscillator: enabled Oscillation stop detection circuit valid Operation clock source: f(XIN) (Note 1) Operation clock source: On-chip oscillator (Note 2) Notes on switch of clock (1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio. f(XIN)/2 (high-speed mode) f(XIN)/8 (middle-speed mode) f(XIN) (double-speed mode, only at a ceramic oscillation) (2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio. ROSC/1 (On-chip oscillator double-speed mode) ROSC/2 (On-chip oscillator high-speed mode) ROSC/8 (On-chip oscillator middle-speed mode) ROSC/128 (On-chip oscillator low-speed mode) (3) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’, ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock. (4) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation. (5) When the state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. 1. CPUM76 = 102 (state 2 → state 3) 2. NOP instruction Transition from Double-speed mode: NOP ✕ 3 Transition from High-speed mode: NOP ✕ 1 Transition from Middle-speed mode: NOP ✕ 0 3. CPU4 = 12 (state 3 → state 4) (6) When the state 3 → state 2 → state 1 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. 1. CPUM76 = 002 or 012 or 112 (state 3 → state 2) 2. NOP instruction Transition from On-chip oscillator double-speed mode: NOP ✕ 4 Transition from On-chip oscillator high-speed mode: NOP ✕ 2 Transition from On-chip oscillator middle-speed mode: NOP ✕ 0 Transition from On-chip oscillator low-speed mode: NOP ✕ 0 3. CPUM3 = 12 (state 2 → state 1) Fig. 84 State transition Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 65 of 117 7542 Group ● Oscillation stop detection circuit The oscillation stop detection circuit is used to detect an oscillation stop when a ceramic resonator or oscillation circuit stops due to disconnection. To use the oscillation stop detection circuit, set the on-chip oscillator to start operating. The oscillation stop detection circuit is enabled by setting the Ceramic or RC oscillation stop detection function active bit to 1. While this circuit is enabled, the operating status of the Ceramic or RC oscillation circuit is monitored using the on-chip oscillator. If an oscillation stop is detected, the oscillation stop detection status bit is set to 1. If the oscillation stop detection reset enable bit is also set to 1, an internal reset is triggered at oscillation stop detection. The Ceramic or RC oscillation stop detection function active bit and the oscillation stop detection status bit are not initialized if an oscillation stop detection reset is triggered and these bits retain their value of 1. Since these bits are initialized to 0 by an external reset, an oscillation stop detection reset can be determined by checking the oscillation stop status bit. The oscillation stop detection status bit is set to 0 by writing 0 to the Ceramic or RC oscillation stop detection function active bit. To enable the oscillation detection circuit, first write 0 to the Ceramic or RC oscillation stop detection function active bit and set the oscillation stop detection status bit to 0. Then set the Ceramic or RC oscillation stop detection function active bit to 1. The Ceramic oscillation, RC oscillation, and external clock input are set as the clocks for oscillation stop detection. Refer to the electrical characteristics for the frequencies for oscillation stop detection. ■ Notes on Oscillation Stop Detection Circuit (1) Do not execute the transition to “state 2’a” shown in Figure 86 State transition of oscillation stop detection circuit. In this state, no reset is triggered and the MCU is stopped even when the XIN oscillation is stopped. (2) After an oscillation stop detection reset, if this reset is enabled while bits Ceramic or RC oscillation stop detection function active and oscillation stop detection status are retained, a reset is triggered again. (3) The oscillation stop detection status bit is initialized under the following conditions: • External reset, power-on reset, low-voltage detection reset, watchdog timer reset, and reset by the STP instruction function. • Write 0 to the Ceramic or RC oscillation stop detection function active Bit. (4) While the oscillation stop detection function is in active, the oscillation stop detection status bit may set to 1 when the watchdog timer underflow. When an oscillation stop detection reset is triggered, reconfirm that oscillation is stopped. (5) The oscillation stop detection circuit is not included in the emulator MCU “M37542RSS”. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 66 of 117 b7 b0 MISRG(address 003816, initial value: 0016) Oscillation stabilization time set bit after release of the STP instruction 0: Set “0116” in timer1, and “FF16” in prescaler 1 automatically 1: Not set automatically Ceramic or RC oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active Oscillation stop reset bit 0: Oscillation stop reset disabled 1: Oscillation stop reset enabled Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Not used (return “0” when read) Reserved bits (Do not write “1” to these bits) Fig. 85 Structure of MISRG 7542 Group CPUM76=102 (Note 4) State 2 f(XIN) oscillation: enabled On-chip oscillator: enabled MISRG1=12 State 2’ MISRG1=02 (MISRG3 is cleared to “0”.) State 3 CPUM76=002 012 112 (Note 3) f(XIN) oscillation: enabled On-chip oscillator: enabled State 2’a (Note 5) Prohibitive state MUC will be locked when Ceramic or RC oscillation is stopped. MISRG2=12 State 2’b When oscillation stop is detected; MISRG3 is set to “1”. Internal RESET occurs. MISRG1=02 (MISRG3 is cleared to “0”.) RESET state 1 f(XIN) oscillation: enabled On-chip oscillator: enabled Applied “L” to RESET pin (external reset) MISRG3 is cleared to “0”. f(XIN) oscillation: enabled On-chip oscillator: enabled Oscillation stop reset disabled CPUM76=102 CPUM76=002 012 112 MISRG2=02 Oscillation stop reset enabled (Note 4) State 3’a Oscillation stop reset disabled When oscillation stop is detected; MISRG3 is set to “1”. Internal RESET does not occur. MISRG1=12 (Note 3) State 3’ Reset released f(XIN) oscillation: enabled On-chip oscillator: enabled When oscillation stop is detected; MISRG3 is set to “1”. Internal RESET does not occur. State 3’c Release from internal reset MISRG3 is set to “1”. Oscillation status can be confirmed by reading MISRG3. MISRG2=12 CPUM76=102 (Note 4) CPUM76=002 012 112 Reset released RESET state 2 (Note 4) f(XIN) oscillation: enabled On-chip oscillator: enabled MISRG2=02 State 3’b Oscillation stop reset enabled When oscillation stop is detected; MISRG3 is set to “1”. Internal RESET occurs. Oscillation stop is detected (internal reset) Oscillation stop detection circuit is in active. (Note 6) Operation clock source: f(XIN) (Note 1) Operation clock source: On-chip oscillator (Note 2) Notes on switch of clock (1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio. f(XIN)/2 (High-speed mode) f(XIN)/8 (Middle-speed mode) f(XIN) (Double-speed mode, only at a ceramic oscillation) (2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio. ROSC/1 (On-chip oscillator double-speed mode) ROSC/2 (On-chip oscillator high-speed mode) ROSC/8 (On-chip oscillator middle-speed mode) ROSC/128 (On-chip oscillator low-speed mode) (3) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing XIN oscillation. (4) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’, ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock. (5) MCU cannot be returned by On-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected. Accordingly, do not execute the transition to state 2'a. (6) STP instruction cannot be used when oscillation stop detection circuit is in active. Fig. 86 State transition 2 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 67 of 117 7542 Group NOTES ON PROGRAMMING State transition Processor Status Register Do not stop the clock selected as the operation clock because of setting of CM3, 4. The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. Decimal Calculations • For calculations in decimal notation, set the decimal mode flag D to “1”, then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. • In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. Ports • The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. A/D Conversion Do not execute the STP instruction during A/D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock φ is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 68 of 117 NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form * 2.Mark Specification Form * For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/en/rom). 7542 Group NOTES ON USE Countermeasures against noise 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. <Reason> The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise. (3) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. <Reason> If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. Noise DIP SDIP SOP XIN XOUT VSS QFP Fig. 87 Selection of packages XIN XOUT VSS O.K. N.G. (2) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20mm). <Reason> The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit Fig. 89 Wiring for clock I/O pins (4) Wiring to CNVss pin Connect the CNVss pin to the Vss pin with the shortest possible wiring. In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the MCU by a jumper switch. <Reason> The processor mode of a microcomputer is influenced by a potential at the CNVss pin. If a potential difference is caused by the noise between pins CNVss and Vss, the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. A wiring of a serial rewrite circuit may function as an antenna which feeds noise into the microcomputer. RESET Flash memory version Noise VSS VSS Jumper switch N.G. Reset circuit VSS RESET VSS O.K. Fig. 88 Wiring for the RESET pin Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 69 of 117 CNVSS CNVSS CNVSS VSS VSS VSS N.G. O.K. Fig. 90 Wiring for CNVss pin O.K. Serial rewrite circuit 7542 Group 2. Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows: • Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. • Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for VSS line and VCC line. • Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. VCC VSS N.G. VCC VSS 3. Wiring to analog input pins • Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. • Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin. Besides, connect the capacitor to the Vss pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. <Reason> Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Noise (Note) Microcomputer O.K. Fig. 91 Bypass capacitor across the VSS line and the VCC line Analog input pin Thermistor N.G. O.K. VSS Note : The resistor is used for dividing resistance with a thermistor. Fig. 92 Analog signal line and a resistor and a capacitor • The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 70 of 117 7542 Group 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. <Reason> In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. <Reason> Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. (3) Oscillator protection using Vss pattern As for a two-sided printed circuit board, print a Vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring. Besides, separate this Vss pattern from other Vss patterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 94 Vss pattern on the underside of an oscillator ➀ Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M XIN XOUT VSS Large current GND ➁ Installing oscillator away from signal lines where potential levels change frequently N.G. Do not cross CNTR XIN XOUT VSS Fig. 93 Wiring for a large current signal line/Writing of signal lines where potential levels change frequently Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 71 of 117 7542 Group 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: <Hardware> • Connect a resistor of 100 Ω or more to an I/O port in series. <Software> • As for an input port, read data several times by a program for checking whether input levels are equal or not. • As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. • Rewrite data to direction registers and pull-up control registers at fixed periods. O.K. Noise Data bus Noise Direction register N.G. Port latch I/O port pins Fig. 95 Setup for I/O ports 6. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. <The main routine> • Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. • Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. • Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. <The interrupt processing routine> • Decrements the SWDT contents by 1 at each interrupt processing. • Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). • Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. ≠N Main routine Interrupt processing routine (SWDT)← N (SWDT) ← (SWDT)—1 CLI Interrupt processing Main processing (SWDT) ≤0? (SWDT) =N? N Interrupt processing routine errors Fig. 96 Watchdog timer by software Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 72 of 117 ≤0 >0 RTI Return Main routine errors 7542 Group FLASH MEMORY MODE The 7542 group’s flash memory version has the flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and the CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). ● Summary This flash memory version has some blocks on the flash memory as shown in Figure 97 and each block can be erased. In addition to the ordinary User ROM area to store the MCU operation control program, the flash memory has a Boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This Boot ROM area can be rewritten in only parallel I/O mode. Table 9 lists the summary of the 7542 Group (flash memory version). Table 9 Summary of 7542 group’s flash memory version Item Power source voltage (Vcc) Temperature at program/erase Program/Erase VPP voltage (VPP) Flash memory mode Erase block division User ROM area/Data ROM area Boot ROM area (Note) Program method Erase method Program/Erase control method Number of commands Number of program/Erase times ROM code protection Specifications VCC = 2.7 to 5.5 V Ta = 0 to 60 °C VCC = 2.7 to 5.5 V 3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode Refer to Fig. 97. Not divided (4K bytes) In units of bytes Block erase Program/Erase control by software command 5 commands 100 Available in parallel I/O mode and standard serial I/O mode Note: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be erased and written in only parallel I/O mode. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 73 of 117 7542 Group 32K bytes ROM Product 16K bytes ROM Product 000016 000016 User ROM area SFR area 700016 004016 Internal RAM area (1K bytes) RAM 043F16 780016 Data block B : 2K bytes Data block A : 2K bytes 800016 700016 Internal RAM area (1K bytes) RAM 043F16 780016 Data block B : 2K bytes Data block A : 2K bytes 7FFF16 0FE016 0FE016 SFR area SFR area 0FFF16 700016 SFR area SFR area 004016 block 2 : 16K bytes Internal flash memory area (4K bytes) (Note 3) 700016 C00016 800016 block 1 : 8K bytes Internal flash memory area (32K bytes) (Note 3) FFFF16 0FFF16 E00016 7FFF16 C00016 block 0 : 8K bytes FFFF16 FFFF16 Internal flash memory area (4K bytes) (Note 3) C00016 block 1 : 8K bytes F00016 E00016 Internal flash memory area (16K bytes) (Note 3) Boot ROM area 4K bytes block 0 : 8K bytes FFFF16 FFFF16 Notes 1: The boot ROM area can be rewritten in a parallel I/O mode. (Access to except boot ROM area is disablrd.) 2: To specify a block, use the maximum address in the block. 3: The mask ROM version has the reserved ROM area. Note the difference of the area. Fig. 97 Block diagram of built-in flash memory ● Boot Mode ● CPU Rewrite Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 97 for details about the Boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the User ROM area. When the microcomputer is reset and the CNVSS pin high after pulling the P37(RP) pin low, P32(CE) pin high, P06/SCLK pin low and P05/TxD2 pin high, the CPU starts operating (start address of program is stored into addresses FFFC16 and FFFD16) using the control program in the Boot ROM area. This mode is called the “Boot mode”. Also, User ROM area can be rewritten using the control program in the Boot ROM area. In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the User ROM area shown in Figure 97 can be rewritten; the Boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the User ROM area and each block area. The control program for CPU rewrite mode can be stored in either User ROM or Boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM area before it can be executed. ● Block Address Block addresses refer to the maximum address of each block. These addresses are used in the block erase command. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 74 of 117 • Outline Performance CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM area before it can be executed. The MCU enters CPU rewrite mode by setting “1” to the CPU rewrite mode select bit (bit 1 of address 0FE016). Then, software commands can be accepted. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. 7542 Group [Flash memory control registers (FMCR0 to FMCR2)] 0FE016 to 0FE216 Figure 98 shows the flash memory control register 0. Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0” (busy). Otherwise, it is “1” (ready). Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. When this bit is set to “1”, the MCU enters CPU rewrite mode. And then, software commands can be accepted. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in the internal RAM for write to bit 1. To set this bit 1 to “1”, it is necessary to write “0” and then write “1” in succession to bit 1. The bit can be set to “0” by only writing “0”. Bit 2 of the flash memory control register 0 is the 8KB user block E/W mode enable bit. By setting this bit in combination with bit 4 (all user block E/W enable bit) of flash memory control register 2 (address 0FE016), Erase/Write to user block in CPU rewrite mode is disabled. b7 Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is “1”, setting “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. Bit 5 of the flash memory control register 0 is the User ROM area select bit and is valid only in the boot mode. Setting this bit to “1” in the boot mode switches an accessible area from the boot ROM area to the user ROM area. To use the CPU rewrite mode in the boot mode, set this bit to “1”. Note that when the microcomputer is booted up in the user ROM area, only the user ROM area is accessible and bit 5 is invalid; on the other hand, when the microcomputer is in the boot mode, bit 5 is valid independent of the CPU rewrite mode. To rewrite bit 5, execute the user-original reprogramming control software transferred to the internal RAM in advance. Bit 6 of the flash memory control register 0 is the program status flag. This bit is set to “1” when writing to flash memory is failed. When program error occurs, the block cannot be used. Bit 7 of the flash memory control register 0 is the erase status flag. This bit is set to “1” when erasing flash memory is failed. When erase error occurs, the block cannot be used. b0 Flash memory control register 0 (FMCR0: address : 0FE016: initial value: 0116) RY/BY status flag 0 : Busy (being written or erased) 1 : Ready CPU rewrite mode select bit (Note 1) 0 : CPU rewrite mode invalid 1 : CPU rewrite mode valid 8KB user block E/W mode enable bit (Note 1, 2) 0 : E/W disabled 1 : E/W enabled Flash memory reset bit (Note 3) 0 : Normal operation 1 : reset Not used (do not write “1” to this bit.) User ROM area select bit (Note 4) 0 : Boot ROM area is accessed 1 : User ROM area is accessed Program status flag 0: Pass 1: Error Erase status flag 0: Pass 1: Error Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: This bit can be written only when CPU rewrite mode select bit is “1”. 3: Effective only when the CPU rewrite mode select bit = “1”. Fix this bit to “0” when the CPU rewrite mode select bit is “0”. 4: Write to this bit in program on RAM Fig. 98 Structure of flash memory control register 0 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 75 of 117 7542 Group Figure 99 shows the flash memory control register 1. Bit 0 of the flash memory control register 1 is the Erase suspend enable bit. By setting this bit to “1”, the erase suspend mode to suspend erase processing temporarily when block erase command is executed can be used. In order to set this bit to “1”, writing “0” and “1” in succession to bit 0. In order to set this bit to “0”, write “0” only to bit 0. Bit 1 of the flash memory control register 1 is the erase suspend request bit. By setting this bit to “1” when erase suspend enable bit is “1”, the erase processing is suspended. Bit 6 of the flash memory control register 1 is the erase suspend flag. This bit is cleared to “0” at the flash erasing. Figure 100 shows the flash memory control register 2. Bit 0 of the flash memory control register 1 is the all user block E/ W enable bit. By setting this bit to “0”, Erase/Write to all user block (blocks 0, 1, 2) is disabled. As a result, error writing in program to write only to data block can be prevented. b7 b0 Flash memory control register 1 (FMCR1: address : 0FE116: initial value: 4016) Erase Suspend enble bit (Notes 1) 0 : Suspend invalid 1 : Suspend valid Erase Suspend request bit (Notes 2) 0 : Erase restart 1 : Suspend request Not used (do not write “1” to this bit.) Erase Suspend flag 0 : Erase active 1 : Erase inactive (Erase Suspend mode) Not used (do not write “1” to this bit.) Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the suspend enable bit = “1”. Fig. 99 Structure of flash memory control register 1 b7 b0 Flash memory control register 2 (FMCR2: address : 0FE216: initial value: 0116) Reserved bit (returns “1” when read) Reserved bits (do not write “1” to this bit.) All user block E/W enable bit (Notes 1, 2) 0 : E/W disabled 1 : E/W enabled Not used (do not write “1” to this bit.) Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. For this bit to be set to “0”, write “0” only to this bit. 2: Effective only when the CPU rewrite mode select bit = “1”. Fig. 100 Structure of flash memory control register 2 Table 10 Erase/Write disable setting CPU rewrite All user block 8KB user block mode select bit E/W enable bit E/W enable bit 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 76 of 117 Block 0: 8KB Block 1: 8KB E/W disabled (RESET) E/W disabled E/W disabled E/W disabled E/W disabled E/W disabled E/W disabled E/W enabled Block 2: 16KB E/W disabled (RESET) E/W disabled E/W disabled E/W disabled E/W disabled E/W disabled E/W enabled E/W enabled Data block A: 2KB Data block B: 2KB E/W disabled (RESET) E/W disabled E/W disabled E/W disabled E/W enabled E/W enabled E/W enabled E/W enabled 7542 Group Figure 101 shows a flowchart for setting/releasing CPU rewrite mode. Start Single-chip mode or Boot mode Set CPU mode register (Note 1) Transfer CPU rewrite mode control program to internal RAM Jump to control program transferred to internal RAM (Subsequent operations are executed by control program in this RAM) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession) Set all user block E/W enable bit Set 8KB user block E/W mode enable bit (for setting to “1”, by writing “0” and then “1” in succession) (Note 2) Using software command executes erase, program, or other operation Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) Set all user block E/W enable bit to “0” Set 8KB user block E/W mode enable bit to “0” Write “0” to CPU rewrite mode select bit End Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B16). 2: As for setting of these bits, refer to Table 10. 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array command or reset the flash memory. Fig. 101 CPU rewrite mode set/release flowchart ■ Notes on CPU Rewrite Mode Take the notes described below when rewriting the flash memory in CPU rewrite mode. ●Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. ●Operation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the clock division ratio selection bits (bits 6 and 7 of address 003B16). ●Watchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. ●Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode. ●Reset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVss = “H”, so that the program will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 77 of 117 7542 Group ● Software Commands Table 11 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. The RY/BY status flag of the flash memory control register is “0” during write operation and “1” when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. • Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (D0 to D7). The read array mode is retained until another command is written. Start Write “4016” Write Write address Write data • Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the contents of the status register are read out at the data bus (D0 to D7) by a read in the second bus cycle. The status register is explained in the next section. Read status register • Clear Status Register Command (5016) This command is used to clear the bits SR4 and SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. • Program Command (4016) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by _____ read status register or the RY/BY status flag. When the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (D0 to D7). The status register bit 7 (SR7) is set to “0” at the same time the write operation starts and is returned to “1” upon completion of the write operation. In this case, the read status register mode remains active until the read array command (FF16) is written. SR7 = “1”? or RY/BY = “1” ? NO YES SR4 = “0”? NO Program error YES Program completed Fig. 102 Program flowchart Table 11 List of software commands (CPU rewrite mode) First bus cycle Command Second bus cycle Data (D0 to D7) Mode Address Data (D0 to D7) Read ✕ SRD (Note 1) Mode Address Read array Write ✕ (Note 4) FF16 Read status register Write ✕ 7016 Clear status register Write ✕ 5016 Program Write ✕ 4016 Write WA (Note 2) WD (Note 2) Block erase Write ✕ 2016 Write BA (Note 3) SRD = Status Register Data WA = Write Address, WD = Write Data BA = Block Address to be erased (Input the maximum address of each block.) ✕ = ✕ denotes a given address in the user ROM area. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 78 of 117 D016 7542 Group • Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. Whether the block erase operation is completed can be confirmed by read status register or the RY/BY status flag of flash memory control register. At the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same time the block erase operation starts and is returned to “1” upon completion of the block erase operation. In this case, the read status register mode remains active until the read array command (FF16) is written. The RY/BY status flag is “0” during block erase operation and “1” when the block erase operation is completed as is the status register bit 7. After the block erase ends, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Start Write “2016” Write “D016” Block address Read status register SR7 = “1”? or RY/BY = “1”? YES SR5 = “0” ? YES Erase completed (write read command “ FF16”) Fig. 103 Erase flowchart Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 79 of 117 NO NO Erase error 7542 Group ● Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an arbitrary address from the User ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the User ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input. Also, the status register can be cleared by writing the clear status register command (5016). After reset, the status register is set to “8016”. Table 12 shows the status register. Each bit in this register is explained below. •Erase status (SR5) The erase status indicates the operating status of erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is reset to “0”. •Program status (SR4) The program status indicates the operating status of write operation. When a write error occurs, it is set to “1”. The program status is reset to “0” when it is cleared. If “1” is written for any of the SR5 and SR4 bits, the read array, program, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, if any commands are not correct, both SR5 and SR4 are set to “1”. •Sequencer status (SR7) The sequencer status indicates the operating status of the flash memory. This bit is set to “0” (busy) during write or erase operation and is set to “1” when these operations ends. After power-on, the sequencer status is set to “1” (ready). Table 12 Definition of each bit in status register Each bit of SRD bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Page 80 of 117 Definition “1” Ready Terminated in error Terminated in error - “0” Busy Terminated normally Terminated normally - 7542 Group ● Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 104 shows a full status check flowchart and the action to be taken when each error occurs. Read status register SR4 = “1” and SR5 = “1” ? YES Command sequence error NO SR5 = “0” ? NO Erase error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should an erase error occur, the block in error cannot be used. YES SR4 = “0” ? NO Program error Should a program error occur, the block in error cannot be used. YES End (block erase, program) Note: When one of SR5 and SR4 is set to “1”, none of the read array, program, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands. Fig. 104 Full status check flowchart and remedial procedure for errors Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 81 of 117 7542 Group ● Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. (1) ROM Code Protect Function The ROM code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the ROM code protect control address (address FFDB16) in parallel I/O mode. Figure 105 shows the ROM code protect control address (address FFDB16). (This address exists in the User ROM area.) b7 If one or both of the pair of ROM code protect bits is set to “0”, the ROM code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. The ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00”, the ROM code protect is turned off, so that the contents of internal flash memory can be readout or modified. Once the ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode to rewrite the contents of the ROM code protect reset bits. Rewriting of only the ROM code protect control address (address FFDB16) cannot be performed. When rewriting the ROM code protect reset bit, rewrite the whole user ROM area (block 0) containing the ROM code protect control address. b0 ROM code protect control address (address FFDB16) 1 1 ROMCP (FF16 when shipped) Reserved bits (“1” at read/write) ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2) b3b2 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled ROM code protect reset bits (Note 3) b5b4 0 0: Protect removed 0 1: Protect set bits effective 1 0: Protect set bits effective 1 1: Protect set bits effective ROM code protect level 1 set bits (ROMCP1) (Note 1) b7b6 0 0: Protect enabled 0 1: Protect enabled 1 0: Protect enabled 1 1: Protect disabled Notes 1: When ROM code protect is turned on, the internal flash memory is protected against readout or modification in parallel I/O mode. 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be modified in parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite mode. Fig. 105 Structure of ROM code protect control address Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 82 of 117 7542 Group (2) ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit data, and its areas are FFD4 16 to FFDA16. Write a program which has had the ID code preset at these addresses to the flash memory. Address FFD416 ID1 FFD516 ID2 FFD616 ID3 FFD716 ID4 FFD816 ID5 FFD916 ID6 FFDA16 ID7 FFDB16 ROM code protect control Interrupt vector area Fig. 106 ID code store addresses Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 83 of 117 7542 Group ● Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 7542 Group (flash memory version). For details, refer to the user’s manual of each writer manufacturer. • User ROM and Boot ROM Areas In parallel I/O mode, the User ROM and Boot ROM areas shown in Figure 97 can be rewritten. Both areas of flash memory can be operated on in the same way. The Boot ROM area is 4 Kbytes in size and located at addresses F00016 through FFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the Boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. Therefore, using the MCU in standard serial I/O mode, do not rewrite to the Boot ROM area. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 84 of 117 7542 Group ● Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode requires a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started when the microcomputer is reset and the CNVSS pin high after pulling the P37(RP) pin low, P32(CE) pin high, P06/SCLK2 pin low and P05/TxD2 pin high. (In the ordinary microcomputer mode, set CNVss pin to “L” level.) This control program is written in the Boot ROM area when the product is shipped from Renesas. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the Boot ROM area is rewritten in parallel I/O mode. The standard serial I/O mode has standard serial I/O mode 1 of the clock synchronous serial and the standard serial I/O mode 2 of the clock asynchronous serial. Table 13 lists the description of pin function (standard serial I/O mode 1). Figures 107 to 109 show the pin connections for the standard serial I/O mode 1. Table 14 lists the description of pin function (standard serial I/O mode 2). Figures 112 to 114 show the pin connections for the standard serial I/O mode 2. In standard serial I/O mode, only the User ROM area shown in Figure 97 can be rewritten. The Boot ROM area cannot be written. In standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, this function determines whether the ID code sent from the peripheral unit (programmer) and those written in the flash memory match.The commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 85 of 117 7542 Group (1) Standard serial I/O mode 1 Table 13 Description of pin function (standard serial I/O mode 1) Pin name Signal name I/O Function VCC,VSS Power supply I Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin. CNVSS CNVSS I After input of port is set, input “H” level. RESET Reset input I Reset input pin. System operates when RESET pin is set to “H” level after CNVss pin is set to “H” level. XIN Clock input I Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. XOUT Clock output O (When system operates only by the on-chip oscillator, an external circuit is not required.) VREF Reference voltage input I Apply reference voltage of A/D to this pin. P00–P03 I/O port P0 I/O Input “L” or “H” level, or keep open. P04 RxD input I Serial data input pin. P05 TxD output O Serial data output pin. P06 SCLK input I Serial clock input pin. P07 BUSY output O BUSY signal output pin. P10–P14 I/O port P1 I/O Input “L” or “H” level, or keep open. P20–P27 I/O port P2 I/O Input “L” or “H” level, or keep open. P30, P31, P33–P36 I/O port P3 I/O Input “L” or “H” level, or keep open. P32 CE input I Input “H” level. P37 RP input I Input “L” level. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 86 of 117 7542 Group RxD TxD SCLK P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 "L" input 24 23 22 21 20 19 18 17 BUSY P07(LED07)/SRDY2 P10/RXD1/CAP0 P11/TXD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0 P21/AN1 25 16 26 15 27 14 28 13 29 M37542FxGP 12 30 11 31 10 32 9 2 3 4 5 6 7 "H" input Vss Note 8 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 1 P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11 )/CMP2 P30(LED10)/CAP1 VSS XOUT XIN Vcc CNVSS Note. Connect the oscillation circuit to XIN and XOUT. (Package type: PLQP0032GB-A) Fig. 107 Pin connection diagram in standard serial I/O mode 1 (PLQP0032GB-A package) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 87 of 117 RESET 7542 Group P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS RESET CNVSS Vcc Note Vss 1 36 2 35 3 34 4 33 5 32 6 31 M37542FxFP P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 7 8 9 10 11 12 13 P11/TXD1 P10/RXD1/CAP0 P07(LED07)/SRDY2 P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 P36(LED16)/INT1 P35(LED15) P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11 )/CMP2 P30(LED10)/CAP1 30 29 28 27 26 25 24 14 23 15 22 16 21 17 20 18 19 BUSY SCLK TXD RXD L input H input Note. Connect the oscillation circuit to XIN and XOUT. (Package type: PRSP0036GA-A) Fig. 108 Pin connection diagram in standard serial I/O mode 1 (PRSP0036GA-A package) P12/SCLK1 P13/SRDY1 P14/CNTR0 Note Vss 32 P11/TXD1 2 31 3 30 P10/RXD1/CAP0 P07(LED07)/SRDY2 P20/AN0 4 29 P21/AN1 P22/AN2 5 28 P23/AN3 P24/AN4 7 P25/AN5 VREF 9 6 8 10 RESET CNVSS VCC XIN 11 XOUT VSS M37542FxSP RESET CNVSS Vcc 1 27 26 25 24 23 22 P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 21 P34(LED14) 13 20 14 19 P33(LED13)/INT1 P32(LED12)/CMP3 15 18 P31(LED11 )/CMP2 16 17 P30(LED10)/CAP1 12 Note. Connect the oscillation circuit to XIN and XOUT. (Package type: PRDP0032BA-A) Fig. 109 Pin connection diagram in standard serial I/O mode 1 (PRDP0032BA-A package) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 88 of 117 BUSY SCLK TXD RXD L input H input 7542 Group • Standard serial I/O mode 1 Figure 110 shows the handling example of control pins on the user system board when the standard serial I/O mode 1 is used. Refer to the serial programmer manual of your programmer to handle pins controlled by the programmer. Target board To user system circuit M37542 flash memory version TXD(P05) VCC SCLK(P06) RXD(P04) BUSY(P07) (P32) (P37) User reset circuit RESET Note 1 CNVSS Note 2 VSS XIN XOUT Notes 1: Connect the user reset circuit to the RESET pin with the shortest possible wiring. In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the MCU by a jumper switch. 2: Connect the CNVss pin to the Vss pin with the shortest possible wiring. In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the MCU by a jumper switch. Fig. 110 Handling example of control pins in standard serial I/O mode 1 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 89 of 117 7542 Group Power source RESET CNVSS P37(RP) P32(CEB) P07(BUSY) (Note) P06(SCLK2) P05(TxD2) P04(RxD2) td(port-CNVSS) td(CNVSS-RESET) td(RESET-SCLK) Symbol td(port-CNVss) td(CNVss-RESET) td(RESET-SCLK) th(RESET-CNVss) th(CNVss-port) Min. 1 1 0.05 1 1 Ratings Typ. Max. 0.5 - Unit ms ms ms ms ms Fig. 111 Timing diagram in standard serial I/O mode 1 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 90 of 117 Note: Keep input of P06 “H” until P07 turns “L”. th(CNVSS-RESET) th(CNVSS-port) 7542 Group (2) Standard serial I/O mode 2 Table 14 Description of pin function (standard serial I/O mode 2) Pin name VCC,VSS CNVSS RESET Signal name Power supply CNVSS Reset input XIN Clock input I XOUT Clock output O VREF P00–P03 P04 P05 P06 P07 P10–P14 P20–P27 P30, P31, P33–P36 P32 P37 Reference voltage input I/O port P0 RxD input TxD output SCLK input BUSY output I/O port P1 I/O port P2 I/O port P3 CE input RP input Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 91 of 117 I/O I I I I I/O I O I O I/O I/O I/O I I Function Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin. After input of port is set, input “H” level. Reset input pin. System operates when RESET pin is set to “H” level after CNVss pin is set to “H” level. Connect an oscillation circuit between the XIN and XOUT pins. As for the connection method, refer to the “clock generating circuit”. (When system operates only by the on-chip oscillator, an external circuit is not required.) Apply reference voltage of A/D to this pin. Input “L” or “H” level, or keep open. Serial data input pin. Serial data output pin. Input “L” level. BUSY signal output pin. Input “L” or “H” level, or keep open. Input “L” or “H” level, or keep open. Input “L” or “H” level, or keep open. Input “H” level. InputI “L” level. 7542 Group RxD TxD input “L” input P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 "L" 24 23 22 21 20 19 18 17 BUSY P07(LED07)/SRDY2 P10/RXD1/CAP0 P11/TXD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0 P21/AN1 25 16 26 15 27 14 28 13 29 M37542FxGP 12 30 11 31 10 32 9 2 3 4 5 6 7 “H” input Vss Note 8 P22/AN2 P23/AN3 P24/AN4 P25/AN5 VREF RESET CNVSS VCC 1 P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11 )/CMP2 P30(LED10)/CAP1 VSS XOUT XIN Vcc CNVSS RESET Note. Connect the oscillation circuit to XIN and XOUT. (Package type: PLQP0032GB-A) Fig. 112 Pin connection diagram in standard serial I/O mode 2 (PLQP0032GB-A package) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 92 of 117 7542 Group RESET CNVSS Vcc Note Vss P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS 1 36 2 35 3 34 4 33 5 32 6 31 M37542FxFP P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 7 8 9 10 11 12 13 30 29 28 27 26 25 24 14 23 15 22 16 21 17 20 18 19 P11/TXD1 P10/RXD1/CAP0 P07(LED07)/SRDY2 P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 P36(LED16)/INT1 P35(LED15) P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11 )/CMP2 P30(LED10)/CAP1 BUSY “L” input TXD RXD “L” input “H” input Note. Connect the oscillation circuit to XIN and XOUT. (Package type: PRSP0036GA-A) Fig. 113 Pin connection diagram in standard serial I/O mode 2 (PRSP0036GA-A package) P12/SCLK1 P13/SRDY1 P14/CNTR0 Note Vss 32 P11/TXD1 2 31 3 30 P10/RXD1/CAP0 P07(LED07)/SRDY2 P20/AN0 4 29 P21/AN1 P22/AN2 5 28 P23/AN3 P24/AN4 7 P25/AN5 VREF 9 6 8 10 RESET CNVSS VCC XIN 11 XOUT VSS M37542FxSP RESET CNVSS Vcc 1 27 26 25 24 23 22 P06(LED06)/SCLK 2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 21 P34(LED14) 13 20 14 19 P33(LED13)/INT1 P32(LED12)/CMP3 15 18 P31(LED11 )/CMP2 16 17 P30(LED10)/CAP1 12 Note. Connect the oscillation circuit to XIN and XOUT. (Package type: PRDP0032BA-A) Fig. 114 Pin connection diagram in standard serial I/O mode 2 (PRDP0032BA-A package) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 93 of 117 BUSY “L” input TXD RXD “L” input “H” input 7542 Group • Standard serial I/O mode 2 Figure 115 shows the handling example of control pins on the user system board when the standard serial I/O mode 2 is used. Refer to the serial programmer manual of your programmer to handle pins controlled by the programmer. Target board To user system circuit M37542 flash memory version VCC TXD(P05) SCLK(P06) RXD(P04) BUSY(P07) (P32) (P37) User reset circuit RESET Note 1 CNVSS Note 2 VSS XIN XOUT Notes 1: Connect the user reset circuit to the RESET pin with the shortest possible wiring. In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the MCU by a jumper switch. 2: Connect the CNVss pin to the Vss pin with the shortest possible wiring. In the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the MCU by a jumper switch. Fig. 115 Handling example of control pins in standard serial I/O mode 2 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 94 of 117 7542 Group Power source RESET CNVSS P37(RP) P32(CEB) P06(SCLK2) P05(TxD2) P04(RxD2) td(port-CNVSS) td(CNVSS-RESET) Symbol td(port-CNVss) td(CNVss-RESET) th(RESET-CNVss) th(CNVss-port) Min. 1 1 1 1 Ratings Typ. Max. - Unit ms ms ms ms Fig. 116 Timing diagram in standard serial I/O mode 2 Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 95 of 117 th(CNVSS-RESET) th(CNVSS-port) Note: In the standard serial I/O2, set P06 and P07 as follows; P06: input “L” level. P07: BUSY signal output pin. Keep open. 7542 Group ELECTRICAL CHARACTERISTICS 1.Absolute Maximum Ratings Table 15 Absolute maximum ratings Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00–P07, P10–P14, P20–P27, P30–P37, VREF Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P07, P10–P14, P20–P27, P30–P37, XOUT Power dissipation Operating temperature Storage temperature Note: 200 mW for the PLQP0032GB-A package product. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 96 of 117 Conditions All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. Ta = 25°C Ratings –0.3 to 6.5 –0.3 to VCC + 0.3 Unit V V –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 –0.3 to VCC + 0.3 V V V 300 (Note) –20 to 85 –40 to 125 mW °C °C 7542 Group Recommended Operating Conditions Table 16 Recommended operating conditions (1) (FLASH ROM version: V CC = 2.7 to 5.5V, Mask ROM version: V CC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol VCC Limits Parameter Power source voltage (High-, Middle-speed mode) (ceramic) (Double-speed mode) Power source voltage (High-, Middle-speed mode) (RC) VSS VREF VIH Power source voltage Analog reference voltage “H” input voltage P00–P07, P10–P14, P20–P27, P30–P37 VIH “H” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) VIH “H” input voltage RESET, XIN VIL “L” input voltage P00–P07, P10–P14, P20–P27, P30–P37 VIL “L” input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) VIL “L” input voltage RESET, CNVSS VIL “L” input voltage XIN ∑IOH(peak) “H” total peak output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 ∑IOL(peak) “L” total peak output current (Note 2) P10–P14, P20–P27 ∑IOL(peak) “L” total peak output current (Note 2) P00–P07, P30–P37 ∑IOH(avg) “H” total average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 ∑IOL(avg) “L” total average output current (Note 2) P10–P14, P20–P27 ∑IOL(avg) “L” total average output current (Note 2) P00–P07, P30–P37 Min. f(XIN) = 8 MHz Mask ROM FLASH ROM f(XIN) = 4 MHz Mask ROM FLASH ROM f(XIN) = 2 MHz Mask ROM FLASH ROM f(XIN) = 8 MHz Mask ROM FLASH ROM f(XIN) = 6.5 MHz Mask ROM FLASH ROM f(XIN) = 2 MHz Mask ROM FLASH ROM f(XIN) = 1 MHz Mask ROM FLASH ROM f(XIN) = 4 MHz Mask ROM FLASH ROM f(XIN) = 2 MHz Mask ROM FLASH ROM f(XIN) = 1 MHz Mask ROM FLASH ROM Unit 4.0 Typ. 5.0 Max. 5.5 2.4 2.7 2.2 2.7 4.5 5.0 5.0 5.0 5.0 5.0 5.5 5.5 5.5 5.5 5.5 V V V V V 4.0 5.0 5.5 V 2.4 2.7 2.2 2.7 4.0 5.0 5.0 5.0 5.0 5.0 5.5 5.5 5.5 5.5 5.5 V V V V V 2.4 2.7 2.2 2.7 5.0 5.0 5.0 5.0 0 5.5 5.5 5.5 5.5 V 2.0 0.8VCC VCC VCC V V V V V V V 2.0 VCC V 0.8VCC VCC V 0 0.2VCC V 0 0.8 V 0 0.2VCC V 0 0.16VCC V –80 mA 80 mA 80 mA –40 mA 40 mA 40 mA Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 97 of 117 7542 Group Recommended Operating Conditions (continued) Table 17 Recommended operating conditions (2) (FLASH ROM version: V CC = 2.7 to 5.5V, Mask ROM version: V CC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) Parameter Limits Min. “H” peak output current (Note 1) “L” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37 P00–P07, P30–P37 (Drive capacity = “L”) P10–P14, P20–P27 “L” peak output current (Note 1) P00–P07, P30–P37 (Drive capacity = “H”) “H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37 “L” average output current (Note 2) P00–P07, P30–P37 (Drive capacity = “L”) P10–P14, P20–P27 “L” average output current (Note 2) P00–P07, P30–P37 (Drive capacity = “H”) Oscillation frequency (Note 3) Mask ROM: VCC = 4.5 to 5.5 V at ceramic oscillation or external clock input FLASH ROM: VCC = 4.5 to 5.5 V Double-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input FLASH ROM: VCC = 4.0 to 5.5 V Double-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input FLASH ROM: VCC = 2.7 to 5.5 V Double-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 2.2 to 5.5 V at ceramic oscillation or external clock input Double-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 4.0 to 5.5 V at ceramic oscillation or external clock input FLASH ROM: VCC = 4.0 to 5.5 V High-, Middle-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 2.4 to 5.5 V at ceramic oscillation or external clock input FLASH ROM: VCC = 2.7 to 5.5 V High-, Middle-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 2.2 to 5.5 V at ceramic oscillation or external clock input High-, Middle-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 4.0 to 5.5 V at RC oscillation FLASH ROM: VCC = 4.0 to 5.5 V High-, Middle-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 2.4 to 5.5 V at RC oscillation FLASH ROM: VCC = 2.7 to 5.5 V High-, Middle-speed mode Oscillation frequency (Note 3) Mask ROM: VCC = 2.2 to 5.5 V at RC oscillation High-, Middle-speed mode Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 98 of 117 Typ. Max. –10 10 Unit mA mA 30 –5 5 mA mA mA 15 8 mA MHz 6.5 MHz 2 MHz 1 MHz 8 MHz 4 MHz 2 MHz 4 MHz 2 MHz 1 MHz 7542 Group Electrical Characteristics Table 18 Electrical characteristics (1) (FLASH ROM version: V CC = 2.7 to 5.5V, Mask ROM version: V CC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. VOH VOL VOL “H” output voltage P00–P07, P10–P14, P20–P27, P30–P37 (Note 1) “L” output voltage P00–P07, P30–P37 (Drive capacity = “L”) P10–P14, P20–P27 “L” output voltage P00–P07, P30–P37 (Drive capacity = “H”) VT+–VT– Hysteresis CNTR0, INT0, INT1, CAP0, CAP1 (Note 2) P00–P07 (Note 3) VT+–VT– Hysteresis RXD0, SCLK0, RXD1, SCLK1 VT+–VT– Hysteresis RESET IIH “H” input current P00–P07, P10–P14, P20–P27, P30–P37 IIH IIH IIL IIL IIL IIL VRAM ROSC DOSC “H” input current RESET “H” input current XIN “L” input current P00–P07, P10–P14, P20–P27, P30–P37 “L” input current RESET “L” input current XIN “L” input current P00–P07, P30–P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency IOH = –5 mA VCC–1.5 VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC–1.0 Mask ROM: VCC = 2.2 to 5.5 V FLASH ROM: VCC = 2.7 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA Mask ROM: VCC = 2.2 to 5.5 V FLASH ROM: VCC = 2.7 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA Mask ROM: VCC = 2.2 to 5.5 V FLASH ROM: VCC = 2.7 to 5.5 V V V V 0.3 V 1.0 V 2.0 V 0.3 V 1.0 V 0.4 V 0.5 V 0.5 V VI = VCC (Pin floating. Pull up transistors “off”) VI = VCC VI = VCC 1.5 5.0 µA 5.0 µA 4.0 VI = VSS (Pin floating. Pull up transistors “off”) VI = VSS µA –5.0 µA –5.0 µA VI = VSS –4.0 VI = VSS (Pull up transistors “on”) When clock stopped VCC = 5.0 V, Ta = 25 °C VCC = 5.0 V, Ta = 25 °C –0.2 –0.5 mA 2000 125 5.5 3000 187.5 V kHz kHz 2.0 1000 62.5 µA Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”. 2: RXD1, SCLK1, INT0, and INT1 (P36 selected) have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level). 3: It is available only when operating key-on wake up. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 99 of 117 7542 Group Electrical Characteristics (continued) Table 19 Electrical characteristics (2) (FLASH ROM version: V CC = 2.7 to 5.5V, Mask ROM version: V CC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. Double-speed mode Mask ROM mA 5.5 9.0 ICC Power source f(XIN) = 8 MHz current FLASH ROM mA Output transistors “off” 4.8 7.5 High-speed mode Mask ROM mA 3.5 6.5 FLASH ROM mA 3.0 5.5 Middle-speed mode Mask ROM mA 2.0 5.0 FLASH ROM mA 1.7 4.2 High-speed mode Mask ROM mA f(XIN) = 2 MHz, 0.4 1.2 Mask ROM: VCC = 2.2 V FLASH ROM: VCC = 2.7 V Output transistors “off” Frequency/1 On-chip oscillator operation mode, Frequency/2 Output transistors “off” Frequency/8 Frequency/128 f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors “off” f(XIN) = 2 MHz, Mask ROM: VCC = 2.2 V FLASH ROM: VCC = 2.7 V (in WIT state), functions except timer 1 disabled, Output transistors “off” On-chip oscillator operation mode, (in WIT state), functions except timer 1 disabled, Output transistors “off” Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 °C All oscillation stopped (in STP state) Output transistors “off” Ta = 85 °C FLASH ROM 1.0 2.8 mA Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM 1.5 1.4 0.9 1.0 0.35 0.65 0.2 0.55 1.6 3.2 2.4 2.2 1.9 1.0 1.3 0.6 1.0 3.2 mA FLASH ROM 1.2 2.6 mA Mask ROM 0.2 mA FLASH ROM 0.6 mA Mask ROM 0.2 0.6 mA FLASH ROM 0.12 0.4 mA Mask ROM FLASH ROM Mask ROM FLASH ROM Mask ROM FLASH ROM 0.5 0.5 0.1 0.55 1.0 3.0 10 10 mA mA µA µA µA µA Note: Increment when A/D conversion is executed includes the reference power source input current (IVREF). Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 100 of 117 mA mA mA mA mA mA mA mA 7542 Group A/D Converter Characteristics Table 20 A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol Parameter — — Resolution Absolute accuracy tCONV Conversion time Min. Typ. Max. 10 ±3 ±4 122 61 Ta = 25 °C Mask ROM VCC = VREF = 2.7 to 5.5 V FLASH ROM AD conversion clock = f(XIN)/2 AD conversion clock = f(XIN) RLADDER Ladder resistor IVREF Reference power source input current II(AD) Limits Test conditions VREF = 5.0 V VREF = 3.0 V 50 30 55 150 90 200 120 5.0 A/D port input current Unit Bits LSB tc(XIN) kΩ µA µA Note: AD conversion accuracy may be low under the following conditions; (1) When the VREF voltage is set to be lower than the VCC voltage, an analog circuit in this microcomputer is affected by noise. The accuracy is lower than the case the VREF voltage is the same as VCC voltage. (2) When the VREF voltage is 3.0 V or less at the low temperature, the AD conversion accuracy may be very lower than at room temperature. When system is used at low temperature, that VREF is 3.0 V or more is recommended. Electrical Characteristics of 7542 Group Flash Memory Table 21 Electrical Characteristics of 7542 Group Flash Memory Symbol Test conditions Parameter Program/Erase endurance (Note 1) Limits Min. Block erase time td(SR-ES) Max. 50 400 µs 100 Byte program time Unit Typ. times 2Kbyte-block 0.2 9 s 8Kbyte-block 0.4 9 s 16Kbyte-block 0.7 9 s 8 ms Time delay from suspend request until erase suspend Erase suspend request interval 10 Program, erase voltage 2.7 5.5 Read voltage 2.7 5.5 V 0 60 °C Program, erase temperature Ta = 55 °C Data hold time 20 ms V year Note 1. Definition of program and erase The program and erase endurance shows an erase endurance for every block. If the program and erase endurance is “n” times (n = 100), “n” times erase can be performed for every block. For example, if performing 1-byte write to the distinct addresses on Block A of 2Kbyte block 2048 times and then erasing that block, program and erase endurance is counted as one time. However, do not perform multiple programs to the same address for one time erase. (disable overwriting). Erase-suspend request (interrupt request) Erase suspend flag Fig. 117 Time delay from suspend request until erase suspend Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 101 of 117 td(SR-ES) 7542 Group Timing Requirements Table 22 Timing requirements (1) (FLASH ROM version: V CC = 4.0 to 5.5V, Mask ROM version: V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. µs 2 tW(RESET) Reset input “L” pulse width ns 125 tC(XIN) External clock input cycle time ns 50 tWH(XIN) External clock input “H” pulse width ns 50 tWL(XIN) External clock input “L” pulse width ns 200 tC(CNTR0) CNTR0 input cycle time ns 80 tWH(CNTR0) CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1) ns 80 tWL(CNTR0) CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1) ns 800 tC(SCLK1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) ns 370 tWH(SCLK1) Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2) ns 370 tWL(SCLK1) Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2) ns 220 tsu(RxD1–SCLK1) Serial I/O1, serial I/O2 input set up time ns 100 th(SCLK1–RxD1) Serial I/O1, serial I/O2 input hold time Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. Table 23 Timing requirements (2) (FLASH ROM version: V CC = 2.7 to 5.5V, Mask ROM version: V CC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2) Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time Min. 2 250 100 100 500 230 230 2000 950 950 400 200 Typ. Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 102 of 117 Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns 7542 Group Table 24 Timing requirements (3) (Mask ROM version: VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) (This is only for the mask ROM version.) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1–SCLK1) th(SCLK1–RxD1) Limits Parameter Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input “H” pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input “L” pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input “H” pulse width (Note 2) Serial I/O1, serial I/O2 clock input “L” pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time Min. 2 500 200 200 1000 460 460 4000 1900 1900 800 400 Typ. Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 003016) is set to “1” (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 103 of 117 Unit Max. µs ns ns ns ns ns ns ns ns ns ns ns 7542 Group Switching Characteristics Table 25 Switching characteristics (1) (FLASH ROM version: V CC = 4.0 to 5.5V, Mask ROM version: V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Parameter Serial I/O1, serial I/O2 clock output “H” pulse width Serial I/O1, serial I/O2 clock output “L” pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. Typ. Max. tC(SCLK1)/2–30 tC(SCLK1)/2–30 140 –30 10 10 30 30 30 30 Unit ns ns ns ns ns ns ns ns Note 1: Pin XOUT is excluded. Table 26 Switching characteristics (2) (FLASH ROM version: V CC = 2.7 to 5.5V, Mask ROM version: V CC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Serial I/O1, serial I/O2 clock output “H” pulse width Serial I/O1, serial I/O2 clock output “L” pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) tC(SCLK1)/2–50 tC(SCLK1)/2–50 350 –30 20 20 50 50 50 50 Typ. Max. ns ns ns ns ns ns ns ns Note 1: Pin XOUT is excluded. Table 27 Switching characteristics (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1–TxD1) tv(SCLK1–TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Parameter Serial I/O1, serial I/O2 clock output “H” pulse width Serial I/O1, serial I/O2 clock output “L” pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Switching characteristics measurement circuit diagram Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 104 of 117 Limits Min. tC(SCLK1)/2–70 tC(SCLK1)/2–70 450 –30 25 25 70 70 70 70 Unit ns ns ns ns ns ns ns ns 7542 Group tC(CNTR0) tWL(CNTR0) tWH(CNTR0) 0.8VCC CNTR0 0.2VCC tWL(CNTR0) tWH(CNTR0) INT0, INT1 CAP0, CAP1 0.8VCC 0.2VCC tW(RESET) RESET 0.8 VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN 0.2VCC tC(SCLK1) tf SCLK1 tWL(SCLK1) tsu(RxD1-SCLK1) td(SCLK1-TxD1) Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 105 of 117 th(SCLK1-RxD1) 0.8VCC 0.2 VCC RXD1 (at receive) Fig. 118 Timing chart tWH(SCLK1) 0.8VCC 0.2VCC TXD1 (at transmit) tr tv(SCLK1-TxD1) 7542 Group PACKAGE OUTLINE JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP32-7x7-0.80 PLQP0032GB-A 32P6U-A 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 16 25 bp c c1 HE *2 E b1 Reference Symbol 32 9 1 ZE Terminal cross section Nom D 6.9 7.0 7.1 E 6.9 7.0 7.1 A2 8 ZD Dimension in Millimeters Min 1.4 HD 8.8 9.0 9.2 HE 8.8 9.0 9.2 A1 0 0.1 0.2 bp 0.32 0.37 0.42 0.09 0.145 A c A F A2 Index mark A1 1.7 0.35 b1 c 0° L1 e y *3 e Detail F bp 0.20 y 0.10 0.7 ZD 0.7 ZE L 0.3 JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-SSOP36-8.4x15-0.80 PRSP0036GA-A 36P2R-A 0.5g 0.7 19 *1 E 36 0.5 1.0 L1 HE 8° 0.8 x x 0.20 0.125 c1 L Max F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 18 Index mark c *2 D A1 A A2 e *3 y bp Reference Symbol Dimension in Millimeters Min Nom Max D 14.8 15.0 15.2 E 8.2 8.4 8.6 A2 2.0 L A 2.4 A1 0.05 bp 0.35 0.4 c 0.13 0.15 0° Detail F HE 11.63 11.93 12.23 e 0.65 0.8 0.95 0.3 0.5 L Page 106 of 117 0.2 10° y Rev.3.03 Jul 11, 2008 REJ03B0006-0303 0.5 0.15 0.7 JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-SDIP32-8.9x28-1.78 PRDP0032BA-A 32P4B 2.2g 17 1 16 *1 E 32 e1 7542 Group c D Reference Symbol L A1 A A2 *2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Dimension in Millimeters Min Nom Max e1 9.86 10.16 10.46 D 27.8 28.0 28.2 E 8.75 8.9 9.05 5.08 A SEATING PLANE *3 b 3 e bp *3 A1 b2 0.51 3.8 A2 bp 0.35 0.45 b2 0.63 0.73 b3 0.9 1.0 1.3 c 0.22 0.27 0.34 e 1.528 1.778 2.028 L 3.0 0° JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-HWQFN36-6x6-0.50 PWQN0036KA-A 36PJW-A 0.07g 0.55 1.03 15° D 27 19 28 27 19 18 28 18 E1 E D2 Lp 10 36 10 9 1 36 9 1 e bp Reference Symbol F Dimension in Millimeters Min Nom D 5.9 6.0 6.1 E 5.9 6.0 6.1 x A2 0.75 A A2 A 0.8 A1 0 bp 0.15 e Lp A1 y Detail F Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 107 of 117 Max 0 0.05 0.2 0.25 0.5 0.5 0.6 x 0.7 0.05 y 0.05 D2 4.26 E1 4.26 7542 Group APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. <Reason> After a reset, the contents of the processor status register (PS) are undefined except for the I flag which is “1”. Reset ↓ Initializing of flags ↓ Main program Fig. 1 Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. Stored PS Fig. 2 Stack memory contents after PHP instruction execution Rev.3.03 Jul 11, 2008 REJ03B0006-0303 (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be initialized to “1” before each calculation. Set D flag to “1” ↓ ADC or SBC instruction ↓ NOP instruction ↓ SEC, CLC, or CLD instruction Fig. 3 Status flag at decimal calculations 3. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4.Multiplication and Division Instructions (1) The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. (2) The execution of these instructions does not change the contents of the processor status register. (S) (S)+1 2. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. Page 108 of 117 7542 Group 5. Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (SFR). The read-modify-write instruction operates in the following sequence: read one-byte of data from memory, modify the data, write the data back to original memory. The following instructions are classified as the read-modify-write instructions in the 740 Family. (1) Bit management instructions: CLB, SEB (2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF (3) Add and subtract instructions: DEC, INC (4) Logical operation instructions (1’s complement): COM Add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = “1” operate in the way as the readmodify-write instruction. Do not execute the read invalid SFR. <Reason> When the read-modify-write instruction is executed to read invalid SFR, the instruction may cause the following consequence: the instruction reads unspecified data from the area due to the read invalid condition. Then the instruction modifies this unspecified data and writes the data to the area. The result will be random data written to the area or some unexpected event. NOTES ON PERIPHERAL FUNCTIONS Notes on I/O Ports 1. Setting of 32-pin version and PWQN0036KA-A package version (1) Set direction registers of ports P2 6, P27, P35 and P36 to output. (2) Select P33 for the INT1 function by the INT1 input port selection bit (bit 2 of interrupt edge selection register (address 3A16)). (3) Be sure to set P36/INT1 input level selection bit (bit 1 of port P1P3 control register (address 1716)) to “0”. 2. Port P0P3 drive capacity control register The number of LED drive port (drive capacity is HIGH) is 8. 3. Pull-up control register When using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. <Reason> Pull-up control is effective only when each direction register is set to the input mode. 4. Notes in stand-by state In stand-by state*1 for low-power dissipation, do not make input levels of an input port and an I/O port “undefined”. Pull-up (connect the port to Vcc) or pull-down (connect the port to Vss) these ports through a resistor. When determining a resistance value, note the following points: • External circuit • Variation of output levels during the ordinary operation When using a built-in pull-up resistor, note on varied current values: • When setting as an input port : Fix its input level • When setting as an output port : Prevent current from flowing out to external. <Reason> The output transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes “undefined” depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input port and an I/O port are “undefined”. This may cause power source current. *1 stand-by state : the stop mode by executing the STP instruction the wait mode by executing the WIT instruction 5. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. <Reason> The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an I/O port, the following is executed to all bits of the port latch. • As for a bit which is set for an input port : The pin state is read in the CPU, and is written to this bit after bit managing. • As for a bit which is set for an output port : The bit value of the port latch is read in the CPU, and is written to this bit after bit managing. Note the following : • Even when a port which is set as an output port is changed for an input port, its port latch holds the output data. • As for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. *2 bit managing instructions : SEB, and CLB instructions Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 109 of 117 7542 Group 6. Direction register The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read-modify-write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. Termination of Unused Pins 1. Terminate unused pins Perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) I/O ports Set the I/O ports for the input mode and connect each pin to VCC or VSS through each resistor of 1 kΩ to 10 kΩ. The port which can select a built-in pull-up resistor can also use the built-in pull-up resistor. When using the I/O ports as the output mode, open them at “L” or “H”. • When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. • Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. Termination remarks (1) I/O ports setting as input mode [1] Do not open in the input mode. <Reason> • The power source current may increase depending on the firststage circuit. • An effect due to noise may be easily produced as compared with proper termination (1) shown on the above “1. Terminate unused pins”. [2] Do not connect to VCC or VSS directly. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur. [3] Do not connect multiple ports in a lump to VCC or VSS through a resistor. <Reason> If the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 110 of 117 Notes on Interrupts 1. Change of relevant register settings When not requiring for the interrupt occurrence synchronous with the following case, take the sequence shown in Figure 4. • When switching external interrupt active edge • When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Set the corresponding interrupt enable bit to “0” (disabled) . ↓ Set the interrupt edge selection bit, active edge switch bit, or the interrupt source selection bit. ↓ NOP (One or more instructions) ↓ Set the corresponding interrupt request bit to “0” (no interrupt request issued). ↓ Set the corresponding interrupt enable bit to “1” (enabled). Fig. 4 Sequence of changing relevant register <Reason> When setting the followings, the interrupt request bit of the corresponding interrupt may be set to “1”. • When switching external interrupt active edge INT0 interrupt edge selection bit (bit 0 of Interrupt edge selection register (address 3A16)) INT1 interrupt edge selection bit (bit 1 of Interrupt edge selection register) CNTR0 active edge switch bit (bit 2 of timer X mode register (address 2B16)) Capture 0 interrupt edge selection bit (bits 1 and 0 of capture mode register (address 2016)) Capture 1 interrupt edge selection bit (bits 3 and 2 of capture mode register) 2. Check of interrupt request bit When executing the BBC or BBS instruction to determine an interrupt request bit immediately after this bit is set to “0”, take the following sequence. <Reason> If the BBC or BBS instruction is executed immediately after an interrupt request bit is cleared to “0”, the value of the interrupt request bit before being cleared to “0” is read. Set the interrupt request bit to “0” (no interrupt issued) ↓ NOP (one or more instructions) ↓ Execute the BBC or BBS instruction Fig. 5 Sequence of check of interrupt request bit 7542 Group 3. Interrupt discrimination bit Use an LDM instruction to clear to “0” an interrupt discrimination bit. LDM #%0000XXXX, $0B Set the following values to “X” “0”: an interrupt discrimination bit to clear “1”: other interrupt discrimination bits Ex.) When a key-on wakeup interrupt discrimination bit is cleared; LDM #%00001110 and $0B. 4. Interrupt discrimination bit and interrupt request bit For key-on wakeup, UART1 bus collision detection, A/D conversion and Timer 1 interrupt, even if each interrupt valid bit (interrupt source set register (address 0A16)) is set “0: Invalid”, each interrupt discrimination bit (interrupt source discrimination register (address 0B16)) is set to “1: interrupt occurs” when corresponding interrupt request occurs. But corresponding interrupt request bit (interrupt request registers 1, 2 (addresses 3C16, 3D16) is not affected. Notes on Timers 1. When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). 2. When a count source of timer X, timer A or timer B is switched, stop a count of the timer. Notes on Timer X 1. CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit (bit 2 of timer X mode register (address 2B16)). When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR0 pin input signal. When this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input signal. 2. Timer X count source selection The f(XIN) (frequency not divided) can be selected by the timer X count source selection bits (bits 1 and 0 of timer count source set register (address 2A16)) only when the ceramic oscillation or the on-chip oscillator is selected. Do not select it for the timer X count source at the RC oscillation. 3. Pulse output mode Set the direction register of port P14, which is also used as CNTR0 pin, to output. When the TXOUT pin is used, set the direction register of port P03, which is also used as TXOUT pin, to output. 4. Pulse width measurement mode Set the direction register of port P14, which is also used as CNTR0 pin, to input. Notes on Timer A, B 1. Setting of timer value When “1: Write to only latch” is set to the timer A (B) write control bit, written data to timer register is set to only latch even if timer is stopped or operating. Accordingly, in order to set the initial value for timer when it is stopped, set “0: Write to latch and timer simultaneously” to timer A (B) write control bit. 2. Read/write of timer A Stop timer A to read/write its data in the following state; XIN oscillation selected by clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B16)), and the on-chip oscillator output is selected as the timer A count source. 3. Read/write of timer B Stop timer B to read/write its data in the following state; XIN oscillation selected by clock division ratio selection bits, the timer A underflow is selected as the timer B count source, and the on-chip oscillator output is selected as the timer A count source. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 111 of 117 7542 Group Notes on Output Compare Notes on Input Capture 1. When the selected source timer of each compare channel is stopped, written data to compare register is loaded to the compare latch simultaneously. 1. If the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. Accordingly, some countermeasure by software is recommended, for example comparing the values that twice of read. 2. Do not write the same data to both of compare latch x0 (x=0, 1, 2, 3) and x1. 3. When setting value of the compare register is larger than timer setting value, compare match signal is not generated. Accordingly, the output waveform is fixed to “L” or “H” level. However, when setting value of another compare register is smaller than timer setting value, this compare match signal is generated. Accordingly, if the corresponding compare latch y (y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1” (valid), compare match interrupt request occurs. 4. When the compare x trigger enable bit is cleared to “0” (disabled), the match trigger to the waveform output circuit is disabled. Accordingly, the output waveform can be fixed to “L” or “H” level. However, in this case, the compare match signal is generated. Accordingly, if the corresponding compare latch y (y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to “1” (valid),compare match interrupt request occurs. 2. Timer A cannot be used for the capture source timer in the following state; • X IN oscillation selected by clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B16)) • Timer A count source: On-chip oscillator output. Timer B cannot be used for the capture source timer in the following state; • XIN oscillation selected by clock division ratio selection bits • Timer B count source: Timer A underflow • Timer A count source: On-chip oscillator output. 3. As shown below, when the capture input is performed to both capture latch 00 and 01 at the same time, the value of capture 0 status bit (bit 4 of capture/compare status register (address 2216)) is undefined (same as capture 1). • When “1” is written to capture latch 00 software trigger bit (bit 0 of capture software trigger register (address 1316)) and capture latch 01 software trigger bit (bit 1 of capture software trigger register) at the same time • When external trigger of capture latch 00 and software trigger of capture latch 01 occur at the same time • When external trigger of capture latch 01 and software trigger of capture latch 00 occur at the same time 4. When the capture interrupt is used as the interrupt for return from stop mode, set the capture 0 noise filter clock selection bits (bits 5 and 4 of capture mode register (address 2016)) to “00 (Filter stop)” (same as capture 1). Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 112 of 117 7542 Group Notes on Serial I/Oi (i=1, 2) 1. Clock synchronous serial I/O (1) When the transmit operation is stopped, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and transmit disabled). <Reason> Since transmission is not stopped and the transmission circuit is not initialized even if only the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in this case, since pins TxD i, RxD i , S CLKi , and S RDYi function as I/O ports, the transmission data is not output). When data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. When the serial I/Oi enable bit is set to “1” at this time, the data during internally shifting is output to the TxDi pin and an operation failure occurs. 3. Notes common to clock synchronous serial I/O and UART (1) Set the serial I/Oi (i=1, 2) control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to “0.” Clear both the transmit enable bit (TE) and the receive enable bit (RE) to “0” Set the bits 0 to 3 and bit 6 of the serial I/Oi control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to “1” Can be set with the LDM instruction at the same time Fig. 6 Sequence of setting serial I/Oi control register again (2) When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled), or clear the serial I/Oi enable bit to “0” (serial I/Oi disabled). (3) When the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive disabled) simultaneously. (any one of data transmission and reception cannot be stopped.) <Reason> In the clock synchronous serial I/O mode, the same clock is used for transmission and reception. If any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit disabled). Also, the transmission circuit cannot be initialized even if the serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled) (same as (1)). (4) When signals are output from the SRDYi pin on the reception side by using an external clock, set all of the receive enable bit, the SRDYi output enable bit, and the transmit enable bit to “1”. (5) When the SRDYi signal input is used, set the using pin to the input mode before data is written to the transmit/receive buffer register. 2. UART When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled). <Reason> Same as (1) shown on the above “1. Clock synchronous serial I/O“. When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled). When the transmit/receive operation is stopped, clear the transmit enable bit to “0” (transmit disabled) and receive enable bit to “0” (receive disabled). Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 113 of 117 (2) The transmit shift completion flag changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (3) When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set “1” to the transmit enable bit while the SCLKi is “H” state. Also, write to the transmit buffer register while the SCLKi is “H” state. (4) When the transmit interrupt is used, set as the following sequence. ➀ Serial I/Oi transmit interrupt enable bit is set to “0” (disabled). ➁ Serial I/Oi transmit enable bit is set to “1”. ➂ Serial I/Oi transmit interrupt request bit is set to “0” after 1 or more instructions have been executed. ➃ Serial I/Oi transmit interrupt enable bit is set to “1” (enabled). <Reason> When the transmit enable bit is set to “1”, the transmit buffer empty flag and transmit shift completion flag are set to “1”. Accordingly, even if the timing when any of the above flags is set to “1” is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. (5) Write to the baud rate generator (BRGi) while the transmit/receive operation is stopped. 7542 Group Notes on Serial I/O1 Notes on Serial I/O2 1. I/O pin function when serial I/O1 is enabled. The pin functions of P12/SCLK1 and P13/SRDY1 are switched to as follows according to the setting values of a serial I/O1 mode selection bit (bit 6 of serial I/O1 control register (address 1A16)) and a serial I/O1 synchronous clock selection bit (bit 1 of serial I/O1 control register). (1) Serial I/O1 mode selection bit → “1” : Clock synchronous type serial I/O is selected. • Setup of a serial I/O1 synchronous clock selection bit “0” : P12 pin turns into an output pin of a synchronous clock. “1” : P12 pin turns into an input pin of a synchronous clock. • Setup of a SRDY1 output enable bit (SRDY) “0” : P13 pin can be used as a normal I/O pin. “1” : P13 pin turns into a SRDY1 output pin. 1. I/O pin function when serial I/O2 is enabled The pin functions of P06/SCLK2 and P07/SRDY2 are switched to as follows according to the setting values of a serial I/O2 mode selection bit (bit 6 of serial I/O2 control register (address 3016)) and a serial I/O2 synchronous clock selection bit (bit 2 of serial I/O2 control register). (2) Serial I/O1 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. • Setup of a serial I/O1 synchronous clock selection bit “0”: P12 pin can be used as a normal I/O pin. “1”: P12 pin turns into an input pin of an external clock. • When clock asynchronous (UART) type serial I/O is selected, it functions P13 pin. It can be used as a normal I/O pin. Note on Bus Collision Detection When serial I/O1 is operating at half-duplex communication, set bus collision detection interrupt to be disabled. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 114 of 117 (1) Serial I/O2 mode selection bit → “1” : Clock synchronous type serial I/O is selected. • Setup of a serial I/O2 synchronous clock selection bit “0” : P06 pin turns into an output pin of a synchronous clock. “1” : P06 pin turns into an input pin of a synchronous clock. • Setup of a SRDY2 output enable bit (SRDY) “0” : P07 pin can be used as a normal I/O pin. “1” : P07 pin turns into a SRDY2 output pin. (2) Serial I/O2 mode selection bit → “0” : Clock asynchronous (UART) type serial I/O is selected. • Setup of a serial I/O2 synchronous clock selection bit “0”: P06 pin can be used as a normal I/O pin. “1”: P06 pin turns into an input pin of an external clock. • When clock asynchronous (UART) type serial I/O is selected, it functions P07 pin. It can be used as a normal I/O pin. 7542 Group Notes on A/D conversion 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01µF to 1µF. Further, be sure to verify the operation of application products on the user side. <Reason> An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A/D conversion/comparison precision to be worse. 2. Clock frequency during A/D conversion The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. This may cause the A/D conversion precision to be worse. Accordingly, set f(XIN) in order that the A/D conversion clock is 250 kHz or over during A/D conversion. 3. A/D conversion clock selection Select f(XIN)/2 as an A/D conversion clock by setting the A/D conversion clock selection bit (bit 3 of A/D control register (address 3416)) when RC oscillation is used. The f(XIN) can be also used as an A/D conversion clock only when ceramic oscillation or on-chip oscillator is used. 4. Analog input pin selection P26/AN6 and P27/AN7 can be used only for PRSP0036GA-A package version. 5. Read A/D conversion register • 8-bit read Read only the A/D conversion low-order register (address 3516). •10-bit read Read the A/D conversion high-ordrer register (address 3616) first, and then, read the A/D conversion low-order register (address 3516). In this case, the high-order 6 bits of address 36 16 returns “0” when read. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 115 of 117 6. A/D conversion accuracy As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value.. (2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Notes on Watchdog Timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the oscillation stabilizing time after the STP instruction is released. In order to avoid the underflow of the watchdog timer, the watchdog timer control register must be written just before executing the STP instruction. 3. The STP instruction function selection bit (bit 6 of watchdog timer control register (address 0039 16)) can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. 4. A count source of watchdog timer is affected by the clock division selection bit of the CPU mode register. The f(XIN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the CPU clock. Notes on RESET pin 1. Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the Vss pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : • Make the length of the wiring which is connected to a capacitor as short as possible. • Be sure to verify the operation of application products on the user side. <Reason> If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure. 7542 Group Notes on Clock Generating Circuit 1. Switch of ceramic and RC oscillations After releasing reset, the oscillation mode selection bit (bit 5 of CPU mode register (address 3B16)) is “0” (ceramic oscillation selected). When the RC oscillation is used, after releasing reset, set this bit to “1”. 2. Double-speed mode The double-speed mode can be used only when a ceramic oscillation is selected. Do not use it when an RC oscillation is selected. 3. CPU mode register Oscillation mode selection bit (bit 5), processor mode bits (bits 1 and 0) of CPU mode register (address 3B16) are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by erroneously writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting, it is disabled to write any data to the bit. (The emulator MCU “M37542RSS” is excluded.) Also, when the read-modify-write instructions (SEB, CLB, etc.) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. 4. Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 84 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 84. 5. On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VCC through a 1 kΩ to 10 kΩ resistor and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that this margin of frequencies when designing application products. 6. Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins X IN and XOUT at the shortest distance. Externally connect a damping resistor Rd depending on the oscillation frequency. A feedback resistor is built-in. Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator. 7. RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 116 of 117 8. External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. Select “0” (ceramic oscillation) to oscillation mode selection bit. 9. Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O, Serial I/O2, A/D converter, Watchdog timer) A count source of watchdog timer is affected by the clock division selection bit of the CPU mode register. The f(XIN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the CPU clock. Notes on Oscillation Control 1. Oscillation stop detection circuit (1) When the stop mode is used, set the oscillation stop detection function to “invalid”. (2) When the ceramic or RC oscillation is stopped by the XIN oscillation control bit (bit 4 of CPU mode register (address 3B16)), set the oscillation stop detection function to “invalid”. 2. Stop mode (1) When the stop mode is used, set the oscillation stop detection function to “invalid”. (2) When the stop mode is used, set “0” (STP instruction enabled) to the STP instruction function selection bit of the watchdog timer control register (bit 6 of watchdog timer control register (address 3916)). (3) The oscillation stabilizing time after release of STP instruction can be selected from “set automatically ”/“not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction (bit 0 of MISRG (address 3816)). When “0” is set to this bit, “01 16” is set to timer 1 and “FF 16” is set to prescaler 1 automatically at the execution of the STP instruction. When “1” is set to this bit, set the wait time to timer 1 and prescaler 1 according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. (4) Do not execute the STP instruction during the A/D conversion. 7542 Group Notes on On-chip Oscillation Division Ratio • When the clock division ratio is switched from f(XIN) to on-chip oscillator by the clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B16)), the on-chip oscillator division ratio (bits 1 and 0 of on-chip oscillation division ratio selection register (address 37 16 )) is “10 2” (on-chip oscillator middle-speed mode (ROSC/8)). Notes on Oscillation Stop Detection Circuit 1. After the reset by the oscillation stop detection, the value of following bits are retained, not initialized. • Ceramic or RC oscillation stop detection function active bit Bit 1 of MISRG (address 3B16) • Oscillation stop detection status bit Bit 3 of MISRG 2. Oscillation stop detection status bit is initialized (“0”) by the following operation. • External reset • Write “0” data to the ceramic or RC oscillation stop detection function active bit. 3. The oscillation stop detection circuit is not included in the emulator MCU “M37542RSS”. Electric Characteristic Differences Between Mask ROM, Flash Memory MCUs There are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask ROM and flash memory version MCUs due to the differences in the manufacturing processes. When manufacturing an application system with the flash memory and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. NOTES ON HARDWARE Handling of Power Source Pin Notes on CPU Rewrite Mode Take the notes described below when rewriting the flash memory in CPU rewrite mode. 1. Operation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using the clock division ratio selection bits (bits 6 and 7 of CPU mode register). 2. Instructions inhibited against use The instructions which refer to the internal data of the flash memory cannot be used during CPU rewrite mode. 3. Interrupts inhibited against use The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. 4. Watchdog timer If the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely initialized during program or erase. 5. Reset Reset is always valid. The MCU is activated using the boot mode at release of reset in the condition of CNVss = “H”, so that the program will begin at the address which is stored in addresses FFFC16 and FFFD16 of the boot ROM area. Rev.3.03 Jul 11, 2008 REJ03B0006-0303 Page 117 of 117 In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended. 7542 Group Datasheet REVISION HISTORY Rev. Date Description Summary Page – 1 8 First edition issued FEATURES; Memory size revised. Memory size; Flash memory size revised. Fig.8; ROM size revised. 9 Table 2; ROM size revised. 10 Central Processing Unit (CPU); Description revised. 28 Fig.26; Port P03 direction register revised. 36 Fig.42; Modulation output revised. 37 Fig.43; Modulation output revised. 53 Reset Circuit; Description revised. 55 (3) RC oscillation; Description revised. 56 (1) Oscillation control • Stop mode Description about FLASH added. 57 Fig.77; revised. 65 to 72 FLASH MEMORY MODE added. 73 to 82 ELECTRICAL CHARACTERISTICS added. 1 FEATURES: Interrupt, Power source voltage, Power dissipation revised. 2.01 Dec 03, 2003 8 Fig. 8: Development schedule revised. 9 Table 2: ROM size for Flash memory version revised. 13 Fig. 12: Note added. 15 Fig. 14: Flash memory control register 2 added. 28 Fig. 26: “CPU mode register” added, description for timer 1 interrupt request revised. 30 Fig. 29: “CPU mode register” added. 33 Fig. 37 and Fig. 38: Pin name added. 34 Fig. 39: Pin name added. 40 Fig. 46 and Fig. 47: Pin name added. 51 A-D Converter revised. 54 Fig. 70 Flash memory control register 2 added. 59 Fig. 79 (5), (6) revised. 64 ■ A-D Converter revised. 65 DATA REQUIRED FOR MASK ORDERS revised. 68 Description of flash memory control register 0 (bit 2), Fig. 83 revised. 69 Description of flash memory control register 2, Fig. 85 and Table 8 added. 70 Fig. 86 revised. 71 Table 9 revised. 85 to103 ELECTRICAL CHARACTERISTICS; General purpose revised. Extended operating temperature version added. 1 FEATURES: The minimum instruction execution time revised. 2.02 Jan 06, 2004 Note 2 eliminated. 10 Stack pointer (S): Reference number of Figure in description revised. 79 Table 12: P07 (BUSY output) added. 82 Fig. 95: “BUSY” added to P07. 83 Fig. 96, Fig. 97: “BUSY” added to P07. 84 Fig. 98, Fig. 99: CNVSS revised. 91 Table 19, Table 20 Timing requirements (General purpose) Vcc for FLASH ROM version and Mask ROM version revised. 93 Table 22, Table 23 Switching characteristics (General purpose) Vcc for FLASH ROM version and Mask ROM version revised. 1.00 Nov 27, 2002 2.00 Apr 21, 2003 A-1 7542 Group Datasheet REVISION HISTORY Rev. Date Description Summary Page Information about 36PJW-A package version added. - Fig.4 Pin configuration added. - Fig.9 Functional block diagram added. - Table 1: Notes 2, 3 revised. - 36PJW-A package added. - Table 2 List of supported products revised. - I/O Ports description and Fig. 19: Note revised. - Table 5: Notes 2, 3 revised. - INTEDGE revised. - Fig.24: Note revised. Table 12: P00–P03, P07 → P00–P03 Fig.100, Fig.101: td(CNVss-port) → th(CNVss-port) Table 17: ICC data for FLASH ROM added. Table 18: Absolute accuracy for FLASH ROM added. Table 29: ICC data for FLASH ROM added. Table 30: Absolute accuracy for FLASH ROM added. Package: Description of 36PJW-A revised. Table 2: M37542M2-XXXHP added. Fig. 79, Fig. 80 a bit name revised. Countermeasure against noise added. (NOTES ON PERIPHERAL FUNCTIONS are included in APPENDIX at the end of this data sheet.) 88 Part name revised. 108 36PJW-A package added. 109 to 118 APPENDIX added. 1 2.05 Jun 08, 2004 FEATURES • Programmable I/O ports, • A/D converter: Description added. 3 Fig.4: Pin 1 to Pin 3 revised. M37542F8HP: Note added. 11 Table 2: M37542F8HP: Note added. 53 Notes on A/D conversion added. 70 Table 7: Number of program/erase times revised. 88 Fig. 110: Figure title and table in figure revised, and Note added. 89 M37542F8HP: Note added. 117 Notes on A/D accuracy added. 119 Notes on Oscillation Stop Detection Circuit 1: • Each bit of Port register Pi eliminated. Note on Power Source Voltage added. All pages Words standardized: On-chip oscillator, A/D converter 2.06 Aug 24, 2004 73 Fig. 97: Bits 0 to 3 revised. 79 (1) ROM Code Protect Function: Some description added. 82 ● Standard serial I/O Mode: Some description revised. 83 to 92 Description of standard serial I/O mode 1 and standard serial I/O mode 2 separated. 86 Fig. 107 Handling example of control pins in standard serial I/O mode 1 added. 91 Fig. 112 Handling example of control pins in standard serial I/O mode 2 added. 2.03 Feb 10, 2004 3 8 9 10 11 18 19 23 26 81 86 91 92 101 102 10 2.04 Apr 14, 2004 11 60 65 to 68 A-2 7542 Group Datasheet REVISION HISTORY Rev. Date Description Summary Page 1 2 ROM size of Flash memory version revised. Fig.1 M37542F8GP → M37542FxGP Fig.2 M37542F8FP → M37542FxFP 3 Fig.3 M37542F8SP → M37542FxSP 5 Table 1 Performance overview added. 10 Table 2 Function of Vcc, Vss revised. 11 Flash memory size revised, and Fig.10 M37542F4 added. 12 Table 3 M37542F4GP,M37542F4FP,M37542F4SP added. 21 Fig. 20 (5) Port P05 revised. 24 Table 7 Termination of unused pins added. 46 Description of Serial I/O revised. 53 [UART2 control register (UART2CON)] revised. 54 Fig. 64 UART2 contorl register revised. 60 Description of Clock Generating Circuit revised. Fig. 74 revised. 63 Fig. 79 revised. 72 Table 9 Temperature at program/erase added. 73 Fig.94 16 Kbyte ROM Product added. 77 Table 11 List of software commands (CPU rewrite mode) revised. 86 Fig.104 M37542F8GP → M37542FxGP 87 Fig.105 M37542F8SP → M37542FxSP Fig.106 M37542F8FP → M37542FxFP 91 Fig.109 M37542F8GP → M37542FxGP 92 Fig.110 M37542F8SP → M37542FxSP Fig.111 M37542F8FP → M37542FxFP 95 M37542F4GP,M37542F4FP,M37542F4SP added. Table 15 Conditions: Description added. 98 Table 18 Note 1 added. 100 Table 20, Fig. 104 added. 105 Table 28 Conditions: Description added. 108 Table 31 Note 1 added. 110 Table 34, Fig. 106 added. 114-122 Extended operating temperature 125 °C version added. 125 (2) How to reference the processor status register revised. Fig. 2 revised. Package revised. Bit name revised: STP instruction disable bit → STP instruction function selection bit 3.01 Nov 02, 2005 57 - Description for “Operation of STP instruction function selection bit” revised. - Notes on Watchdog Timer added. - Fig.68: Blodk diagram of watchdog timer revised. - Fig.69: Bit 6 and Bit 7 of WDTCON revised. Bit 6: Bit name and its description revised. (Bit function is not changed.) → STP instruction function selection bit 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution 61 -Notes on Clock Generating Circuit : Note on Count source added. 132 Notes on Watchdog Timer : Note on Count source added. 133 Notes on Clock Generating Circuit : Note on Count source added. 3.00 Jun 01, 2005 A-3 7542 Group Datasheet REVISION HISTORY Rev. Date Description Summary Page 12 17 Table 3 : ROM size revised and note 2 added. ROM : Description added. Fig. 15 : Note 2 added. 24 Table 7 : XIN and XOUT added. 57, 132 Notes on Watchdog Timer : Note 3 revised. 71 5. Setup for I/O ports : Note eliminated. 73 Fig 94 : Block diagram revised and note 3 added. 125 4. BRK instruction eliminated. 132 1. Analog input pin : Description revised. 1 3.03 Jul 11, 2008 FEATURES: Description revised. DESCRIPTION, FEATURES: “serial I/O” → “serial interface” 2 APPLICATION: “car” deleted. Fig. 1, Fig. 2 revised. 5 Table 1: Parameter revised, Note 1 deleted. 10 Table 2: Note 1 deleted. 11 Fig. 10 revised. 12 Table 3 revised. 21 Fig. 20 revised. 22 Fig. 21 revised. 25 to 29 Interrupts revised. 47 “Serial I/O” → “Serial interface” 66 • Oscillation stop detection circuit: Description revised 77 Fig. 101: Note 2, Note 3 revised. 87 Fig. 107 revised. 88 Fig. 108, Fig. 109 revised. 92 Fig. 112 revised. 93 Fig. 113 revised. 96 to 105 ELECTRICAL CHARACTERISTICS: 1.7542Group (General purpose); Description revised, “(General purpose)” deleted 2.7542Group (Extended operating temperature version), 3.7542Group (Extended operating temperature 125 °C version) deleted. 111 Notes on Timer A, B: “(bit 0 (bit 2 of timer .... (address 1D16))” deleted. 3.02 Oct 31, 2006 All trademarks and registered trademarks are the property of their respective owners. A-4 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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