Six-Sigma Methodologies Support Back-End Yield and Quality Metrics Improvement Tom Hand, Jennifer Welborn, and Jim Oerth Skyworks Solutions, 20 Sylvan Road, Woburn, MA 01801 [email protected] (781) 376-3539 Keywords: … Backend Process Visual Yield Six Sigma We believe that data drives improvement. Within the data, we discovered trends of yield dependency on operator at certain process steps, traced some types of damage to inprocess tools, and made data-driven decisions about alternate process flows to increase yield. We followed the trail wherever the data leads, getting back up into the process pipeline, eliminating the cause of scrap and waste. Figure 1: Analysis of Total Defectives by Operator 1200 1000 800 600 400 30X operator MV WB MJM 0 LT 200 FK This successful strategy started with SMART goals, aligning team members in the right direction. Skyworks wafer fab then uses a specific methodology to guide yield improvement activities in a consistent manner. This methodology ensures that resources will be applied to activities that will have the most impact. [1] We then use the six-sigma DMAIC process to understand the problem. Steps in this process include precise Definition of the problem, establishment of data collection activities (Measurement) to get meaningful data (counts that count), Analyzing distributions of data using tools such as analysis of variance (ANOVA), control charts, Pareto, t-test, and DOE to prioritize resources and find solutions to Improve yield, and establishment of Control methods to sustain the yield improvement. AOI vs. HVI Before starting on the road to visual yield recovery, it was imperative to understand the causes of yield loss. At that time, we were using HVI (human visual inspection) as the inspection method. As Figure 1 shows, there was significant operator-to-operator variation in the number of defects found. There was similar variation in the classification of the type of those defects. The combined variations led to a 15X uncertainty in the validity of the data. This information, combined with external reports on the repeatability and accuracy of HVI gave us the justification to purchase our first AOI (automated optical inspection) system. CAT This paper examines detailed process improvement strategies employed by the Skyworks Wafer Fab Backend Core Team. The team has achieved backend process (postprobe) yield increase of 3% per year for each of the last three years. Yield improvement activities also improve quality by reducing the PPM defective delivered to the downstream operations (the customer). Further, sustained yield improvement contributes significant cost savings. DEFINE PHASE AL INTRODUCTION METHODOLOGY Total defectives Abstract Six-sigma methodologies lead to understanding of root causes of yield loss in the back-end process. A datadriven decision making process is used to allocate resources and to optimize process flows. As a result, the yield of the backend process was increased by nine percentage points over the last three years. Figure 3: Low-Yielding Wafer Pareto AUTOMATED DEFECT CLASSIFICATION 7 120.0% 5 100.0% 5 80.0% 0 60.0% 2 40.0% 5 20.0% Cum ulative Percent Figure 2: Typical ROI Setup Low-Yielding Wafers Category Pareto Percent Defective One key to successful use of AOI for defect classification is through the use of Regions of Interest (ROIs). In this case ROIs are placed around critical features, and defects found within those critical areas are assigned the appropriate defect classification. See Figure 2. 0.0% er th O AO fo re be d e pp e Sc ra Pr ob M I ag e e am Sc r ib D isp ro ce ss Br ok en 0 Defect Type Figure 4: Defect Classification Pareto Defect Category Pareto MEASURE PHASE MES systems are established to automatically query databases and return yield performance reports to the engineering group on a regular periodic schedule. Customized reports are created within the MES system to investigate specialized relationships which might include process, tool, or operator effects on yield. Once the inspection recipes have been set up for AOI and integrated with the MES systems to capture the data, it is just a matter of time before volumes of data start streaming in (an engineers dream!). P ercent Defective 2 .5 2 1 120.0% .0 0 % 100.0% 0 % 80.0% .0 0 % .5 1 60.0% 0 % 40.0% .0 0 % 0 .5 Cum ulative P ercent 3 20.0% 0 % 0.0% 0 .0 0 % Gate Other Chipout Doubles Broken Die Defect Type ANALYZE PHASE This is probably the longest phase, and involves cooperation of the whole team to follow up on the actions suggested by the data. The data collected during the measure phase is used in conjunction with data analysis software to understand the extent of the extent of the problem, and in some cases to suggest solutions. Initially, two Pareto analyses were used to direct further in-depth analysis into the cause of yield loss. The first is a Pareto of causes of low yielding wafers; the second is a Pareto of defect categories. These are shown in Figures 3 and 4. The preceding two Paretos show the areas that were causing the most pain in terms of yield loss, and guided our reduction efforts. This was and continues to be an iterative process. As we reduce or eliminate the largest contributors to yield loss, a new category becomes the number one Pareto to be addressed. When the largest contributors to yield loss are identified, the challenge becomes to understand the causes. In some cases, there may be an understanding of the cause and effect relationship. Other cases require an in-depth investigation using the analytical tools of Six-Sigma. Figure 5: Visual Yield Improvement Plan Wafermap showing lines of gate damage Plan to Increase Visual Yield Defect Type/ Yield Loss Improvement Method Expected Improvement ECD Broken Wafer / 0.6% Six Sigma Team 0.3% Some benefit in June, complete by end of September Double Die/ 0.36% Scribe Parameter DOE 0.2% Complete DOE by end of June, benefit in July (Die Damage)/ 0.87% Wash Between Scribe and Break 0.4% Dependent on Scribe Move to Backside, ECD end of August Chipouts/ 0.82% Longhill Stretcher 0.3% Some benefit in June, ECD June 30th Other/ 1.1% Wafer Washer with High Pressure, Brush, Surfactant, and/or Megasonic 0.3% ECD 8/1 Gate damage appearing in lines leads to suspicion that probe, scribe, or break is involved in the defect. We suspect that the operator noticed the bad scribe lines, and used the roller breaker on the scribe tool to break those lines. This is not a documented process, and the capability was disabled on the tool. Total Improvement 1.5% There will be a number of case studies presented in the body of the paper showing how we broke down the problem areas to understand the cause and eliminate the offending defects. There are some illustrations below. This leads us into the improve phase. We took other steps within the scribe and break area to minimize the opportunity for die damage by decreasing handling contact to the wafer front surface, improving on our storage conditions between steps, and adding some cleaning steps prior to critical steps susceptible to damage. IMPROVE PHASE During the improve phase, a separate six-sigma team might convene to address each of the high contributing items to the defect Pareto. This is decided on a case-by case basis, depending on the complexity of the problem. Figure 8:Contamination Caused by Manual Handling Figure 6: Gate Defects: Die Damage at Scribe and Break. Largest Yield Loss During Scribe Operation is Die Damage Missing gates detected by August before test are electrical rejects Defects added by handling There was a fab-wide effort, using data like that above, to educate the operators about the damage caused by improper handling. This involved members of the Operations, Engineering and Training teams. Once they realized that the wafers are very fragile, and that there are consequences of mis-handling, the defect rate decreased. Figure 7: Damage Caused by Undocumented “Improvement” Having established yield improvement through the application of Six-Sigma tools, the last step is to establish controls to sustain the yield improvement into the future. Figure 10: Long-Term Yield Trend Chart up 9% CONTROL PHASE 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 Oct-08 Jul-08 Apr-08 Jan-08 Oct-07 Jul-07 Apr-07 Jan-07 Oct-06 Jul-06 Apr-06 Jan-06 8 3 CONCLUSIONS Six Sigma methodologies can be applied to the problem of visual yield to produce significant results. Further, sustained yield enhancement contributes significant cost savings, and improves customer quality. RESULTS Figure 9: Low-Yielding Wafers Reduced 50% or More per Category. Total Low-Yielding Wafers Reduced 5X. Percentage of wafers lower than yield target by defect category, FY 2008 7 6 5 3 Broken Bad Scribe Probe Damage Scrapped Before AOI Misprocess 2 Other Total 4 Acknowledgements The authors would like to thank the Skyworks Backend Core Team for their support and effort through this process. REFERENCES [1] J. Oerth, C.Doucette, S.Singh, S.Doonan “Yield Improvement Methodology in a pHEMT GaAs Fabrication Facility” 2008 GaAs Mantech Conference [2] D. Le Saux “The Effective Use of Process Control Plans and Process Failure Mode Effects Analysis in a GaAs Semiconductor Manufacturing Environment” 2006 GaAs Mantech Conference ACRONYMS AOI: Automated Optical Inspection HVI: Human Visual Inspection 1 0 O ct N obe ov e r D mb ec er em b Ja er nu Fe ary br au ry M ar ch Ap ril M ay Ju ne Ju l A y Se ugu st pt em b O er ct ob er % of wafers shipped below yield target Visual Yield, Jan06-Oct08 Yield, % One of the most effective methods of control is to establish yield control limits at the AOI step. If a wafer yield is below a minimum value, the wafer and/or process must be placed on hold for investigation. This allows for quick feedback and prevents an undetected problem from continuing. Each process must go through a process FMEA analysis. The process FMEA asks a series of questions: What can go wrong with the process? What effect would this have on the product? How severe would this be? What could cause the failure to occur? What is the probability of occurrence? What controls are already in place? How effective are these controls? [2] The FMEA proactively defines the weaknesses, and takes steps to reduce those weaknesses if they are a serious risk. The processes are also controlled through the use of a PCP/PFC (process control plan/process flow chart). These provide a documented “summary description” of the methods used to minimize process and product variation. They provide a structured approach for the design, selection and implementation of value added control methods. [2] Weekly, monthly, and quarterly monitoring of yields using a scorecard by process, product, and technology also provide a structured control method. [1] Backend Core Team meetings discuss yield each week as one of the key agenda items, which maintains focus. Last, but not least as a control method is the detailed information contained within the work instructions. Month