w WM8960-6158-FL32-M-REV1 Example Configurations DOC TYPE: EXAMPLE CONFIGURATIONS BOARD REFERENCE: WM8960-6158-FL32-M-REV1 BOARD TYPE: Customer Mini Board WOLFSON DEVICE(S): WM8960 DATE: June 2008 DOC REVISION: Rev 1.0 INTRODUCTION The WM8960-6158-FL32-M-REV1 Customer Mini Board is compatible with the 6158-EV1 customer evaluation board and together provide a complete hardware platform for evaluation of the WM8960. The WM8960 Customer Mini Board can also be used independently and connected directly to a processor board using flying wires or appropriate headers. This document will cover both, but performance data will be based on the Wolfson system with 6158-EV1 main board. Configurations covered are listed below: • DAC Playback to headphone on HP_L/R • ADC record from L/RINPUT1 • analogue bypass from L/RINPUT3 to 16Ω headphone on HPL/HPR • DAC playback to 8Ω speaker (Mini board) This document should be used as a starting point for evaluation of WM8960 but it will not cover every possible configuration. Assumptions: 1. The user is familiar with the 6158-EV1 main board and that the board is configured correctly for the path of interest (see related documents below) 2. The user has set up WISCE as per instruction and has control of the DUT (register settings provided in this document) Related documents: 1. WM8960-6158-FL32-M-REV1_Schematic_Layout.pdf 2. 6158-EV1-REV1_Schematic_Layout.pdf 3. WISCE Quick Start Guide.pdf WOLFSON MICROELECTRONICS plc To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ June 2008, Rev 1.0 Copyright ©2008 Wolfson Microelectronics plc WM8960-6158-FL32-M-REV1 Customer Information TABLE OF CONTENTS INTRODUCTION .............................................................................................................1 TABLE OF CONTENTS ..................................................................................................2 BOARD CONFIGURATION STAND-ALONE ..................................................................3 CONNECTION DIAGRAM.......................................................................................................3 I/O TABLE ...............................................................................................................................4 BOARD CONFIGURATION WITH 6158-EV1-REV1 MAIN BOARD ...............................5 DAC PLAYBACK TO HEADPHONE ON HP_L/R ....................................................................5 ADC RECORD FROM L/RINPUT1 ..........................................................................................8 ANALOGUE BYPASS FROM L/RINPUT3 TO 16Ω HEADPHONE ON HPL/HPR .................10 DAC PLAYBACK TO 8Ω SPEAKER (MINI BOARD) .............................................................12 APPLICATION SUPPORT ............................................................................................14 IMPORTANT NOTICE ...................................................................................................15 w Customer Information June 2008, Rev 1.0 2 WM8960-6158-FL32-M-REV1 Customer Information BOARD CONFIGURATION STAND-ALONE The WM8960 Customer Mini Board can be used a stand-alone module for direct connection to a processor board via flying leads or dedicated headers. This section will detail important considerations and provide all information required to do this without risking damage to the device. CONNECTION DIAGRAM Figure 1 below shows the connections required to power-up and control the WM8960 Customer Mini Board. Please refer to the Table 1 for further detail on external I/O connections. CLASS D SPEAKER CONTROL IF SPK_RP/RN SCLK SDIN SPK_RN SPKVDD SPK_RP SPK_LN SPK_LP/LN SPK_LP SPKVDD HP_R OUT_3 HP_L AUDIO IF ANALOGUE OUT ADCDAT ADCLRC/GPIO1 DACDAT DACLRC BCLK MCLK DBVDD L/R HPOUT AC coupled DCVDD RINPUT3/JD3 RINPUT2 RINPUT1 LINPUT1 LINPUT2 LINPUT3/JD2 MICBIAS MIC ANALOGUE IN Figure 1 Stand-Alone Board Configuration w Customer Information June 2008, Rev 1.0 3 WM8960-6158-FL32-M-REV1 Customer Information I/O TABLE SIGNAL BOARD REFERENCE IMPORTANT NOTES Voltage Supplies H4: pin 16 AVDD = 2.7V to 3.6V AVDD must be less or equal to SPKVDD1 and SPKVDD2 DBVDD H2: pin 4 DBVDD = 1.71V to 3.6V DCVDD H1: pin 16 DCVDD = 1.71V to 3.6V DCVDD must be less than or equal to AVDD and DBVDD SPKVDD1 SPKVDD2 Ground SPKVDD = 2.7V to 5.5V Common supply: H3: pin 10, H4: pin 4 AVDD DGND Common GND: Analogue, digital and speaker grounds must always be SPKGND1 H2: pin 2, H3: pin 8, within 0.3V of each other SPKGND2 H3: pin 16, H4: pin 8 AGND Control Interface SCLK SDIN Master Clock H3: pin 2 H3: pin 4 All control interface signals should swing between DGND and DBVDD MCLK H2: pin 6 Signal should swing between DGND and DBVDD H2: pin 8 H2: pin 10 H2: pin 12 H2: pin 14 H2: pin 16 All audio interface signals should swing between DGND and DBVDD Audio Interface BCLK DACLRC DACDAT ADCLRC/GPIO1 ADCDAT Analogue Inputs LINPUT1 H1: pin 8 LINPUT2 H1: pin 6 LINPUT3/JD2 H1: pin 4 RINPUT1 H1: pin 10 RINPUT2 H1: pin 12 RINPUT3/JD3 H1: pin 14 Analogue Outputs Full scale swing should not exceed AVDD/3.3 Vrms MICBIAS H1: pin 2 Microphone Bias VMID TP27 Midrail voltage decoupling capacitor SPK_RN H3: pin 6 Right speaker negative output (unfiltered) TP19 Right speaker negative output (low-pass filtered) SPK_RP SPK_LN H3: pin 12 Right speaker positive output (unfiltered) TP22 Right speaker positive output (low-pass filtered) H3: pin 14 Left speaker negative output (unfiltered) TP23 Left speaker negative output (low-pass filtered) H4: pin 2 Left speaker positive output (unfiltered) TP25 Left speaker positive output (low-pass filtered) HP_L H4: pin 14 HP output (left channel) or left channel of AC coupled HP Jack (J3) HP_R H4: pin 10 HP output (right channel) or right channel of AC coupled HP Jack (J3) OUT3 H4: pin 12 Mono, left, right or buffered midrail output for capless mode SPK_LP Table 1 I/O Configuration w Customer Information June 2008, Rev 1.0 4 WM8960-6158-FL32-M-REV1 Customer Information BOARD CONFIGURATION WITH 6158-EV1-REV1 MAIN BOARD This section focuses on evaluation of the WM8960-6158-FL32-M-REV1 Customer Mini Board in combination with the 6158-EV1 main board. This system is the reference platform for measurement data contained in this document. Please note that only a limited number of usage modes will be covered. DAC PLAYBACK TO HEADPHONE ON HP_L/R The following section details board configuration for DAC Playback to headphone on HP_L/R. w Customer Information SCLK SDIN MCLK BCLK ADCLRC/GPIO1 ADCDAT DACLRC DACDAT VMID AVDD AGND BLOCK DIAGRAM June 2008, Rev 1.0 5 WM8960-6158-FL32-M-REV1 Customer Information BOARD CONFIGURATION USB HP L/R Digital Data In S/PDIF = Jumper fitted on main board (concealed by mini board) REGISTER SETTINGS Register settings provided below are simply the minimum requirement to configure the desired path and have not in any way been optimised. w Customer Information REG INDEX DATA VALUE R15 0x000 Reset WM8960 R25 0x0C0 VMID=50K, Enable VREF R26 0x1E0 Enable DACL, DACR, LOUT1 and ROUT1 R47 0x00C Enable left output mixer and right output mixer R34 0x100 Left DAC to left output mixer enabled (LD2LO), 0dB R37 0x100 Right DAC to right output mixer enabled (RD2RO), 0dB R2 0x179 LOUT1 Vol = 0dB, volume update enabled R3 0x179 ROUT1 Vol = 0dB, volume update enabled R5 0x000 Unmute DAC digital soft mute COMMENT June 2008, Rev 1.0 6 WM8960-6158-FL32-M-REV1 Customer Information PERFORMANCE PLOT WM8960-6158-FL32-M-REV1 -- DAC-HP THD+N v Amplitude -60 -65 -70 -75 d B r A -80 -85 -90 -95 -100 -105 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Cyan Blue Magenta Red Solid Solid Solid Solid 2 2 2 2 Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Left Left HPL HPR HPL A-weight HPR A-weight System AP2 Board: WM8960-6158-FL32-M-REV1-S Device Date Code: 79AADUT Input Path: SPDIF_IN Input Signal: 997Hz; 0dBFS; 24-bit; 256fs (fs=48kHz) Output Path: HP_L/R Output Reference: -0.069 dBV Supplies : AVDD=DBVDD=DCVDD=+3.3V BW filter : 22Hz - 20kHz Additional Filtering: As s tated Dither: None RMS or Averaging: Averaging Load = 10kOhm DAC_THD+N_vs _Amplitude_to_HPLR_48kHz.at27 w Customer Information June 2008, Rev 1.0 7 WM8960-6158-FL32-M-REV1 Customer Information ADC RECORD FROM L/RINPUT1 The following section details board configuration for ADC record from L/RINPUT1. SCLK SDIN MCLK BCLK ADCLRC/GPIO1 ADCDAT DACLRC DACDAT VMID AVDD AGND BLOCK DIAGRAM BOARD CONFIGURATION USB S/PDIF out w Customer Information RIN1 LIN1 S/PDIF in = Jumper fitted on main board (concealed by mini board) June 2008, Rev 1.0 8 WM8960-6158-FL32-M-REV1 Customer Information REGISTER SETTINGS Register settings provided below are simply the minimum requirement to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE R15 0x000 Reset WM8960 R25 0x0FC VMID=50K, Enable VREF, AINL, AINR, ADCL and ADCR R47 0x030 Enable left and right channel input PGA R32 0x108 LINPUT1 to PGA (LMN1), Connect left input PGA to left input boost (LMIC2B), Left PGA Boost = 0dB R33 0x108 RINPUT1 to PGA (RMN1), Connect right input PGA to right input boost (RMIC2B), Right PGA Boost = 0dB R0 0x117 Unmute left input PGA (LINMUTE), Left Input PGA Vol = 0dB, Volume Update R1 0x117 Unmute right input PGA (RINMUTE), Right Input PGA Vol = 0dB, Volume Update R21 0x1C3 Left ADC Vol = 0dB, Volume Update R22 0x1C3 Right ADC Vol = 0dB, Volume Update COMMENT PERFORMANCE PLOT WM8960-6158-FL32-M-REV1 -- ADC THD+N v Amplitude -- L/RINPUT1 -70 -72 -74 -76 -78 -80 -82 d B F S -84 -86 -88 -90 -92 -94 -96 -98 -100 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 dBV Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Blue Cyan Red Magenta Solid Solid Solid Solid 2 2 2 2 DSP Anlr.THD+N Ampl A DSP Anlr.THD+N Ampl B DSP Anlr.THD+N Ampl A DSP Anlr.THD+N Ampl B Left Left Left Left LINPUT1 RINPUT1 LINPUT1 A-weight RINPUT1 A-weight Test System: AP2 Board: WM8960-6158-FL32-M-REV1-S Device Date Code: 79AADUT Input Path: L/RINPUT1 Input Signal: 0.997kHz; 0dBV; Output Path: S/PDIF_OUT Output Signal: 24 bit; 48kHz (256fs ) Supplies: AVDD=DBVDD=DCVDD=+3.3V BW Filtering: 22Hz - 20kHz LP Additional Filtering Type: As stated RMS or Averaging: RMS ADC_THD+N_vs_Amplitude_LineIn1_to_SPDIF_48kHz.at27 w Customer Information June 2008, Rev 1.0 9 WM8960-6158-FL32-M-REV1 Customer Information ANALOGUE BYPASS FROM L/RINPUT3 TO 16Ω HEADPHONE ON HPL/HPR The following section details board configuration for analogue bypass from L/RINPUT3 to 16Ω headphone on HPL/HPR. SCLK SDIN MCLK BCLK ADCLRC/GPIO1 ADCDAT DACLRC DACDAT VMID AVDD AGND BLOCK DIAGRAM L/RIN3 BOARD CONFIGURATION w Customer Information June 2008, Rev 1.0 10 WM8960-6158-FL32-M-REV1 Customer Information REGISTER SETTINGS Register settings provided below are simply the minimum requirement to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE R15 0x000 Reset WM8960 R25 0x0F0 VMID=50K, Enable VREF, AINL and AINR R26 0x060 Enable LOUT1 and ROUT1 R32 0x000 LINPUT1 not connected to PGA (LMN1) R33 0x000 RINPUT1 not connected to PGA (RMN1) R47 0x00C Enable left and right channel input PGA R34 0x080 Enable LINPUT3 to left output mixer (LI2LO), LINPUT3 to Left mixer vol = 0dB R37 0x080 Enable RINPUT3 to right output mixer (RI2RO), RINPUT3 to Right mixer vol = 0dB R2 0x179 LOUT1 Vol = 0dB, volume update enabled R3 0x179 ROUT1 Vol = 0dB, volume update enabled COMMENT PERFORMANCE PLOT WM8960-6158-FL32-M-REV1 -- Analogue BypassTHD+N v Amplitude (L/RINPUT3, HPL/R) T -30 -40 -50 d B r -60 -70 A -80 -90 -100 -110 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBV Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Cyan Blue Magenta Red Solid Solid Solid Solid 2 2 2 2 Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Left Left HPL (16R) HPR (16R) HPL (16R) A-weight HPR (16R) A-weight System AP2 Board: WM8960-6158-FL32-M-REV1-S Device Date Code: 79AADUT Input Signal: 997Hz; 0dBV; Reference Levels: 0dBrA = -1.288 dBV Supplies : AVDD=DCVDD=DBVDD = +3.3V Input Signal Path: L/RINPUT3 Output Signal Path: HPL/R (16R Load) BW Filtering: 22Hz-20kHz Additional Filtering Type: As stated Dither = Off RMS or Averaging = Average Load = 16R THD+N_vs _Amplitude_LRINPUT3_to_LROUT1_Bypass .at27 w Customer Information June 2008, Rev 1.0 11 WM8960-6158-FL32-M-REV1 Customer Information DAC PLAYBACK TO 8Ω SPEAKER (MINI BOARD) The following section details board configuration for DAC playback to 8Ω speaker (Mini board). BLOCK DIAGRAM SPK_L SPK_R BOARD CONFIGURATION GND 5V USB Digital Data In S/PDIF = Jumper fitted on main board (concealed by mini board) w Customer Information June 2008, Rev 1.0 12 WM8960-6158-FL32-M-REV1 Customer Information REGISTER SETTINGS Register settings provided below are simply the minimum requirement to configure the desired path and have not in any way been optimised. REG INDEX DATA VALUE COMMENT R15 0x000 Reset WM8960 R25 0x0C0 VMID=50K, Enable VREF R26 0x198 Enable DACL, DACR, SPKL and SPKR R47 0x00C Enable left output mixer and right output mixer R49 0x0F7 Left and Right Speakers Enabled R51 0x11B DCGAIN = 1.52x (+3.6dB) and ACGAIN = 1.52x (+3.6dB) R34 0x100 Left DAC to left output mixer enabled (LD2LO), 0dB R37 0x100 Right DAC to right output mixer enabled (RD2RO), 0dB R40 0x179 LSPK Vol = 0dB, volume update enabled R41 0x179 RSPK Vol = 0dB, volume update enabled R5 0x000 Unmute DAC digital soft mute PERFORMANCE PLOT WM8960-6158-FL32-M-REV1 -- DAC-SPK THD+N v Amplitude -60 -65 -70 -75 d B r A -80 -85 -90 -95 -100 -105 -110 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Sweep Trace Color Line Style Thick Data Axis Comment 1 1 2 2 1 2 1 2 Cyan Blue Magenta Red Solid Solid Solid Solid 2 2 2 2 Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Anlr.THD+N Ampl Left Left Left Left SPK_L SPK_R SPK_L A-weight SPK_R A-weight System AP2 + AUX-00025 Board: WM8960-6158-FL32-M-REV1-S Device Date Code: 79AADUT Input Path: SPDIF_IN Input Signal: 997Hz; 0dBFS; 24-bit; 256fs (fs=48kHz) Output Path: SPK_L/R Output Reference: +9.359 dBV Supplies : AVDD=DBVDD=DCVDD=+3.3V, SPKVDD=+5.0V BW filter : 22Hz - 20kHz Additional Filtering: As s tated Dither: None RMS or Averaging: Averaging Load = 8R + 10uH DAC_THD+N_vs_Amplitude_to_SPK_5V_48kHz.at27 w Customer Information June 2008, Rev 1.0 13 WM8960-6158-FL32-M-REV1 Customer Information APPLICATION SUPPORT If you require more information or require technical support, please contact the Wolfson Microelectronics Applications group through the following channels: Email: Telephone Apps: Fax: Mail: [email protected] +44 (0) 131 272 7070 +44 (0) 131 272 7001 Applications Engineering at the address on the last page or contact your local Wolfson representative. Additional information may be made available on our web site at: http://www.wolfsonmicro.com w Customer Information June 2008, Rev 1.0 14 Customer Information WM8960-6158-FL32-M-REV1 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 E-mail :: [email protected] w Customer Information June 2008, Rev 1.0 15