Datasheet

AOZ3046PI
EZBuck™ 4 A Synchronous Buck Regulator
General Description
Features
The AOZ3046PI is a high efficiency, simple to use, 4 A
synchronous buck regulator. The AOZ3046PI operates
from a 7.5 V to 18 V input voltage range, and provides up
to 4 A of continuous output current with an output voltage
adjustable down to 0.8 V.
 7.5 V to 18 V operating input voltage range
 350 µA quiescent current typical applications
 60 mΩ internal high-side switch and 30 mΩ internal
low-side switch (at 12 V)
 PEM (pulse energy mode) enables 82 % plus
efficiency with IOUT = 10 mA (VIN = 12 V, VOUT = 5 V)
The AOZ3046PI comes in an exposed pad SO-8
package and is rated over a -40 °C to +85 °C operating
ambient temperature range.
 Up to 95 % efficiency
 Internal soft start
 Output voltage adjustable to 0.8 V
 4 A continuous output current
 500 kHz PWM operation
 Cycle-by-cycle current limit
 Pre-bias start-up
 Short-circuit protection
 Thermal shutdown
 Exposed pad SO-8 package
Applications
 Point of load DC/DC converters
 LCD TV
 Set top boxes
 DVD and Blu-ray players/recorders
 Cable modems
Typical Application
VIN
CCC
C1
10µF
VIN
EN
VCC
VOUT
AOZ3046
COMP
VOUT
LX
R1
RC
CC
L1 5.8µH
FB
AGND
PGND
C2, C3
22µF
R2
Figure 1. 5 V, 4 A Synchronous Buck Regulator, Fs = 500 KHz
Rev. 2.0 October 2014
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Page 1 of 14
AOZ3046PI
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ3046PI
-40 °C to +85 °C
EPAD SO-8
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
PGND
1
VIN
2
AGND
3
VCC
4
PAD
(LX)
8
VOUT
7
EN
6
COMP
5
FB
Exposed Pad SO-8
(Top View)
Pin Description
Pin Number
Pin Name
1
PGND
2
VIN
Supply voltage input. When VIN rises above the UVLO threshold and EN is logic high,
the device starts up.
3
AGND
Analog ground. AGND is the reference point for controller section. AGND needs to be
electrically connected to PGND.
4
VCC
5
FB
6
COMP
7
EN
8
VOUT
Exposed pad
LX
Rev. 2.0 October 2014
Pin Function
Power ground. PGND needs to be electrically connected to AGND.
Internal LDO output.
Feedback input. The FB pin is used to set the output voltage via a resistive voltage divider
between the output and AGND.
External loop compensation pin. Connect a RC network between COMP and AGND to
compensate the control loop.
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the
device. If on/off control in not needed, connect EN to VIN and do not leave it open.
VOUT sense pin for protection purposes.
Switching node. LX is the drain of the internal power FETs. LX is used as the thermal pad
of the power stage.
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AOZ3046PI
Block Diagram
VCC
UVLO
& POR
EN
VIN
LDO
Regulator
OTP
+
Reference
& Bias
ISen
Iinfo
Softstart
–
Q1
ILimit
+
+
EAmp
FB
–
–
PWM
Control
Logic
PWM
Comp
+
VOUT
PWM/PEM
Logic
+
FET
Driver
LX
Q2
Output
Sense
COMP
500Khz
Oscillator
+
PWM/PEM
Control Logic
PEM Control
Logic
–
Vref
Iinfo
Iinfo
AGND
PGND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Parameter
Supply Voltage (VIN)
LX to AGND
Rating
Parameter
20 V
-0.7 V to VIN +0.3 V
LX to AGND (20 ns)
-5 V to 22 V
EN, VOUT to AGND
-0.3 V to VIN +0.3 V
VCC, FB, COMP to AGND
PGND to AGND
-0.3 V to 6.0 V
-0.3 V to +0.3 V
Junction Temperature (TJ)
+150 °C
Storage Temperature (TS)
-65 °C to +150 °C
ESD Rating(1)
2.0 kV
Supply Voltage (VIN)
Rating
7.5 V to 18 V
Output Voltage Range
0.8 V to 0.85*VIN
Ambient Temperature (TA)
-40 °C to +85 °C
Package Thermal Resistance
Exposed Pad SO-8 (JA)(2)
50 °C/W
Note:
2. The value of JA is measured with the device mounted on a 1-in2
FR-4 board with 2 oz. copper, in a still air environment with
TA = 25 °C. The value in any given application depends on the user’s
specific board design.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 kΩ in series with 100 pF.
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Page 3 of 14
AOZ3046PI
Electrical Characteristics
TA = 25 °C, VIN = VEN = 12 V, VOUT = 5 V unless otherwise specified(3)
Symbol
VIN
VUVLO
IIN
Parameter
Conditions
Supply Voltage
Input Under-Voltage Lockout
Threshold
Supply Current (Quiescent)
Typ.
7.5
VIN Rising
7
VIN Falling
6.7
VIN = 12 V, VOUT = 5 V, IOUT = 0 A
350
IOFF
Shutdown Supply Current
VEN = 0 V
VFB
Feedback Voltage
TA = 25 °C
0.788
Max.
Units
18
V
V
500
µA
1
2
µA
0.8
0.812
V
Load Regulation
0.5
%
Line Regulation
1
%
IFB
Feedback Voltage Input Current
VEN
EN Input Threshold
200
Off Threshold
On Threshold
VHYS
Min.
0.6
2
EN Input Hysteresis
200
EN Leakage Current
V
mV
1
SS Time
nA
4
µA
ms
MODULATOR
fO
Frequency
DMAX
Maximum Duty Cycle
TMIN
Controllable Minimum On Time
IOUT = 2 A
400
500
600
kHz
200
ns
85
%
IOUT = 2 A
Current Sense Transconductance
8
A/ V
Error Amplifier Transconductance
200
µA / V
5.8
A
PROTECTION
ILIM
VOVP
Current Limit
Over-Voltage Protection
4.8
Off Threshold
960
On Threshold
860
TJ Rising
150
TJ Falling
100
High-Side Switch On-Resistance
VIN = 12 V
60
mΩ
Low-Side Switch On-Resistance
VIN = 12 V
30
mΩ
Over-Temperature Shutdown Limit
mV
°C
OUTPUT STAGE
Note:
3. Specification in BOLD indicate an ambient temperature range of -40 °C to +85 °C. These specifications are guaranteed by design.
Rev. 2.0 October 2014
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Page 4 of 14
AOZ3046PI
Typical Performance Characteristics
Circuit of Figure 1. TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V, L = 4.7 µH unless otherwise specified.
Full Load Operation
Light Load Operation
VLX
10V/div
VLX
10V/div
Vo ripple
50mV/div
IL
1A/div
IL
0.5A/div
Vo ripple
50mV/div
Vin ripple
0.2V/div
Vin ripple
0.5V/div
1µs/div
2µs/div
Light Load to Heavy Load Operation
Heavy Load to Light Load Operation
VLX
10V/div
VLX
2V/div
Vo
0.2V/div
Vo
0.2V/div
IL
2A/div
IL
2A/div
20µs/div
20µs/div
Short Circuit Protection
Short Circuit Recovery
VLX
10V/div
VLX
10V/div
Vo
2V/div
Vo
2V/div
IL
5A/div
IL
5A/div
20ms/div
Rev. 2.0 October 2014
20ms/div
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Page 5 of 14
AOZ3046PI
Typical Performance Characteristics (continued)
Circuit of Figure 1. TA = 25 °C, VIN = VEN = 12 V, VOUT = 3.3 V, L = 4.7 µH unless otherwise specified.
Start Up to Full Load
50% to 100% Load Transient
Vin
5V/div
Vo
0.2V/div
Vo
2V/div
Io
2A/div
Io
2A/div
5ms/div
100µs/div
Efficiency
AOZ3046PI (VIN=12V) Efficiency vs. Load Current
100
Efficiency (%)
90
80
70
5V OUTPUT
3.3V OUTPUT
60
50
0
0.1
1.0
10
Load Current (A)
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AOZ3046PI
Detailed Description
The AOZ3046PI is a current-mode step down regulator
with an integrated high-side PMOS switch and a low-side
NMOS switch. The AOZ3046PI operates from a 7.5 V to
18 V input voltage range and supplies up to 4 A of load
current. Features include enable control, power-on reset,
input under voltage lockout, output over voltage
protection, internal soft-start and thermal shut down.
The AOZ3046PI is available in an exposed pad SO-8
package.
Enable and Soft Start
The AOZ3046PI has an internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. The soft start process
begins when the input voltage rises to 7 V and voltage on
the EN pin is HIGH. In the soft start process, the
output voltage is typically ramped to regulation voltage in
4 ms. The 4 ms soft start time is set internally.
The EN pin of the AOZ3046PI is active high. Connect the
EN pin to VIN if the enable function is not used. Pulling
EN to ground will disable the AOZ3046PI. Do not leave
EN open. The voltage on the EN pin must be above 2 V
to enable the AOZ3046PI. When the EN pin voltage falls
below 0.6 V, the AOZ3046PI is disabled.
The inductor current flows from the input through the
inductor to the output. When the current signal exceeds
the error voltage, the high-side switch is off. The inductor
current is freewheeling through the internal low-side
N-MOSFET switch to output. The internal adaptive FET
driver guarantees no turn on overlap of both the
high-side and the low-side switch.
Compared with regulators using freewheeling Schottky
diodes, the AOZ3046PI uses a freewheeling NMOSFET
to realize synchronous rectification. This greatly
improves the converter efficiency and reduces power
loss in the low-side switch.
The AOZ3046PI uses a P-Channel MOSFET as the
high-side switch. This saves the bootstrap capacitor
normally seen in a circuit using an NMOS switch.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin using a resistor divider network as shown in
Figure 1. The resistor divider network includes R1 and
R2. Usually, a design is started by picking a fixed R2
value and calculating the required R1 with the equation
below:
R 1

V O = 0.8   1 + -------
R 2

Light Load and PWM Operation
Under low output current settings, the AOZ3046PI will
operate with pulse energy mode to obtain high efficiency.
In pulse energy mode, the PWM will not turn off until the
inductor current reaches to 800 mA and the current
signal exceeds the error voltage.
Some standard value of R1 and R2 for the most common
output voltages are listed in Table 1.
VO (V)
R1 (kΩ)
R2 (kΩ)
0.8
1.0
Open
Steady-State Operation
1.2
4.99
10
Under heavy load steady-state conditions, the converter
operates in fixed frequency and Continuous-Conduction
Mode (CCM).
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
The AOZ3046PI integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference voltage is amplified
by the internal transconductance error amplifier. The
error voltage, which shows on the COMP pin, is
compared against the current signal, which is the sum of
inductor current signal and ramp compensation signal, at
the PWM comparator input. If the current signal is less
than the error voltage, the internal high-side switch is on.
3.3
31.1
10
5.0
52.3
10
Rev. 2.0 October 2014
Table 1.
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
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AOZ3046PI
Protection Features
Application Information
The AOZ3046PI has multiple protection features to
prevent system circuit damage under abnormal
conditions.
The basic AOZ3046PI application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ3046PI employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4 V and 3.1 V internally.
The peak inductor current is automatically limited
cycle-by-cycle.
When the output is shorted to ground under fault
conditions, the inductor current slowly decays during a
switching cycle because the output voltage is 0 V.
To prevent catastrophic failure, a secondary current limit
is designed inside the AOZ3046PI. The measured
inductor current is compared against a preset voltage
which represents the current limit. When the output
current is greater than the current limit, the high side
switch will be turned off. The converter will initiate a soft
start once the over-current condition is resolved.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 7 V, the converter starts
operation. When input voltage falls below 6.5 V, the
converter will be shut down.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. The sensor shuts down the internal control
circuit and high side PMOS if the junction temperature
exceeds 150 ºC. The regulator will restart automatically
under the control of the soft-start circuit when the junction
temperature decreases to 100 ºC.
The input capacitor must be connected to the VIN pin and
the PGND pin of AOZ3046PI to maintain steady input
voltage and filter out the pulsing input current. The
voltage rating of input capacitor must be greater than
maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
VO  VO
IO

V IN = -----------------   1 – ---------  --------f  C IN 
V IN V IN
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
VO 
VO 
-  1 – --------
I CIN_RMS = I O  -------V IN 
V IN
if we let m equal the conversion ratio:
VO
-------- = m
V IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2 below. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
0.5
0.4
ICIN_RMS(m) 0.3
IO
0.2
0.1
0
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Rev. 2.0 October 2014
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Page 8 of 14
AOZ3046PI
For reliable operation and best performance, the input
capacitors must have a current rating higher than
ICIN_RMS at the worst operating conditions. Ceramic
capacitors are preferred for input capacitors because of
their low ESR and high current rating. Depending on the
application circuits, other low ESR tantalum capacitors
may be used. When selecting ceramic capacitors, X5R or
X7R type dielectric ceramic capacitors should be used
for their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor
manufactures are based on a certain operating life time.
Further de-rating may need to be considered for long
term reliability.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
V O = I L   ESR CO + -------------------------

8fC 
O
Inductor
where,
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For a given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
CO is output capacitor value, and
VO 
VO 
-
I L = -----------   1 – -------fL 
V IN
The peak inductor current is:
When a low ESR ceramic capacitor is used as the output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
V O = I L  ------------------------8fC
I L
I Lpeak = I O + -------2
O
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on the inductor is designed to be
20 % to 40 % of output current.
When selecting the inductor, confirm it is able to handle
the peak current without saturation at the highest
operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on the inductor needs to be checked
for thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. However,
they cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
Rev. 2.0 October 2014
ESRCO is the equivalent series resistance of the output
capacitor.
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
V O = I L  ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitors are
recommended as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
I L
I CO_RMS = ---------12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, the output capacitor could
be overstressed.
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AOZ3046PI
Loop Compensation
The AOZ3046PI employs peak current mode control for
ease of use and fast transient response. Peak current
mode control eliminates the double pole effect of the
output L&C filter. It also greatly simplifies the
compensation loop design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
1
f P1 = ----------------------------------2  C O  R L
The zero is a ESR zero due to the output capacitor and
its ESR. It is can be calculated by:
1
f Z1 = -----------------------------------------------2  C O  ESR CO
To design the compensation circuit, a target crossover
frequency fC to close the loop must be selected. The
system crossover frequency is where the control loop
has unity gain. The crossover is the also called the
converter bandwidth. Generally a higher bandwidth
means faster response to load transients. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
loop, converter stability under all line and load condition
must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of the switching frequency.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
VO
2  C C
R C = f C  ----------  ----------------------------G G
V
FB
where;
EA
CS
CO is the output filter capacitor,
where;
RL is load resistor value, and
fC is the desired crossover frequency. For best performance,
fC is set to be about 1/10 of the switching frequency;
ESRCO is the equivalent series resistance of output capacitor.
The compensation design shapes the converter control
loop transfer function for the desired gain and phase.
Several different types of compensation networks can be
used with the AOZ3046PI. For most cases, a series
capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ3046PI, FB and COMP are the inverting input
and the output of the internal error amplifier. A series
R and C compensation network connected to COMP
provides one pole and one zero. The pole is:
G EA
f P2 = ------------------------------------------2  C C  G VEA
VFB is 0.8V,
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V, and
GCS is the current sense circuit transconductance, which is
8 A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of the selected
crossover frequency. CC can is selected by:
1
C C = ----------------------------------2  R C  f P1
The above equation can be simplified to:
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is the compensation capacitor in Figure 1.
CO  RL
C C = --------------------RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
1
f Z2 = ----------------------------------2  C C  R C
Rev. 2.0 October 2014
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Page 10 of 14
AOZ3046PI
Thermal Management and Layout
Considerations
Layout Considerations
In the AOZ3046PI buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pad, to the filter inductor, to the output capacitor and
load, and then returns to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from the inductor,
to the output capacitors and load, to the low side
NMOSFET. Current flows in the second loop when the
low side NMOSFET is on.
In PCB layout, minimizing the area of the two loops will
reduce the noise of the circuit and improves efficiency.
A ground plane is strongly recommended to connect the
input capacitor, the output capacitor, and the PGND pin
of the AOZ3046PI.
In the AOZ3046PI buck regulator circuit, the major power
dissipating components are the AOZ3046PI and the
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power:
P total_loss = V IN  I IN – V O  I O
The AOZ3046PI is an exposed pad SO-8 package.
Several layout tips are listed for the best electric and
thermal performance.
1. The exposed pad (LX) is connected to the internal
PFET and NFET drains. Connected a large copper
plane to the LX pin to help thermal dissipation.
2. Do not use a thermal relief connection to the VIN pin
or the PGND pin. Pour a maximized copper area to
the PGND pin and the VIN pin to help thermal
dissipation.
3. The input capacitor should be connected as close as
possible to the VIN pin and the PGND pin.
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and only connect
them at one point to avoid the PGND pin noise
coupling to the AGND pin.
5. Make the current trace from the LX pad to L to Co to
the PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal trace away from the LX pad.
The power dissipation of the inductor can be
approximately calculated by the output current and DCR
value of the inductor:
VOUT
P inductor_loss = IO2  R inductor  1.1
The actual junction temperature can be calculated by the
power dissipation in the AOZ3046PI and the thermal
impedance from junction to ambient:
T junction =  P total_loss – P inductor_loss    JA
The maximum junction temperature of the AOZ3046PI is
150 ºC, which limits the maximum load current capability.
PGND 1
8 VOUT
VIN 2
The thermal performance of the AOZ3046PI is strongly
affected by the PCB layout. Care should be taken during
the design process to ensure that the IC will operate
under the recommended environmental conditions.
Rev. 2.0 October 2014
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7 EN
LX
AGND 3
VCC 4
6 COMP
FB
5
VOUT
Page 11 of 14
AOZ3046PI
Package Dimensions, SO-8 EP1
Gauge plane
0.2500
D0
C
L
L1
E2
E1
E3
E
L1'
D1
Note 5
D
θ
7 (4x)
A2
e
B
A
A1
Dimensions in millimeters
RECOMMENDED LAND PATTERN
3.70
2.20
5.74
2.71
2.87
0.80
1.27
0.635
UNIT: mm
Symbols
A
Min.
1.40
Nom.
1.55
A1
A2
B
0.00
1.40
0.31
0.05
1.50
0.406
C
D
D0
D1
E
e
E1
E2
E3
L
y
θ
| L1–L1' |
L1
0.17
4.80
3.20
3.10
5.80
—
3.80
2.21
—
4.96
3.40
3.30
6.00
1.27
3.90
2.41
0.40 REF
0.40
0.95
—
—
0°
—
Max.
1.70
0.10
1.60
0.51
0.25
5.00
3.60
3.50
6.20
—
4.00
2.61
1.27
0.10
8°
3°
0.04
0.12
1.04 REF
Dimensions in inches
Symbols
A
Min.
Nom.
Max.
0.055
0.061
0.002
0.059
0.067
0.004
0.063
0.016
—
0.195
0.020
0.010
0.197
A1
A2
B
0.000
0.055
C
D
D0
D1
E
e
E1
E2
E3
L
y
θ
| L1–L1' |
L1
0.007
0.189
0.012
0.134 0.142
0.130 0.138
0.236 0.244
0.050
—
0.153 0.157
0.095 0.103
0.016 REF
0.016 0.037 0.050
—
0.004
—
0.126
0.122
0.228
—
0.150
0.087
0°
—
3°
8°
0.002 0.005
0.041 REF
Notes:
1. Package body sizes exclude mold flash and gate burrs.
2. Dimension L is measured in gauge plane.
3. Tolerance 0.10mm unless otherwise specified.
4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Followed from JEDEC MS-012
Rev. 2.0 October 2014
www.aosmd.com
Page 12 of 14
AOZ3046PI
Tape and Reel Dimensions, SO-8 EP1
Carrier Tape
P1
D1
P2
T
E1
E2
E
B0
K0
A0
D0
P0
Feeding Direction
UNIT: mm
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
E
1.50
±0.10
12.00
±0.10
Reel
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P2
2.00
±0.10
P1
4.00
±0.10
T
0.25
±0.10
W1
S
G
N
M
K
V
R
H
W
UNIT: mm
N
W
Tape Size Reel Size
M
12mm
ø330
ø330.00 ø97.00 13.00
±0.10 ±0.30
±0.50
W1
17.40
±1.00
H
K
ø13.00
10.60
+0.50/-0.20
S
2.00
±0.50
G
—
R
—
V
—
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 2.0 October 2014
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 13 of 14
AOZ3046PI
Part Marking
Z3046PI
FAYWLT
Part Number Code
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 2.0 October 2014
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 14 of 14