Datasheet

AOZ1363DI
16V High Current Load Switch with Rapid Turn-Off
and Current Monitoring Protection
General Description
Features
The AOZ1363DI is a high-side load switch intended for
applications that require circuit protection. The device
operates from voltages between 5V and 16V, and
capable of supplying 6A of continuous current. The
internal current limiting circuit protects the input supply
voltage from large load current. The AOZ1363DI
provides thermal protection function that limits excessive
power dissipation. The device employs an externally
programmable soft-start circuitry to control inrush current
due to highly capacitive loads associated with hot-plug
events. It features low quiescent current of 400µA and
the supply current reduces to less than 10µA in
shutdown.
 5V to 16V operating input voltage
The device can output current monitoring information
with an accuracy of 10% at a specified load current of 3A.
The device can detect the over-current fault condition
and execute the switch power down within a maximum
delay time of 100ns. It features an input overvoltage
protection where the device powers down when the
power input voltage exceeds 19V.
 40m maximum on resistance
 Fast 100ns switch turn off time during OCP
 Current monitoring with 10% accuracy (3A)
 Externally programmable soft-start
 Low quiescent current
 Under-voltage lockout
 Thermal shutdown protection
 Input over-voltage protection
 2.0kV ESD rating
 Small 3mm x 3mm DFN-12L package
Applications
 Notebook PCs
 Hot swap supplies
 Micro-servers
The AOZ1363DI is available in a 3mm x 3mm DFN-12L
package and can operate over -40 C to +85 C
temperature range.
Typical Application
OFF ON
5V
R2
100k
1
2
C3
0.47nF
3
4
VIN
12V Input
C1
100μF
5
6
EN
OUT
VCC
OUT
GND
AOZ1363DI OUT
FLT_B
IN
NC
ISEN
NC
SS
12
11
12V Output
C2
4.7μF
10
9
8
7
Rsen
C4
0.3nF
Figure 1. Typial Application Circuit (with Current Monitoring)
Rev. 1.0 July 2014
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Page 1 of 13
AOZ1363DI
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1363DI
-40°C to +85°C
3mm x 3mm DFN-12L
RoHS Compliant
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.
Pin Configuration
EN
1
VCC
2
11 OUT
GND
3
10 OUT
FLT_B
4
IN
NC
12
IN
OUT
9
NC
5
8
ISEN
6
7
SS
3mm x 3mm DFN-12L
(Top View)
Pin Description
Pin Number
Pin Name
Pin Function
1
EN
Enable Input. Active high. For automatic enabling, this pin is highly recommended to
connect to VCC.
2
VCC
VCC is a bypass pin. Connect a 0.47nF capacitor from VCC to GND.
3
GND
Ground.
4
FLT_B
5, EPAD
IN
N-channel MOSFET Drain. Connect a 100µF capacitor from IN to GND
6, 9
NC
No Connection.
Fault Output pin. This is an open drain output that is externally pulled high with a
pull-up resistor. Drain is internally pulled down to GND to indicate a fault condition.
Connect to 5V, 3.3V, or VCC through a 100kΩ pull-up resistor.
7
SS
8
ISEN
Current Sense Information Output. See Figure 3 for Rsen value.
10, 11, 12
OUT
N-channel MOSFET Source. Connect a 4.7µF capacitor from OUT to GND.
Rev. 1.0 July 2014
Externally Programmable Soft-Start pin.
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Page 2 of 13
AOZ1363DI
Absolute Maximum Ratings
Maximum Operating Ratings
Exceeding the Absolute Maximum ratings may damage the
device.
The device is not guaranteed to operate beyond the Maximum
Operating Ratings.
Parameter
Rating
IN, OUT, ISEN to GND
Parameter
-0.3V to +24V
VCC, EN, SS, FLAG
Rating
Thermal Resistance (DFN 3x3)
40°C/W
-0.3V to 6V
Maximum Continuous Current
Maximum Junction Temperature (TJ)
6A (25°C)
+150°C
ESD Rating (HBM)
2.0kV
Electrical Characteristics
VIN = 12V, TA = 25°C unless otherwise stated.
Symbol
VIN
Parameter
Input Supply Voltage
VUVLO
Undervoltage Lockout Threshold
VUVHYS
Undervoltage Lockout Hysteresis
VUVP
VUVHYS
Conditions
Input Overvoltage Protection
Typ.
Max
16
V
4.1
4.4
V
5
IN rising
Units
400
mV
IN rising
19
V
400
Input Overvoltage Protection Hysteresis
1.5
IIN_ON
Input Quiescent Current
EN = 4V, no load
IIN_OFF
Input Shutdown Current
ILEAK
RDS(ON)
Min.
V
600
µA
EN = GND, no load
10
µA
Output Leakage Current
EN = GND, no load
10
µA
Switch On Resistance
VIN= 12V
23
40
mΩ
11
+25%
A
ILIM
Current Limit
-25%
IOFF
Offset Current in ISEN
IIN = 0A
2
µA
AIF
Current Monitor Gain
IIN = 1A~6A
5
µA/A
10
IMON
Current Monitor Accuracy
IIN = 3A
VLOW
Fault Low Voltage
IFLT = 1mA
ILK_FLT
%
0.5
V
Fault Leakage Current
1
µA
tFLT
Fault Flag Delay Time
100
ns
tSS
Soft-Start Time
VEN_L
Enable Input Low Voltage
VEN_H
Enable Input High Voltage
VEN_HYS
Enable Input Hysteresis
IEN_BIAS
Enable Input Bias Current
CSS = 300pF
100
µs
0.8
2
V
V
100
mV
1
µA
Turn-On Delay Time
EN_50% to OUT_10%
RL = 120Ω, CL = 1µF
220
µs
tON
Turn-On Rise Time
OUT_10% to 90%
RL=120Ω, CL = 1µF
160
µs
TSD
Thermal Shutdown Threshold
130
°C
TSD_HYS
Thermal Shutdown Hysteresis
30
Td_on
TCL
TFDP
°C
Current Limit Detection Delay
50(1)
ns
N-Channel Turn Off Delay
50(1)
ns
Note: 1. Guaranteed by design.
Rev. 1.0 July 2014
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Page 3 of 13
AOZ1363DI
CURRENT LIMIT SET
DIFFERENTIAL SENSED
VOLTAGE
40ns
FLT_B
FAULT DETECTION (OCP)
10%
10ns
MAIN SWITCH GATE
(NOT PIN OUT)
INTERNALLY PULLED-DOWN
50ns
MAIN SWITCH
(NOT PIN OUT)
OFF STATE
ON STATE
90%
90%
OUT
tCL
10%
tD(ON)
tFPD
100ns
(85°C)
tr
Figure 2. Over Current Limit Timing Diagram
V(ISEN) = (AIF * IDC + IOFF) * RSEN
V(ISEN) = (5μA/A * 6A + 2μA) * 100kΩ = 3.2V
V(ISEN)
VOCP(~4.7V)
3.2V
RSEN = 100kΩ
VOFF(=0.2V)
0
6A
I(OCP)
= 9A
IIN
OCP
FLAG
Figure 3. Current Monitoring and Reverse Current
Rev. 1.0 July 2014
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Page 4 of 13
AOZ1363DI
Protection Table
Fault Condition
LSW Position
Fault Flag
System State
Comparator Add-on
UVLO (falling)
Open
Low
Stand-by
Hysteresis + Deglitch
OCP
Open
Low
Latch-off
Deglitch
OTP
Open
Low
Stand-by
Hysteresis
EN (low)
Open
H-Z
Shutdown
Deglitch
Protection Diagram
19V
IN
OUT
3.9V
3.5V
EN
UVLO
4.5V
4V
VCC
11A
IIN
FLT_B
Latch-off
OVP
OCP
UVLO
Shutdown
Functional Block Diagram
12V Input
M1
IN
OUT
3.9V
C1
100μF
C2
4.7μF
Vbias
UVLO
SS
Soft
Start
C4
0.3nF
CSA
Charge
Pump
Internal
Regulator
EN
Ioff
VCL
Rsen
5V
VCC(4V)
Fast
Turn-off
OCP
(IIN>11A)
FLT_B
VCC
Slow
Turn-off
C3
0.47nF
Current
Information
ISEN
OSC
IN
Enable
Output
Fault Detect
& Latch
R2
100k
Fault Flag
M2
(Active Low)
OTP
(Temp>130oC)
OVP (VIN>19V)
UVLO (VIN<3.5V)
Fault Detect
& Recover
GND
Rev. 1.0 July 2014
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Page 5 of 13
AOZ1363DI
Functional Characteristics
Turn ON Sequence
Turn OFF Sequence
(VIN=12V, RL=2Ω, C1=100μF, C2=4.7μF)
(VIN=12V, RL=2Ω, C1=100μF, C2=4.7μF)
VIN
2V/div
VIN
2V/div
VOUT
2V/div
VOUT
2V/div
EN
1V/div
EN
1V/div
IOUT
1A/div
IOUT
1A/div
50μs/div
5μs/div
Fast Output Shutdown During
Current Limit Response
Current Limit Response: Latch OFF
(VIN=12V, RL=2Ω, C1=100μF, C2=4.7μF)
(VIN=12V, RL=2Ω, C1=100μF, C2=4.7μF)
VIN/VOUT
2V/div
VIN
VOUT Falling
VIN/VOUT
2V/div
IOUT Limit: 10.5A
FLT_B
1V/div
IOUT Limit Trip Point: 10.5A
50ns
IOUT
2A/div
FLT_B
1V/div
IOUT
2A/div
100ns/div
Rev. 1.0 July 2014
500μs/div
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Page 6 of 13
AOZ1363DI
Typical Characteristics
Ambient Temperature vs. Current
120
110
Temperature (°C)
Current Limit Level (A)
Current Limit vs. Temperature
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
25
100
90
80
70
60
50
35
45 55
40
4.0
65 75 85 95 105 115 125
Temperature (°C)
RDSON vs. Temperature
5.0
5.5 6.0 6.5 7.0
DC Current (A)
7.5
8.0
Input Quiescent Current vs. Input Voltage
35
620
34
580
33
Supply Current (μA)
N-Channel RDSON A(mΩ)
4.5
32
31
30
29
28
27
540
500
460
420
380
26
340
25
24
25
35
45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
300
5
6
7
9
10
8
Input Voltage (V)
11
12
Input Shutdown Current vs. Input Voltage
Shutdown Current (μA)
4.8
4.4
4.0
3.6
3.2
2.8
2.4
2.0
Rev. 1.0 July 2014
5
6
7
8
9
10
Input Voltage (V)
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11
12
Page 7 of 13
AOZ1363DI
Application Information
Parallel Load Switch Configuration
U1
OFF ON
EN
R3 1M
1
2
5V Input
VCC
R2
100k
C3
470pF
3
4
12V Input
VIN
5
6
C1
47μF
FLT_B
EN
VCC
OUT
GND
OUT
FLT_B
2
3
4
5
6
C1
47μF
NC
IN
ISEN
NC
U2
C3
470pF
OUT
SS
EP
10
9
D1
DPAK
ISEN
8
7
C2
4.7μF
Rsen/2
AOZ1363DI
VCC
OUT
GND
OUT
FLT_B
NC
IN
ISEN
SS
EP
The same techniques and methodology previously
explained should be applied to any Multi-Load Switch
parallel configuration. Layout techniques for multi-load
switch topology should be referenced to the
Recommended Layout Guidelines section.
Short Protection
OUT
C5
47μF
11
R4
0Ω
EN
NC
12V Output
12
C4
330pF
C5
47μF
1
R2
100k
AOZ1363DI
A 4.7µF capacitor will be mounted between the Output
(pins 10,11 and 12) and EP of each AOZ1363DI load
switch. All output pins of load switch devices will be tied
together through a wide track on the top layer for
optimize cooling. This common Output track will lead to
the Load downstream.
12
11
10
9
D2
DPAK
C2
4.7μF
8
7
C4
330pF
R4
0Ω
Figure 4. Parallel Configuration Application Schematic
The AOZ1363DI fast load switch can also be parallel
configured in applications that require efficiency
optimization. Overall conduction losses during the ON
cycle can be reduced in half by mounting two load
switches, as shown above. The EN pins can be tied
together and a common rising edge signal enables both
devices simultaneously. Each load switch device must
have a 470pF surface mounted ceramic capacitor across
VCC and GND (pin 2 and pin 3) – see PCB floor plan in
the Layout Guidelines. The VCC pin then connected
together onto a common 5V VCC rail. A 100kΩ resistor
tied between each of the devices’ VCC pin and FLT_B
pin for user flag function. Both FLT_B pins will be tied
together to a single trace for easy user access. Each
device will employ its own pair of 47µF capacitor next to
the IN (pin 5 and EP) and PGND. Both VIN pins will be
tied together through a wide track, connecting to the 12V
supply rail.
AOZ1363 has the protection function against the
destructive output short current thanks to the ultra fast
turn-off feature as long as the short phenomenon takes
place in the upper switch of the totem pole. In Figure 5A,
when the short phenomenon happens in the upper
MOSFET(M2) of the totem pole type load the excessive
short current starts ramping up speedily but since
AOZ1363 can detect it, turn off MOSFET quickly within
100ns and flag the fault signal to main controller the
whole system can is protected safely.
However, in case the output is short to the GND like
Figure 5B, AOZ1363 needs a diode(D1) between OUT
and GND to clamp the excessive negative voltage in the
output due to parasitic inductance.
The C1 and C2 capacitor should be located in nearest
point to IN and OUT each other and the C2 should be
lower than 4.7µF for the fast short detection.
IN
OUT
M2 Short
M1
Totem pole
type load
OFF
C1
PWM
C2
AOZ1363DI
M2
L1
C3
GND
M3
Figure 5A. Application Against Totem Pole Load Short
IN
OUT
Load
Short
M1
The SS cap of 330pF will be mounted next to each
device’s SS pin and each respective GND. Both SS pins
will be tied to a common trace on the PCB. The ISEN
resistor should be configured such that the typical value
ISEN resistor, Rsen = 100kΩ will be divided by the same
amount of AOZ1363DI devices used.
OFF
C1
C2
AOZ1363DI
D1
GND
Figure 5B. Application Against Load Rail Short to Ground
Rev. 1.0 July 2014
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Page 8 of 13
AOZ1363DI
Recommended Bill of Materials
U1
AOZ1363DI
OFF ON
1
R3 1M
5V
R2
100k
VIN
2
C3
470pF
3
4
12V Input
5
6
C1
47μF
EN
OUT
VCC
OUT
GND
OUT
FLT_B
NC
IN
ISEN
NC
SS
EP
C5
47μF
12V Output
12
11
10
D1
DPAK
9
C2
4.7μF
8
7
Rsen
C4
330pF
R4
0Ω
Component
Value
Description / Rating
Vendor
Part #
U1
--
--
Alpha Omega
AOZ1363DI
C1, C5
4.7µF
CAP CER 47UF 16V 20% X5R 1210
Taiyo Yuden
EMK325BJ476MM-T
C2
4.7µF
CAP CER 4.7UF 50V 10% X5R 1206
Taiyo Yuden
UMK316BJ475KL-T
C3
470pF
CAP CER 470PF 50V 10% X7R 0603
Murata Elec.
GRM188R71H471KA01J
C4
330pF
CAP CER 330PF 50V 10% X7R 0603
Murata Elec.
GRM188R71H331KA0ID
RSEN
100kΩ
1/10W 1% JUMP 0603 SMD
Panasonic (ECG)
ERJ-3GEYJ104V
R2
100kΩ
1/10W 1% JUMP 0603 SMD
Panasonic (ECG)
ERJ-3GEYJ104V
R3
1MΩ
1/10W 1% JUMP 0603 SMD
Yaged
RC0603FR-071ML
R4
0Ω
1/10W 1% JUMP 0603 SMD
Yaged
RC0603JR-070RL
D1
CQ714
CQ 5D CQ714 B2535G
AKA
CQ714B2535G
Rev. 1.0 July 2014
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Page 9 of 13
AOZ1363DI
Recommended Layout Guidelines
The AOZ1363DI load switch is a device that is capable of
delivering a steady flow of DC current. It provides up to
6A of continuous current into two DrMos modules for
step-down conversion in continuous conduction mode.
The floor plan in Figure 6 is focused on providing the IN
(pin 5 and exposed pad) and the OUT (pins 10,11 and
12) with plenty of top layer exposed copper for thermal
relief, thus, transferring most of the power dissipated as
heat down to the PCB. The top layer layout diagram in
Figure 6 shows an optimal method for cooling.
Furthermore, the input bypass capacitors CIN1 and CIN2
are surface mounted ceramic capacitors mounted
directly to the exposed VIN paddle. The 4.7µF MLCC
should be located as close as physically possible to the
output pins 10-12 with return path star power grounded
with the input capacitors. The AOZ1363DI employs an
extremely fast 100ns turn off mechanism during an overcurrent event. When the DC current through the large
internal NMOS switch exceeds its maximum threshold of
11.2A at 25°C, a fast gate discharging circuit is deployed
causing the output to decay to zero. The layout
configuration of Figure 6 enables the fast discharging of
the 4.7µF output capacitor very effectively through the
load downstream.
R4 (0Ω) is the only point to
connect AGND and PGND together
Wide VIN track for
thermal sensing location
Allcocated area for
Current Sense Information
Allcocated area for
thermal sensing point
Figure 7. Top Layer Floor Plan
Please note the GND (upside down triangle) and PGND
(earth ground) symbols in Figure 7. The PGND symbols
should only be connected to the Input and Output
capacitors and nowhere else. All GND symbols should
be used for the rest of the external components including
the IC’s pin 3. All GND connections should be star
grounded together separate from the PGND connections.
Bottom layer has been allocated for PGND use only so
the Input and the Output capacitors are directly tied to the
bottom layer through via connectors. Only a single point
will be used to connect both AGND and PGND for
optimal noise isolation. Please refer to Figure 6 for R4
valued at 0Ω.
All Input (pin 5 and Exposed Pad) and Output (pins 10,
11 and 12) traces should be at top layer for optimal trace
resistances. Current going through vias is not
acceptable. Traces on top layer may be duplicated to the
second layer (bottom layer) and via connecting both the
top and bottom traces as near as possible to the IC
region is advisable to provide thermal relief.
Figure 8. Bottom Layer Floor Plan
All of the above details must be applied when considering
to implement a multi–device parallel configuration (2 or 3
devices).
Rev. 1.0 July 2014
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Page 10 of 13
AOZ1363DI
Package Dimensions, DFN 3x3, 12L
D
12x
bbb
12
e
b
C A B
12
aaa C 2x
R
E
1
Pin1
Identification
E1
L
aaa C 2x
D1
TOP VIEW
BOTTOM VIEW
ccc C
A1
Seating
Plane
A
ddd C
SIDE VIEW
C
RECOMMENDED LAND PATTERN
Symbols Min.
0.23
0.40
0.27
0.50
1.32
2.64
1.70
Dimensions in millimeters
2.44
UNIT: mm
A
A1
b
c
D
D1
E
E1
e
L
R
aaa
bbb
ccc
ddd
0.70
0.00
0.18
---
Nom.
0.75
0.02
0.23
0.203
3.00 BSC
2.39
2.44
3.00 BSC
1.55
1.70
0.50 BSC
0.28
0.38
0.20
0.15
0.10
0.10
0.08
Max.
0.80
0.05
0.28
--2.54
1.80
0.48
Dimensions in inches
Symbols Min.
A
A1
b
c
D
D1
E
E1
e
L
R
aaa
bbb
ccc
ddd
Nom.
Max.
0.028
0.000
0.007
---
0.030 0.031
0.001 0.002
0.009 0.011
0.008
--0.118 BSC
0.094 0.096 0.010
0.118 BSC
0.061 0.067 0.071
0.020 BSC
0.011 0.015 0.019
0.008
0.006
0.004
0.004
0.003
Notes:
1. Dimensions and tolerances conform to ASME Y14.5M-1994.
2. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
3. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal
has the optional radius on the other end of the terminal, dimension b should not be measured in that radius area.
4. Coplanarity ddd applies to the terminals and all other bottom surface metallization.
Rev. 1.0 July 2014
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Page 11 of 13
AOZ1363DI
Tape and Reel Dimensions, DFN 3x3, 12L
Carrier Tape
D0
P1
A–A
D1
A
E1
K0
E2
E
B0
A
P2
T
P0
A0
Feeding Direction
UNIT: mm
Package
DFN 3x3_EP
A0
B0
3.40 3.35
±0.10 ±0.10
D0
K0
1.50
1.10
±0.10 +0.10/-0.0
D1
E
E1
E2
P0
P1
P2
T
1.50
+0.10/-0.0
12.00
±0.30
1.75
±0.10
5.50
±0.05
8.00
±0.10
4.00
±0.10
2.00
±0.05
0.30
±0.05
Reel
W1
N
S
G
K
M
V
R
H
W
UNIT: mm
Tape Size Reel Size
M
N
12mm
ø330
ø330.00 ø97.00
±0.50
±0.10
W1
H
K
S
W
13.00 17.40 ø13.00 10.60 2.00
±0.50
±0.30 ±1.00 +0.5/-0.2
G
N/A
R
N/A
V
N/A
Leader / Trailer & Orientation
Unit Per Reel:
5000pcs
Trailer Tape
300mm Min.
Rev. 1.0 July 2014
Components Tape
Orientation in Pocket
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Leader Tape
500mm Min.
Page 12 of 13
AOZ1363DI
Part Marking
AOZ1363DI
(DFN3x3-12)
1363
Part Number Code
I0AW
Industrial Temperature
Range
LT
NoOption
Year & Week Code
Assembly Lot Code
Assembly Location Code
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make changes
to such information at any time without further notice. This document does not constitute the grant of any intellectual
property rights or representation of non-infringement of any third party’s intellectual property rights.
LIFE SUPPORT POLICY
ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 July 2014
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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