2016 DI2CSB IP Core I2C Bus Interface Slave - Base version v. 3.00 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. APPLICATIONS ● ● ● ● ● ● Embedded microprocessor boards Consumer and professional audio/video Home and automotive radio Low-power applications Communication systems Cost-effective reliable automotive systems DELIVERABLES ♦ Source code: ● ● ● ♦ VHDL & VERILOG test bench environment ● ● ● IP CORE OVERVIEW 2 The I C is a two-wire, bi-directional serial bus, which provides simple and efficient method of data transmission over a short distance, between many devices. The DI2CSB provides an interface between passive target devices e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can work as a slave receiver or transmitter, depending on a working mode, determined by the master device. A very simple interface, composed with the read, write and data signals, allows easy connection with target devices. The core doesn’t require programming and is ready to work after power-up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all fea2 tures required by the I C specification. The DI2CSB supports all transmission speed modes. KEY FEATURES 2 ● ● Conforms to v.4.0 of the I C specification Slave operation ○ ○ ● Support for all transmission speeds ○ ○ ○ ○ ● ● ● ● ● ● ● ● ● Slave transmitter Slave receiver Standard (up to 100 kb/s) Fast (up to 400 kb/s) Fast Plus (up to 1 Mb/s) High Speed (up to 3,4 Mb/s) Allows operation from a wide range of input clock frequencies Support for reads, writes, burst reads, burst writes, and repeated start 7-bit addressing No programming required Simple interface allows easy connection with target device e.g. memory, LCD display, pressure sensors etc. Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF ♦ Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation ● ● ● ♦ ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support ● ● IP Core implementation support 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code called HDL Source code FPGA EDIF/NGO/NGD/QXP/VQM called Netlist 1 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. BLOCK DIAGRAM The figure below shows the DI2CSB IP Core block diagram. Receive Receive Data datai(7:0) datao(7:0) address(23:0) Shift Register Target Device Interface busz sz we rd Send Data Input Filter sdai Output Register sdao Own Address Detection Control Logic Synchronization Logic rst clk Input Filter scli DI2CX CORES OVERVIEW 2 - - Spike filtering User defined timing High-speed mode Fast Plus mode Fast mode - Standard mode - 10-bit addressing - - 7-bit addressing Arbitration Passive device interface CPU interface Slave operation - - Clock synchronization 3.0 3.0 3.0 3.0 Interrupt generation DI2CM DI2CS DI2CSB DI2CMS Master operation 2 Design I C specification version The main features of each DCD I C compliant cores have been summarized in the table below. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. - I2C Cores summary table SYMBOL datai(7:0) datao(7:0) address(23:0) scli sdai clk rst rd wr sdao busz 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. UNITS SUMMARY CONTACT Target device Interface – Performs the interface functions between DI2CSB internal blocks and target device. Allows easy connection of the core with passive devices e.g. memory, LCD display, pressure sensors, I/O devices etc. Control Logic – Manages execution of all commands sent via interface. Synchronizes internal data flow. Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales Shift Register – Controls SDA line, performs data and address shifts, during the data transmission and reception. Input Filter – Performs spike filtering. Synchronization Logic – Synchronizes data and address shifts, during the data transmission and reception. SCLI spikes are filtered by this unit. PINS DESCRIPTION PIN TYPE DESCRIPTION clk input Global clock rst input Global reset datai(7:0) input Data bus from target device scli input I2C bus clock line (input) sdai input I2C bus data line (input) datao(7:0) output Data bus to target device address(23:0) output Address of accessed register busz output Turns datao into Z state wr output Write strobe for target device rd output Read strobe for target device PERFORMANCE The following table gives a survey about the Core area and performance in LATTICE® devices after Place & Route (all key features included): Device SC ECP2 ECP2M XP2 EC ECP XP ispXPGA ORCA 4 ORCA 3 Speed grade LUTs/PFUs -7 76 / 42 -7 78 / 42 -7 70 / 27 -7 70 / 27 -5 118 / 27 -5 118 / 27 -5 118 / 27 -5 79 / 21 -3 90 / 15 -7 73 / 17 Core performance in LATTICE® devices Fmax 323 MHz 317 MHz 318 MHz 263 MHz 203 MHz 212 MHz 180 MHz 180 MHz 129 MHz 84 MHz 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.