2016 Audio Platform IP Core USB 2.0 Audio Design Platform v.1.10 COMPANY OVERVIEW Digital Core Design is a leading IP Core provider and a System-on-Chip design house. The company was founded in 1999 and since the very beginning has been focused on IP Core architecture improvements. Our innovative, silicon proven solutions have been employed by over 300 customers and with more than 500 hundred licenses sold to companies like Intel, Siemens, Philips, General Electric, Sony and Toyota. Based on more than 70 different architectures, starting from serial interfaces to advanced microcontrollers and SoCs, we are designing solutions tailored to your needs. IP CORE OVERVIEW The USB 2.0 Audio Design Platform is a complete, integrated solution, designed to be used in USB based Audio Devices, such as speakers and microphones. The complete Audio Design Platform includes: ● ● ● ● ● ● ● ● DUSB2 peripheral controller designed to support 12 Mb/s “Full Speed” (FS) and 480 Mb/s “High Speed” (HS) serial data transmission rates DP8051XP ultra high performance, speed optimized, fully customizable 8051 8-bit microcontroller with built-in DoCD™ debug IP core Audio Device stack-optimized software for DP8051XP 8-bit CPU FPGA board with ready to use, pre-programmed example USB stereo speakers application HAD2 – DoCD™ Hardware Assisted Debugger board DoCD™ Debug Software DoCD™ driver for Keil development software DoCD™ driver for IAR development software MAIN FEATURES ● ● ● ● ● ● ● ● ● ● ● ● ● Full compliance with the USB 2.0 specification Full-speed 12 Mbps operation High-speed 480 Mbps operation Supports UTMI Transceiver Macrocell Interface Suspend and resume power management functions 100% software compatible with 8051 industry standard Up to 256 bytes of internal (on-chip) Data Memory Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory Up to 16M bytes of external (off-chip) Data Memory User programmable Program Memory Wait States solution for wide range of memories speed User programmable External Data Memory Wait States solution for wide range of memories speed Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states Scan test ready DELIVERABLES ♦ ● ● ● ♦ ● ● ● ● ♦ ♦ DUSB2 & DP8051XP source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF Netlist DUSB2 & DP8051XP test bench environments NCSim automatic simulation macros ModelSim automatic simulation macros Active-HDL automatic simulation macros Tests with reference responses Audio Devices software stack source code FPGA board with ready to use, preprogrammed example application HAD2 - DoCD™ Hardware Assisted Debugger board DoCD™ Debug Software DoCD™ driver for Keil development software DoCD™ driver for IAR development software Technical documentation ♦ ♦ ♦ ♦ ♦ ● ● ● ♦ ♦ Installation notes HDL core specification Datasheet Synthesis scripts Technical support ● ● IP Core implementation support 3 months maintenance ● ● Delivery of the IP Core and documentation updates, minor and major versions changes Phone & email support UNITS SUMMARY UTMI Interface – This module is clocked by utmiclk clock and manages communication with USB 2.0 Transceiver Macrocell. It is responsible for reset detection, speed handshake, token, data and handshake packet reception and transmission. CPU Interface – This module is clocked by cpuclk clock and manages communication with DP8051XP CPU. In this module DUSB2 core configuration and status registers are located. SRAM Interface – This module manages communication with Synchronous Random Access Memory. It generates address, read and write signals for the SRAM memory and buffers data bytes during the FIFO read and write operations. EP0 endpoint –The EP0 control endpoint is special bidirectional endpoint used for device configuration and allows generic USB control and status access. EP1 endpoint – The EP1 data endpoint is unidirectional configurable endpoint used for application specific data transmission. DP8051XP CPU – Ultra high performance, speed optimized 8-bit embedded controller, 100% software compatible with industry standard 8051. 2 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. PINS DESCRIPTION PIN TYPE reset utmiclk utmilinestate(1:0) utmidatai(7:0) utmirxvalid utmirxactive utmirxerror utmitxready sramdataia(7:0) sramdataib(7:0) cpuclk input input input input input input input input input input input prgramdata[7:0] input prgromdata[7:0] input ramdatai[7:0] sfrdatai[7:0] xdatai[7:0] int0 int1 utmiopmode(1:0) utmidatao(7:0) utmisuspendm utmixcvrselect utmitermselect utmitxvalid sramaddra(13:0) sramaddrb(13:0) sramdataoa(7:0) sramdataob(7:0) sramwea sramweb prgaddr[15:0] prgdatao[7:0] prgramwr ramaddr[7:0] ramdatao[7:0] ramoe ramwe sfraddr[6:0] sfrdatao[7:0] sfroe sfrwe xaddr[23:0] xdatao[7:0] xdataz xprgrd xprgwr xdatard xdatawr input input input input input output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output DESCRIPTION Global reset USB clock USB line state USB parallel data input bus USB receive valid USB receive active USB receive error USB transmit ready SRAM port A data input bus SRAM port B data input bus CPU clock Data bus from internal RAM program memory Data bus from internal ROM progogram memory Data bus from internal data memory Data bus from user SFR’s Data bus from external memories External interrupt 0 External interrupt 1 USB operational mode USB parallel data output bus USB suspend USB transceiver select USB termination select USB transmit valid SRAM port A address bus SRAM port B address bus SRAM port A data output bus SRAM port B data output bus SRAM port A write enable SRAM port B write enable Internal program memory address bus Data bus for internal program memory Internal program memory write Internal Data Memory address bus Data bus for internal data memory Internal data memory output enable Internal data memory write enable Address bus for user SFR’s Data bus for user SFR’s User SFR’s output enable User SFR’s write enable Address bus for external memories Data bus for external memories Turn xdata bus into ‘Z’ state External program memory read External program memory write External data memory read External data memory write LICENSING Comprehensible and clearly defined licensing methods without royalty-per-chip fees make use of our IP Cores easy and simple. Single-Site license option – dedicated to small and middle sized companies, which run their business in one place. Multi-Site license option – dedicated to corporate customers, who operate at several locations. The licensed product can be used in selected company branches. In all cases the number of IP Core instantiations within a project and the number of manufactured chips are unlimited. The license is royalty-per-chip free. There are no restrictions regarding the time of use. There are two formats of the delivered IP Core: VHDL or Verilog RTL synthesizable source code FPGA EDIF/NGO/NGD/QXP/VQM (Netlist) SYMBOL cpuclk prgromdata(7:0) prgramdata(7:0) prgaddr(15:0) prgdatao(7:0) prgramwr ramdatai(7:0) ramaddr(7:0) ramdatao(7:0) ramwe ramoe sfrdatai(7:0) xdatai(7:0) ready sfraddr(6:0) sfrdatao(7:0) sfrwe sfroe xaddr(23:0) xdatao(7:0) xdataz xprgrd xprgwr xdatard xdatawr sxdmdatai(7:0) sxdmaddr(23:0) sxdmdatao(7:0) sxdmwe sxdmoe int0 int1 utmiclk utmilinestate(1:0) utmidatai(7:0) utmirxvalid utmirxactive utmirxerror utmitxready sramdataia(7:0) sramdataib(7:0) utmiopmode(1:0) cpudatao(7:0) utmitxvalid utmisuspendm utmixcvrselect utmitermselect sramaddra(13:0) sramaddrb(13:0) sramdataoa(7:0) sramdataob(7:0) sramwea sramweb reset 3 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners. BLOCK DIAGRAM utmiclk utmilinestate(1:0) utmidatai(7:0) utmirxvalid utmirxactive utmirxerror utmitxready utmiopmode(1:0) utmidatao(7:0) utmisuspendm utmixcvrselect utmitermselect utmitxvalid sramaddra(13:0) sramaddrb(13:0) sramdataoa(7:0) sramdataob(7:0) sramwea sramweb sramdataia(7:0) sramdataib(7:0) UTMI Interface DP8051XP CPU SRAM Interface EP0 Component cpuclk prgromdata(7:0) prgramdata(7:0) prgramaddr(16:0) prgramdatao(7:0) prgramwr ramdatai(7:0) ramaddr ramdatao(7:0) ramwe ramoe sfrdatai(7:0) sfraddr(6:0) sfrdatao(7:0) sfrwe sfroe xdatai(7:0) xaddr(23:0) xdatao(7:0) xdataz xprgrd xprgwr xdatard xdatawr int0 int1 Area [Slices] CPU interface UTMI interface SRAM interface EP0 endpoint EP1 endpoint DP8051XP CPU DoCD™ debug IP core 120 145 65 80 85 540 230 [FFs] 170 230 95 140 155 320 270 Total area 1265 1640 Core components area utilization in XILINX® VIRTEX-5 devices CONTACT Digital Core Design Headquarters: Wroclawska 94, 41-902 Bytom, POLAND e-mail: tel.: fax: [email protected] 0048 32 282 82 66 0048 32 282 74 37 Distributors: Please check: http://dcd.pl/sales EP1 EP2 CPU Interface reset PERFORMANCE The following tables give a survey about the Core area and performance in Programmable Logic Devices after Place & Route. Device SPARTAN-III SPARTAN-IIIE VIRTEX-4 VIRTEX-5 Speed grade cpuclk Fmax -5 50 MHz -5 60 MHz -12 75 MHz -3 90 MHz Core performance in XILINX® devices utmiclk Fmax >100 MHz >100 MHz >100 MHz >100 MHz An area utilized by a complete, integrated USB 2.0 HID Design Platform in vendor specific technologies is summarized in the table below. Component Area [Slices] [FFs] CPU interface 225 170 UTMI interface 265 230 SRAM interface 115 95 EP0 endpoint 150 140 EP1 endpoint 160 155 DP8051XP CPU 1100 320 DoCD™ debug IP core 375 270 Total area 2390 1380 Core components area utilization in XILINX® devices except VIRTEX5 family 4 Copyright © 1999-2016 DCD – Digital Core Design. All Rights Reserved. All trademarks mentioned in this document are the property of their respective owners.