Application note v4.04 DP8051 core interfacing with Internal Synchronous Data Memory The figure below shows the example DP8051 core interfacing with Internal Synchronous Data Memory. 8 ramaddr address* 8 ramdatao data ramwe we* 8 ramdatai clk DP8051 clk q clk Single Ported Synchronous RAM clk * signals internally registered by clk DP8051 core interfacing with synchronous Data Memory 0ns 20ns 40ns 60ns 80ns 100ns 120ns 1 clk addr sample 1 clk ramaddr addr addr ramdatao ramwe 1 clk ramoe max 1 clk read sample ramdatai data data Figure 1. Internal synchronous Data Memory read cycle waveform Note: clk ‐ system clock period ramaddr ‐ internal data memory address addr ‐ actually read memory address data ‐ data read from addr address read sample ‐ data has been read from data memory and written into des‐ tination register Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved -1- All trademarks mentioned in this document are trademarks of their respective owners. Application note v4.04 0ns 20ns 40ns 60ns 80ns 100ns 120ns 1 clk addr sample 1 clk ramaddr addr ramdatao addr value A value B ramwe sample ramwe ramoe max 1 clk RAM(addr) old value value A Figure 2. Internal synchronous Data Memory write cycle waveform Note: clk ramaddr ramwe value x value B ‐ system clock period ‐ internal data memory address ‐ internal data memory write enable signal ‐ data written into data memory at address addr Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved -2- All trademarks mentioned in this document are trademarks of their respective owners.