Download

FS8308 Low Power PLL Frequency Synthesizer IC
Advance Information
Princeton Technology Corp. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. Princeton Technology Corp. assumes no responsibility
for the use of any circuits shown in this datasheet.
Description
The FS8308 is a serial data input, phase-locked loop IC with programmable input and reference frequency dividers. When combined with a VCO, this IC becomes the core of a
very low power frequency synthesizer well-suited for mobile communication applications,
e.x. paging systems and family radio service (FRS). There are some features implemented
in this IC, including an 18-bit programmable input frequency divider, a terminal for reference oscillator buffer output, as well as stand-by control through programming, and etc.
Details are listed in the following.
Features
‹ Up to 40 MHz external crystal oscillator reference frequency under normal condition
‹ Low current consumption (IDD,total typically 1.2 mA at fFIN = 500 MHz and VDD1 = 1.0
V)
‹ With Schmitt trigger added for noise-immune programming input
‹ 18-bit programmable input frequency divider (including a ÷ 64/65 prescaler) with
divide ratio range from 4032 to 262143
‹ 13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with
divide ratio range from 40 to 65528
‹ Optional lock detector output (LD, fR/2, fV/2)
‹ Charge pump output for passive low-pass filter
‹ Wide tuning range of charge pump output for external VCO (VSS+0.5 to VDD2-0.5)
‹
‹
‹
‹
Switchover terminal for constant of loop filter or general open drain output
Reference oscillator buffer output
Programmable stand-by control
TSSOP 16L package (0.65mm pitch)
Applications
‹ Pager
‹ Family radio service (FRS)
‹ Wireless communication system
Page 1
April 2003
Advance Information
FS8308
Package and Pin Assignment: 16L, TSSOP
Symbols
Dimensions in mm
1
16
2
15
HiMARK
FS8308
XIN
XOUT
VDD2
NC
DO
VSS
FIN
VDD1
3
4
5
6
7
8
14
13
12
11
10
9
BO
TEST
SW
LE
DATA
CLK
LD
NC
Dimensions in inch
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
---
---
1.20
---
---
0.048
A1
0.05
---
0.15
0.002
---
0.006
A2
0.80
1.00
1.05
0.031
0.039
0.041
b
0.19
---
0.30
0.007
---
0.012
C
0.09
---
0.20
0.004
---
0.008
D
4.90
5.00
5.10
0.193
0.197
0.201
E
---
6.40
---
---
0.252
---
E1
4.30
4.40
4.50
0.169
0.173
0.177
e
---
0.65
---
---
0.026
---
L
0.45
0.60
0.75
0.018
0.024
0.030
y
---
---
0.10
---
---
0.004
θ
0°
---
8°
0°
---
8°
Note: Tolerance + 0.1mm unless otherwise specified
Page 2
April 2003
Advance Information
FS8308
Pin Descriptions
Number
Name
I/O
Description
1
XIN
I
Reference crystal oscillator or external clock input with internally biased amplifier
(any external input to XIN must be ac-coupled)
2
XOUT
O
Reference crystal oscillator or external clock output
3
VDD2
POWER
4
NC
NC
5
DO
O
6
VSS
GND
7
FIN
I
8
VDD1
POWER
9
NC
NC
10
LD
O
Lock detector output (high when PLL is locked)
11
CLK
I
Shift register clock input
12
DATA
I
Serial data input
13
LE
I
Latch enable input
14
SW
O
Switchover terminal for constant of loop filter or a general open drain output
15
TEST
I
Test mode control input with internal pull-down resistor
16
BO
O
Terminal of reference crystal oscillator buffer output
Nominal 3.0 V supply voltage
No connection
Single-ended charge pump output for passive low-pass filter
Ground
VCO frequency input with internally biased input amplifier
(any external input to FIN must be ac-coupled)
Nominal 1.0 V supply voltage
No connection
Block Diagram
FIN
DATA
CLK
LE
TEST
÷ 64/65
N-LATCH
CONTROL
LOGIC
SHIFT REGISTER
÷8
CHARGE
PUMP
DO
LOCK
DETECTOR
LD
SW
SW
PFD
R-LATCH S-LATCH
BO
XIN
N-COUNTER
R-COUNTER
WINDOW
GENERATOR
XOUT
Page 3
April 2003
Advance Information
FS8308
Absolute Maximum Ratings
VSS = 0 V
Parameter
Symbol
Rating
Unit
VDD1
VSS – 0.3 to VSS + 2.0
V
VDD2
VSS – 0.3 to VSS + 6.0
V
Input voltage range
VFIN
VSS – 0.3 to VDD + 0.3
V
Operating temperature range
TPS
–30 to 60
o
C
Storage temperature range
TSTG
–40 to 125
o
C
Soldering temperature range
TSLD
255
o
C
Soldering time range
tSLD
10
Supply voltage
s
Recommended Operating Conditions
VSS = 0 V
Parameter
Symbol
Value
Unit
min.
typ.
max.
VDD1
0.95
1.0
2.0
V
VDD2
2.4
3.0
3.6
V
TA
–30
25
60
o
Supply voltage range
Operating temperature
Page 4
C
April 2003
Advance Information
FS8308
Electrical Characteristics
(VDD1 = 0.95 to 2.0 V, VDD2 = 2.4 to 3.6 V, VSS = 0 V, TA = 0 to 60°C unless otherwise noted)
Parameter
Value
Symbol
Condition
IDD,total
VDD1 = 1.0 V
fFIN = 500 MHz
fXIN =24 MHz
Standby current consumption
IDD,standby
PS=”H”
FIN operating frequency range
fFIN
PFIN = -15dBm
VDD1 = 1.0 V, PS=”L”
XIN operating frequency range
fXIN
VDD1 = 1.0 V
FIN input voltage swing
PFIN
-15
dBm
XIN input voltage swing
VXIN
0.3
Vpk-pk
CLK, DATA, LE logic LOW input voltage
VIL
CLK, DATA, LE logic HIGH input voltage
VIH
Current consumption
min.
Unit
typ.
max.
1.2
1.5
mA
10
µA
20
500
MHz
7
40
MHz
0.3
VDD0.3
V
V
XIN logic LOW input current
IIL,XIN
VIL = 0 V
10
µA
XIN logic HIGH input current
IIH,XIN
VIH = VDD1
10
µA
FIN logic LOW input current
IIL,FIN
VIL = 0 V
60
µA
FIN logic HIGH input current
IIH,FIN
VIH = VDD1
60
µA
Charge Pump Drive Current
IDO
VDD2 = 3.0V, VDO = 1.5V
1.0
mA
Charge Pump Sink Current
IDO
VDD2 = 3.0V, VDO = 1.5V
1.0
mA
LD, FV, FR logic LOW output current
IOL
VOL = 0.4 V
0.1
mA
LD, FV, FR logic HIGH output current
IOH
VOH = VDD2 – 0.4 V
0.1
mA
SW logic LOW output current
ISW,OFF
SW = ’L’
VSW = VDD2 = 3.0V
SW logic HIGH output current
ISW,ON
SW = ’H’
VSW = VDD2 = 3.0V
10
2.8
µA
mA
DATA to CLK setup time
tSU1
2
µs
CLK to LE setup time
tSU2
2
µs
tHOLD
2
µs
Hold time
Page 5
April 2003
Advance Information
FS8308
Functional Description
Programmable Input Frequency Divider
The VCO input to the FIN pin is divided by the programmable divider and then internally
output to the phase/frequency detector (PFD) as fV. The programmable input frequency
divider consists of a ÷ 64/65 (P/P+1) dual-modulus prescaler in prior to a 18-bit (N)
counter, which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B)
counter. The total divide ratio, N, is related to values for P, A, and B through the relation
N = (P + 1) × A + P × (B – A) = P × B + A,
with B ≥ A . The minimum available programmable divisor for continuous counting is
given by P × ( P – 1 ) = 64 × 63 = 4032, and the valid total divide ratio range for the
input divider is M = 4032 to 262143.
Take N=10000 for example, since P=64 and hence that B=156 and A=16. Therefore, the
binary codes of B and A should be 0000 1001 1100 and 010000, respectively. An alternative approach is to translate the decimal N into binary code directly. And then just take the
last 6-bit as A and the remaining 12-bit as B. By far the binary code of N=10000 is
00 0010 0111 0001 0000. One can get the same result as the former method.
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable divider and then internally
output to the PFD as fR. The programmable reference frequency divider consists of a fixed
÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to
values for S and R through the relation
T = S × R = 8 × R.
The usable divisior range of the reference counter is R = 5 to 8191 and therefore, the
valid total divide ratio range for the reference divider is T = 40 to 65528 (in steps of
8.)
Page 6
April 2003
Advance Information
FS8308
Serial Input Data Format
The divsors of the input and reference dividers are input using a 20-bit serial interface
consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format
of the serial data is shown in Fig. 1. The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first. The last two bits are
recognized as the latch select control bits. Data on the DATA line should be changed on
the falling edge of CLK, and LE should be held low while data is being written to the shift
register. Data is transferred from the shift register to either one of the frequency divider
latches or the optional control latch when LE is set high. When the latch select control bits
are set high-low or low-low, data is loaded to the 18-bit N-counter latch, and when the
latch select control bits are set high-high, the 2 MSBs are ignored, the next 13 data bits are
loaded to the 13-bit R-counter latch and the remaining 3 LSBs are used to control testing
modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 =
low. To disable LD output (i.e. set LD low), R14 should be set low. When the latch select
control bits are set low-high, the 2 MSBs are recognized as PS and SW, which are used as
stand-by control and open drain output control, respectively. The detail of two control bits
setting is summarized in Table 1. In normal work condition, PS is set to low. When PS is
programmed to high, it will enter stand-by mode.
Serial input data timing waveforms are shown in Fig. 2.
Fig. 1 – Serial input data format
MSB
LSB
13-bit data for R-counter
R14
R16
R15
2ND CONTROL BIT
1ST CONTROL BIT
18-bit data for N-counter
ignored
optionalcontrol
SW
PS
ignored
Table 1: Control Bit Setting
1st CB
2nd CB
Fetching Target of Serial Data Input
X
0
N-counter
0
1
PS and SW
1
1
R-counter
Page 7
April 2003
Advance Information
FS8308
Fig. 2 – Serial input data timing waveforms
DATA
tHOLD
tSU1
CLK
tSU2
DATA
1
2
3
4
5
6
7
8
2ND CB
1ST CB
LSB
MSB
LE
9 10 11 12 13 14 15 16 17 18 19 20
CLK
LE
Page 8
April 2003
Advance Information
FS8308
Phase/Frequency Detector (PFD)
The PFD compares an internal input frequency divider output signal, fV, with an internal
reference frequency divider output signal, fR, and generates an error signal, DO, which is
proportional to the phase error between fV and fR. The DO output is intended for use with
a passive filter as shown in Fig. 2.
Lock Detector (LD)
When phase comparator detects phase difference, LD terminal outputs “L”. When phase
comparator locks, LD terminal outputs “H”. On standby, outputs “H”. The criteria for lock
condition is that the phase difference between fV and fR is less than 2/xin and continues for
more than three consecutive times.
The input/output waveforms for the PFD and LD are shown in Fig. 3.
Fig. 2 – Passive low-pass filter circuit
to VCO
DO
C2
R1
C1
Fig. 3 – PFD input/output waveforms
2/xin
fR
fV
high-Z
high-Z
high-Z
DO
LD
< 2/xin
< 2/xin
Page 9
< 2/xin
April 2003
Advance Information
FS8308
Stand-by Mode
The stand-by mode for the PLL is entered by programming the PS bit to high. In the standby mode, the XIN and FIN amplifiers, N-counter, and R-counter are stopped, as well as the
internal current bias for charge pump block, the N- and R-counters are also reset, and the
DO and DB outputs are set to the high impedance state. As long as voltage is supplied to
VDD2, data loaded to the latches is kept. To exit from stand-by mode to normal operation,
the PS bit must be programmed to low.
Reference Crystal Oscillator Buffer Output (BO)
This IC provides a reference crystal oscillator buffer output intended to be used as a crystal local oscillator to a 2nd mixer. The terminal is represented as BO. For cases to enhance
the buffer output swing, increasing VDD1 will be an efficient way.
Filter Switch Control (SW)
Control of SW terminal by “SW” bit. This terminal is for switching time-constant of loop
filter. Output type of this terminal is open drain output. When constant of loop filter
doesn’t change by this switch, general open drain output is available. Note that there is an
internal 200Ω resistor connected between and drain terminal and output pin.
Page 10
April 2003
Advance Information
FS8308
Application Circuit
LNA
1st mixer
1st IF
amplifier
2nd mixer
2nd IF
amplifier Discriminator
Wave
shaper
LPF
Frequency
multiplier (×4,5)
2nd LO
1st LO
XIN
BO
TEST
VDD2
SW
DO
VSS
FIN
VDD1
FS8308
NC
HiMARK
XOUT
RAM
ROM
CPU
Decoder
LE
DATA
CLK
LD
NC
LCD driver
Driver
LCD
DC/DC
converter
Page 11
April 2003
Advance Information
FS8308
Typical Characteristics
Input Sensitivity (dBm)
FIN Input Sensitivity vs. Input Frequency
0
-4
-8
-12
-16
-20
-24
-28
-32
-36
-40
Vdd2=3.0V
fXIN=24MHz, R=5
Vdd1=1.0V
Vdd1=1.1V
Vdd1=1.2V
0
100 200 300 400 500 600
fFIN (MHz)
Page 12
April 2003
Advance Information
FS8308
Current Consumption of Idd1 vs. Operating Frequency
Vdd2=3.0V, Pfin=-15dBm
fXIN=24MHz, R=5
2.0
Idd1 (mA)
1.6
1.2
0.8
Vdd1=1.0V
Vdd1=1.1V
Vdd1=1.2V
0.4
0.0
0
100
200 300 400
fFIN (MHz)
500
600
Current Consumption of Idd2 vs. Supply Voltage Vdd2
0.40
Idd2 (mA)
0.36
0.32
0.28
0.24
0.20
0.16
1.6 2.0 2.4 2.8 3.2 3.6 4.0
Vdd2 (V)
Page 13
April 2003
Advance Information
FS8308
Charge Pump Output Characteristics
Vdd2=3.0V
1.2
IDO (mA)
0.8
FR > FV
0.4
0.0
Drive Current
Sink Current
-0.4
-0.8
-1.2
FR < FV
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VDO (V)
Charge Pump Output Current vs. Power Supply Voltage
Charge Pump Output Current
1.1
1.0
IDO (mA)
0.9
VDO =
0.8
1
Vdd2
2
0.7
Drive Current
Sink Current
0.6
0.5
0.4
1.5
2.0
2.5 3.0
Vdd2 (V)
Page 14
3.5
4.0
April 2003
Advance Information
FS8308
Single Voltage Operation
This IC requires two separate power supplies to operate. If only one voltage source is
available, ex. use battery to serve as power source, the user can apply the configuration as
shown in the following which is referred to as single voltage operation.
R
VDD1
FS8308
VDD2
HiMARK
POWER SUPPLY
Since there is only one voltage source provided in the so-called single voltage configuration, which is directly connected to Vdd2, one needs to choose a reasonable R value to set
Vdd1 to operate within the safe region, whose requirement is Vdd1 > 0.95V. Keep in mind
that the lower Vdd1 is, the less current this IC will consume, but the poorer crystal buffer
output it drives. In order to balance the trade-off between the current consumption and
crystal buffer driving capability, Vdd1 is suggested to be about 1.1V. Vdd1 vs. Vdd2 for various R at fin=470MHz is plotted in the following figure. Note that although smaller resistor
R makes this IC consume more current, the reward is with wider power supply input
range. Typical value of R is recommended to be around 1.6KΩ..
Single Voltage Characteristic: Vdd1 vs. Vdd2 for Various R
1.5
1.4
R=1.2K
R=1.6K
R=1.8K
R=2.0K
Vdd1 (V)
1.3
1.2
1.1
Safe Operation Region
1.0
0.9
fin=470MHz, Pfin=-10dBm
xin=24MHz, N=4032, R=5
0.8
1.5
2.0
2.5
3.0
Vdd2 (V)
Page 15
3.5
4.0
April 2003